path: root/src/usr/hwpf/hwp/dram_training/memory_errors.xml

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     $Source: src/usr/hwpf/hwp/dram_training/memory_errors.xml $
   
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     COPYRIGHT International Business Machines Corp. 2012
   
     p1
   
     Object Code Only (OCO) source materials
     Licensed Internal Code Source Materials
     IBM HostBoot Licensed Internal Code
   
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     Origin: 30
   
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<hwpErrors>
<!-- *********************************************************************** -->

  <hwpError>
    <rc>RC_MSS_RCD_PARITY_ERROR_PORT0</rc>
    <description>An rcd parity error has been registered on port_0    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_RCD_PARITY_ERROR_PORT1</rc>
    <description>An rcd parity error has been registered on port_1    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_RCD_PARITY_ERROR_LIMIT</rc>
    <description>The number of rcd parity errors have exceeded the maximum allowable number    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_CCS_HUNG</rc>
    <description>The ccs failed to return from in_progress status and failed to describe an error further.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_CCS_READ_MISCOMPARE</rc>
    <description>The ccs errors at runtime and registers a read miscompare.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_CCS_UE_SUE</rc>
    <description>The ccs errors at runtime and registers a UE or SUE    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_CCS_CAL_TIMEOUT</rc>
    <description>The ccs errors at runtime and registers a calibration operation timeout    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_PLACE_HOLDER_ERROR</rc>
    <description>Not for production code.  This return code is used for cases where the error code has not been approved yet.  Eventually, no code should use this error code.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_EFF_CONFIG_RANK_GROUP_RC_ERROR_001A</rc>
    <description>Plug rule violation in EFF_CONFIG_RANK_GROUP.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_EFF_CONFIG_RC_ERROR_001A</rc>
    <description>Plug rule violation in EFF_CONFIG.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_UNEXPECTED_MEM_CLK_STATUS</rc>
    <description>A read of the memory clock status register returned an unexpected value.     </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_UNEXPECTED_NEST_CLK_STATUS</rc>
    <description>A read of the nest clock status register returned an unexpected value.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_INIT1_OPCG_DONE_ERROR</rc>
    <description>Timed out waiting for OPCG done bit(15).    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_INIT1_FSISTATUS_FAIL</rc>
    <description>Failed VDD status check on FSI2PIB Status Reg bit(16).    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_PLL_LOCK_TIMEOUT</rc>
    <description>Timed out waiting for PLL locks in FSI2PIB Status Reg bits(24,25).     </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_THOLD_ERROR</rc>
    <description>THOLDS after Clock Start cmd do NOT match to the expected value.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_CCREG_MISMATCH</rc>
    <description>Clock Control Register does not match the expected value.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_ARRAY_REPAIR_BUSY</rc>
    <description>Array repair loader is busy now. 0x00050003 bit(0)=1     </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_ARRAY_REPAIR_NOT_DONE</rc>
    <description>Array repair loader did NOT report repair done.     </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_ECC_TRAP_ERROR</rc>
    <description>ECC trap register reported error. 0x00050004 bit(0-7) != 0x00    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_DP18_0_PLL_FAILED_TO_LOCK</rc>
    <description>DP18  0x0C000 PLL failed to lock!  See lock status register at address: 0x8000C0000301143F    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_DP18_1_PLL_FAILED_TO_LOCK</rc>
    <description>DP18  0x1C000 PLL failed to lock!  See lock status register at address: 0x8001C0000301143F    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_AD32S_0_PLL_FAILED_TO_LOCK</rc>
    <description>AD32S 0x0C001 PLL failed to lock!  See lock status register at address: 0x8000C0010301143F    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_AD32S_1_PLL_FAILED_TO_LOCK</rc>
    <description>AD32S 0x1C001 PLL failed to lock!  See lock status register at address: 0x8001C0010301143F    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_GENERAL_PUTSCOM_ERROR</rc>
    <description>PutScom failed!   See previous error message for details.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_GENERAL_GETSCOM_ERROR</rc>
    <description>GetScom failed!   See previous error message for details.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_UNEXPECTED_CLOCK_STATUS</rc>
    <description>Unexpected clock status!  See previous error message for details.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_UNEXPECTED_FIR_STATUS</rc>
    <description>Unexpected FIR status!  See previous error message for details.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_INIT_CAL_FAILED</rc>
    <description>Inital Calibration failed.  Check init cal error register at address: 0x8001C0180301143F     </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_VOLT_UNRECOGNIZED_DRAM_DEVICE_TYPE</rc>
    <description>Unsupported DIMM type found.  All dimms must be DDR3 or DDR4    </description>
    <ffdc>DEVICE_TYPE</ffdc>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_VOLT_DDR_TYPE_MIXING_UNSUPPORTED</rc>
    <description>Mixing of DDR3 and DDR4 not supported.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_VOLT_DDR_TYPE_REQUIRED_VOLTAGE</rc>
    <description>One or more DIMMs do not support required voltage for DDR type.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_GENERAL_SIMSTKFAC_ERROR</rc>
    <description>simSTKFAC failed!   See previous error message for details    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_GET_FAPI_ATTRIBUTE_ERROR</rc>
    <description>Failed to get FAPI attribute!   See previous error message for details.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_GET_SIM_HIERARCHY_ERROR</rc>
    <description>Failed to get simulation hierarchy from eCmd target.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_UNSUPPORTED_FREQ_CALCULATED</rc>
    <description>The frequency calculated with spd data is not supported by the jedec standards.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_MAINT_START_NOT_RESET</rc>
    <description>MCMCCQ[0]: maint_cmd_start not reset by hw.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_MAINT_STOP_NOT_RESET</rc>
    <description>MCMCCQ[1]: maint_cmd_stop not reset by hw.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_MAINT_CMD_IN_PROGRESS</rc>
    <description>MBMSRQ[0]: Can't start new cmd if previous cmd still in progress.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_MAINT_NO_MEM_CNFG</rc>
    <description>MBAXCRn[0:3] = 0, meaning no memory configured behind this MBA.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_MAINT_CCS_MUX_NOT_MAINLINE</rc>
    <description>CCS_MODEQ[29] = 1, meaning mux set for CCS instead of mainline.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_MAINT_ECC_DISABLED</rc>
    <description>MBSECC[0] non zero, meaning ECC check/correct disabled.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_MAINT_INVALID_CMD</rc>
    <description>MBAFIRQ[0], invalid_maint_cmd.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_MAINT_INVALID_ADDR</rc>
    <description>MBAFIRQ[1], cmd started with invalid_maint_address.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_MAINT_CMD_TIMEOUT</rc>
    <description>Maint cmd timeout.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_MAINT_INVALID_DRAM_SIZE_WIDTH</rc>
    <description>Invalid dramSize or dramWidth in MBAXCRn.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_MAINT_INVALID_DIMM_CNFG</rc>
    <description>MBAXCRn configured with invalid combination of configType, configSubType, slotConfig.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_MAINT_NO_X4_SYMBOL</rc>
    <description>Symbol mark not allowed in x4 mode.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_MAINT_INVALID_MARKSTORE</rc>
    <description>Invalid galois field in markstore.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_MAINT_INVALID_SYMBOL_INDEX</rc>
    <description>Symbol index out of range.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_MAINT_INVALID_CHIP_INDEX</rc>
    <description>Not first symbol index of a chip.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_MAINT_MARKSTORE_WRITE_BLOCKED</rc>
    <description>Markstore write may have been blocked due to MPE FIR set.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER</rc>
    <description>Trying to steer invalid symbol.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_MAINT_NO_X8_ECC_SPARE</rc>
    <description>Invalid to use ECC spare in x8 mode.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_UNSUPPORTED_SPD_DATA</rc>
    <description>Invalid SPD data returned.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_NO_COMMON_SUPPORTED_CL</rc>
    <description>Current Configuration has no common supported CL Values.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_EXCEED_TAA_MAX_NO_CL</rc>
    <description> Exceeded TAA MAX with Lowest frequency.  No compatable CL.    </description>
  </hwpError>

  <hwpError>
    <rc>RC_MSS_MODULE_TYPE_MIX</rc>
    <description> Differing DIMM types in the same configuration.   </description>
  </hwpError>

</hwpErrors>