RC_MSS_RCD_PARITY_ERROR_PORT0
An rcd parity error has been registered on port_0
RC_MSS_RCD_PARITY_ERROR_PORT1
An rcd parity error has been registered on port_1
RC_MSS_RCD_PARITY_ERROR_LIMIT
The number of rcd parity errors have exceeded the maximum allowable number
RC_MSS_CCS_HUNG
The ccs failed to return from in_progress status and failed to describe an error further.
RC_MSS_CCS_READ_MISCOMPARE
The ccs errors at runtime and registers a read miscompare.
RC_MSS_CCS_UE_SUE
The ccs errors at runtime and registers a UE or SUE
RC_MSS_CCS_CAL_TIMEOUT
The ccs errors at runtime and registers a calibration operation timeout
RC_MSS_PLACE_HOLDER_ERROR
Not for production code. This return code is used for cases where the error code has not been approved yet. Eventually, no code should use this error code.
RC_MSS_EFF_CONFIG_RANK_GROUP_RC_ERROR_001A
Plug rule violation in EFF_CONFIG_RANK_GROUP.
RC_MSS_EFF_CONFIG_RC_ERROR_001A
Plug rule violation in EFF_CONFIG.
RC_MSS_UNEXPECTED_MEM_CLK_STATUS
A read of the memory clock status register returned an unexpected value.
RC_MSS_UNEXPECTED_NEST_CLK_STATUS
A read of the nest clock status register returned an unexpected value.
RC_MSS_INIT1_OPCG_DONE_ERROR
Timed out waiting for OPCG done bit(15).
RC_MSS_INIT1_FSISTATUS_FAIL
Failed VDD status check on FSI2PIB Status Reg bit(16).
RC_MSS_PLL_LOCK_TIMEOUT
Timed out waiting for PLL locks in FSI2PIB Status Reg bits(24,25).
RC_MSS_THOLD_ERROR
THOLDS after Clock Start cmd do NOT match to the expected value.
RC_MSS_CCREG_MISMATCH
Clock Control Register does not match the expected value.
RC_MSS_ARRAY_REPAIR_BUSY
Array repair loader is busy now. 0x00050003 bit(0)=1
RC_MSS_ARRAY_REPAIR_NOT_DONE
Array repair loader did NOT report repair done.
RC_MSS_ECC_TRAP_ERROR
ECC trap register reported error. 0x00050004 bit(0-7) != 0x00
RC_MSS_DP18_0_PLL_FAILED_TO_LOCK
DP18 0x0C000 PLL failed to lock! See lock status register at address: 0x8000C0000301143F
RC_MSS_DP18_1_PLL_FAILED_TO_LOCK
DP18 0x1C000 PLL failed to lock! See lock status register at address: 0x8001C0000301143F
RC_MSS_AD32S_0_PLL_FAILED_TO_LOCK
AD32S 0x0C001 PLL failed to lock! See lock status register at address: 0x8000C0010301143F
RC_MSS_AD32S_1_PLL_FAILED_TO_LOCK
AD32S 0x1C001 PLL failed to lock! See lock status register at address: 0x8001C0010301143F
RC_MSS_GENERAL_PUTSCOM_ERROR
PutScom failed! See previous error message for details.
RC_MSS_GENERAL_GETSCOM_ERROR
GetScom failed! See previous error message for details.
RC_MSS_UNEXPECTED_CLOCK_STATUS
Unexpected clock status! See previous error message for details.
RC_MSS_UNEXPECTED_FIR_STATUS
Unexpected FIR status! See previous error message for details.
RC_MSS_INIT_CAL_FAILED
Inital Calibration failed. Check init cal error register at address: 0x8001C0180301143F
RC_MSS_VOLT_UNRECOGNIZED_DRAM_DEVICE_TYPE
Unsupported DIMM type found. All dimms must be DDR3 or DDR4
DEVICE_TYPE
RC_MSS_VOLT_DDR_TYPE_MIXING_UNSUPPORTED
Mixing of DDR3 and DDR4 not supported.
RC_MSS_VOLT_DDR_TYPE_REQUIRED_VOLTAGE
One or more DIMMs do not support required voltage for DDR type.
RC_MSS_GENERAL_SIMSTKFAC_ERROR
simSTKFAC failed! See previous error message for details
RC_MSS_GET_FAPI_ATTRIBUTE_ERROR
Failed to get FAPI attribute! See previous error message for details.
RC_MSS_GET_SIM_HIERARCHY_ERROR
Failed to get simulation hierarchy from eCmd target.
RC_MSS_UNSUPPORTED_FREQ_CALCULATED
The frequency calculated with spd data is not supported by the jedec standards.
RC_MSS_MAINT_START_NOT_RESET
MCMCCQ[0]: maint_cmd_start not reset by hw.
RC_MSS_MAINT_STOP_NOT_RESET
MCMCCQ[1]: maint_cmd_stop not reset by hw.
RC_MSS_MAINT_CMD_IN_PROGRESS
MBMSRQ[0]: Can't start new cmd if previous cmd still in progress.
RC_MSS_MAINT_NO_MEM_CNFG
MBAXCRn[0:3] = 0, meaning no memory configured behind this MBA.
RC_MSS_MAINT_CCS_MUX_NOT_MAINLINE
CCS_MODEQ[29] = 1, meaning mux set for CCS instead of mainline.
RC_MSS_MAINT_ECC_DISABLED
MBSECC[0] non zero, meaning ECC check/correct disabled.
RC_MSS_MAINT_INVALID_CMD
MBAFIRQ[0], invalid_maint_cmd.
RC_MSS_MAINT_INVALID_ADDR
MBAFIRQ[1], cmd started with invalid_maint_address.
RC_MSS_MAINT_CMD_TIMEOUT
Maint cmd timeout.
RC_MSS_MAINT_INVALID_DRAM_SIZE_WIDTH
Invalid dramSize or dramWidth in MBAXCRn.
RC_MSS_MAINT_INVALID_DIMM_CNFG
MBAXCRn configured with invalid combination of configType, configSubType, slotConfig.
RC_MSS_MAINT_NO_X4_SYMBOL
Symbol mark not allowed in x4 mode.
RC_MSS_MAINT_INVALID_MARKSTORE
Invalid galois field in markstore.
RC_MSS_MAINT_INVALID_SYMBOL_INDEX
Symbol index out of range.
RC_MSS_MAINT_INVALID_CHIP_INDEX
Not first symbol index of a chip.
RC_MSS_MAINT_MARKSTORE_WRITE_BLOCKED
Markstore write may have been blocked due to MPE FIR set.
RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER
Trying to steer invalid symbol.
RC_MSS_MAINT_NO_X8_ECC_SPARE
Invalid to use ECC spare in x8 mode.
RC_MSS_UNSUPPORTED_SPD_DATA
Invalid SPD data returned.
RC_MSS_NO_COMMON_SUPPORTED_CL
Current Configuration has no common supported CL Values.
RC_MSS_EXCEED_TAA_MAX_NO_CL
Exceeded TAA MAX with Lowest frequency. No compatable CL.
RC_MSS_MODULE_TYPE_MIX
Differing DIMM types in the same configuration.