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* Fixing order of setting clock muxes & functional reset & removing sim only scomsCHRISTINA L. GRAVES2019-02-121-40/+5
* Adding in configurations for PNOR/LPC communicationCHRISTINA L. GRAVES2019-02-121-0/+40
* FAPI_INF entering and exiting message updatesAnusha Reddy Rangareddygari2019-02-121-2/+2
* Adding in LPC functional reset to sbe_lpc_initCHRISTINA L. GRAVES2019-02-122-7/+6
* Level 2 Procedure - p9_sbe_lpc_initSunil.Kumar2019-02-123-26/+68
* L1 Rev istep 0.(6-8,11,13,14),1.1,2.(1-13,15,18-20,22,26,27,30,32,34) V2Abhishek Agarwal2019-02-122-0/+117
* Find cpu struct directly in doorbell interrupt handlerDean Sanner2019-02-122-4/+9
* Add more agressive memory allocation callsDan Crowell2019-02-127-8/+43
* Add missing implied include to populate_hbruntime.HDan Crowell2019-02-121-1/+3
* Disable NVDIMM Trigger Before Draminit and Deassert DDR_RESETn During MPIPLTsung Yeung2019-02-1213-388/+881
* PRD: Adjust row repair capture data sizeCaleb Palmer2019-02-123-1/+19
* Add additional 2133 and 1866 ps values for spd parsing.Evan Lojewski2019-02-111-1/+4
* Skip NPU scominit until ARTMISS register gets updatedChristian Geddes2019-02-111-1/+5
* Add call to p9a_ocmb_enable to istep 10.4Christian Geddes2019-02-114-6/+104
* Update OBUS PLL Bucket attribute getter with Axone EC levelsChristian Geddes2019-02-111-1/+17
* Update simics to latest build for Axone simics bringupChristian Geddes2019-02-112-4/+4
* Make sure FIRDATA is filled in axone pnor, remove UVBWLIST sectionChristian Geddes2019-02-111-2/+2
* Fix 1-rank row repair case in p9c draminit_training and draminit_mcLouis Stermole2019-02-107-16/+312
* Use virtual address buffer to read mvpd ringsCorey Swenson2019-02-105-16/+72
* Add ATTR_MSS_MEM_MVPD_FWMS to generic xml and fix accessorLouis Stermole2019-02-101-0/+14
* Add p9a_mss_volt procedureLouis Stermole2019-02-101-0/+45
* Add generic attribute accessor script and makefilesLouis Stermole2019-02-101-0/+4
* Update setup_fw_boot_config() to read out actual values from attributesAlvin Wang2019-02-101-14/+0
* Correct invalid HUID and chiplet id values for NPU targetsMatt Raybuck2019-02-081-2/+6
* Updates to processMrw.pl to fix erroneous chiplet idsMatt Raybuck2019-02-081-8/+176
* HBBL LPC Error CheckingBill Hoffa2019-02-088-27/+73
* NVDIMM SBE Support to Trigger CSAVE - xip_customizeTsung Yeung2019-02-081-2/+3
* VDM(Part 1): Introduced new members in CME and CPMR image headersPrem Shanker Jha2019-02-081-1/+9
* Adds blank files for EFD APIStephen Glancy2019-02-075-0/+120
* Add empty explorer "check_for_ready" procedure filesAndre Marin2019-02-072-0/+48
* Unset CONFIG_FILE env var if in standalone environmentChristian Geddes2019-02-071-3/+3
* Move libconsole into base imageDan Crowell2019-02-071-1/+1
* Adds explorer OMI training codeStephen Glancy2019-02-062-3/+31
* Adds Explorer OMI setup - step 12.8aStephen Glancy2019-02-066-0/+429
* Adds blank Explorer MMIO setup filesStephen Glancy2019-02-066-0/+161
* Adds empty files for exp_draminit_mc and p9a_omi_trainAlvin Wang2019-02-068-0/+192
* Added p9a_omi_train procedureAlvin Wang2019-02-062-0/+155
* Add relationships for MCC to PRDDan Crowell2019-02-061-0/+3
* Add FSPBUILD to CI scriptsDan Crowell2019-02-063-27/+53
* Revert "Adds exp_draminit_mc"Jennifer A. Stofer2019-02-0516-609/+319
* Updates MWD_COARSE to run multiple patternsStephen Glancy2019-02-056-2/+142
* Adds exp_draminit_mcAlvin Wang2019-02-0518-332/+625
* Add SPD DDIMM DDR4 module except for PMIC fieldsAndre Marin2019-02-0511-14/+4490
* Generalize set fields in pre_data_initAndre Marin2019-02-053-61/+52
* Use singleton instance of TargetService in mmio.CChristian Geddes2019-02-051-1/+1
* Skip dmi_io_dccal in AxoneChristian Geddes2019-02-051-55/+64
* Add new memory related chiplet types to scomtrans functionChristian Geddes2019-02-051-2/+17
* Add temporary Axone simics workarounds to progress IPLChristian Geddes2019-02-053-1/+18
* P9 Obus MNFG CRC and ECC Error ThresholdChris Steffen2019-02-053-4/+154
* Change target types to 64-bit and add P10 target typesThi Tran2019-02-053-65/+75
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