diff options
| author | Christian Geddes <crgeddes@us.ibm.com> | 2019-01-31 17:01:58 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-02-05 16:56:05 -0600 |
| commit | de4076a6de0b26d96974f616cb28788e19c7e5a8 (patch) | |
| tree | 069f88c2f02cc8556c8fe2500e15e9e382996b4a /src | |
| parent | d054b917fa8bd693a248628519c81b9143e87af1 (diff) | |
| download | talos-hostboot-de4076a6de0b26d96974f616cb28788e19c7e5a8.tar.gz talos-hostboot-de4076a6de0b26d96974f616cb28788e19c7e5a8.zip | |
Add new memory related chiplet types to scomtrans function
Somehow this got missed when we did a first pass adding in scom
support for axone. Hit this will doing bringup, one of the scominit
HWPs was failing without this while trying to target a MCC chiplet.
Change-Id: Ie17ed1d6a5bdb7ec0e06623436d3eec26dafbf31
RTC: 196806
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71177
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/usr/scom/scomtrans.C | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/src/usr/scom/scomtrans.C b/src/usr/scom/scomtrans.C index 371fde0ad..e60e75ae6 100644 --- a/src/usr/scom/scomtrans.C +++ b/src/usr/scom/scomtrans.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -935,11 +935,26 @@ bool getChipUnitP9 (TARGETING::TYPE i_type, o_chipUnit = PU_CAPP_CHIPUNIT; break; } - case(TARGETING::TYPE_MC) : + case(TARGETING::TYPE_MC) : { o_chipUnit = PU_MC_CHIPUNIT; break; } + case(TARGETING::TYPE_MCC) : + { + o_chipUnit = PU_MCC_CHIPUNIT; + break; + } + case(TARGETING::TYPE_OMI) : + { + o_chipUnit = PU_OMI_CHIPUNIT; + break; + } + case(TARGETING::TYPE_OMIC) : + { + o_chipUnit = PU_OMIC_CHIPUNIT; + break; + } default: { l_isError = true; |
