P9 Obus MNFG CRC and ECC Error Threshold

- When in MNFG Threshold Mode, we will mask CRC/ECC Errors and
  setup performance counters to tally the number of errors.

Change-Id: I16ea4af0917a7f707ef09a54a0d329bf69212365
CQ: SW455443
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71016
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Megan P. Nguyen <pmegan@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71119
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>

3 files changed, 154 insertions, 4 deletions

diff --git a/src/import/chips/p9/procedures/hwp/io/p9_io_obus_post_trainadv.C b/src/import/chips/p9/procedures/hwp/io/p9_io_obus_post_trainadv.C
index 94228551b..86492ce39 100644
--- a/src/import/chips/p9/procedures/hwp/io/p9_io_obus_post_trainadv.C
+++ b/src/import/chips/p9/procedures/hwp/io/p9_io_obus_post_trainadv.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2017,2018                        */
+/* Contributors Listed Below - COPYRIGHT 2017,2019                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -53,11 +53,88 @@
 // Includes
 // ----------------------------------------------------------------------------
 #include <p9_io_obus_post_trainadv.H>
+#include <p9_obus_scom_addresses.H>
+#include <p9_obus_scom_addresses_fld.H>
 
 // ----------------------------------------------------------------------------
 // Procedure Function
 // ----------------------------------------------------------------------------
 
+fapi2::ReturnCode p9_io_obus_mnfg_setup_ecc_crc_masks(
+    const fapi2::Target<fapi2::TARGET_TYPE_OBUS>& i_tgt)
+{
+    // Setup ECC & CRC Masks
+    fapi2::buffer<uint64_t> l_fir_mask;
+    l_fir_mask.setBit<OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_SL_ECC_CORRECTABLE>();
+    l_fir_mask.setBit<OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_SL_ECC_CORRECTABLE>();
+    l_fir_mask.setBit<OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_TOO_MANY_CRC_ERRORS>();
+    l_fir_mask.setBit<OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_TOO_MANY_CRC_ERRORS>();
+    FAPI_TRY(fapi2::putScom(i_tgt, OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_OR, l_fir_mask));
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+fapi2::ReturnCode p9_io_obus_mnfg_setup_perf_counters(
+    const fapi2::Target<fapi2::TARGET_TYPE_OBUS>& i_tgt)
+{
+    // Setup Performance Counters
+    fapi2::buffer<uint64_t> l_data;
+    // Ex. putscom pu 0901081D 1B1400001B140000 -pall;
+    l_data.insertFromRight<OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_0,
+                           OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_0_LEN>(0x1B);
+    l_data.insertFromRight<OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_1,
+                           OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_1_LEN>(0x14);
+    l_data.insertFromRight<OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_4,
+                           OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_4_LEN>(0x1B);
+    l_data.insertFromRight<OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_5,
+                           OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_5_LEN>(0x14);
+    FAPI_TRY(fapi2::putScom(i_tgt, OBUS_LL0_IOOL_PERF_SEL_CONFIG, l_data));
+
+    // Ex. putscom pu 0901081C A050505000000000 -pall;
+    l_data.flush<0>();
+    l_data.insertFromRight<OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_0,
+                           OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_0_LEN>(0b10);
+    l_data.insertFromRight<OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_1,
+                           OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_1_LEN>(0b10);
+    l_data.insertFromRight<OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_4,
+                           OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_4_LEN>(0b01);
+    l_data.insertFromRight<OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_5,
+                           OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_5_LEN>(0b01);
+    l_data.insertFromRight<OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_0,
+                           OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_0_LEN>(0b01);
+    l_data.insertFromRight<OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_1,
+                           OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_1_LEN>(0b01);
+    l_data.insertFromRight<OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_4,
+                           OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_4_LEN>(0b01);
+    l_data.insertFromRight<OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_5,
+                           OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_5_LEN>(0b01);
+    FAPI_TRY(fapi2::putScom(i_tgt, OBUS_LL0_IOOL_PERF_TRACE_CONFIG, l_data));
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+fapi2::ReturnCode p9_io_obus_mnfg_adj_tally_logic(
+    const fapi2::Target<fapi2::TARGET_TYPE_OBUS>& i_tgt,
+    const uint64_t i_allowed_errors)
+{
+    // Adjust Tally Logic to Never Clear ECC & CRC Count
+    fapi2::buffer<uint64_t> l_data;
+
+    FAPI_TRY(fapi2::getScom(i_tgt, OBUS_LL0_IOOL_OPTICAL_CONFIG, l_data));
+    l_data.insertFromRight<OBUS_LL0_IOOL_OPTICAL_CONFIG_BAD_LANE_DURATION,
+                           OBUS_LL0_IOOL_OPTICAL_CONFIG_BAD_LANE_DURATION_LEN>(0xF);
+    l_data.insertFromRight<OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK_FAIL_DURATION,
+                           OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK_FAIL_DURATION_LEN>(0xF);
+    l_data.insertFromRight<OBUS_LL0_IOOL_OPTICAL_CONFIG_BAD_LANE_MAX,
+                           OBUS_LL0_IOOL_OPTICAL_CONFIG_BAD_LANE_MAX_LEN>(i_allowed_errors);
+    l_data.insertFromRight<OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK_FAIL_MAX,
+                           OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK_FAIL_MAX_LEN>(i_allowed_errors);
+    FAPI_TRY(fapi2::putScom(i_tgt, OBUS_LL0_IOOL_OPTICAL_CONFIG, l_data));
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+
 /**
  * @brief A simple HWP that runs after io_run_training.
  *  This function is called on every Obus.
@@ -68,6 +145,58 @@ fapi2::ReturnCode p9_io_obus_post_trainadv(
     const fapi2::Target<fapi2::TARGET_TYPE_OBUS>& i_tgt)
 {
     FAPI_IMP("Entering...");
+
+    // Get Sys Target
+    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> l_sys_tgt;
+
+    uint64_t l_mfg_flags = 0x0;
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MNFG_FLAGS, l_sys_tgt, l_mfg_flags));
+
+    if(l_mfg_flags == fapi2::ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS)
+    {
+        uint8_t l_mfg_error_threshold = 0x0;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_O_MNFG_ERROR_THRESHOLD, l_sys_tgt, l_mfg_error_threshold));
+
+        if(l_mfg_error_threshold != fapi2:: ENUM_ATTR_IO_O_MNFG_ERROR_THRESHOLD_CORNER_MODE)
+        {
+            // Setup ECC & CRC Masks
+            FAPI_TRY(p9_io_obus_mnfg_setup_ecc_crc_masks(i_tgt),
+                     "Error from p9_io_obus_mnfg_setup_ecc_crc_masks()");
+
+            // Setup Performance Counters
+            FAPI_TRY(p9_io_obus_mnfg_setup_perf_counters(i_tgt),
+                     "error from p9_io_obus_mnfg_setup_perf_counters()");
+
+            // setup performance counters
+            //   Make it so there are only 5 ECC errors allowed per lane or 5 CRC errors allowed per link (corner mode)
+            //   Ex. putscom pu 0901080F 0F000F00000000000 -bor -pall
+            //   Ex. putscom pu 0901080F FF85FF85FFFFFFFF -band -pall
+            FAPI_TRY(p9_io_obus_mnfg_adj_tally_logic(i_tgt, 5),
+                     "error from p9_io_obus_mnfg_adj_tally_logic()");
+
+        }
+        else if(l_mfg_error_threshold != fapi2:: ENUM_ATTR_IO_O_MNFG_ERROR_THRESHOLD_RELIABILITY_MODE)
+        {
+            // Setup ECC & CRC Masks
+            FAPI_TRY(p9_io_obus_mnfg_setup_ecc_crc_masks(i_tgt),
+                     "Error from p9_io_obus_mnfg_setup_ecc_crc_masks()");
+
+            // Setup Performance Counters
+            FAPI_TRY(p9_io_obus_mnfg_setup_perf_counters(i_tgt),
+                     "error from p9_io_obus_mnfg_setup_perf_counters()");
+
+            // Setup Performance Counters
+            //   Make it so there are only 10 ECC errors allowed per lane or 10 CRC errors allowed
+            //   per link (reliability test) --- Have a flag to go between 3.5/3.7 settings
+            //   Ex. putscom pu 0901080F 0F000F00000000000 -bor -pall
+            //   Ex. putscom pu 0901080F FF8AFF8AFFFFFFFF -band -pall
+            FAPI_TRY(p9_io_obus_mnfg_adj_tally_logic(i_tgt, 10),
+                     "error from p9_io_obus_mnfg_adj_tally_logic()");
+
+        }
+    }
+
+fapi_try_exit:
     FAPI_IMP("Exiting...");
     return fapi2::current_err;
 }
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_io_obus_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_io_obus_attributes.xml
index 4755ba0ed..fc9efabf5 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/p9_io_obus_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_io_obus_attributes.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- OpenPOWER HostBoot Project                                             -->
 <!--                                                                        -->
-<!-- Contributors Listed Below - COPYRIGHT 2015,2018                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2019                        -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -244,7 +244,7 @@
 <attribute>
   <id>ATTR_IO_O_MFG_STRESS_PR_OFFSET_ODD</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-  <description>i
+  <description>
     This attribute provides an a way to stress the SMP Abus Odd Lanes
     in Manufacturing. By applying a phase rotator offset we can further
     stress the phy.  This is a 6-bit 2's complement value that would be
@@ -255,4 +255,21 @@
   <platInit/>
 </attribute>
 <!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_IO_O_MNFG_ERROR_THRESHOLD</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    When in MNFG mode, we want to change the CRC/ECC thresholds and FIR
+    masks.  This is put into place for our longer manufacturing test runs.
+  </description>
+  <valueType>uint8</valueType>
+  <enum>
+    NONE = 0x0,
+    CORNER_MODE = 0x1,
+    RELIABILITY_MODE = 0x2
+  </enum>
+  <initToZero/>
+  <platInit/>
+</attribute>
+<!-- ********************************************************************** -->
 </attributes>
diff --git a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml
index aaaaa717a..fde4be57f 100644
--- a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml
+++ b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- OpenPOWER HostBoot Project                                             -->
 <!--                                                                        -->
-<!-- Contributors Listed Below - COPYRIGHT 2016,2018                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2016,2019                        -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -173,6 +173,10 @@
         <default>0x00</default>
     </attribute>
     <attribute>
+        <id>ATTR_IO_O_MNFG_ERROR_THRESHOLD</id>
+        <default>0x00</default>
+    </attribute>
+    <attribute>
         <id>ATTR_CME_CHTM_TRACE_ENABLE</id>
         <default>0x00</default>
     </attribute>