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* Support HB running in SMFDean Sanner2018-09-241-7/+31
| | | | | | | | | | | | | | | | | | | | | | Support SMF for P9N/P9C. Lots of minor tweaks to make this work, but the biggest is to run userspace in problem state This is needed because for SMF Hostboot will need to run in S=1, HV=0,PR=1 (and kernel in S=1, HV=1, PR=0) This commit makes P9 HB userpsace run in HV=0 PR=1 and kernel in HV=1, PR=0. Change-Id: Ia4771df5e8858c6b7ae54b0746e62b283afb4bc4 RTC: 197243 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/50530 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* kernel: Fix cmp in shutdown.S for modern binutilsJoel Stanley2017-06-271-4/+4
| | | | | | | | | | | | | | | | | | | | | | This is a further fix that was missed in 10983d35f568 ("Convert cmpi to cmpwi to fix build for modern binutils"). In the past binutils would assume 'cmp' meant 'cmpw'. Modern binutils require the explict use of cmpw or cmpd. The first two instances are dealing with SPRs, which are 32-bit, so cmpw is correct. It is not clear what to do in the third use of cmp, but given old toolchains have generated cmpw lets assume that we should maintain the behaviour. Change-Id: Iee5dd5903dcd7ac4028bab0176e08ce3db23b2d5 Signed-off-by: Joel Stanley <joel.stanley@au1.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42476 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Updates for new scratch registers in P9Andrew Geissler2016-08-161-2/+2
| | | | | | | | | | | | | | | P9 moves us from 8 scratch registers to 4. This commit handles this change and also adds the base support for partial cache. Change-Id: Ibe050c663744285dd3e77850649236a669dadbd6 RTC: 150923 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27462 Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Set HRMOR on all threads in kernel_shutdownDean Sanner2015-12-171-5/+6
| | | | | | | | Change-Id: Ib4226eb3b1afe03d100ac0610994f23dc0372311 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22794 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Change copyright prolog for all files to Apache.Patrick Williams2014-05-211-10/+10
| | | | | | | Change-Id: I5664587b4f889099290ef50d50fa9ce5e580e1eb Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11167 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Use new scratch reg for hb_done and set early in IPLAndrew Geissler2014-03-131-1/+1
| | | | | | | | | | | | | | | | | This is to support using the scratch register for the power off message. I moved to a new scratch register since we were sharing with a SBE scratch reg that was needed early in HB IPL. NOTE! This will have a co-req with an FSP track so we'll need to coordinate. CMVC-Coreq: 917527 Change-Id: I5f81f15126d6ad8d2c9459c5afe730554256c037 RTC: 95818 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9220 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: MIKE J. JONES <mjjones@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* implement start_payload for multi-drawerDoug Gilbert2014-01-101-22/+35
| | | | | | | | RTC: 71994 Change-Id: I422f349d5588731a5e7cfc504d96e497958d6b95 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/7426 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Basic devtree supportDean Sanner2013-08-091-22/+25
| | | | | | | | | | Simple devtree support for Sapphire in SPless mode Change-Id: I4a70bfc5cd3eb3dbd1b443869c046c789f98cc95 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3739 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Set "high" thread priority as 2 rather than 3.Patrick Williams2012-09-051-5/+3
| | | | | | | | | | | | | | | | | | | | | The Power processor has instructions of the form 'or a,a,a' that allow code to change the priority of a hw-thread relative to the others. We initially used 'or 1,1,1' as low priority and 'or 3,3,3' as high priority. This is used in, for instance, spinlocks to reduce the priority of a hw-thread while waiting for another thread to perform an activity. This code originally came from HAL. In reading the Power ISA closer I realized that 'or 3,3,3' has no effect when in user-space code, which means that a spinlock-like effect in user code is going to end up with the thread stuck at low priority until the next context switch. To prevent this we are going to change from 1/3 to 1/2 as the priority levels. Change-Id: I60ee866cde37499106f5e1e1d68a0b5ddeedf403 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1569 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Write scratch register in start_payload / shutdown.Patrick Williams2012-09-041-0/+6
| | | | | | | | | | Change-Id: I47a8ad7914c6833c476a7944be5d352f45467f3a RTC: 47725 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1646 Tested-by: Jenkins Server Reviewed-by: Mark W. Wenning <wenning@us.ibm.com> Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Ensure PHYP thread order is correct.Patrick Williams2012-08-221-0/+162
* Choose thread with the lowest PIR as the last to enter payload. * Use HRMOR update process from Murano Book IV. RTC: 43166 Change-Id: I629f4a55cba1967a13c31a16095697b7142ca407 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1529 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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