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author | Patrick Williams <iawillia@us.ibm.com> | 2012-08-20 15:52:07 -0500 |
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committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2012-09-05 15:42:19 -0500 |
commit | 1c6e1a4cddde411b6219b9e881039ffbda0deb4f (patch) | |
tree | 1e1ff02f7e51c0f7667ae30154e3bb326838fca4 /src/kernel/shutdown.S | |
parent | c07b8bb150f1464e17ebf3672460564ec3e8947c (diff) | |
download | talos-hostboot-1c6e1a4cddde411b6219b9e881039ffbda0deb4f.tar.gz talos-hostboot-1c6e1a4cddde411b6219b9e881039ffbda0deb4f.zip |
Set "high" thread priority as 2 rather than 3.
The Power processor has instructions of the form 'or a,a,a'
that allow code to change the priority of a hw-thread relative
to the others. We initially used 'or 1,1,1' as low priority
and 'or 3,3,3' as high priority. This is used in, for instance,
spinlocks to reduce the priority of a hw-thread while waiting
for another thread to perform an activity.
This code originally came from HAL. In reading the Power ISA
closer I realized that 'or 3,3,3' has no effect when in
user-space code, which means that a spinlock-like effect in
user code is going to end up with the thread stuck at low
priority until the next context switch. To prevent this we
are going to change from 1/3 to 1/2 as the priority levels.
Change-Id: I60ee866cde37499106f5e1e1d68a0b5ddeedf403
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1569
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/kernel/shutdown.S')
-rw-r--r-- | src/kernel/shutdown.S | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/src/kernel/shutdown.S b/src/kernel/shutdown.S index 2e03a58a7..bb7657318 100644 --- a/src/kernel/shutdown.S +++ b/src/kernel/shutdown.S @@ -38,7 +38,7 @@ bne 1b; \ /* Instruction barrier to ensure exit. */ \ isync; \ - or 3,3,3; /* Increase thread priority */ + or 2,2,2; /* Increase thread priority */ .section .text @@ -89,8 +89,7 @@ kernel_shutdown: kernel_shutdown_ea0_1_mode: ;// Perform barrier - 1 KERNEL_BARRIER(r8, r3, r11) - isync - or 3,3,3 ;// Increase thread priority + ;// Update HRMOR on master. mfspr r10, PIR andi. r10, r10, 7 @@ -153,13 +152,12 @@ kernel_shutdown_ea0_1_mode: bdnz 1b isync ;// Raise thread priority and leave ourselves. - or 3,3,3 + or 2,2,2 ;// Clear "Hostboot active" scratch register. li r3, (0x40 + 0x38) ;// See sys/mmio.h mtspr SPRC, r3 li r3, 0x0 mtspr SPRD, r3 - b 2b .section .data |