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* Add new path in EEPROM device op to allow reading from new EECACHEChristian Geddes2019-02-162-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Recently a new EECACHE section was introduced to Hostboot. This section gets populated with a copy of every PRIMARY_VPD eeprom (someday could contain other eeprom roles also) during host_discover_targets. This commit add support to allow users to select where they want to perform their EEPROM device operation. If they pass CACHE to the deviceOp macro then a read will come from the pnor cache, writes will write to pnor cache and then also write to the eeprom HW. If HARDWARE is passed in then reads and writes will be directly done on the eeprom hardware. If AUTOSELECT is passed the code will check our cache to see if we have a copy of the eeprom in question, if we have a copy we will go the CACHE path, if no copy exists we will go the HARDWARE path. Along with this change some reorganization was done w/ the eeprom related files. RTC: 196805 Change-Id: If2c4e5d3e338a1a10780740c1a019eb4af003b73 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70822 Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Roland Veloz <rveloz@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Create error log and fail if Proc's EC is found to be 0x0Christian Geddes2018-11-271-1/+2
| | | | | | | | | | | | | | | | | | | | While looking up the SBE version we will look at the processor's EC level to determine how to lookup the version. If we find that the EC level is 0 then something went wrong. In HW the register describing the procs EC will always be fused to some non-zero so we shouldnt see this in HW , in simics if this happens it is likely because simics has not implemented this register yet. Change-Id: I24bc0caaf3d2c9a574943ca07069bd6fb99cf1a6 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68804 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Ilya Smirnov <ismirno@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Only allow key transition in istep 10.2Nick Bofferding2018-11-151-1/+16
| | | | | | | | | | | | | In certain cases, if a key transition driver was booted and the nest frequency had to be updated, the key transition flow would erroneously activate in istep 7.3 (call_mss_freq). This change confines key transitioning to istep 10.2 Change-Id: I450703e21bf68644298f77fcdfca62eae5c667e4 CQ: SW451376 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68685 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Only switch sides and perform hreset if SEEPROM side versions matchChristian Geddes2018-07-192-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | In the event that the SBE fails hostboot will attempt to recover it. During runtime hostboot will attempt an HRESET if the SBE is in a failed state. When the SBE performs the HRESET it will save some important information that will persist through the reset. If one side is failing to recover the retry code will attempt to switch sides and do the hreset. If the SBE seeproms have different versions of the SBE code the data that was supposed to persist through the HRESET will be in incorrect places because the version mismatch. Because of this we cannot switch seeprom sides and perform a hreset if the seeproms have different level of the SBE code. CQ: SW438029 Change-Id: Ic7078a886088cc4d5355cc076e72d0fc36f85027 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61605 Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Read HW Key Hash From SBE Seeprom via ChipOp when applicableMike Baiocchi2018-07-063-3/+9
| | | | | | | | | | | | | | | | This commit uses SBEIO ChipOps to read the HW Key Hash from the SBE Seeprom when reading from the Seeprom that booted the processor. This will help avoid I2C collisions when both Hostboot and the SBE try to access the same SBE Seeprom at the same time. Change-Id: I5693cc59aa2a7259f07363328bd8513c943f0a06 CQ:SW435288 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61958 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* In non-MNFG, only match SBE keys for the sides that bootJaymes Wilks2018-06-281-1/+6
| | | | | | | | | | | | | | | | | | | FSP was not IPL'ing from SBE side 1 when production key is corrupt in SEEPROM of SBE side 0 (due to the key mismatch check). This change gets around that by only matching SBE keys for the sides that booted in non-MNFG case. Change-Id: I1dfcb5c7f7e281125fdbcfc8b8f3a84747c90f59 CQ:SW420430 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60571 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com> Reviewed-by: ILYA SMIRNOV <ismirno@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Secure Boot: Inform FSP of key transition progressNick Bofferding2018-05-101-2/+21
| | | | | | | | | | | | | | | | | | | | | | | The existing key transition flow updates all SBE SEEPROMs within the system in the same boot, thereby quiescing all SBEs. This compromises the ability of FSP to detect a key transition TI at the end of the update process because the SBE is not alive to service FSP's incoming SBE FIFO request to read the memory holding the attention information. This change adds new support to log the key transition progress in a node target attribute introduced in an earlier commit and send that status to FSP via a new mailbox message. Change-Id: I828184ae8be89ac87137d7510a3c375cef2e05d7 CQ: SW418697 CMVC-Prereq: 1053806 CMVC-Prereq: 1053552 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56677 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com> Reviewed-by: Marshall J. Wilks <mjwilks@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Created individual update flags for both SEEPROM 0 and SEEPROM 1Roland Veloz2018-03-121-4/+10
| | | | | | | | | | | | | | | | | | I created individual update flags for both SEEPROM 0 and SEEPROM 1 to better target which seeprom to update. Now SEEPROM 0 or SEEPROM 1 or both can be singled out for update(s). Change-Id: I91f1b66f6a1f2e42d37173fb9e21f87e440d3a21 RTC: 189218 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55173 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Force an SBE update upon boot failure as well as break out common dataRoland Veloz2018-02-283-182/+232
| | | | | | | | | | | | | | | | | | | | | | This commit takes care of two stories since they are related to each other. First, moved all common data (structs, enums, constant literals) from file sbe_update.H into sbe_common.H. This will allow content to be shared between FSP and HB with out having to have simultaneous updates. Secondly, an update will be forced if bit 3 of the SB keyword flags dictates it, regardless of whether an update is recommended or not by other logic. Change-Id: I3bd3c5cdd648309637bdf657db8f0935670c7d12 RTC:181140 RTC:181141 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54408 Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Brian E. Bakke <bbakke@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Story 179465 - Smarter HBBL id handling ...Brian Bakke2017-11-191-0/+16
| | | | | | | | | | | | | | | to avoid constant SBE updates Change-Id: Id02c7eb95a8e83274968477514130512ee553968 RTC: 179465 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49748 Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Use readSeeprom PSU chipop to get SBE seeprom image versionChristian Geddes2017-11-171-2/+21
| | | | | | | | | | | | | | | | | | | | During an SBE update we were getting I2C collisions when trying to access pnor on the "running" or "active" side of the seeprom. This commit adds support for a PSU chipOp called "readSeeprom" which allows the host to make a request to the SBE to copy a specified chunk of pnor out to a buffer in memory which the host can access. This commit also uses this chipOp in place of the I2C read during the SBE update of the active seeprom side. Change-Id: I4b639ebe6090dcc0bdbb42f13fcb12c23260a8b4 RTC: 180959 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48408 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* SBE update plan for OpenPOWERMarty Gloff2017-08-092-0/+17
| | | | | | | | | | | | | | | | | | | | We need to have a new way to handle the SBE update flow for OpenPOWER. Update the SBE code one side at a time to avoid a scenario where a bad code load bricks the system. Start by loading side 0 (primary), then re-IPL, and finally load side 1 (backup). A new config flag is used, SBE_UPDATE_CONSECUTIVE. Change-Id: Icf18ebec173c2f42fe200fb9cd547b9ebc580acc RTC: 176755 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43893 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com> Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Remove SBEC pnor partition from p9 codeStephen Cprek2017-07-241-4/+3
| | | | | | | | | | | | | Change-Id: I13e79a6542353e42ac809cc60295947dfb1acb96 RTC: 163810 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43048 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Block SBE updates during mpiplDzuy Nguyen2017-07-181-0/+1
| | | | | | | | | | | | | Change-Id: Ie59495404ec27d6be865063fc930e895340d9be2 RTC: 169683 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42853 Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Log build level for SBE and HCODE customizationMarty Gloff2017-07-171-2/+13
| | | | | | | | | | | | | | | | | | Extract build information from the XIP header for the SBE and HCODE images. Trace the information. Also use it as FFDC for related error logs. Save the SBE build information in the SB keyword of MVPD. Change-Id: I600a71ae6cbf342643261da14f6b3b2e6bf3cbf1 RTC: 168827 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42951 Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* xip_customize: GPTR/overlays stage 1 supportClaus Michael Olsen2017-07-141-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated to poll Nimbus DD level and whether there's support for overlays in the XIP interface. Further, updated to add three extra args in xip_customize API, two of which are to support a third ring work buffer for the overlays handling. This has necessitated making changes to hcode_image_build (HIB) API as well. Note that the calling codes of xip_customize and HIB need to be updated to supply the additional args in their APIs. Note that this code stage 1 will work for Nimbus DD2 with Gptr rings in Mvpd, and no Gptr rings in the HW image. It will, however, not work if there's content in .overlays or if there's Gptr rings already in the .rings section. Thus, the stage 1 code here will work with a DD2 image (i.e., that does NOT have Gptr rings in .rings in HW image) as long as noone has put any real Gptr initfiles in for processing (which would result in ring content in .overlays). We must ensure that the stage 2 code of xip_customize gets merged on the HB side to enable processing of .overlays content before we actually add any Gptr initfiles for the .overlays section into EKB. Change-Id: I3d6ab8a9add239c92819613dcae21ef5faf0a1c5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40591 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sumit Kumar <sumit_kumar@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40898 Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Tested-by: Dean Sanner <dsanner@us.ibm.com>
* Add in calls to p9_get_sbe_msg_register and handler functions (4/4)Elizabeth Liner2017-06-291-0/+709
| | | | | | | | | | | | | | | This commit adds in an additional hwp needed for the SBE conditions handling, p9_get_sbe_msg_register. This HWP pulls out the SBE register and determines if it got to runtime or not. From there there are handler functions that decide what to do next. Change-Id: I0e17b345bb983ed6373ec36ea2a6eb9b5e1bf3f1 RTC:173809 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41503 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Verify the correct HW Key Hash is used in Customized SBE ImageMike Baiocchi2017-06-112-5/+18
| | | | | | | | | | | | | | | | | | This commit keeps track of what HW Key Hash is added to HBBL before customizing the SBE Image and then checks that this HW Key Hash is found in the customized SBE Image. It did this by updating getHwKeyHashFromSbeImage() to possibly read the HW Key Hash from system memory along with its default behavior of reading it from a SBE Seeprom. Change-Id: I0139fb959102de74b12874f30e7d2ec0bf918e3f RTC:175330 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41453 Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Read the HW Key Hash from a Processor's SBE SeepromMike Baiocchi2017-04-032-1/+22
| | | | | | | | | | | | | | | | This commit adds an interface to read the HW Key Hash located in the HBBL section of each Processor's two SBE Seeproms. Change-Id: I906434269746c296c646f7b0594575c58b145294 RTC: 167585 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38465 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Fix IPL: zzfp247 SBE update failMarty Gloff2017-03-221-6/+3
| | | | | | | | | | | | | | | Base SBE boot side for slave processor off SB keyword in MVPD rather than off boot side used by master processor. Change-Id: I3165d536f104c0d1f394de93a390bd0f722e4777 CQ: SW383676 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38152 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add SecureROM version info and Change SBE update to use max HBBL sizeStephen Cprek2017-03-012-17/+0
| | | | | | | | | | | | | | | The HBBL also contains the securerom code and hw keys' hash for verification purposes. So looking for the end of the HBBL code leaves out those sections Change-Id: I73a1b5c50e3a5b3f642ca569b90e79dbe4c4ba1e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35979 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Remove deprecated SBE side resolutionDan Crowell2017-02-271-10/+2
| | | | | | | | | | | | | | | | The HB Bootloader now owns the responsibility of selecting the appropriate side of PNOR to use when loading the HBB image. There is no longer a HBB pointer in the SBE image itself. This commit removes the code that dealt with that support. There is also some cleaning up of a few other related functions. Change-Id: I35bfccb3590f81867d8222333cb4be66718828fa Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36358 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Enforce single-threaded rule for Hardware ProceduresDan Crowell2017-01-231-1/+4
| | | | | | | | | | | | | | | | | | | | Because we aren't using read thread-local storage for the FAPI variables (opmode, piberrmask, current_err) we need to ensure that we never have multiple HWPs running at the same time. The external interface that we use in all cases is FAPI_INVOKE_HWP so that is where a mutex is placed. This change also uncovered a couple bugs in how we were executing some non-fapi HWPs in the SBE update code so I fixed those as well. Change-Id: Ie8817da62dd4e6bc9ed3ac2debf126f6d05c2b23 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34518 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* SBE Update Changes and HacksMarty Gloff2017-01-201-36/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While verifying SBE boot from both SEEPROM sides, several changes were identified and a hack was created to fix a HWP bug. 1) Replace use of SBE::setNestFreqAttributes with use of TARGETING::setFrequencyAttributes. 2) Update TARGETING::setFrequencyAttributes to not pass in i2cBusDiv, but instead to calculate this value. 3) Update TARGETING::setFrequencyAttributes to find the PLL bucket for the new nest frequency. 4) Add a call to TARGETING::setFrequencyAttributes in call_mss_freq. 5) Remove finding PLL bucket from call_host_voltage_config. It is not required since TARGETING::setFrequencyAttributes is being called. 6) Remove SBE::setNestFreqAttributes and SBE::checkSeepromNestFreq from sbe_update.C as they are not being used. 7) Remove various variables, fields, and parameters because they are unneeded after work above. 8) Add hack to set SBE boot side indicator back to primary side before doShutdown in sbe_update.C. 9) Add syncAllAttributesToFsp call before doShutdown in sbe_update.C. 10) Add attributes for the nest PLL frequency data. Change-Id: I97ea6386eb583a71c0dbec70adb9977e749dbfd3 RTC:152404 CMVC-Prereq:1014451 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34735 Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com> Reviewed-by: Marshall J. Wilks <mjwilks@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Select boot seeprom for slave processorsMarty Gloff2016-12-221-0/+12
| | | | | | | | | | | | | | Add a function to set the boot SEEPROM for the target processor based off the setting for the master processor. Change-Id: Ie39ca011952ea5cf10a8b752268116265cc4fabd RTC:162326 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34022 Reviewed-by: Matt Derksen <v2cibmd@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Changes to get slave SBE workingDan Crowell2016-10-261-0/+7
| | | | | | | | | | | | | | Add flag to actually start SBE FW Set ATTR_NEST_PLL_BUCKET Increase timeout for SBE start Setup all required freq attributes before setting up SBE Change-Id: Ic3b7c8c6b482787b8c37b2b5b04a8344213119cf Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31682 Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Read MC Sync Mode from SBEDan Crowell2016-10-071-0/+9
| | | | | | | | | | | | | | | | The SBE boots the system into a specific mode for MC/Nest running synchronously. Hostboot needs to detect the mode that we booted in and set our live copy based on that since it may be out of sync from what our attribute might say. Change-Id: I4d7839eb4dd7e40fa045006abfdedc35b16f956c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30811 Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Interface to determine what nest freq the system booted withAndres Lugo-Reyes2016-09-201-2/+8
| | | | | | | | | | | Change-Id: Idea9e3ae8d08052e960c00c225522bbe8da3ea5e RTC:157890 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29505 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Insert bootloader image into SBE SEEPROMMarty Gloff2016-09-142-4/+18
| | | | | | | | | | | | | | 4) Bootloader-related changes associated with Story 138226: Changes for P9 SBE. Change-Id: If9788c3bb2b56fbbaf4f668a1e153da79ad1757f RTC: 139757 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28276 Reviewed-by: Matt Derksen <v2cibmd@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Implement XIP Customization for Core InformationMarty Gloff2016-09-071-1/+1
| | | | | | | | | | | | | | | | | Loop to run xip_customize on the pnor image for each core must still be implemented. This commit also enables the call of p9_xip_customize only when not in the FSP environment. Change-Id: Iafc04e2ba05def7794315f9178b55dd2f2de35e4 RTC:158044 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28098 Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Matt Derksen <v2cibmd@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Changes for P9 SBE - Enable/Remove Istep calls/processingMarty Gloff2016-09-031-1/+5
| | | | | | | | | | | | | | | | | | | | | | 3) Clean up TODO's in isteps 08, 09, and 10 In istep08 enable resolveProcessorSbeSeeproms call from call_host_slave_sbe_config.C and remove findSBEInPnor call and other processing from call_proc_check_slave_sbe_seeprom_complete.C. In istep09 remove updateProcessorSbeSeeproms call and nest frequency processing from call_fabric_erepair.C. In istep10 enable updateProcessorSbeSeeproms call from call_host_slave_sbe_update.C and enable loop to set use of xscom in call_proc_build_smp.C. Change-Id: I79237f530738e3088d1b3aedafdc6ad1139d21a8 RTC: 156597 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26801 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Function to set Nest Frequency based off DIMM memory capabilityaalugore2015-09-181-0/+16
| | | | | | | | | | | | | | | | | -Needed for 32x32GB DIMM support -Finds max capable frequency of system and all present DIMMs and deconfigures any DIMM that cannot run at desired frequency -If necessary, Sets Nest Freq and triggers SBE update Change-Id: I9bba92f55f1b67ff4a15d79113f19d39272ec72d RTC:122884 Depends-on:I1dca7196cd02a2704a238665b73b522c9e103936 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/17829 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* SBE Update Support for Adjusted Nest FrequencyAndres Lugo-Reyes2015-09-181-1/+18
| | | | | | | | | | | | | | | | This commit adds a check in istep 8.1 to see if the SBE Seeproms are programmed with the same NEST_FREQ_MHZ attribute value that the system is currently running at. If necessary, it will update the SBE Seeproms in this step which might result in a re-IPL. Change-Id: I1dca7196cd02a2704a238665b73b522c9e103936 RTC:133406 Depends-on:I9bba92f55f1b67ff4a15d79113f19d39272ec72d Backport: release-fips840 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20229 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* GOLDEN SBE Update Support - Reconcile SBE images and PNOR sidesMike Baiocchi2015-03-012-2/+21
| | | | | | | | | | | | | | | | This code adds a new function at istep 6 to reconcile the two SBE Seeproms with the PNOR side and mode (ie, 2-sided, golden, etc). It also updates what happens in istep 9 in SBE_UPDATE_INDEPENDENT mode. Change-Id: If71ca52338a179b8cf38cfa336d9790737844715 RTC: 120734 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/15790 Tested-by: Jenkins Server Reviewed-by: PRACHI GUPTA <pragupta@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Change copyright prolog for all files to Apache.Patrick Williams2014-05-212-21/+21
| | | | | | | Change-Id: I5664587b4f889099290ef50d50fa9ce5e580e1eb Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11167 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* SBE Update ensures all processors have Master Processor's SBE LevelMike Baiocchi2014-05-211-0/+4
| | | | | | | | | | | | | | | A function was added at the very end of the SBE Update procedure to ensure that any processor continuing with the IPL has the same SBE Image level as the Master Processor. Any processor that had an error during the update process is also deconfigured since we can't trust its SBE Image level. Change-Id: Id6dd46ca71ad97ca9f0e6ba30110ea400102a3b4 RTC: 101539 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/10868 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* SBE Update won't run in istep IPLMike Baiocchi2014-01-291-2/+4
| | | | | | | | | | | | | | | SBE Update code will check if system is in istep mode and that there is a FSP present. If both are true, then SBE Update will be skipped. Also, informational error logs are created for each successfully updated SBE Seeprom. Change-Id: Ibfd2209d85704c757fde95334b350c1e2b6282c3 RTC: 89503 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/8431 Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: Brian H. Horton <brianh@linux.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Enable Hostboot SBE UpdatesMike Baiocchi2014-01-091-0/+2
| | | | | | | | | | | | | Along with enabling hostboot SBE Updates, this commit also improves the interaction with the p8_xip_customize() HW procedure. Change-Id: Iea1eda7581cba8f9569594678f0cb0b9abb7c742 RTC: 89503 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/7806 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Restart IPL after SBE UpdateMike Baiocchi2013-12-091-0/+2
| | | | | | | | | | | | | | | Along with some SBE Update improvements, this commit adds additional code to re-IPL the system after an SBE Update has taken place. NOTE: Full SBE Update code path to be enabled with RTC 89503. Change-Id: I6beaee026d3fc6aaa76bfc7ca387d6765754f0c3 RTC: 47033 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/6986 Tested-by: Jenkins Server Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Initial Support for Updating SBE SEEPROMMike Baiocchi2013-10-282-0/+160
This initial commit will be used to create the new SBE directories and files. It also supports the usr functions to find and copy SBE PNOR images. NOTE: It will not enable Updating SBE SEEPROMs in the IPL. Change-Id: I3f545a134493c7595ce50fd885478bbe606de472 RTC: 47032 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/6311 Tested-by: Jenkins Server Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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