| Commit message (Collapse) | Author | Age | Files | Lines |
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Added error log user detail sections into several error
paths of FSI deveice driver functions. These sections added
targets and registers to the error log.
Change-Id: I37622381ab0dd48454a9810233cdb11d725c5ed6
RTC: 44490
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3305
Tested-by: Jenkins Server
Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Changing the presence detect logic for the chips to look at VPD
in addition to the FSI presence. Creates errors if they don't
agree, except in VPO where FSI presence detection is busted.
Change-Id: I17246413abad5c8cb78a9166606f666bb860c081
RTC: 44075
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1277
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Task 4086
If the powerbus is alive we will use the remote master's OPB logic
directly instead of using the master proc's logic and cascading
through the MFSI port.
Added a target-specific mutex to handle concurrency issues.
Note - the new code path cannot be tested until XSCOM is completed
with Story 4382
I also modified some error handling to take care of errors exposed
by the fsipres testcase.
Verified on SALERNO and 2-proc VENICE models.
Change-Id: If48ddde60cef819ff6b921e00bdbab5027830be4
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/569
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: I282a764fbfb81cf13cc9d41ee275bafff478d20e
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/519
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com>
Reviewed-by: Terry J. Opie <opiet@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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RTC Story 3792
- Added 7 more Venice targets and 7 more Centaur targets to the
simics_VENICE.system.xml to match the latest simics config
Note: remove Centaurs are currently disabled due to SW107421
- Modified testcases to be more tolerant of system config differences
- Changes to initialization flow to be more tolerant of missing
chips
- Expanded the size of the HB_DATA section of PNOR to hold the
additional targets (up to 128KB space now, actual is 36KB)
Change-Id: Ic92708ccb147fb18bf992ef3ac318a287d32fafe
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/445
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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There are a group of attributes defined for FSI now.
-ATTR_FSI_MASTER_CHIP
-ATTR_FSI_MASTER_TYPE
-ATTR_FSI_MASTER_PORT
-ATTR_FSI_SLAVE_CASCADE
-ATTR_FSI_OPTION_FLAGS
Also includes work for Story 3996. The attributes are now broken
into 3 distinct pieces:
- attribute_types.xml : defines hostboot attributes
- target_types.xml : defines different types of targets
- XXX.system.xml : system-specific information, equivalent to what
we'll get from system workbook
These are then used to generic system-specific binaries, currently
for 3 platforms:
- simics_SALERNO_targeting.bin
- simics_VENICE_targeting.bin
- vbu_targeting.bin
Change-Id: I2bf920cc62cceb761ab44a07df433da44249d0e0
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/426
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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This code will initialize the FSI hardware and allow access
to remote slaves.
Note - current code is hardcoded to using the MFSI-0 port on the
master processor wrapped back into its own CFAM.
Note2 - One testcase is disabled pending integration of required
fixes to the simics models.
Contains work for
- Task 3830 : FSI Master Regs
- Task 3831 : FSI Slave Regs
Change-Id: I8dd5f0e03cf083e35cf8241db22ad6d76ba85fac
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/359
Tested-by: Jenkins Server
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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-Initial work for FSI Device Driver (Story 3334)
-Read/Write interface (Story 3550)
Code is capable of basic read and write operations provided that the
Simics models are updated
Note: contains early work for FSI Initialization that should be ignored for now
Change-Id: I08e795422de127b62c2d1629d7a4e0f12b21e348
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/287
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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