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* TOR space reductionsMartin Peschke2017-01-3013-1104/+1380
* p9_tod_save_config L1 and L2CHRISTINA L. GRAVES2017-01-303-0/+201
* Remove action bit settings for HCA from p9_chiplet_scominit.Ben Gass2017-01-271-26/+0
* Adding in a comment to p9_tod_move_tod_to_tb to explain that 0x20 isCHRISTINA L. GRAVES2017-01-271-1/+2
* L3 work for volt and freq_systemsJacob Harvey2017-01-2511-175/+255
* Implement BC attributes and make eff_dimm classJacob Harvey2017-01-2512-5081/+5689
* FBC updates for HW383616, HW384245Joe McGill2017-01-245-21/+129
* Adding skip group dials for cache when chip=groupLuke Murray2017-01-241-0/+41
* Adding chip_ec_feature attributes for dd2 buildBen Gass2017-01-244-11/+1323
* added refresh monitoring inits, fixes refresh overrun issueShelton Leung2017-01-242-0/+12
* rdtag_dly formulas based on PHY delaysShelton Leung2017-01-242-121/+52
* PM: Suppressing TOR Traces by using debug level 0.Prem Shanker Jha2017-01-241-7/+7
* Fixed periodic cal bug causing data failsStephen Glancy2017-01-241-1/+3
* Adding dial to INT scom inits for HW395947Jenny Huynh2017-01-241-2/+9
* PM: Bug Fix pertaining to SCOM Restore Entry for NCU_DARN_RNG_BARPrem Shanker Jha2017-01-241-13/+21
* Add structure and read of MCBIST compare test resultsLouis Stermole2017-01-242-1/+322
* Change MCBIST 1R work around to actually check the pause bitsBrian Silver2017-01-241-2/+9
* p9_pm_pfet_init: redo log2 function to fix delay settingsGreg Still2017-01-241-90/+91
* Added Quad Power Management Mode Register Clear for Quad Power HwpRaja Das2017-01-231-1/+10
* Updating VPD XML descriptionsJacob Harvey2017-01-202-28/+46
* Modify eff_config to take a flag to only set SPD attributesAndre Marin2017-01-202-12/+29
* WOF Enablement in PGPERahul Batra2017-01-192-17/+40
* p9_pm_stop_gpe_init: added a checkAmit Kumar2017-01-192-2/+25
* Add RDIMM raw card reference B2 and unit testAndre Marin2017-01-192-3/+28
* add SS PLL settings to support 94 MHz PCI operationJoe McGill2017-01-191-0/+18
* Fix PM procedure problems found during hardware bringupCorey Swenson2017-01-192-8/+6
* configure FBC pump mode in SBEJoe McGill2017-01-1810-242/+69
* INT FIR updatesJoe McGill2017-01-181-9/+9
* MCD FIR updatesJoe McGill2017-01-181-3/+3
* CXA FIR updatesJoe McGill2017-01-171-7/+7
* VAS FIR updatesJoe McGill2017-01-171-7/+7
* NX FIR updatesJoe McGill2017-01-171-12/+12
* PCI FIR initialization updatesJoe McGill2017-01-172-77/+91
* p9_mss_attr_update -- support CRP Lx keyword v2Joe McGill2017-01-171-3/+5
* Set the quad stop state on non master chipsDean Sanner2017-01-171-1/+17
* FIR updates -- pervasive/core/PPEJoe McGill2017-01-162-47/+75
* PSI FIR updatesJoe McGill2017-01-161-5/+5
* p9_chiplet_scominit -- set FBC IOE/IOO DL TL FIR programming, mask HCA FIRsJoe McGill2017-01-164-38/+97
* NPU FIR updatesJoe McGill2017-01-161-9/+8
* Move SEQ ODT Write Configuration from draminit_training to scominitAndre Marin2017-01-162-9/+7
* Changing sync miss count max to 2 instead of 1CHRISTINA L. GRAVES2017-01-162-4/+8
* p9_setup_bars -- skip NPU BAR inits when NPU region is partial goodJoe McGill2017-01-161-3/+8
* HW397255 Sync Enablement workaroundThi Tran2017-01-161-92/+151
* PM: Fixed placement issue associated with core repair rings in HOMER.Prem Shanker Jha2017-01-161-5/+8
* p9_getecid -- set PCIE DD1.0x workaround attributesJoe McGill2017-01-154-0/+89
* p9_pcie_scominit procedure update to addresss PHY issuesRick Mata Jr2017-01-144-86/+300
* default PBIEQ settings to safe modeJoe McGill2017-01-141-1/+5
* Add in empty eff_dimm files for mirroring purposesJacob Harvey2017-01-132-0/+48
* STOP: Set chiplet ids in sgpe and cmeYue Du2017-01-132-3/+73
* Change mss::pos for DIMM to leverage FAPI_POSBrian Silver2017-01-131-31/+30
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