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* p9_sbe_npll_setup: Level 3Joachim Fenkes2017-08-201-0/+56
* L3 Update - p9_l2/l3_flush.CThi Tran2017-08-202-15/+28
* Removed unnecessary FFDCSachin Gupta2017-08-201-2/+0
* p9_sbe_check_master_stop15: Level 3Joachim Fenkes2017-08-201-13/+21
* Optimized PPE FFDC collection frameworkAmit Tendolkar2017-08-201-0/+25
* suspend hwp changes and additional ffdcAdam Hale2017-08-201-2/+17
* Istep4: procedures upgrade to level3Yue Du2017-08-205-81/+312
* Dummy commit to enable optimized ppe ffdc collection on SBEAmit Tendolkar2017-08-201-0/+35
* p9_sbe_select_ex: add fused core booting supportGreg Still2017-08-201-9/+54
* L3 update -- p9_suspend_ioThi Tran2017-08-201-2/+2
* Propagate "fused_core" IPL option into PU chipJoachim Fenkes2017-08-201-0/+5
* L3 updates -- p9_sbe_mcs_setup, p9_revert_sbe_mcs_setupJoe McGill2017-08-201-2/+16
* p9_fastarray: Level 3Joachim Fenkes2017-08-201-0/+165
* Fix generation of set_sbe_error.H by removing redundant targetMatt K. Light2017-08-201-2/+0
* p9_sbe_tp_switch_gears, p9_sbe_gear_switcher: Level 3Joachim Fenkes2017-08-202-19/+92
* L3 update -- p9_sbe_fabricinitJoe McGill2017-08-201-5/+55
* L3 update -- p9_sbe_scominitJoe McGill2017-08-201-6/+20
* Added workaround for INT unit for DD1CHRISTINA L. GRAVES2017-08-201-8/+16
* Workaround to fix issue where Powerbus loses track of EQs in DD1Raja Das2017-08-201-1/+7
* Added an empty file for p9_hcd_cache_initf error to be mirroredRaja Das2017-08-201-0/+30
* Hcode: add a new xml error fileYue Du2017-08-201-0/+37
* L2 p9_suspend_powmanCHRISTINA L. GRAVES2017-08-201-0/+39
* Adding in system checkstop if anything fails and removing PHB targetsCHRISTINA L. GRAVES2017-08-201-0/+12
* p9_sbe_check_master_stop15 fix for runningGreg Still2017-08-201-13/+4
* FFDC UpdatesAnusha Reddy Rangareddygari2017-08-203-44/+160
* Removing checkstop checksAnusha Reddy Rangareddygari2017-08-201-7/+0
* L2 for p9_sbe_check_quiesceCHRISTINA L. GRAVES2017-08-201-0/+199
* p9_suspend_io procedure with updates from review feedbackRicardo Mata2017-08-201-0/+74
* FAPI2 - Enable register ffdc supportRichard J. Knight2017-08-201-0/+3
* L2 HWP -- p9_setup_barsJoe McGill2017-08-201-0/+25
* p9_sbe_scominit_errors.xml -- add empty file to establish PPE mirrorJoe McGill2017-08-201-0/+27
* Add sbeError tag to all SBE related error xml filesRichard J. Knight2017-08-2013-0/+44
* Adding in writing to HRMOR for bootloaderCHRISTINA L. GRAVES2017-08-201-0/+11
* Level 2 HWP for p9_sbe_tp_chiplet_init3Anusha Reddy Rangareddygari2017-08-201-0/+17
* Level 2 HWP for p9_sbe_npll_setupAnusha Reddy Rangareddygari2017-08-201-3/+9
* Cache/Core: Istep4 procedure changes for model 9038 and aboveYue Du2017-08-203-4/+28
* Level 2 HWP for p9_sbe_nest_startclocks,p9_sbe_startclock_chipletsAnusha Reddy Rangareddygari2017-08-201-7/+1
* HWP's for p9_perv_sbe_cmn,p9_sbe_arrayinit,p9_sbe_tp_arrayinitAnusha Reddy Rangareddygari2017-08-202-14/+2
* HWP-CACHE/CORE:istep4 procedures updatesYue Du2017-08-201-0/+16
* p9_sbe_tp_switch_gears - error xml fileAnusha Reddy Rangareddygari2017-08-201-0/+41
* HWP-CORE/CACHE: Update Istep 4 procedures regressed on model 34Yue Du2017-08-203-4/+96
* p9_block_wakeup_intr Level 2Greg Still2017-08-201-0/+7
* p9_sbe_check_master_stop15 Level 2Greg Still2017-08-201-8/+27
* p9_sbe_select_ex Level 2Greg Still2017-08-201-5/+23
* p9_sbe_check_master_stop15 Level 1Greg Still2017-08-201-0/+48
* Level 2 HWP for p9_sbe_startclock_chipletsAnusha Reddy Rangareddygari2017-08-201-0/+37
* L1 and L2 for p9_l3_flush procedureCHRISTINA L. GRAVES2017-08-201-0/+62
* p9_sbe_select_ex Level 1Greg Still2017-08-201-0/+35
* Updates for p9_revert_sbe_mcs_setup, p9_sbe_mcs_setup (Level 2)Joe McGill2017-08-202-8/+2
* PPE-HWP: [Level 2] Cache/Core chiplet_reset/init/scan0+startclocksYue Du2017-08-203-0/+190
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