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| author | Greg Still <stillgs@us.ibm.com> | 2015-11-16 07:35:01 -0600 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-08-20 09:54:36 -0400 |
| commit | c3dffc9d2b55c18bb764e0bdc81f8e0cf9281ffd (patch) | |
| tree | 0300d5243c1a5e1a3cd8e1473a931e2faefffa95 /src/import/chips/p9/procedures/xml | |
| parent | 6170bd34072a9a6b07fb1b95b6a87f338f88a2a6 (diff) | |
| download | talos-hostboot-c3dffc9d2b55c18bb764e0bdc81f8e0cf9281ffd.tar.gz talos-hostboot-c3dffc9d2b55c18bb764e0bdc81f8e0cf9281ffd.zip | |
p9_sbe_select_ex Level 2
- SUET tested (this included updates to suet.scomdef)
- Awan unit (re)test (note yet through IPL script inclusion)
- Update Multicast Group assignment per HW/FW interlock
- Addressed review comments, including Round 2
- Changed to use of PERV targets only as ATTR_CHIP_UNIT_POS
of these are supported on the SBE
- Added support for ATTR_MASTER_CORE and ATTR_MASTER_EX where
core/EX numbers (not Pervasive chiplet numbers) of the boot
core and EX are stored
- Fix attribute conflict
Change-Id: I1a85e106547e7abe2413ac5aa419730ee172a811
Original-Change-Id: I5c52c4c378f40361bca84a5dbba5b28dd286380d
RTC: 141486
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22508
Tested-by: Jenkins Server
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44843
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/error_info/p9_sbe_select_ex_errors.xml | 28 |
1 files changed, 23 insertions, 5 deletions
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_select_ex_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_select_ex_errors.xml index 97e2b1bf7..52e7c663f 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_select_ex_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_select_ex_errors.xml @@ -22,14 +22,32 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> +<!-- This is an automatically generated file. --> +<!-- File: p9_sbe_tp_arrayinit_errors.xml. --> +<!-- Halt codes for p9_sbe_tp_arrayinit --> + <hwpErrors> <!-- ******************************************************************** --> <hwpError> - <rc>RC_SELECT_EX_NONE_FOUND</rc> - <description> - Procedure: p9_sbe_select_ex.C - Indicates the no EX element (single core) was found. - </description> + <rc>RC_SBE_SELECT_EX_NO_CORES</rc> + <description>No good cores were found in the Partial Good attribures</description> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_SELECT_EX_NO_EQS</rc> + <description>No good cache chiplets were found in the Partial Good attribures</description> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_SELECT_EX_CORE_EQ_CONFIG_ERROR</rc> + <description>Did not find the matching EQ for the first core</description> + <ffdc>CORE_NUM</ffdc> + <ffdc>EQ_NUM</ffdc> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_SELECT_EX_NO_CORE_AVAIL_ERROR</rc> + <description>No cores are configurable with current partial good and gard settings</description> </hwpError> <!-- ******************************************************************** --> </hwpErrors> |
