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path: root/src/import/chips/p9/procedures/hwp/memory
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* Implement L2 eff_config_thermal, bulk_pwr_throttleJacob Harvey2016-11-0115-317/+737
* Change bad bit processing to process bad bit attributesBrian Silver2016-10-316-101/+451
* Add magic port capabilties for DDR PHYBrian Silver2016-10-314-21/+138
* Fixed CL and timing bugs, unit test augmentationsStephen Glancy2016-10-3114-761/+1844
* Change ADR output registers for init during resetBrian Silver2016-10-301-2/+2
* Change parity error FIR clear from after MRS to beforeBrian Silver2016-10-301-3/+4
* Implement p9_mss_throttle_memJacob Harvey2016-10-283-17/+72
* Add mss throttle files L1Andre Marin2016-10-282-0/+109
* Started implementation of bulk_pwr_throttlesJacob Harvey2016-10-279-525/+632
* Modifying ATTRs for memory power thermalJacob Harvey2016-10-251-31/+46
* Fixed 1R WR DQS update issueStephen Glancy2016-10-251-1/+27
* Implement MRW attributes; dram_clks, db_util, 2n_modeBrian Silver2016-10-251-8/+5
* Fix p9_mss_utils_to_throttle, create throttles API, attribute cleanupAndre Marin2016-10-251-20/+39
* Fix throttle procedure & MSS attribute clean upAndre Marin2016-10-251-9/+10
* Add mss throttle files L1Andre Marin2016-10-251-0/+81
* Modifying ATTRs for memory power thermalJacob Harvey2016-10-243-19/+93
* Add mss throttle files L1Andre Marin2016-10-242-0/+110
* Add remaining DP16 duty cycle registersBrian Silver2016-10-211-1/+12
* Add ATTR_MSS_MRW_POWER_CONTROL_REQUESTEDJacob Harvey2016-10-201-2/+25
* Change DLL cal init for spare DP8 - don't calBrian Silver2016-10-191-12/+1
* Add disabled bit processing for DDR PHY initial calibrationBrian Silver2016-10-198-23/+430
* MCBIST additional test types and features for shmoosMcIlvain2016-10-185-22/+885
* Implemented mss_power_curve attr decoderJacob Harvey2016-10-182-0/+554
* Modifying ATTRs for memory power thermalJacob Harvey2016-10-182-2/+137
* Implement MRW attributes; dram_clks, db_util, 2n_modeBrian Silver2016-10-181-1/+1
* Fix p9_mss_utils_to_throttle, create throttles API, attribute cleanupAndre Marin2016-10-181-0/+71
* Change MCBIST DD1 workaround, don't change subtests unless checking rankBrian Silver2016-10-181-9/+17
* Added WR VREF latch files for HB compileStephen Glancy2016-10-182-0/+68
* Fix Galois symbol 7 in MSS ECCLouis Stermole2016-10-171-1/+1
* p9_pstate_paramter_block L2 commitSudheendra K Srivathsa2016-10-171-0/+21
* Add RCD parity, clear parity FIR before trainingBrian Silver2016-10-178-29/+139
* Changes to limit DLL cal on spare DP8, stop CSS before startingBrian Silver2016-10-169-144/+201
* Add empty files for training fir setupBrian Silver2016-10-162-0/+48
* Add FW/Cronus VPD integrationAndre Marin2016-10-131-85/+96
* Change CTLE processing to not be off-by-oneBrian Silver2016-10-131-41/+57
* Functions for Accessing SI Control RegistersChris Yan2016-10-132-17/+17
* Changes for PHY zctl, bb lock, force_mclk_lowBrian Silver2016-10-125-37/+114
* Implemented mss_power_curve attr decoderJacob Harvey2016-10-122-5/+56
* Change p9_mss_scrub to do a sf_write/sf_read on hardwareBrian Silver2016-10-121-4/+7
* Added mrw_refresh_rate, added power curve xmlJacob Harvey2016-10-111-8/+94
* Change phy_scominit to run from p9_mss_scominit stepBrian Silver2016-10-102-3/+3
* Fix incorrect RCWs settings for power-on DIMMAndre Marin2016-10-101-1/+1
* pervasive_attributes.xml -- add input refclock termination controlsJoe McGill2016-10-071-0/+40
* Add support for ATTR_MSS_VPD_MT_WINDAGE_RD_CTRBrian Silver2016-10-075-10/+110
* Added WR VREF workaround for error logicStephen Glancy2016-10-075-3/+114
* Added Shmoo Wrapper CapabilitiesBriana Foxworth2016-10-071-0/+5
* Fix dimm address mirroring to be based on SPD settingLouis Stermole2016-10-072-42/+291
* Change TEMP_REFRESH_MODE to default to disabledBrian Silver2016-10-071-1/+3
* L2 version - p9_sbe_sequence_drtmSantosh2016-10-051-0/+20
* Change polling loop count and initial cal calculationBrian Silver2016-10-052-32/+16
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