| Commit message (Expand) | Author | Age | Files | Lines |
* | Implement L2 eff_config_thermal, bulk_pwr_throttle | Jacob Harvey | 2016-11-01 | 15 | -317/+737 |
* | Change bad bit processing to process bad bit attributes | Brian Silver | 2016-10-31 | 6 | -101/+451 |
* | Add magic port capabilties for DDR PHY | Brian Silver | 2016-10-31 | 4 | -21/+138 |
* | Fixed CL and timing bugs, unit test augmentations | Stephen Glancy | 2016-10-31 | 14 | -761/+1844 |
* | Change ADR output registers for init during reset | Brian Silver | 2016-10-30 | 1 | -2/+2 |
* | Change parity error FIR clear from after MRS to before | Brian Silver | 2016-10-30 | 1 | -3/+4 |
* | Implement p9_mss_throttle_mem | Jacob Harvey | 2016-10-28 | 3 | -17/+72 |
* | Add mss throttle files L1 | Andre Marin | 2016-10-28 | 2 | -0/+109 |
* | Started implementation of bulk_pwr_throttles | Jacob Harvey | 2016-10-27 | 9 | -525/+632 |
* | Modifying ATTRs for memory power thermal | Jacob Harvey | 2016-10-25 | 1 | -31/+46 |
* | Fixed 1R WR DQS update issue | Stephen Glancy | 2016-10-25 | 1 | -1/+27 |
* | Implement MRW attributes; dram_clks, db_util, 2n_mode | Brian Silver | 2016-10-25 | 1 | -8/+5 |
* | Fix p9_mss_utils_to_throttle, create throttles API, attribute cleanup | Andre Marin | 2016-10-25 | 1 | -20/+39 |
* | Fix throttle procedure & MSS attribute clean up | Andre Marin | 2016-10-25 | 1 | -9/+10 |
* | Add mss throttle files L1 | Andre Marin | 2016-10-25 | 1 | -0/+81 |
* | Modifying ATTRs for memory power thermal | Jacob Harvey | 2016-10-24 | 3 | -19/+93 |
* | Add mss throttle files L1 | Andre Marin | 2016-10-24 | 2 | -0/+110 |
* | Add remaining DP16 duty cycle registers | Brian Silver | 2016-10-21 | 1 | -1/+12 |
* | Add ATTR_MSS_MRW_POWER_CONTROL_REQUESTED | Jacob Harvey | 2016-10-20 | 1 | -2/+25 |
* | Change DLL cal init for spare DP8 - don't cal | Brian Silver | 2016-10-19 | 1 | -12/+1 |
* | Add disabled bit processing for DDR PHY initial calibration | Brian Silver | 2016-10-19 | 8 | -23/+430 |
* | MCBIST additional test types and features for shmoos | McIlvain | 2016-10-18 | 5 | -22/+885 |
* | Implemented mss_power_curve attr decoder | Jacob Harvey | 2016-10-18 | 2 | -0/+554 |
* | Modifying ATTRs for memory power thermal | Jacob Harvey | 2016-10-18 | 2 | -2/+137 |
* | Implement MRW attributes; dram_clks, db_util, 2n_mode | Brian Silver | 2016-10-18 | 1 | -1/+1 |
* | Fix p9_mss_utils_to_throttle, create throttles API, attribute cleanup | Andre Marin | 2016-10-18 | 1 | -0/+71 |
* | Change MCBIST DD1 workaround, don't change subtests unless checking rank | Brian Silver | 2016-10-18 | 1 | -9/+17 |
* | Added WR VREF latch files for HB compile | Stephen Glancy | 2016-10-18 | 2 | -0/+68 |
* | Fix Galois symbol 7 in MSS ECC | Louis Stermole | 2016-10-17 | 1 | -1/+1 |
* | p9_pstate_paramter_block L2 commit | Sudheendra K Srivathsa | 2016-10-17 | 1 | -0/+21 |
* | Add RCD parity, clear parity FIR before training | Brian Silver | 2016-10-17 | 8 | -29/+139 |
* | Changes to limit DLL cal on spare DP8, stop CSS before starting | Brian Silver | 2016-10-16 | 9 | -144/+201 |
* | Add empty files for training fir setup | Brian Silver | 2016-10-16 | 2 | -0/+48 |
* | Add FW/Cronus VPD integration | Andre Marin | 2016-10-13 | 1 | -85/+96 |
* | Change CTLE processing to not be off-by-one | Brian Silver | 2016-10-13 | 1 | -41/+57 |
* | Functions for Accessing SI Control Registers | Chris Yan | 2016-10-13 | 2 | -17/+17 |
* | Changes for PHY zctl, bb lock, force_mclk_low | Brian Silver | 2016-10-12 | 5 | -37/+114 |
* | Implemented mss_power_curve attr decoder | Jacob Harvey | 2016-10-12 | 2 | -5/+56 |
* | Change p9_mss_scrub to do a sf_write/sf_read on hardware | Brian Silver | 2016-10-12 | 1 | -4/+7 |
* | Added mrw_refresh_rate, added power curve xml | Jacob Harvey | 2016-10-11 | 1 | -8/+94 |
* | Change phy_scominit to run from p9_mss_scominit step | Brian Silver | 2016-10-10 | 2 | -3/+3 |
* | Fix incorrect RCWs settings for power-on DIMM | Andre Marin | 2016-10-10 | 1 | -1/+1 |
* | pervasive_attributes.xml -- add input refclock termination controls | Joe McGill | 2016-10-07 | 1 | -0/+40 |
* | Add support for ATTR_MSS_VPD_MT_WINDAGE_RD_CTR | Brian Silver | 2016-10-07 | 5 | -10/+110 |
* | Added WR VREF workaround for error logic | Stephen Glancy | 2016-10-07 | 5 | -3/+114 |
* | Added Shmoo Wrapper Capabilities | Briana Foxworth | 2016-10-07 | 1 | -0/+5 |
* | Fix dimm address mirroring to be based on SPD setting | Louis Stermole | 2016-10-07 | 2 | -42/+291 |
* | Change TEMP_REFRESH_MODE to default to disabled | Brian Silver | 2016-10-07 | 1 | -1/+3 |
* | L2 version - p9_sbe_sequence_drtm | Santosh | 2016-10-05 | 1 | -0/+20 |
* | Change polling loop count and initial cal calculation | Brian Silver | 2016-10-05 | 2 | -32/+16 |