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path: root/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H
Commit message (Expand)AuthorAgeFilesLines
* Updates dramint training structureStephen Glancy2017-11-101-0/+15
* Update HPW Level for MSS API libraryAndre Marin2017-11-011-1/+1
* Implementing draminit_training_advJacob Harvey2017-08-291-2/+123
* L3 support for ddr_phy_reset, termination_controlJacob Harvey2017-07-191-1/+1
* Turn off A17 if not neededJacob Harvey2017-06-251-4/+15
* Added register reset functionality for DD2Stephen Glancy2017-06-071-13/+67
* Removes traits to mirror DD2 hardwareStephen Glancy2017-05-221-4/+0
* Add PHY sequencer refresh settings after draminitAndre Marin2017-05-121-0/+15
* Move scom API to share among controllersAndre Marin2017-03-181-1/+1
* Disable RTT_WR during WR_LEVEL cal step, and set equivalent terminationsLouis Stermole2017-03-151-1/+2
* Fixed MPR pattern bit-ordering bugStephen Glancy2017-02-131-4/+5
* Fixed register values for RD VREFStephen Glancy2017-02-111-6/+17
* Move SEQ ODT Write Configuration from draminit_training to scominitAndre Marin2017-01-161-2/+2
* Add settings for DDR 2N modeBrian Silver2016-12-141-2/+4
* Add RCD parity, clear parity FIR before trainingBrian Silver2016-10-171-1/+8
* Add SEQ timing parameters, DP16 RD Diag config 5 initsBrian Silver2016-09-141-0/+35
* Change SEQ timings, SEQ ODT, WC config and DQS polarityBrian Silver2016-09-121-0/+329
* Add empty files for PHY SEQ, workarounds for mirroringBrian Silver2016-09-061-0/+24
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