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seq.H
Commit message (
Expand
)
Author
Age
Files
Lines
*
Updates dramint training structure
Stephen Glancy
2017-11-10
1
-0
/
+15
*
Update HPW Level for MSS API library
Andre Marin
2017-11-01
1
-1
/
+1
*
Implementing draminit_training_adv
Jacob Harvey
2017-08-29
1
-2
/
+123
*
L3 support for ddr_phy_reset, termination_control
Jacob Harvey
2017-07-19
1
-1
/
+1
*
Turn off A17 if not needed
Jacob Harvey
2017-06-25
1
-4
/
+15
*
Added register reset functionality for DD2
Stephen Glancy
2017-06-07
1
-13
/
+67
*
Removes traits to mirror DD2 hardware
Stephen Glancy
2017-05-22
1
-4
/
+0
*
Add PHY sequencer refresh settings after draminit
Andre Marin
2017-05-12
1
-0
/
+15
*
Move scom API to share among controllers
Andre Marin
2017-03-18
1
-1
/
+1
*
Disable RTT_WR during WR_LEVEL cal step, and set equivalent terminations
Louis Stermole
2017-03-15
1
-1
/
+2
*
Fixed MPR pattern bit-ordering bug
Stephen Glancy
2017-02-13
1
-4
/
+5
*
Fixed register values for RD VREF
Stephen Glancy
2017-02-11
1
-6
/
+17
*
Move SEQ ODT Write Configuration from draminit_training to scominit
Andre Marin
2017-01-16
1
-2
/
+2
*
Add settings for DDR 2N mode
Brian Silver
2016-12-14
1
-2
/
+4
*
Add RCD parity, clear parity FIR before training
Brian Silver
2016-10-17
1
-1
/
+8
*
Add SEQ timing parameters, DP16 RD Diag config 5 inits
Brian Silver
2016-09-14
1
-0
/
+35
*
Change SEQ timings, SEQ ODT, WC config and DQS polarity
Brian Silver
2016-09-12
1
-0
/
+329
*
Add empty files for PHY SEQ, workarounds for mirroring
Brian Silver
2016-09-06
1
-0
/
+24