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| author | Brian Silver <bsilver@us.ibm.com> | 2016-12-08 13:18:12 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-12-14 10:23:32 -0500 |
| commit | c5f29463bc36f9e631559457400643965864a3ea (patch) | |
| tree | e47607e3a1a3fd7fd6a40a7bb40fbb1d11d10c6b /src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H | |
| parent | b4e35e636bedf9f8785a49708ffe5d68aed97971 (diff) | |
| download | talos-hostboot-c5f29463bc36f9e631559457400643965864a3ea.tar.gz talos-hostboot-c5f29463bc36f9e631559457400643965864a3ea.zip | |
Add settings for DDR 2N mode
Change-Id: I9b94efd61fb706ed2869098d2abca760562859f6
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33611
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33616
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H index 6b1dd6a25..115e977e4 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H @@ -39,6 +39,7 @@ #include <fapi2.H> #include <p9_mc_scom_addresses.H> #include <p9_mc_scom_addresses_fld.H> +#include <mss_attribute_accessors_manual.H> #include <lib/utils/scom.H> namespace mss @@ -111,6 +112,7 @@ class seqTraits<fapi2::TARGET_TYPE_MCA> TMRSC_CYCLES_LEN = MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TMRSC_CYCLES_LEN, DELAYED_PARITY = MCA_DDRPHY_SEQ_CONFIG0_P0_DELAYED_PAR, + TWO_N_MODE = MCA_DDRPHY_SEQ_CONFIG0_P0_TWO_CYCLE_ADDR_EN, }; }; @@ -323,10 +325,10 @@ fapi_try_exit: template< fapi2::TargetType T, typename TT = seqTraits<T> > inline fapi2::ReturnCode reset_config0( const fapi2::Target<T>& i_target ) { - // TK ATTR_VPD_DRAM_2N_MODE_ENABLED 49, 0b1, (def_2N_mode); # enable 2 cycle addr mode BRS - fapi2::buffer<uint64_t> l_data; + l_data.writeBit<TT::TWO_N_MODE>(mss::two_n_mode_helper(i_target)); + // DDR4 needs delayed partiy TK for DDR5/DDR3 ... l_data.setBit<TT::DELAYED_PARITY>(); FAPI_TRY( write_config0(i_target, l_data) ); |
