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path: root/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
Commit message (Expand)AuthorAgeFilesLines
* Implementing draminit_training_advJacob Harvey2017-08-291-0/+20
* L3 support for ddr_phy_reset, termination_controlJacob Harvey2017-07-191-19/+17
* Added register reset functionality for DD2Stephen Glancy2017-06-071-18/+85
* Removes traits to mirror DD2 hardwareStephen Glancy2017-05-221-6/+0
* Fixes RD VREF runtime calculationStephen Glancy2017-05-071-1/+3
* Fix up setup_cal and vref attrsJacob Harvey2017-04-171-1/+1
* Change accesses to IS_SIM to use mss accessorJacob Harvey2017-04-071-1/+1
* Fixed register values for RD VREFStephen Glancy2017-02-111-4/+4
* Enable read VREF calibrationBrian Silver2016-11-091-17/+41
* Change PHY to use GPO, RLO, WLO from VPDBrian Silver2016-09-081-3/+1
* Changes related to PHY register reviewBrian Silver2016-09-031-5/+3
* Fix eff_config, remove custom_dimmJacob Harvey2016-08-301-14/+3
* Update prologs of mirrored files to apache licenseStephen Cprek2016-08-051-8/+14
* Add eff_config functionality needed for RIT, fix cas_latency bug & attr filesAndre Marin2016-05-191-1/+1
* Change PHY PC, RC and DP16 register blocks to functional APIBrian Silver2016-05-041-338/+346
* Change include paths in memory/lib, testsBrian Silver2016-04-211-1/+1
* Change read control API to match desired design, add design docBrian Silver2016-04-011-2/+29
* Change RC_CONFIG2 for sim settings (BL8)Brian Silver2016-04-011-22/+23
* Fixed doxygen errors and typosJacob Harvey2016-04-011-35/+35
* Add PHY RC class, update setup cal for 2D wc/rcBrian Silver2016-04-011-0/+458
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