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authorJacob Harvey <jlharvey@us.ibm.com>2016-02-05 15:24:59 -0600
committerDaniel M. Crowell <dcrowell@us.ibm.com>2016-04-01 21:23:21 -0400
commitdba9ee6be396b29a072d9c5fc87ff346542c396e (patch)
treed3edf1b1207aad6dd8d7b9b93473067be1dd6e48 /src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
parenta08c13b301d1ee48a40474261711c6dc8174b108 (diff)
downloadtalos-hostboot-dba9ee6be396b29a072d9c5fc87ff346542c396e.tar.gz
talos-hostboot-dba9ee6be396b29a072d9c5fc87ff346542c396e.zip
Fixed doxygen errors and typos
Change-Id: I86313e4af81003744f0ab6c507d019a39c4a4992 Original-Change-Id: I94120c654c32b5c3513740ce8aae4b4cc632fc41 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24281 Tested-by: Jenkins Server Reviewed-by: Andre A. Marin <aamarin@us.ibm.com> Reviewed-by: Brian Silver <bsilver@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22767 Tested-by: FSP CI Jenkins Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H')
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H70
1 files changed, 35 insertions, 35 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
index 96ffa509a..243d3cbe4 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
@@ -18,7 +18,7 @@
/* IBM_PROLOG_END_TAG */
///
-/// @file read_cntrl
+/// @file read_cntrl.H
/// @brief Subroutines for the PHY read control registers
///
// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
@@ -48,7 +48,7 @@ template< fapi2::TargetType T >
class rcTraits;
///
-/// @class rcTraits<fapi2::TARGET_TYPE_MBA>
+/// @class rcTraits
/// @brief a collection of traits associated with the Centaur PHY
///
template<>
@@ -57,7 +57,7 @@ class rcTraits<fapi2::TARGET_TYPE_MBA>
};
///
-/// @class rcTraits<fapi2::TARGET_TYPE_MCA>
+/// @class rcTraits
/// @brief a collection of traits associated with the Nimbus PHY read control
///
template<>
@@ -123,8 +123,8 @@ class rcTraits<fapi2::TARGET_TYPE_MCA>
///
/// @class mss::rc
/// @brief Read Control reset config 0
-/// @tparam T, fapi2 Target Type - derived
-/// @tparam TT, traits type defaults to rcTraits<T>
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to rcTraits<T>
///
template< fapi2::TargetType T, typename TT = rcTraits<T> >
class rc
@@ -133,8 +133,8 @@ class rc
///
/// @brief Read RC_VREF_CONFIG0
- /// @param[in] i_target, the fapi2 target of the port
- /// @param[out] o_data, the value of the register
+ /// @param[in] i_target the fapi2 target of the port
+ /// @param[out] o_data the value of the register
/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
///
static inline fapi2::ReturnCode read_vref_config0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
@@ -146,8 +146,8 @@ class rc
///
/// @brief Write RC_VREF_CONFIG0
- /// @param[in] i_target, the fapi2 target of the port
- /// @param[in] i_data, the value of the register
+ /// @param[in] i_target the fapi2 target of the port
+ /// @param[in] i_data the value of the register
/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
///
static inline fapi2::ReturnCode write_vref_config0( const fapi2::Target<T>& i_target,
@@ -161,8 +161,8 @@ class rc
///
/// @brief Read RC_VREF_CONFIG1
- /// @param[in] i_target, the fapi2 target of the port
- /// @param[out] o_data, the value of the register
+ /// @param[in] i_target the fapi2 target of the port
+ /// @param[out] o_data the value of the register
/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
///
static inline fapi2::ReturnCode read_vref_config1( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
@@ -174,8 +174,8 @@ class rc
///
/// @brief Write RC_VREF_CONFIG1
- /// @param[in] i_target, the fapi2 target of the port
- /// @param[in] i_data, the value of the register
+ /// @param[in] i_target the fapi2 target of the port
+ /// @param[in] i_data the value of the register
/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
///
static inline fapi2::ReturnCode write_vref_config1( const fapi2::Target<T>& i_target,
@@ -190,8 +190,8 @@ class rc
///
/// @brief Read RC_CONFIG0
- /// @param[in] i_target, the fapi2 target of the port
- /// @param[out] o_data, the value of the register
+ /// @param[in] i_target the fapi2 target of the port
+ /// @param[out] o_data the value of the register
/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
///
static inline fapi2::ReturnCode read_config0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
@@ -203,8 +203,8 @@ class rc
///
/// @brief Write RC_CONFIG0
- /// @param[in] i_target, the fapi2 target of the port
- /// @param[in] i_data, the value of the register
+ /// @param[in] i_target the fapi2 target of the port
+ /// @param[in] i_data the value of the register
/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
///
static inline fapi2::ReturnCode write_config0( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
@@ -218,8 +218,8 @@ class rc
///
/// @brief Read RC_CONFIG1
- /// @param[in] i_target, the fapi2 target of the port
- /// @param[out] o_data, the value of the register
+ /// @param[in] i_target the fapi2 target of the port
+ /// @param[out] o_data the value of the register
/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
///
static inline fapi2::ReturnCode read_config1( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
@@ -231,8 +231,8 @@ class rc
///
/// @brief Write RC_CONFIG1
- /// @param[in] i_target, the fapi2 target of the port
- /// @param[in] i_data, the value of the register
+ /// @param[in] i_target the fapi2 target of the port
+ /// @param[in] i_data the value of the register
/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
///
static inline fapi2::ReturnCode write_config1( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
@@ -245,8 +245,8 @@ class rc
///
/// @brief Read RC_CONFIG2
- /// @param[in] i_target, the fapi2 target of the port
- /// @param[out] o_data, the value of the register
+ /// @param[in] i_target the fapi2 target of the port
+ /// @param[out] o_data the value of the register
/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
///
static inline fapi2::ReturnCode read_config2( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
@@ -258,8 +258,8 @@ class rc
///
/// @brief Write RC_CONFIG2
- /// @param[in] i_target, the fapi2 target of the port
- /// @param[in] i_data, the value of the register
+ /// @param[in] i_target the fapi2 target of the port
+ /// @param[in] i_data the value of the register
/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
///
static inline fapi2::ReturnCode write_config2( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
@@ -272,8 +272,8 @@ class rc
///
/// @brief Read RC_CONFIG3
- /// @param[in] i_target, the fapi2 target of the port
- /// @param[out] o_data, the value of the register
+ /// @param[in] i_target the fapi2 target of the port
+ /// @param[out] o_data the value of the register
/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
///
static inline fapi2::ReturnCode read_config3( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
@@ -285,8 +285,8 @@ class rc
///
/// @brief Write RC_CONFIG3
- /// @param[in] i_target, the fapi2 target of the port
- /// @param[in] i_data, the value of the register
+ /// @param[in] i_target the fapi2 target of the port
+ /// @param[in] i_data the value of the register
/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
///
static inline fapi2::ReturnCode write_config3( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
@@ -299,7 +299,7 @@ class rc
///
/// @brief reset rc_config0
- /// @param[in] i_target, fapi2 target of the port
+ /// @param[in] i_target fapi2 target of the port
/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
///
static inline fapi2::ReturnCode reset_config0( const fapi2::Target<T>& i_target )
@@ -322,7 +322,7 @@ class rc
///
/// @brief reset rc_config1
- /// @param[in] i_target, fapi2 target of the port
+ /// @param[in] i_target fapi2 target of the port
/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
///
static inline fapi2::ReturnCode reset_config1( const fapi2::Target<T>& i_target )
@@ -338,7 +338,7 @@ class rc
///
/// @brief reset rc_config2
- /// @param[in] i_target, fapi2 target of the port
+ /// @param[in] i_target fapi2 target of the port
/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
///
static inline fapi2::ReturnCode reset_config2( const fapi2::Target<T>& i_target )
@@ -374,7 +374,7 @@ class rc
///
/// @brief reset rc_config3
- /// @param[in] i_target, fapi2 target of the port
+ /// @param[in] i_target fapi2 target of the port
/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
///
static inline fapi2::ReturnCode reset_config3( const fapi2::Target<T>& i_target )
@@ -395,7 +395,7 @@ class rc
///
/// @brief reset rc_vref_config0
- /// @param[in] i_target, fapi2 target of the port
+ /// @param[in] i_target fapi2 target of the port
/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
///
static inline fapi2::ReturnCode reset_vref_config0( const fapi2::Target<T>& i_target )
@@ -431,7 +431,7 @@ class rc
///
/// @brief reset rc_vref_config1
- /// @param[in] i_target, fapi2 target of the port
+ /// @param[in] i_target fapi2 target of the port
/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok
///
static inline fapi2::ReturnCode reset_vref_config1( const fapi2::Target<T>& i_target )
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