summaryrefslogtreecommitdiffstats
path: root/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C
Commit message (Expand)AuthorAgeFilesLines
* Fixed the ccs port merge conflicts and added lab codeMatthew Hickman2019-05-131-3/+6
* Fixes LRDIMM command to command timingStephen Glancy2019-04-301-9/+7
* Fix duplicate symbol errors from DEFAULT_MC_TYPELouis Stermole2019-04-051-0/+1
* Adds some BCW safe delay for LRDIMMLi Meng2019-02-121-3/+5
* Fixes LRDIMM initialization attributes and timingsStephen Glancy2019-01-161-3/+4
* Fixes LRDIMM eff_config bugsStephen Glancy2018-11-051-3/+13
* Fixes BCW load bugsStephen Glancy2018-10-291-1/+1
* Adds per-Buffer addressability API for LRDIMMStephen Glancy2018-10-031-1/+1
* Adds insert function space helpers for LRDIMMStephen Glancy2018-09-271-44/+49
* Adds skeleton code for LRDIMMStephen Glancy2018-09-181-0/+2
* Moves conversions to be in the generic code spaceStephen Glancy2018-08-201-1/+1
* Fixes CKE levels during RCD initializationStephen Glancy2018-06-141-5/+8
* L3 draminit and mss_libJacob Harvey2017-07-261-11/+14
* Add pos API to be shared among controllers, move generic files to utilsAndre Marin2017-03-151-1/+1
* Add c_str generic API and update makefilesAndre Marin2017-02-101-2/+2
* Add BCW API for rank presence, buffer training, mrep timing and UTs.Andre Marin2017-01-031-29/+32
* Add common functionality between RCD and data buffer control word APIAndre Marin2016-12-071-9/+10
* Add DDR4 data buffer control words (BCWs) infrastructure & UT's.Andre Marin2016-12-061-0/+128
OpenPOWER on IntegriCloud