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bcw_load_ddr4.C
Commit message (
Expand
)
Author
Age
Files
Lines
*
Fixed the ccs port merge conflicts and added lab code
Matthew Hickman
2019-05-13
1
-3
/
+6
*
Fixes LRDIMM command to command timing
Stephen Glancy
2019-04-30
1
-9
/
+7
*
Fix duplicate symbol errors from DEFAULT_MC_TYPE
Louis Stermole
2019-04-05
1
-0
/
+1
*
Adds some BCW safe delay for LRDIMM
Li Meng
2019-02-12
1
-3
/
+5
*
Fixes LRDIMM initialization attributes and timings
Stephen Glancy
2019-01-16
1
-3
/
+4
*
Fixes LRDIMM eff_config bugs
Stephen Glancy
2018-11-05
1
-3
/
+13
*
Fixes BCW load bugs
Stephen Glancy
2018-10-29
1
-1
/
+1
*
Adds per-Buffer addressability API for LRDIMM
Stephen Glancy
2018-10-03
1
-1
/
+1
*
Adds insert function space helpers for LRDIMM
Stephen Glancy
2018-09-27
1
-44
/
+49
*
Adds skeleton code for LRDIMM
Stephen Glancy
2018-09-18
1
-0
/
+2
*
Moves conversions to be in the generic code space
Stephen Glancy
2018-08-20
1
-1
/
+1
*
Fixes CKE levels during RCD initialization
Stephen Glancy
2018-06-14
1
-5
/
+8
*
L3 draminit and mss_lib
Jacob Harvey
2017-07-26
1
-11
/
+14
*
Add pos API to be shared among controllers, move generic files to utils
Andre Marin
2017-03-15
1
-1
/
+1
*
Add c_str generic API and update makefiles
Andre Marin
2017-02-10
1
-2
/
+2
*
Add BCW API for rank presence, buffer training, mrep timing and UTs.
Andre Marin
2017-01-03
1
-29
/
+32
*
Add common functionality between RCD and data buffer control word API
Andre Marin
2016-12-07
1
-9
/
+10
*
Add DDR4 data buffer control words (BCWs) infrastructure & UT's.
Andre Marin
2016-12-06
1
-0
/
+128