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authorAndre Marin <aamarin@us.ibm.com>2016-12-01 03:56:02 -0600
committerDaniel M. Crowell <dcrowell@us.ibm.com>2016-12-07 13:55:06 -0500
commitd1fe32b96c0f48c266da346fa2d05676b3f1e4f8 (patch)
treed1ab3c66b7be16d9a4f813df15324953e3b9b0d8 /src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C
parent6d5be25917e0bd675147bf0cec03dc9da517d53a (diff)
downloadtalos-hostboot-d1fe32b96c0f48c266da346fa2d05676b3f1e4f8.tar.gz
talos-hostboot-d1fe32b96c0f48c266da346fa2d05676b3f1e4f8.zip
Add common functionality between RCD and data buffer control word API
Change-Id: I601f143578a796f30ad582c1581f73ebf413840c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33247 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33260 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C')
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C19
1 files changed, 10 insertions, 9 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C
index 3182654bf..379dee9ac 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C
@@ -42,6 +42,7 @@
#include <lib/ccs/ccs.H>
#include <lib/dimm/bcw_load_ddr4.H>
#include <lib/dimm/bcw_load.H>
+#include <lib/dimm/ddr4/control_word_ddr4.H>
#include <lib/mss_attribute_accessors.H>
using fapi2::TARGET_TYPE_MCBIST;
@@ -67,10 +68,10 @@ fapi2::ReturnCode bcw_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target
// Per DDR4BC01
uint64_t l_tDLLK = 0;
- FAPI_TRY( tdllk(i_target, l_tDLLK), "Failed to get tdllk for %s", mss::c_str(i_target) );
+ FAPI_TRY( tdllk(i_target, l_tDLLK), "Failed to get tDLLK for %s", mss::c_str(i_target) );
{
- static const std::vector< bcw_data > l_bcw_4bit_data =
+ static const std::vector< cw_data > l_bcw_4bit_data =
{
// function space #, bcw #, attribute accessor, timing delay
{ 0, 0, eff_dimm_ddr4_bc00, mss::tmrc() },
@@ -101,20 +102,20 @@ fapi2::ReturnCode bcw_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target
// We set the 4-bit buffer control words first (they live in function space 0
// hw is supposed to default to function space 0 but Just.In.Case.
FAPI_TRY( function_space_select<0>(i_target, io_inst) );
- FAPI_TRY( bcw_engine<BCW_4BIT>(i_target, l_bcw_4bit_data, io_inst) );
+ FAPI_TRY( control_word_engine<BCW_4BIT>(i_target, l_bcw_4bit_data, io_inst) );
// We set our 8-bit buffer control words but switch function space
// for control words that live in a different one
// (feels a little on the light side...)
FAPI_TRY( function_space_select<6>(i_target, io_inst) );
- FAPI_TRY( bcw_engine<BCW_8BIT>(i_target,
- bcw_data(6, 4, eff_dimm_ddr4_f6bc4x, mss::tmrc()),
- io_inst) );
+ FAPI_TRY( control_word_engine<BCW_8BIT>(i_target,
+ cw_data(6, 4, eff_dimm_ddr4_f6bc4x, mss::tmrc()),
+ io_inst) );
FAPI_TRY( function_space_select<5>(i_target, io_inst) );
- FAPI_TRY( bcw_engine<BCW_8BIT>(i_target,
- bcw_data(5, 6, eff_dimm_ddr4_f5bc6x, mss::tmrc()),
- io_inst) );
+ FAPI_TRY( control_word_engine<BCW_8BIT>(i_target,
+ cw_data(5, 6, eff_dimm_ddr4_f5bc6x, mss::tmrc()),
+ io_inst) );
// Its recommended to always return to the function space
// "pointer" back to 0 so we always know where we are starting from
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