diff options
Diffstat (limited to 'src/usr')
50 files changed, 6003 insertions, 2547 deletions
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_init.H b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_init.H index 7019b2cc4..dc92fcc4b 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_init.H +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_init.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -30,20 +30,21 @@ // *! OWNER NAME: Klaus P. Gungl Email: kgungl@de.ibm.com // *! // *! General Description: -// *! +// *! // *! include file for pba_init with constants, definitions, prototypes // *! //------------------------------------------------------------------------------ -// +// -#ifndef _PROC_PBAINIT_H_ -#define _PROC_PBAINIT_H_ +#ifndef _P8_PBAINIT_H_ +#define _P8_PBAINIT_H_ #include "p8_scom_addresses.H" typedef fapi::ReturnCode (*p8_pba_init_FP_t) (const fapi::Target& , uint64_t ); -// constant definitions for valid command scope. LIMIT is used by setup routine for plausibility checking. +// constant definitions for valid command scope. LIMIT is used by setup routine +// for plausibility checking. #define PBA_CMD_SCOPE_NODAL 0x00 #define PBA_CMD_SCOPE_GROUP 0x01 @@ -53,50 +54,64 @@ typedef fapi::ReturnCode (*p8_pba_init_FP_t) (const fapi::Target& , uint64_t ); #define PBA_CMD_SCOPE_FOREIGN1 0x05 #define PBA_CMD_SCOPE_LIMIT 0x06 -enum cmd_scope_t +enum cmd_scope_t { - CMD_SCOPE_NODAL, - CMD_SCOPE_GROUP, - CMD_SCOPE_SYSTEM, - CMD_SCOPE_RGP, - CMD_SCOPE_FOREIGN0, - CMD_SCOPE_FOREIGN1 + CMD_SCOPE_NODAL, + CMD_SCOPE_GROUP, + CMD_SCOPE_SYSTEM, + CMD_SCOPE_RGP, + CMD_SCOPE_FOREIGN0, + CMD_SCOPE_FOREIGN1 }; // enum cmd_scope_type {NODAL, GROUP, SYSTEM, RGP, FOREIGN0, FOREIGN1 }; -// addresses of PBA and PBABAR, actually a duplicate of definitions in "p8_scom_addresses.H" but here an array to be indexed. -const uint64_t PBA_BARs[4] = +// addresses of PBA and PBABAR, actually a duplicate of definitions in +// "p8_scom_addresses.H" but here an array to be indexed. +const uint64_t PBA_BARs[4] = { - PBA_BAR0_0x02013F00, - PBA_BAR1_0x02013F01, - PBA_BAR2_0x02013F02, + PBA_BAR0_0x02013F00, + PBA_BAR1_0x02013F01, + PBA_BAR2_0x02013F02, PBA_BAR3_0x02013F03 }; -const uint64_t PBA_BARMSKs[4] = +const uint64_t PBA_BARMSKs[4] = { - PBA_BARMSK0_0x02013F04, - PBA_BARMSK1_0x02013F05, - PBA_BARMSK2_0x02013F06, + PBA_BARMSK0_0x02013F04, + PBA_BARMSK1_0x02013F05, + PBA_BARMSK2_0x02013F06, PBA_BARMSK3_0x02013F07 }; -const uint64_t PBA_SLVCTLs[4] = +const uint64_t PBA_SLVCTLs[4] = +{ + PBA_SLVCTL0_0x00064004, + PBA_SLVCTL1_0x00064005, + PBA_SLVCTL2_0x00064006, + PBA_SLVCTL3_0x00064007 +}; + +const uint64_t PBA_SLVRESETs[4] = { - PBA_SLVCTL0_0x00064004, - PBA_SLVCTL1_0x00064005, - PBA_SLVCTL2_0x00064006, - PBA_SLVCTL3_0x00064007}; + 0x8000000000000000ull, + 0xA000000000000000ull, + 0xC000000000000000ull, + 0xE000000000000000ull +}; + +// Maximum number of Polls for PBA slave reset +#define MAX_PBA_RESET_POLLS 16 +#define PBA_RESET_POLL_DELAY 1 // in microseconds // bar mask is valid for bits 23 to 43, in a 64bit value this is -// 1 2 3 4 5 6 +// 1 2 3 4 5 6 // 0123456789012345678901234567890123456789012345678901234567890123 // 0000000000000000000000011111111111111111111100000000000000000000 // 0 0 0 0 0 1 F F F F F 0 0 0 0 0 // 0000000000000011111111111111111111111111111100000000000000000000 // 0 0 0 3 F F F F F F F 0 0 0 0 0 -// 0123456701234567 +// 0123456701234567 #define BAR_MASK_LIMIT 0x000001FFFFF00000ull #define BAR_ADDR_LIMIT 0x0003FFFFFFF00000ull @@ -140,7 +155,7 @@ typedef union { typedef struct { bar_reg_type bar_reg; - barmsk_reg_type barmsk_reg; + barmsk_reg_type barmsk_reg; } struct_pba_bar_init_type; @@ -151,7 +166,7 @@ typedef struct { unsigned short reserved_2:10; unsigned long addr:30; unsigned long reserved_3:20; - }; + }; struct struct_pba_barmsk{ unsigned long reserved_1:23; unsigned long mask:21; @@ -182,7 +197,7 @@ typedef union pbaxcfg_typ{ unsigned long reserved_2 :23 ; } fields; } pbaxcfg_t; - + @@ -190,11 +205,11 @@ typedef union pbaxcfg_typ{ // Function prototypes // ---------------------------------------------------------------------- -extern "C" +extern "C" { -fapi::ReturnCode -p8_pba_init (const fapi::Target& i_target, +fapi::ReturnCode +p8_pba_init (const fapi::Target& i_target, uint64_t mode ); @@ -203,6 +218,6 @@ p8_pba_init (const fapi::Target& i_target, -#endif // _PROC_PBAINITQ_H_ +#endif // _P8_PBAINITQ_H_ diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.C b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.C index 0bf8aca9d..a3eeb412d 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.C +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_pfet_init.C,v 1.2 2013/01/29 19:39:45 jmcgill Exp $ +// $Id: p8_pfet_init.C,v 1.3 2013/03/18 17:58:33 pchatnah Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pfet_init.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -266,7 +266,7 @@ pfet_init(const Target& i_target) if (l_rc) { FAPI_ERR("fapiGetAttribute ATTR_FREQ_PROC_REFCLOCK"); - FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFET_GET_ATTR); + // FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFET_GET_ATTR); break; } @@ -277,7 +277,7 @@ pfet_init(const Target& i_target) if (l_rc) { FAPI_ERR("fapiGetAttribute ATTR_PM_PFET_POWERUP_CORE_DELAY0"); - FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFET_GET_ATTR); + // FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFET_GET_ATTR); break; } @@ -288,7 +288,7 @@ pfet_init(const Target& i_target) if (l_rc) { FAPI_ERR("fapiGetAttribute ATTR_PM_PFET_POWERUP_CORE_DELAY1"); - FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFET_GET_ATTR); + // FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFET_GET_ATTR); break; } @@ -299,7 +299,7 @@ pfet_init(const Target& i_target) if (l_rc) { FAPI_ERR("fapiGetAttribute ATTR_PM_PFET_POWERDOWN_CORE_DELAY0"); - FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFET_GET_ATTR); + // FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFET_GET_ATTR); break; } @@ -310,7 +310,7 @@ pfet_init(const Target& i_target) if (l_rc) { FAPI_ERR("fapiGetAttribute ATTR_PM_PFET_POWERDOWN_CORE_DELAY1"); - FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFET_GET_ATTR); + // FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFET_GET_ATTR); break; } @@ -321,7 +321,7 @@ pfet_init(const Target& i_target) if (l_rc) { FAPI_ERR("fapiGetAttribute ATTR_PM_PFET_POWERUP_ECO_DELAY0"); - FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFET_GET_ATTR); + // FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFET_GET_ATTR); break; } @@ -333,7 +333,7 @@ pfet_init(const Target& i_target) if (l_rc) { FAPI_ERR("fapiGetAttribute ATTR_PM_PFET_POWERUP_ECO_DELAY1"); - FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFET_GET_ATTR); + // FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFET_GET_ATTR); break; } @@ -343,7 +343,7 @@ pfet_init(const Target& i_target) if (l_rc) { FAPI_ERR("fapiGetAttribute ATTR_PM_PFET_POWERDOWN_ECO_DELAY0"); - FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFET_GET_ATTR); + // FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFET_GET_ATTR); break; } @@ -354,7 +354,7 @@ pfet_init(const Target& i_target) if (l_rc) { FAPI_ERR("fapiGetAttribute ATTR_PM_PFET_POWERDOWN_ECO_DELAY1"); - FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFET_GET_ATTR); + // FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFET_GET_ATTR); break; } diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pm.H b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pm.H index 6999f9bf0..c9e54eaa0 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pm.H +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pm.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_pm.H,v 1.2 2012/12/07 20:20:10 stillgs Exp $ +// $Id: p8_pm.H,v 1.3 2013/03/05 23:01:11 stillgs Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm.H,v $ //------------------------------------------------------------------------------ // *| @@ -69,6 +69,39 @@ enum p8_PM_FLOW_MODE { #endif // _P8_PM_FLOW_MODE +// Macros to enhance readability yet provide for error handling +// Assume the error path is to break out of the current loop. If nested loops +// are employed, the error_flag can be used to break out of the necessary +// levels. +#define PUTSCOM(_mi_target, _mi_address, _mi_buffer){ \ + l_rc = fapiPutScom(_mi_target, _mi_address, _mi_buffer); \ + if(!l_rc.ok()) \ + { \ + FAPI_ERR("PutScom error to address 0x%08llx", _mi_address); \ + error_flag=true; \ + break; \ + } \ +} + +#define GETSCOM(_mi_target, _mi_address, _mi_buffer){ \ + l_rc = fapiGetScom(_mi_target, _mi_address, _mi_buffer); \ + if(!l_rc.ok()) \ + { \ + FAPI_ERR("GetScom error to address 0x%08llx", _mi_address); \ + error_flag=true; \ + break; \ + } \ +} + +#define E_RC_CHECK(_mi_e_rc, _mi_l_rc){ \ + if (e_rc) \ + { \ + FAPI_ERR("Error (0x%x) accessing ecmdDataBufferBase", _mi_e_rc);\ + _mi_l_rc.setEcmdError(_mi_e_rc); \ + break; \ + } \ +} + } // extern "C" #endif // _P8_PM_H_ diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/pgp_pba.h b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/pgp_pba.h index 20b59ce62..365be5e6d 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/pgp_pba.h +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/pgp_pba.h @@ -1,30 +1,29 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/pgp_pba.h $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/pgp_pba.h $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __PGP_PBA_H__ #define __PGP_PBA_H__ -// $Id: pgp_pba.h,v 1.1 2012/08/13 13:04:35 stillgs Exp $ +// $Id: pgp_pba.h,v 1.2 2012/10/05 18:42:15 pchatnah Exp $ /// \file pgp_pba.h /// \brief PBA unit header. Local and mechanically generated macros. @@ -32,7 +31,7 @@ /// \todo Add Doxygen grouping to constant groups //#include "pba_register_addresses.h" -#include "pba_firmware_registers.h" +#include "pba_firmware_register.H" #define POWERBUS_CACHE_LINE_SIZE 128 #define LOG_POWERBUS_CACHE_LINE_SIZE 7 diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_delta_scan_rw.h b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_delta_scan_rw.h index 4699072ea..4e5e8b51e 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_delta_scan_rw.h +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_delta_scan_rw.h @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_delta_scan_rw.h,v 1.38 2013/03/06 18:21:46 cmolsen Exp $ +// $Id: p8_delta_scan_rw.h,v 1.40 2013/03/22 04:12:02 cmolsen Exp $ #define OVERRIDE_OFFSET 8 // Byte offset of forward pointer's addr relative // to base forward pointer's addr. #define SIZE_IMAGE_BUF_MAX 5000000 // Max ~50MB image buffer size. @@ -89,6 +89,7 @@ #define IMGBUILD_INVALID_IMAGE 10 // Invalid image. #define IMGBUILD_IMAGE_SIZE_MISMATCH 11 // Mismatch between image sizes. #define IMGBUILD_IMAGE_SIZE_MESS 12 // Messed up image or section sizes. +#define IMGBUILD_ERR_DECOMPRESSION 13 // Error assoc with decompressing RS4. #define IMGBUILD_ERR_PORE_INLINE 20 // Pore inline error. #define IMGBUILD_ERR_PORE_INLINE_ASM 21 // Err assoc w/inline assembler. #define IMGBUILD_ERR_WF_CREATE 45 // Err assoc w/create_wiggle_flip_prg. diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.C b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.C index 7c60726b0..a4f1f6009 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.C +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_image_help_base.C,v 1.6 2013/01/02 03:01:28 cmolsen Exp $ +// $Id: p8_image_help_base.C,v 1.9 2013/03/01 22:23:03 cmolsen Exp $ /*------------------------------------------------------------------------------*/ /* *! TITLE : p8_image_help_base.c */ /* *! DESCRIPTION : Basic helper functions for building and extracting */ @@ -54,132 +54,133 @@ extern "C" { // DeltaRingLayout, so you can use the non-ptr members to point to values // in the image. // -int get_ring_layout_from_image2( const void *i_imageIn, - uint32_t i_ddLevel, - uint8_t i_sysPhase, - DeltaRingLayout **o_rs4RingLayout, - void **nextRing) +int get_ring_layout_from_image2( const void *i_imageIn, + uint32_t i_ddLevel, + uint8_t i_sysPhase, + DeltaRingLayout **o_rs4RingLayout, + void **nextRing) { - uint32_t rc=0, rcLoc=0; - uint8_t bRingFound=0, bRingEOS=0; - DeltaRingLayout *thisRingLayout, *nextRingLayout; //Pointers into memory mapped image. DO NOT CHANGE MEMBERS! - uint32_t sizeInitf; - SbeXipSection hostSection; - void *initfHostAddress0; - - SBE_XIP_ERROR_STRINGS(g_errorStrings); + uint32_t rc=0, rcLoc=0; + uint8_t bRingFound=0, bRingEOS=0; + DeltaRingLayout *thisRingLayout, *nextRingLayout; //Pointers into memory mapped image. DO NOT CHANGE MEMBERS! + uint32_t sizeRings; + SbeXipSection hostSection; + void *ringsHostAddress0; + + SBE_XIP_ERROR_STRINGS(g_errorStrings); - // Always first get the .initf stats from the TOC: - // - .initf host address offset and - // - .initf size - // + // Always first get the .rings stats from the TOC: + // - .rings host address offset and + // - .rings size + // rc = sbe_xip_get_section( i_imageIn, SBE_XIP_SECTION_RINGS, &hostSection); if (rc) { MY_INF("ERROR : sbe_xip_get_section() failed: %s", SBE_XIP_ERROR_STRING(g_errorStrings, rc)); - MY_INF("Probable cause:"); - MY_INF("\tThe section (=SBE_XIP_SECTION_RINGS=%i) was not found.",SBE_XIP_SECTION_RINGS); - return IMGBUILD_ERR_KEYWORD_NOT_FOUND; + MY_INF("Probable cause:"); + MY_INF("\tThe section (=SBE_XIP_SECTION_RINGS=%i) was not found.",SBE_XIP_SECTION_RINGS); + return IMGBUILD_ERR_KEYWORD_NOT_FOUND; } if (hostSection.iv_offset==0) { - MY_INF("INFO : No ring data exists for the section ID = SBE_XIP_SECTION_RINGS (ID=%i).",SBE_XIP_SECTION_RINGS); - return DSLWB_RING_SEARCH_NO_MATCH; // Implies exhaust search as well. + MY_INF("INFO : No ring data exists for the section ID = SBE_XIP_SECTION_RINGS (ID=%i).",SBE_XIP_SECTION_RINGS); + return DSLWB_RING_SEARCH_NO_MATCH; // Implies exhaust search as well. } - initfHostAddress0 = (void*)((uintptr_t)i_imageIn + hostSection.iv_offset); - sizeInitf = hostSection.iv_size; + ringsHostAddress0 = (void*)((uintptr_t)i_imageIn + hostSection.iv_offset); + sizeRings = hostSection.iv_size; - // On first call, get the base offset to the .initf section. - // On subsequent calls, we're into the search for ddLevel and sysPhase, so use nextRing instead. - // - if (*nextRing==NULL) - nextRingLayout = (DeltaRingLayout*)initfHostAddress0; - else - nextRingLayout = (DeltaRingLayout*)*nextRing; + // On first call, get the base offset to the .rings section. + // On subsequent calls, we're into the search for ddLevel and sysPhase, so use nextRing instead. + // + if (*nextRing==NULL) + nextRingLayout = (DeltaRingLayout*)ringsHostAddress0; + else + nextRingLayout = (DeltaRingLayout*)*nextRing; - MY_DBG("initfHostAddress0 = 0x%016llx",(uint64_t)initfHostAddress0); - MY_DBG("sizeInitf = %i", sizeInitf); - MY_DBG("nextRingLayout = 0x%016llx",(uint64_t)nextRingLayout); - - // Populate the output RS4 ring BE layout structure as well as local structure in host LE format where needed. - // Note! Entire memory content is in BE format. So we do LE conversions where needed. - // - bRingFound = 0; - bRingEOS = 0; - - // SEARCH loop: Parse ring blocks successively until we find a ring that matches: - // ddLevel == i_ddLevel - // sysPhase == i_sysPhase - // - while (!bRingFound && !bRingEOS) { - thisRingLayout = nextRingLayout; - MY_DBG("Next backItemPtr = 0x%016llx",myRev64(thisRingLayout->backItemPtr)); - MY_DBG("Next ddLevel = 0x%02x",myRev32(thisRingLayout->ddLevel)); - MY_DBG("Next sysPhase = %i",thisRingLayout->sysPhase); - MY_DBG("Next override = %i",thisRingLayout->override); - MY_DBG("Next reserved1 = %i",thisRingLayout->reserved1); - MY_DBG("Next reserved2 = %i",thisRingLayout->reserved2); - - if (myRev32(thisRingLayout->ddLevel)==i_ddLevel) { // Is there a non-specific DD level, like for sys phase? - if ((thisRingLayout->sysPhase==0 && i_sysPhase==0) || - (thisRingLayout->sysPhase==1 && i_sysPhase==1) || - (thisRingLayout->sysPhase==2 && (i_sysPhase==0 || i_sysPhase==1))) { - bRingFound = 1; - MY_DBG("\tRing match found!"); - } - } - nextRingLayout = (DeltaRingLayout*)((uintptr_t)thisRingLayout + myRev32(thisRingLayout->sizeOfThis)); - *nextRing = (void*)nextRingLayout; - if (nextRingLayout>=(DeltaRingLayout*)((uintptr_t)initfHostAddress0+sizeInitf)) { - bRingEOS = 1; - *nextRing = NULL; - MY_DBG("\tRing search exhausted!"); - } - - } // End of SEARCH. + MY_DBG("ringsHostAddress0 = 0x%016llx",(uint64_t)ringsHostAddress0); + MY_DBG("sizeRings = %i", sizeRings); + MY_DBG("nextRingLayout = 0x%016llx",(uint64_t)nextRingLayout); + + // Populate the output RS4 ring BE layout structure as well as local structure in host LE format where needed. + // Note! Entire memory content is in BE format. So we do LE conversions where needed. + // + bRingFound = 0; + bRingEOS = 0; + + // SEARCH loop: Parse ring blocks successively until we find a ring that matches: + // ddLevel == i_ddLevel + // sysPhase == i_sysPhase + // + while (!bRingFound && !bRingEOS) { + thisRingLayout = nextRingLayout; + MY_DBG("Next backItemPtr = 0x%016llx",myRev64(thisRingLayout->backItemPtr)); + MY_DBG("Next ddLevel = 0x%02x",myRev32(thisRingLayout->ddLevel)); + MY_DBG("Next sysPhase = %i",thisRingLayout->sysPhase); + MY_DBG("Next override = %i",thisRingLayout->override); + MY_DBG("Next reserved1 = %i",thisRingLayout->reserved1); + MY_DBG("Next reserved2 = %i",thisRingLayout->reserved2); + + if (myRev32(thisRingLayout->ddLevel)==i_ddLevel) { // Is there a non-specific DD level, like for sys phase? + if ((thisRingLayout->sysPhase==0 && i_sysPhase==0) || + (thisRingLayout->sysPhase==1 && i_sysPhase==1) || + (thisRingLayout->sysPhase==2 && (i_sysPhase==0 || i_sysPhase==1))) { + bRingFound = 1; + MY_DBG("\tRing match found!"); + } + } + nextRingLayout = (DeltaRingLayout*)((uintptr_t)thisRingLayout + myRev32(thisRingLayout->sizeOfThis)); + *nextRing = (void*)nextRingLayout; + if (nextRingLayout>=(DeltaRingLayout*)((uintptr_t)ringsHostAddress0+sizeRings)) { + bRingEOS = 1; + *nextRing = NULL; + MY_DBG("\tRing search exhausted!"); + } + + } // End of SEARCH. - if (bRingFound) { - if (bRingEOS) - rcLoc = DSLWB_RING_SEARCH_EXHAUST_MATCH; - else - rcLoc = DSLWB_RING_SEARCH_MATCH; - } - else { - *nextRing = NULL; - if (bRingEOS) - return DSLWB_RING_SEARCH_NO_MATCH; // Implies exhaust search as well. - else { - MY_INF("Messed up ring search. Check code and .rings content. Returning nothing."); - return DSLWB_RING_SEARCH_MESS; - } - } + if (bRingFound) { + if (bRingEOS) + rcLoc = DSLWB_RING_SEARCH_EXHAUST_MATCH; + else + rcLoc = DSLWB_RING_SEARCH_MATCH; + } + else { + *nextRing = NULL; + if (bRingEOS) + return DSLWB_RING_SEARCH_NO_MATCH; // Implies exhaust search as well. + else { + MY_INF("Messed up ring search. Check code and .rings content. Returning nothing."); + return DSLWB_RING_SEARCH_MESS; + } + } *o_rs4RingLayout = thisRingLayout; - // Check that the ring layout structure in the memory is 8-byte aligned. This must be so because: - // - The entryOffset address must be on an 8-byte boundary because the start of the .initf ELF section must - // be 8-byte aligned AND because the rs4Delta member is the last member and which must itself be 8-byte aligned. - // - These two things together means that both the beginning and end of the delta ring layout must be 8-byte - // aligned, and thus the whole block,i.e. sizeOfThis, must be 8-byte aligned. - // Also check that the RS4 delta ring is 8-byte aligned. - // Also check that the RS4 launcher is 8-byte aligned. - // - if (((uintptr_t)thisRingLayout-(uintptr_t)i_imageIn)%8 || - myRev32(thisRingLayout->sizeOfThis)%8 || - myRev64(thisRingLayout->entryOffset)%8 ) { - MY_INF("Ring block or ring code section is not 8-byte aligned:"); - MY_INF(" thisRingLayout-imageIn = %i",(uintptr_t)thisRingLayout-(uintptr_t)i_imageIn); - MY_INF(" thisRingLayout->sizeOfThis = %i",myRev32(thisRingLayout->sizeOfThis)); - MY_INF(" thisRingLayout->entryOffset = %i",(uint32_t)myRev64(thisRingLayout->entryOffset)); - return IMGBUILD_ERR_MISALIGNED_RING_LAYOUT; - } + // Check that the ring layout structure in the memory is 8-byte aligned: + // - The entryOffset address must be on an 8-byte boundary because the start of the + // .rings section must be 8-byte aligned AND because the rs4Delta member is the + // last member and which must itself be 8-byte aligned. These two things together + // means that both the beginning and end of the delta ring layout must be 8-byte + // aligned, and thus the whole block,i.e. sizeOfThis, must be 8-byte aligned. + // Also check that the RS4 delta ring is 8-byte aligned. + // Also check that the RS4 launcher is 8-byte aligned. + // + if (((uintptr_t)thisRingLayout-(uintptr_t)i_imageIn)%8 || + myRev32(thisRingLayout->sizeOfThis)%8 || + myRev64(thisRingLayout->entryOffset)%8 ) { + MY_INF("Ring block or ring code section is not 8-byte aligned:"); + MY_INF(" thisRingLayout-imageIn = 0x%08x",(uint32_t)((uintptr_t)thisRingLayout-(uintptr_t)i_imageIn)); + MY_INF(" thisRingLayout->sizeOfThis = 0x%08x",myRev32(thisRingLayout->sizeOfThis)); + MY_INF(" thisRingLayout->entryOffset = 0x%016llx",(uint64_t)myRev64(thisRingLayout->entryOffset)); + return IMGBUILD_ERR_MISALIGNED_RING_LAYOUT; + } - if (*nextRing > (void*)((uintptr_t)initfHostAddress0 + sizeInitf)) { - MY_INF("Book keeping got messed up during .initf search. Initf section does not appear aligned."); - MY_INF("initfHostAddress0+sizeInitf = 0x%016llx",(uint64_t)initfHostAddress0+sizeInitf); - MY_INF("nextRing = %i",*(uint32_t*)nextRing); - MY_INF("Continuing..."); - } + if (*nextRing > (void*)((uintptr_t)ringsHostAddress0 + sizeRings)) { + MY_INF("Book keeping got messed up during .rings search. .rings section does not appear aligned."); + MY_INF("ringsHostAddress0+sizeRings = 0x%016llx",(uint64_t)ringsHostAddress0+sizeRings); + MY_INF("nextRing = 0x%016llx",*(uint64_t*)nextRing); + MY_INF("Continuing..."); + } - return rcLoc; + return rcLoc; } @@ -188,7 +189,7 @@ int get_ring_layout_from_image2( const void *i_imageIn, // Comments: // - Appends an RS4 or WF ring block to the .rings section. It doesn't care // what type of ring it is. The only data that might be updated in the ring -// block is the back pointer which is shared between both types of rings. +// block is the backItemPtr which is shared between both types of rings. // - If ringName=NULL: Assumes fwd ptr already exists in .ipl_data or .data // section. Back pointer in ring block is unchanged. // - If ringName!=NULL: Adds fwd ptr to .ipl_data or .data section. Updates back @@ -200,78 +201,81 @@ int get_ring_layout_from_image2( const void *i_imageIn, // - overridable: Indicates if a ring can be overridden. It is ignored if // ringName==NULL. // - Assumes ring block is in BE format. -int write_ring_block_to_image( void *io_image, +int write_ring_block_to_image( void *io_image, const char *i_ringName, - DeltaRingLayout *i_ringBlock, - const uint8_t i_idxVector, - const uint8_t i_override, - const uint8_t i_overridable, - const uint32_t i_sizeImageMax) + DeltaRingLayout *i_ringBlock, + const uint8_t i_idxVector, + const uint8_t i_override, + const uint8_t i_overridable, + const uint32_t i_sizeImageMax) { - uint32_t rc=0; - SbeXipItem tocItem; - uint32_t offsetRingBlock=1; // Initialize to anything but zero. - uint32_t sizeImage=0; - uint64_t ringPoreAddress=0,backPtr=0,fwdPtrCheck; + uint32_t rc=0; + SbeXipItem tocItem; + uint32_t offsetRingBlock=1; // Initialize to anything but zero. + uint32_t sizeImage=0; + uint64_t ringPoreAddress=0,backPtr=0,fwdPtrCheck; - SBE_XIP_ERROR_STRINGS(g_errorStrings); + SBE_XIP_ERROR_STRINGS(g_errorStrings); - if (myRev64(i_ringBlock->entryOffset)%8) { - MY_INF("Ring code section is not 8-byte aligned."); - return IMGBUILD_ERR_MISALIGNED_RING_LAYOUT; - } + if (myRev64(i_ringBlock->entryOffset)%8) { + MY_ERR("Ring code section is not 8-byte aligned."); + return IMGBUILD_ERR_MISALIGNED_RING_LAYOUT; + } if (i_ringName) { - // Obtain the back pointer to the .data item, i.e. the location of the ptr associated with the - // ring/var name in the TOC. - // - rc = sbe_xip_find( io_image, i_ringName, &tocItem); - if (rc) { + // Obtain the back pointer to the .data item, i.e. the location of the ptr associated with the + // ring/var name in the TOC. + // + rc = sbe_xip_find( io_image, i_ringName, &tocItem); + if (rc) { MY_ERR("sbe_xip_find() failed w/rc=%i", rc); - MY_ERR("Probable cause: Ring name (=%s) not found in image.", i_ringName); - return IMGBUILD_ERR_KEYWORD_NOT_FOUND; - } - i_ringBlock->backItemPtr = myRev64( tocItem.iv_address + - i_idxVector*8*(1+i_overridable) + - 8*i_override*i_overridable ); + MY_ERR("Probable cause: Ring name (=%s) not found in image.", i_ringName); + return IMGBUILD_ERR_KEYWORD_NOT_FOUND; + } + i_ringBlock->backItemPtr = myRev64( tocItem.iv_address + + i_idxVector*8*(1+i_overridable) + + 8*i_override*i_overridable ); } - // Append ring block to .rings section. - // - rc = sbe_xip_append(io_image, - SBE_XIP_SECTION_RINGS, - (void*)i_ringBlock, - myRev32(i_ringBlock->sizeOfThis), - i_sizeImageMax, - &offsetRingBlock); + // Append ring block to .rings section. + // + rc = sbe_xip_append(io_image, + SBE_XIP_SECTION_RINGS, + (void*)i_ringBlock, + myRev32(i_ringBlock->sizeOfThis), + i_sizeImageMax, + &offsetRingBlock); if (rc) { - MY_INF("sbe_xip_append() failed: %s", SBE_XIP_ERROR_STRING(g_errorStrings, rc)); + MY_ERR("sbe_xip_append() failed: %s", SBE_XIP_ERROR_STRING(g_errorStrings, rc)); + sbe_xip_image_size(io_image,&sizeImage); + MY_ERR("Input image size: %i\n", sizeImage); + MY_ERR("Max image size allowed: %i\n", i_sizeImageMax); return IMGBUILD_ERR_APPEND; } - // ...get new image size and test if successful update. - rc = sbe_xip_image_size( io_image, &sizeImage); - MY_DBG("Updated image size (after append): %i",sizeImage); + // ...get new image size and test if successful update. + rc = sbe_xip_image_size( io_image, &sizeImage); + MY_DBG("Updated image size (after append): %i",sizeImage); if (rc) { - MY_INF("sbe_xip_image_size() of output image failed: %s", SBE_XIP_ERROR_STRING(g_errorStrings, rc)); + MY_ERR("sbe_xip_image_size() of output image failed: %s", SBE_XIP_ERROR_STRING(g_errorStrings, rc)); return IMGBUILD_ERR_XIP_MISC; } rc = sbe_xip_validate( io_image, sizeImage); if (rc) { - MY_INF("sbe_xip_validate() of output image failed: %s", SBE_XIP_ERROR_STRING(g_errorStrings, rc)); + MY_ERR("sbe_xip_validate() of output image failed: %s", SBE_XIP_ERROR_STRING(g_errorStrings, rc)); return IMGBUILD_ERR_XIP_MISC; } - - // Update forward pointer associated with the ring/var name + any override offset. - // - // Convert the ring offset (wrt .rings address) to an PORE address - rc = sbe_xip_section2pore(io_image, SBE_XIP_SECTION_RINGS, offsetRingBlock, &ringPoreAddress); + + // Update forward pointer associated with the ring/var name + any override offset. + // + // Convert the ring offset (wrt .rings address) to an PORE address + rc = sbe_xip_section2pore(io_image, SBE_XIP_SECTION_RINGS, offsetRingBlock, &ringPoreAddress); MY_DBG("fwdPtr=0x%016llx", ringPoreAddress); if (rc) { - MY_INF("sbe_xip_section2pore() failed: %s", SBE_XIP_ERROR_STRING(g_errorStrings, rc)); + MY_ERR("sbe_xip_section2pore() failed: %s", SBE_XIP_ERROR_STRING(g_errorStrings, rc)); return IMGBUILD_ERR_XIP_MISC; } - // Now, update the forward pointer. + // Now, update the forward pointer. // // First, retrieve the ring block's backPtr which tells us where the fwd ptr // is located. @@ -281,40 +285,40 @@ int write_ring_block_to_image( void *io_image, // backItemPtr in the input ring block already has this from the ref image, // and it shouldn't have changed after having been ported over to an // IPL/Seeprom image. - backPtr = myRev64(i_ringBlock->backItemPtr); - MY_DBG("backPtr = 0x%016llx", backPtr); + backPtr = myRev64(i_ringBlock->backItemPtr); + MY_DBG("backPtr = 0x%016llx", backPtr); // Second, put the ring's Pore addr into the location pointed to by the back ptr. - rc = sbe_xip_write_uint64( io_image, - backPtr, - ringPoreAddress); + rc = sbe_xip_write_uint64( io_image, + backPtr, + ringPoreAddress); // Third, let's read it back to make sure we're OK a little further down. - rc = rc+sbe_xip_read_uint64(io_image, - backPtr, - &fwdPtrCheck); - if (rc) { - MY_INF("sbe_xip_[write,read]_uint64() failed: %s", SBE_XIP_ERROR_STRING(g_errorStrings, rc)); - return IMGBUILD_ERR_XIP_MISC; - } + rc = rc+sbe_xip_read_uint64(io_image, + backPtr, + &fwdPtrCheck); + if (rc) { + MY_ERR("sbe_xip_[write,read]_uint64() failed: %s", SBE_XIP_ERROR_STRING(g_errorStrings, rc)); + return IMGBUILD_ERR_XIP_MISC; + } // Check for pointer mess. - if (fwdPtrCheck!=ringPoreAddress || backPtr!=myRev64(i_ringBlock->backItemPtr)) { - MY_INF("Forward or backward pointer mess. Check code."); - MY_INF("fwdPtr =0x%016llx",ringPoreAddress); - MY_INF("fwdPtrCheck =0x%016llx",fwdPtrCheck); - MY_INF("layout bckPtr=0x%016llx",myRev64(i_ringBlock->backItemPtr)); - MY_INF("backPtr =0x%016llx",backPtr); - return IMGBUILD_ERR_FWD_BACK_PTR_MESS; - } - // ...test if successful update. + if (fwdPtrCheck!=ringPoreAddress || backPtr!=myRev64(i_ringBlock->backItemPtr)) { + MY_ERR("Forward or backward pointer mess. Check code."); + MY_ERR("fwdPtr =0x%016llx",ringPoreAddress); + MY_ERR("fwdPtrCheck =0x%016llx",fwdPtrCheck); + MY_ERR("layout bckPtr=0x%016llx",myRev64(i_ringBlock->backItemPtr)); + MY_ERR("backPtr =0x%016llx",backPtr); + return IMGBUILD_ERR_FWD_BACK_PTR_MESS; + } + // ...test if successful update. rc = sbe_xip_validate( io_image, sizeImage); if (rc) { - MY_INF("sbe_xip_validate() of output image failed: %s", SBE_XIP_ERROR_STRING(g_errorStrings, rc)); - MY_INF("Probable cause: sbe_xip_write_uint64() updated at the wrong address (=0x%016llx)", - myRev64(i_ringBlock->backItemPtr)); + MY_ERR("sbe_xip_validate() of output image failed: %s", SBE_XIP_ERROR_STRING(g_errorStrings, rc)); + MY_ERR("Probable cause: sbe_xip_write_uint64() updated at the wrong address (=0x%016llx)", + myRev64(i_ringBlock->backItemPtr)); return IMGBUILD_ERR_XIP_MISC; } - return IMGBUILD_SUCCESS; + return IMGBUILD_SUCCESS; } @@ -330,33 +334,124 @@ uint64_t calc_ring_layout_entry_offset( if (i_typeRingLayout==0) { // RS4 ring block. ringBlock.entryOffset = (uint64_t)( - sizeof(ringBlock.entryOffset) + - sizeof(ringBlock.backItemPtr) + - sizeof(ringBlock.sizeOfThis) + - sizeof(ringBlock.sizeOfMeta) + - sizeof(ringBlock.ddLevel) + - sizeof(ringBlock.sysPhase) + - sizeof(ringBlock.override) + - sizeof(ringBlock.reserved1) + - sizeof(ringBlock.reserved2) + - myByteAlign(8, i_sizeMetaData) ); // 8-byte align RS4 launch. - } - else - if (i_typeRingLayout==1) { - // Wiggle-flip ring block. + sizeof(ringBlock.entryOffset) + + sizeof(ringBlock.backItemPtr) + + sizeof(ringBlock.sizeOfThis) + + sizeof(ringBlock.sizeOfMeta) + + sizeof(ringBlock.ddLevel) + + sizeof(ringBlock.sysPhase) + + sizeof(ringBlock.override) + + sizeof(ringBlock.reserved1) + + sizeof(ringBlock.reserved2) + + myByteAlign(8, i_sizeMetaData) ); // 8-byte align RS4 launch. + } + else + if (i_typeRingLayout==1) { + // Wiggle-flip ring block. ringBlock.entryOffset = (uint64_t)( - sizeof(ringBlock.entryOffset) + - sizeof(ringBlock.backItemPtr) + - sizeof(ringBlock.sizeOfThis) + - sizeof(ringBlock.sizeOfMeta) + - myByteAlign(8, i_sizeMetaData) ); // 8-byte align WF prg. - } - else - return MAX_UINT64_T; - + sizeof(ringBlock.entryOffset) + + sizeof(ringBlock.backItemPtr) + + sizeof(ringBlock.sizeOfThis) + + sizeof(ringBlock.sizeOfMeta) + + myByteAlign(8, i_sizeMetaData) ); // 8-byte align WF prg. + } + else + return MAX_UINT64_T; + return ringBlock.entryOffset; } +// Function: over_write_ring_data_in_image() +// Comments: +// - Overwrites RS4 or WF ring block data in the .rings section. It doesn't care +// what type of ring it is. The only data that might be updated in the ring +// block is the sizeOfThis which is shared between both types of rings. +// - If ringName=NULL: ? +// - If ringName!=NULL: ? +// - ringData: The actual RS4 ring data, incl container, or the WF program. +// - sizeRingData: Byte size of ring data. This includes RS4 launch in case of RS4. +// - idxVector: Contains the index number of a vector array. This is pretty much +// limited for ex_ chiplet IDs. It is ignored if ringName==NULL. +// - override: Indicates if the ring is an override ring. It is ignored if +// ringName==NULL. +// - overridable: Indicates if a ring can be overridden. It is ignored if +// ringName==NULL. +int over_write_ring_data_in_image( void *io_image, + const char *i_ringName, + const void *i_ringData, // WF or RS4 + const uint32_t i_sizeRingData, // Byte size + const uint8_t i_idxVector, + const uint8_t i_override, + const uint8_t i_overridable ) +{ + uint32_t rc=0; + SbeXipItem tocItem; + uint32_t sizeImage=0; + void *hostVectorBase, *hostVectorThis; + DeltaRingLayout *hostRingBlock; + void *hostRingData; + + // Test if valid image to start with since we're going to mess with it w/o using + // sbe_xip functions. + sbe_xip_image_size( io_image, &sizeImage); + rc = sbe_xip_validate( io_image, sizeImage); + if (rc) { + MY_ERR("sbe_xip_validate() failed w/rc=%i\n", rc); + return IMGBUILD_ERR_XIP_MISC; + } + + // Calculate the host location of the ring. + // + rc = sbe_xip_find( io_image, i_ringName, &tocItem); + if (rc) { + MY_ERR("sbe_xip_find() failed w/rc=%i", rc); + MY_ERR("Probable cause: Ring name (=%s) not found in image.", i_ringName); + return IMGBUILD_ERR_KEYWORD_NOT_FOUND; + } + sbe_xip_pore2host( io_image, tocItem.iv_address, &hostVectorBase); + hostVectorThis = (void*) ( (uint64_t)hostVectorBase + + i_idxVector*8*(1+i_overridable) + + 8*i_override*i_overridable ); + hostRingBlock = (DeltaRingLayout*)(*(uintptr_t*)hostVectorThis); + hostRingData = (void*)( (uint64_t)hostRingBlock + hostRingBlock->entryOffset ); + + // Over write ringData onto existing ring data content in image. + // + memcpy(hostRingData, i_ringData, i_sizeRingData); + + // Update size of new ring block. + // + hostRingBlock->sizeOfThis = hostRingBlock->entryOffset + i_sizeRingData; + + // Test if successful update. + rc = sbe_xip_validate( io_image, sizeImage); + if (rc) { + MY_ERR("sbe_xip_validate() failed w/rc=%i\n", rc); + MY_ERR("We really screwed up the image here. This is a coding error. Here's some data:\n"); + MY_ERR("io_image = 0x%016llx\n",(uint64_t)io_image); + MY_ERR("hostVectorBase = 0x%016llx\n",(uint64_t)hostVectorBase); + MY_ERR("hostVectorThis = 0x%016llx\n",(uint64_t)hostVectorThis); + MY_ERR("hostRingBlock = 0x%016llx\n",(uint64_t)hostRingBlock); + MY_ERR("hostRingData = 0x%016llx\n",(uint64_t)hostRingData); + return IMGBUILD_ERR_XIP_MISC; + } + + MY_DBG("Dumping ring layout of over-writen ring:"); + MY_DBG(" entryOffset = 0x%016llx",myRev64(hostRingBlock->entryOffset)); + MY_DBG(" backItemPtr = 0x%016llx",myRev64(hostRingBlock->backItemPtr)); + MY_DBG(" sizeOfThis = %i",myRev32(hostRingBlock->sizeOfThis)); + MY_DBG(" sizeOfMeta = %i",myRev32(hostRingBlock->sizeOfMeta)); + MY_DBG(" ddLevel = %i",myRev32(hostRingBlock->ddLevel)); + MY_DBG(" sysPhase = %i",hostRingBlock->sysPhase); + MY_DBG(" override = %i",hostRingBlock->override); + MY_DBG(" reserved1+2 = %i",hostRingBlock->reserved1|hostRingBlock->reserved2); + + + return IMGBUILD_SUCCESS; +} + + + } diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_ring_identification.c b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_ring_identification.c index 3923c5d59..7a061f12d 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_ring_identification.c +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_ring_identification.c @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_ring_identification.c,v 1.14 2012/12/19 12:49:27 cmolsen Exp $ +// $Id: p8_ring_identification.c,v 1.18 2013/02/12 23:30:07 cmolsen Exp $ /*------------------------------------------------------------------------------*/ /* *! (C) Copyright International Business Machines Corp. 2012 */ /* *! All Rights Reserved -- Property of IBM */ @@ -34,121 +34,119 @@ #include <p8_ring_identification.H> const RingIdList RING_ID_LIST_PG[] = { - /* ringName ringId chipIdMin chipIdMax ringNameImg mvpdKeyword */ - { "ab_gptr_ab", 0xA0, 0x08, 0x08, "ab_gptr_ab_ring", VPD_KEYWORD_PDG }, - { "ab_gptr_ioa", 0xA1, 0x08, 0x08, "ab_gptr_ioa_ring", VPD_KEYWORD_PDG }, - { "ab_gptr_perv", 0xA2, 0x08, 0x08, "ab_gptr_perv_ring", VPD_KEYWORD_PDG }, - { "ab_gptr_pll", 0xA3, 0x08, 0x08, "ab_gptr_pll_ring", VPD_KEYWORD_PDG }, - { "ab_time", 0xA4, 0x08, 0x08, "ab_time_ring", VPD_KEYWORD_PDG }, - { "ex_gptr_core", 0xA5, 0xFF, 0xFF, "ex_gptr_core_ring", VPD_KEYWORD_PDG }, //Chip specific - { "ex_gptr_dpll", 0xA6, 0xFF, 0xFF, "ex_gptr_dpll_ring", VPD_KEYWORD_PDG }, //Chip specific - { "ex_gptr_l2", 0xA7, 0xFF, 0xFF, "ex_gptr_l2_ring", VPD_KEYWORD_PDG }, //Chip specific - { "ex_gptr_l3", 0xA8, 0xFF, 0xFF, "ex_gptr_l3_ring", VPD_KEYWORD_PDG }, //Chip specific - { "ex_gptr_l3refr", 0xA9, 0xFF, 0xFF, "ex_gptr_l3refr_ring", VPD_KEYWORD_PDG }, //Chip specific - { "ex_gptr_perv", 0xAA, 0xFF, 0xFF, "ex_gptr_perv_ring", VPD_KEYWORD_PDG }, //Chip specific - { "ex_time_core", 0xAB, 0x10, 0x1F, "ex_time_core_ring", VPD_KEYWORD_PDG }, //Chiplet specfc - { "ex_time_eco", 0xAC, 0x10, 0x1F, "ex_time_eco_ring", VPD_KEYWORD_PDG }, //Chiplet specfc - { "pb_gptr_dmipll", 0xAD, 0x02, 0x02, "pb_gptr_dmipll_ring", VPD_KEYWORD_PDG }, - { "pb_gptr_mcr", 0xAE, 0x02, 0x02, "pb_gptr_mcr_ring", VPD_KEYWORD_PDG }, - { "pb_gptr_nest", 0xAF, 0x02, 0x02, "pb_gptr_nest_ring", VPD_KEYWORD_PDG }, - { "pb_gptr_nx", 0xB0, 0x02, 0x02, "pb_gptr_nx_ring", VPD_KEYWORD_PDG }, - { "pb_gptr_pcis", 0xB1, 0x02, 0x02, "pb_gptr_pcis_ring", VPD_KEYWORD_PDG }, - { "pb_gptr_perv", 0xB2, 0x02, 0x02, "pb_gptr_perv_ring", VPD_KEYWORD_PDG }, - { "pb_time", 0xB3, 0x02, 0x02, "pb_time_ring", VPD_KEYWORD_PDG }, - { "pb_time_mcr", 0xB4, 0x02, 0x02, "pb_time_mcr_ring", VPD_KEYWORD_PDG }, - { "pb_time_nx", 0xB5, 0x02, 0x02, "pb_time_nx_ring", VPD_KEYWORD_PDG }, - { "pci_gptr_iopci", 0xB6, 0x09, 0x09, "pci_gptr_iopci_ring", VPD_KEYWORD_PDG }, - { "pci_gptr_pbf", 0xB7, 0x09, 0x09, "pci_gptr_pbf_ring", VPD_KEYWORD_PDG }, - { "pci_gptr_pci0", 0xB8, 0x09, 0x09, "pci_gptr_pci0_ring", VPD_KEYWORD_PDG }, - { "pci_gptr_pci1", 0xB9, 0x09, 0x09, "pci_gptr_pci1_ring", VPD_KEYWORD_PDG }, - { "pci_gptr_pci2", 0xBA, 0x09, 0x09, "pci_gptr_pci2_ring", VPD_KEYWORD_PDG }, - { "pci_gptr_perv", 0xBB, 0x09, 0x09, "pci_gptr_perv_ring", VPD_KEYWORD_PDG }, - { "pci_gptr_pll", 0xBC, 0x09, 0x09, "pci_gptr_pll_ring", VPD_KEYWORD_PDG }, - { "pci_time", 0xBD, 0x09, 0x09, "pci_time_ring", VPD_KEYWORD_PDG }, - { "perv_gptr_net", 0xBE, 0x00, 0x00, "perv_gptr_net_ring", VPD_KEYWORD_PDG }, - { "perv_gptr_occ", 0xBF, 0x00, 0x00, "perv_gptr_occ_ring", VPD_KEYWORD_PDG }, - { "perv_gptr_perv", 0xC0, 0x00, 0x00, "perv_gptr_perv_ring", VPD_KEYWORD_PDG }, - { "perv_gptr_pib", 0xC1, 0x00, 0x00, "perv_gptr_pib_ring", VPD_KEYWORD_PDG }, - { "perv_gptr_pll", 0xC2, 0x00, 0x00, "perv_gptr_pll_ring", VPD_KEYWORD_PDG }, - { "perv_time", 0xC3, 0x00, 0x00, "perv_time_ring", VPD_KEYWORD_PDG }, - { "xb_gptr_iox", 0xC4, 0x04, 0x04, "xb_gptr_iox_ring", VPD_KEYWORD_PDG }, - { "xb_gptr_iopci", 0xC5, 0x04, 0x04, "xb_gptr_iopci_ring", VPD_KEYWORD_PDG }, - { "xb_gptr_pben", 0xC6, 0x04, 0x04, "xb_gptr_pben_ring", VPD_KEYWORD_PDG }, - { "xb_gptr_perv", 0xC7, 0x04, 0x04, "xb_gptr_perv_ring", VPD_KEYWORD_PDG }, - { "xb_time", 0xC8, 0x04, 0x04, "xb_time_ring", VPD_KEYWORD_PDG }, + /* ringName ringId chipletId ringNameImg mvpdKeyword wc */ + /* min max */ + {"ab_gptr_ab", 0xA0, 0x08, 0x08, "ab_gptr_ab_ring", VPD_KEYWORD_PDG, 0}, + {"ab_gptr_ioa", 0xA1, 0x08, 0x08, "ab_gptr_ioa_ring", VPD_KEYWORD_PDG, 0}, + {"ab_gptr_perv", 0xA2, 0x08, 0x08, "ab_gptr_perv_ring", VPD_KEYWORD_PDG, 0}, + {"ab_gptr_pll", 0xA3, 0x08, 0x08, "ab_gptr_pll_ring", VPD_KEYWORD_PDG, 0}, + {"ab_time", 0xA4, 0x08, 0x08, "ab_time_ring", VPD_KEYWORD_PDG, 0}, + {"ex_gptr_core", 0xA5, 0xFF, 0xFF, "ex_gptr_core_ring", VPD_KEYWORD_PDG, 0}, //Chip specific + {"ex_gptr_dpll", 0xA6, 0xFF, 0xFF, "ex_gptr_dpll_ring", VPD_KEYWORD_PDG, 0}, //Chip specific + {"ex_gptr_l2", 0xA7, 0xFF, 0xFF, "ex_gptr_l2_ring", VPD_KEYWORD_PDG, 0}, //Chip specific + {"ex_gptr_l3", 0xA8, 0xFF, 0xFF, "ex_gptr_l3_ring", VPD_KEYWORD_PDG, 0}, //Chip specific + {"ex_gptr_l3refr", 0xA9, 0xFF, 0xFF, "ex_gptr_l3refr_ring", VPD_KEYWORD_PDG, 0}, //Chip specific + {"ex_gptr_perv", 0xAA, 0xFF, 0xFF, "ex_gptr_perv_ring", VPD_KEYWORD_PDG, 0}, //Chip specific + {"ex_time_core", 0xAB, 0x10, 0x1F, "ex_time_core_ring", VPD_KEYWORD_PDG, 0}, //Chiplet specfc + {"ex_time_eco", 0xAC, 0x10, 0x1F, "ex_time_eco_ring", VPD_KEYWORD_PDG, 0}, //Chiplet specfc + {"pb_gptr_dmipll", 0xAD, 0x02, 0x02, "pb_gptr_dmipll_ring", VPD_KEYWORD_PDG, 0}, + {"pb_gptr_mcr", 0xAE, 0x02, 0x02, "pb_gptr_mcr_ring", VPD_KEYWORD_PDG, 0}, + {"pb_gptr_nest", 0xAF, 0x02, 0x02, "pb_gptr_nest_ring", VPD_KEYWORD_PDG, 0}, + {"pb_gptr_nx", 0xB0, 0x02, 0x02, "pb_gptr_nx_ring", VPD_KEYWORD_PDG, 0}, + {"pb_gptr_pcis", 0xB1, 0x02, 0x02, "pb_gptr_pcis_ring", VPD_KEYWORD_PDG, 0}, + {"pb_gptr_perv", 0xB2, 0x02, 0x02, "pb_gptr_perv_ring", VPD_KEYWORD_PDG, 0}, + {"pb_time", 0xB3, 0x02, 0x02, "pb_time_ring", VPD_KEYWORD_PDG, 0}, + {"pb_time_mcr", 0xB4, 0x02, 0x02, "pb_time_mcr_ring", VPD_KEYWORD_PDG, 0}, + {"pb_time_nx", 0xB5, 0x02, 0x02, "pb_time_nx_ring", VPD_KEYWORD_PDG, 0}, + {"pci_gptr_iopci", 0xB6, 0x09, 0x09, "pci_gptr_iopci_ring", VPD_KEYWORD_PDG, 0}, + {"pci_gptr_pbf", 0xB7, 0x09, 0x09, "pci_gptr_pbf_ring", VPD_KEYWORD_PDG, 0}, + {"pci_gptr_pci0", 0xB8, 0x09, 0x09, "pci_gptr_pci0_ring", VPD_KEYWORD_PDG, 0}, + {"pci_gptr_pci1", 0xB9, 0x09, 0x09, "pci_gptr_pci1_ring", VPD_KEYWORD_PDG, 0}, + {"pci_gptr_pci2", 0xBA, 0x09, 0x09, "pci_gptr_pci2_ring", VPD_KEYWORD_PDG, 0}, + {"pci_gptr_perv", 0xBB, 0x09, 0x09, "pci_gptr_perv_ring", VPD_KEYWORD_PDG, 0}, + {"pci_gptr_pll", 0xBC, 0x09, 0x09, "pci_gptr_pll_ring", VPD_KEYWORD_PDG, 0}, + {"pci_time", 0xBD, 0x09, 0x09, "pci_time_ring", VPD_KEYWORD_PDG, 0}, + {"perv_gptr_net", 0xBE, 0x00, 0x00, "perv_gptr_net_ring", VPD_KEYWORD_PDG, 0}, + {"perv_gptr_occ", 0xBF, 0x00, 0x00, "perv_gptr_occ_ring", VPD_KEYWORD_PDG, 0}, + {"perv_gptr_perv", 0xC0, 0x00, 0x00, "perv_gptr_perv_ring", VPD_KEYWORD_PDG, 0}, + {"perv_gptr_pib", 0xC1, 0x00, 0x00, "perv_gptr_pib_ring", VPD_KEYWORD_PDG, 0}, + {"perv_gptr_pll", 0xC2, 0x00, 0x00, "perv_gptr_pll_ring", VPD_KEYWORD_PDG, 0}, + {"perv_time", 0xC3, 0x00, 0x00, "perv_time_ring", VPD_KEYWORD_PDG, 0}, + {"xb_gptr_iopci", 0xC4, 0x04, 0x04, "xb_gptr_iopci_ring", VPD_KEYWORD_PDG, 0}, + {"xb_gptr_iox", 0xC5, 0x04, 0x04, "xb_gptr_iox_ring", VPD_KEYWORD_PDG, 0}, + {"xb_gptr_pben", 0xC6, 0x04, 0x04, "xb_gptr_pben_ring", VPD_KEYWORD_PDG, 0}, + {"xb_gptr_perv", 0xC7, 0x04, 0x04, "xb_gptr_perv_ring", VPD_KEYWORD_PDG, 0}, + {"xb_time", 0xC8, 0x04, 0x04, "xb_time_ring", VPD_KEYWORD_PDG, 0}, + {"pb_gptr_mcl", 0xC9, 0x02, 0x02, "pb_gptr_mcl_ring", VPD_KEYWORD_PDG, 0}, + {"pb_time_mcl", 0xCA, 0x02, 0x02, "pb_time_mcl_ring", VPD_KEYWORD_PDG, 0}, }; const RingIdList RING_ID_LIST_PR[] = { /* ringName ringId chipIdMin chipIdMax ringNameImg mvpdKeyword */ - { "ab_repr", 0xE0, 0x08, 0x08, "ab_repr_ring", VPD_KEYWORD_PDR }, - { "ex_repr_core", 0xE1, 0x10, 0x1F, "ex_repr_core_ring", VPD_KEYWORD_PDR }, - { "ex_repr_eco", 0xE2, 0x10, 0x1F, "ex_repr_eco_ring", VPD_KEYWORD_PDR }, - { "pb_repr", 0xE3, 0x02, 0x02, "pb_repr_ring", VPD_KEYWORD_PDR }, - { "pb_repr_mcr", 0xE4, 0x02, 0x02, "pb_repr_mcr_ring", VPD_KEYWORD_PDR }, - { "pb_repr_nx", 0xE5, 0x02, 0x02, "pb_repr_nx_ring", VPD_KEYWORD_PDR }, - { "pci_repr", 0xE6, 0x09, 0x09, "pci_repr_ring", VPD_KEYWORD_PDR }, - { "perv_repr", 0xE7, 0x00, 0x00, "perv_repr_ring", VPD_KEYWORD_PDR }, - { "perv_repr_net", 0xE8, 0x00, 0x00, "perv_repr_net_ring", VPD_KEYWORD_PDR }, - { "perv_repr_pib", 0xE9, 0x00, 0x00, "perv_repr_pib_ring", VPD_KEYWORD_PDR }, - { "xb_repr", 0xEA, 0x04, 0x04, "xb_repr_ring", VPD_KEYWORD_PDR }, + {"ab_repr", 0xE0, 0x08, 0x08, "ab_repr_ring", VPD_KEYWORD_PDR, 0}, + {"ex_repr_core", 0xE1, 0x10, 0x1F, "ex_repr_core_ring", VPD_KEYWORD_PDR, 1}, + {"ex_repr_eco", 0xE2, 0x10, 0x1F, "ex_repr_eco_ring", VPD_KEYWORD_PDR, 1}, + {"pb_repr", 0xE3, 0x02, 0x02, "pb_repr_ring", VPD_KEYWORD_PDR, 0}, + {"pb_repr_mcr", 0xE4, 0x02, 0x02, "pb_repr_mcr_ring", VPD_KEYWORD_PDR, 0}, + {"pb_repr_nx", 0xE5, 0x02, 0x02, "pb_repr_nx_ring", VPD_KEYWORD_PDR, 0}, + {"pci_repr", 0xE6, 0x09, 0x09, "pci_repr_ring", VPD_KEYWORD_PDR, 0}, + {"perv_repr", 0xE7, 0x00, 0x00, "perv_repr_ring", VPD_KEYWORD_PDR, 0}, + {"perv_repr_net", 0xE8, 0x00, 0x00, "perv_repr_net_ring", VPD_KEYWORD_PDR, 0}, + {"perv_repr_pib", 0xE9, 0x00, 0x00, "perv_repr_pib_ring", VPD_KEYWORD_PDR, 0}, + {"xb_repr", 0xEA, 0x04, 0x04, "xb_repr_ring", VPD_KEYWORD_PDR, 0}, + {"pb_repr_mcl", 0xEB, 0x02, 0x02, "pb_repr_mcl_ring", VPD_KEYWORD_PDR, 0}, }; const uint32_t RING_ID_LIST_PG_SIZE = sizeof(RING_ID_LIST_PG)/sizeof(RING_ID_LIST_PG[0]); const uint32_t RING_ID_LIST_PR_SIZE = sizeof(RING_ID_LIST_PR)/sizeof(RING_ID_LIST_PR[0]); -// The following defines are probably safe to decommision at this point. -const RingIdList RING_ID_LIST[] = { - /* ringName ringId chipIdMin chipIdMax ringNameImg mvpdKeyword */ - { "ab_repr", 0xE0, 0x08, 0x08, "ab_repr_ring", VPD_KEYWORD_PDR }, - { "ex_repr_core", 0xE1, 0x10, 0x1F, "ex_repr_core_ring", VPD_KEYWORD_PDR }, - { "ex_repr_eco", 0xE2, 0x10, 0x1F, "ex_repr_eco_ring", VPD_KEYWORD_PDR }, - { "pb_repr", 0xE3, 0x02, 0x02, "pb_repr_ring", VPD_KEYWORD_PDR }, - { "pb_repr_mcr", 0xE4, 0x02, 0x02, "pb_repr_mcr_ring", VPD_KEYWORD_PDR }, - { "pb_repr_nx", 0xE5, 0x02, 0x02, "pb_repr_nx_ring", VPD_KEYWORD_PDR }, - { "pci_repr", 0xE6, 0x09, 0x09, "pci_repr_ring", VPD_KEYWORD_PDR }, - { "perv_repr", 0xE7, 0x00, 0x00, "perv_repr_ring", VPD_KEYWORD_PDR }, - { "perv_repr_net", 0xE8, 0x00, 0x00, "perv_repr_net_ring", VPD_KEYWORD_PDR }, - { "perv_repr_pib", 0xE9, 0x00, 0x00, "perv_repr_pib_ring", VPD_KEYWORD_PDR }, - { "xb_repr", 0xEA, 0x04, 0x04, "xb_repr_ring", VPD_KEYWORD_PDR }, -}; -const uint32_t RING_ID_LIST_SIZE = sizeof(RING_ID_LIST)/sizeof(RING_ID_LIST[0]); - // get_vpd_ring_list_entry() retrieves the MVPD list entry based on either a ringName // or a ringId. If both are supplied, only the ringName is used. If ringName==NULL, // then the ringId is used. A pointer to the RingIdList is returned. int get_vpd_ring_list_entry(const char *i_ringName, - const uint8_t i_ringId, - RingIdList **i_ringIdList) + const uint8_t i_ringId, + RingIdList **i_ringIdList) { - int rc=0, NOT_FOUND=0, FOUND=1; + int rc=0, NOT_FOUND=1, FOUND=0; uint8_t iVpdType; uint8_t iRing; - RingIdList *ring_id_list=NULL; - uint8_t ring_id_list_size; + RingIdList *ring_id_list=NULL; + uint8_t ring_id_list_size; - rc = NOT_FOUND; - for (iVpdType=0; iVpdType<NUM_OF_VPD_TYPES; iVpdType++) { + rc = NOT_FOUND; + for (iVpdType=0; iVpdType<NUM_OF_VPD_TYPES; iVpdType++) { if (iVpdType==0) { - ring_id_list = (RingIdList*)RING_ID_LIST_PG; - ring_id_list_size = (uint32_t)RING_ID_LIST_PG_SIZE; - } - else { - ring_id_list = (RingIdList*)RING_ID_LIST_PR; - ring_id_list_size = (uint32_t)RING_ID_LIST_PR_SIZE; - } - // Search the MVPD reference lists. - if (i_ringName) { - for (iRing=0; iRing<ring_id_list_size; iRing++) { - if (strcmp((ring_id_list+iRing)->ringNameImg,i_ringName)==0) { - *i_ringIdList = ring_id_list+iRing; - return FOUND; - } - } - } - // Since ringName was not supplied, search for ringId. - // 2012-11-12: TBD. + ring_id_list = (RingIdList*)RING_ID_LIST_PG; + ring_id_list_size = (uint32_t)RING_ID_LIST_PG_SIZE; + } + else { + ring_id_list = (RingIdList*)RING_ID_LIST_PR; + ring_id_list_size = (uint32_t)RING_ID_LIST_PR_SIZE; + } + // Search the MVPD reference lists for either a: + // - ringName match with or w/o _image in the name, or + // - ringId match. + if (i_ringName) { + // Search for ringName match. + for (iRing=0; iRing<ring_id_list_size; iRing++) { + if ( strcmp((ring_id_list+iRing)->ringName, i_ringName)==0 || + strcmp((ring_id_list+iRing)->ringNameImg,i_ringName)==0 ) { + *i_ringIdList = ring_id_list+iRing; + return FOUND; + } + } + } + else { + // Search for ringId match (since ringName was not supplied). + for (iRing=0; iRing<ring_id_list_size; iRing++) { + if ((ring_id_list+iRing)->ringId==i_ringId) { + *i_ringIdList = ring_id_list+iRing; + return FOUND; + } + } + } - } - return rc; + } + return rc; } diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pgas.h b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pgas.h index ad0a99d78..f17f5395c 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pgas.h +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pgas.h @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -25,7 +25,7 @@ #define __PGAS__ -// $Id: pgas.h,v 1.17 2012/08/15 19:24:49 bcbrock Exp $ +// $Id: pgas.h,v 1.19 2013/01/09 23:01:38 bcbrock Exp $ // ** WARNING : This file is maintained as part of the OCC firmware. Do ** // ** not edit this file in the PMX area, the hardware procedure area, ** @@ -339,6 +339,14 @@ .endif .endm + // A register pair required to be A0, A1 in any order + .macro ..axay, reg1, reg2, err="Expecting A0, A1 in either order" + .if !((((\reg1) == A0) && ((\reg2) == A1)) || \ + (((\reg1) == A1) && ((\reg2) == A0))) + .error "\err" + .endif + .endm + // A register pair required to be the same register .macro ..same, dest, src @@ -750,6 +758,60 @@ .endm + ////////////////////////////////////////////////////////////////////// + // EXTRPRC - Extract and right-justify the PIB/PCB return code + // TPRCB[N]Z - Test PIB return code and branch if [not] zero + // TPRCBGT - Test PIB return code and branch if greater-than + // TPRCBLE - Test PIB return code and branch if less-then or equal + ////////////////////////////////////////////////////////////////////// + // + // To support cases where PORE code expects or must explicitly handle + // non-0 PIB return codes, the PIB return code and parity indication + // are stored in bits 32 (parity) and 33-35 (return code) of the IFR. + // These macros extract the four PIB/PCB status bits from the IFR and + // right-justifies them into the data register provided. For EXTRPRC + // that is the total function of the macro. The TPRCB[N]Z macros + // provide a simple non-destructive test and branch for zero (success) + // and non-zero (potential problem) codes after the extraction. + // + // In complex error handling scenarios one would typically compare the + // PIB return code against an upper-bound, e.g., the offline response + // (0x2), and then take further action. If the parity error bit is set + // then this would produce an aggregate "return code" higher than any + // that one would typically want to ignore. The TPRCBGT/TPRCBLE macros + // provide this function; however the test destroys the extracted + // return code so that if further analysis is required the code will + // need to be a extracted again. + ////////////////////////////////////////////////////////////////////// + + .macro extrprc, dest:req + ..data (\dest) + mr (\dest), IFR + extrdi (\dest), (\dest), 4, 32 + .endm + + .macro tprcbz, dest:req, target:req + extrprc (\dest) + braz (\dest), (\target) + .endm + + .macro tprcbnz, dest:req, target:req + extrprc (\dest) + branz (\dest), (\target) + .endm + + .macro tprcbgt, dest:req, target:req, bound:req + extrprc (\dest) + subs (\dest), (\dest), (\bound) + tfbugt (\dest), (\target) + .endm + + .macro tprcble, dest:req, target:req, bound:req + extrprc (\dest) + subs (\dest), (\dest), (\bound) + tfbule (\dest), (\target) + .endm + ////////////////////////////////////////////////////////////////////// // LPCS - Load Pervasive Chiplet from Scom address ////////////////////////////////////////////////////////////////////// diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_bitmanip.H b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_bitmanip.H index b9ba60424..337d9e63e 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_bitmanip.H +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_bitmanip.H @@ -1,26 +1,25 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/hwpf/hwp/build_winkle_images/proc_slw_build/pore_bitmanip.H $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_bitmanip.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __PORE_BITMANIP_H #define __PORE_BITMANIP_H @@ -354,6 +353,34 @@ .endm +/// Destructively insert a right-justified immediate value into a bit field +/// read out from a scom address +/// +/// \param[out] dest The destination Data register (D0/D1) to be modified. +/// +/// \param[in] b The bit positon (64-bit, big-endian) where the bit field +/// begins. +/// +/// \param[in] n The number of contiguous bits beginning at bit \a b to +/// modify +/// +/// \param[in] n The scom address to read +/// +/// \param[in] n The pervasive base register contain the correct base for +/// the address +/// +/// The execution of this macro computes: +/// +/// - dest <- (dest & ~BITS(b, n)) | ((imm & BITS(64 - n, n)) << (64 - n - b)) + + .macro insertbitsscom, dest:req, address:req, prv:req, b:req, n:req, imm:req + ..checkbits (\b), (\n) + ldandi (\dest), (\address), (\prv), ~BITS((\b), (\n)) + ori (\dest), (\dest), \ + (((\imm) & BITS(64 - (\n), (\n))) << ((64 - (\n) - (\b)))) + .endm + + /// Poll for a bit to be set in a SCOM register with timeout /// /// \param[in] dest A Data register (D0/D1) to use for the polling diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_inline.h b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_inline.h index 50dd6b7f9..23a5863ba 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_inline.h +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_inline.h @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -23,7 +23,7 @@ #ifndef __PORE_INLINE_H__ #define __PORE_INLINE_H__ -// $Id: pore_inline.h,v 1.16 2012/11/12 19:54:15 bcbrock Exp $ +// $Id: pore_inline.h,v 1.18 2013/02/06 01:10:35 bcbrock Exp $ // ** WARNING : This file is maintained as part of the OCC firmware. Do ** // ** not edit this file in the PMX area or the hardware procedure area ** @@ -53,6 +53,19 @@ extern "C" { #ifndef __ASSEMBLER__ +// PHYP tools do not support 'static' functions and variables as it interferes +// with their concurrent patch methodology. So when compiling for PHYP the +// PORE instruction "macros" are simply declared "inline". This also extends +// into the implementation C files - so under PHYP all previosuly local static +// functions will now be global functions. We retain 'static' to reduce code +// size and improve abstraction for OCC applications. + +#ifdef PPC_HYP +#define PORE_STATIC +#else +#define PORE_STATIC static +#endif + /// Error code strings from the PORE inline assembler/disassembler /// /// The PoreInlineContext object stores error codes that occur during @@ -543,25 +556,25 @@ pore_inline_disassemble(PoreInlineContext *ctx, PoreInlineDisassembly *dis); // Native PORE instruction assembly, using PGAS opcode names and operand -// ordering rules. +// ordering rules. // NOP, TRAP, RET -static inline int +PORE_STATIC inline int pore_NOP(PoreInlineContext *ctx) { return pore_inline_instruction1(ctx, PGAS_OPCODE_NOP, 0); } -static inline int +PORE_STATIC inline int pore_TRAP(PoreInlineContext *ctx) { return pore_inline_instruction1(ctx, PGAS_OPCODE_TRAP, 0); } -static inline int +PORE_STATIC inline int pore_RET(PoreInlineContext *ctx) { return pore_inline_instruction1(ctx, PGAS_OPCODE_RET, 0); @@ -573,7 +586,7 @@ pore_RET(PoreInlineContext *ctx) int pore_WAITS(PoreInlineContext *ctx, uint32_t cycles); -static inline int +PORE_STATIC inline int pore_HALT(PoreInlineContext *ctx) { return pore_inline_instruction1(ctx, PGAS_OPCODE_WAITS, 0); @@ -585,19 +598,19 @@ pore_HOOKI(PoreInlineContext *ctx, uint32_t index, uint64_t imm); // BRA, BSR, LOOP -static inline int +PORE_STATIC inline int pore_BRA(PoreInlineContext *ctx, PoreInlineLocation target) { return pore_inline_bra(ctx, PGAS_OPCODE_BRA, target); } -static inline int +PORE_STATIC inline int pore_BSR(PoreInlineContext *ctx, PoreInlineLocation target) { return pore_inline_bra(ctx, PGAS_OPCODE_BSR, target); } -static inline int +PORE_STATIC inline int pore_LOOP(PoreInlineContext *ctx, PoreInlineLocation target) { return pore_inline_bra(ctx, PGAS_OPCODE_LOOP, target); @@ -606,14 +619,14 @@ pore_LOOP(PoreInlineContext *ctx, PoreInlineLocation target) // BRAZ, BRANZ -static inline int +PORE_STATIC inline int pore_BRAZ(PoreInlineContext *ctx, int reg, PoreInlineLocation target) { return pore_inline_brac(ctx, PGAS_OPCODE_BRAZ, reg, target); } -static inline int +PORE_STATIC inline int pore_BRANZ(PoreInlineContext *ctx, int reg, PoreInlineLocation target) { return pore_inline_brac(ctx, PGAS_OPCODE_BRANZ, reg, target); @@ -622,7 +635,7 @@ pore_BRANZ(PoreInlineContext *ctx, int reg, PoreInlineLocation target) // CMPIBRAEQ, CMPIBRANE, CMPIBSREQ -static inline int +PORE_STATIC inline int pore_CMPIBRAEQ(PoreInlineContext *ctx, int reg, PoreInlineLocation target, uint64_t imm) { @@ -630,7 +643,7 @@ pore_CMPIBRAEQ(PoreInlineContext *ctx, } -static inline int +PORE_STATIC inline int pore_CMPIBRANE(PoreInlineContext *ctx, int reg, PoreInlineLocation target, uint64_t imm) { @@ -638,7 +651,7 @@ pore_CMPIBRANE(PoreInlineContext *ctx, } -static inline int +PORE_STATIC inline int pore_CMPIBSREQ(PoreInlineContext *ctx, int reg, PoreInlineLocation target, uint64_t imm) { @@ -648,12 +661,12 @@ pore_CMPIBSREQ(PoreInlineContext *ctx, // BRAD, BSRD -static inline int +PORE_STATIC inline int pore_BRAD(PoreInlineContext *ctx, int reg) { return pore_inline_brad(ctx, PGAS_OPCODE_BRAD, reg); } -static inline int +PORE_STATIC inline int pore_BSRD(PoreInlineContext *ctx, int reg) { return pore_inline_brad(ctx, PGAS_OPCODE_BSRD, reg); } @@ -661,19 +674,19 @@ pore_BSRD(PoreInlineContext *ctx, int reg) { // ANDI, ORI, XORI -static inline int +PORE_STATIC inline int pore_ANDI(PoreInlineContext *ctx, int dest, int src, uint64_t imm) { return pore_inline_ilogic(ctx, PGAS_OPCODE_ANDI, dest, src, imm); } -static inline int +PORE_STATIC inline int pore_ORI(PoreInlineContext *ctx, int dest, int src, uint64_t imm) { return pore_inline_ilogic(ctx, PGAS_OPCODE_ORI, dest, src, imm); } -static inline int +PORE_STATIC inline int pore_XORI(PoreInlineContext *ctx, int dest, int src, uint64_t imm) { return pore_inline_ilogic(ctx, PGAS_OPCODE_XORI, dest, src, imm); @@ -682,31 +695,31 @@ pore_XORI(PoreInlineContext *ctx, int dest, int src, uint64_t imm) // AND, OR, XOR, ADD, SUB -static inline int +PORE_STATIC inline int pore_AND(PoreInlineContext *ctx, int dest, int src1, int src2) { return pore_inline_alurr(ctx, PGAS_OPCODE_AND, dest, src1, src2); } -static inline int +PORE_STATIC inline int pore_OR(PoreInlineContext *ctx, int dest, int src1, int src2) { return pore_inline_alurr(ctx, PGAS_OPCODE_OR, dest, src1, src2); } -static inline int +PORE_STATIC inline int pore_XOR(PoreInlineContext *ctx, int dest, int src1, int src2) { return pore_inline_alurr(ctx, PGAS_OPCODE_XOR, dest, src1, src2); } -static inline int +PORE_STATIC inline int pore_ADD(PoreInlineContext *ctx, int dest, int src1, int src2) { return pore_inline_alurr(ctx, PGAS_OPCODE_ADD, dest, src1, src2); } -static inline int +PORE_STATIC inline int pore_SUB(PoreInlineContext *ctx, int dest, int src1, int src2) { return pore_inline_alurr(ctx, PGAS_OPCODE_SUB, dest, src1, src2); @@ -715,13 +728,13 @@ pore_SUB(PoreInlineContext *ctx, int dest, int src1, int src2) // ADDS, SUBS -static inline int +PORE_STATIC inline int pore_ADDS(PoreInlineContext *ctx, int dest, int src, int imm) { return pore_inline_adds(ctx, PGAS_OPCODE_ADDS, dest, src, imm); } -static inline int +PORE_STATIC inline int pore_SUBS(PoreInlineContext *ctx, int dest, int src, int imm) { return pore_inline_adds(ctx, PGAS_OPCODE_SUBS, dest, src, imm); @@ -748,7 +761,7 @@ pore_LI(PoreInlineContext *ctx, int dest, uint64_t imm); // LD, LDANDI, STD, STI, BSI, BCI -static inline int +PORE_STATIC inline int pore_LD(PoreInlineContext *ctx, int dest, int32_t offset, int base) { return @@ -756,7 +769,7 @@ pore_LD(PoreInlineContext *ctx, int dest, int32_t offset, int base) PORE_INLINE_PSEUDO_LD, dest, offset, base, 0); } -static inline int +PORE_STATIC inline int pore_LDANDI(PoreInlineContext *ctx, int dest, int32_t offset, int base, uint64_t imm) { @@ -766,7 +779,7 @@ pore_LDANDI(PoreInlineContext *ctx, dest, offset, base, imm); } -static inline int +PORE_STATIC inline int pore_STD(PoreInlineContext *ctx, int src, int32_t offset, int base) { return @@ -774,7 +787,7 @@ pore_STD(PoreInlineContext *ctx, int src, int32_t offset, int base) PORE_INLINE_PSEUDO_STD, src, offset, base, 0); } -static inline int +PORE_STATIC inline int pore_STI(PoreInlineContext *ctx, int32_t offset, int base, uint64_t imm) { return @@ -782,7 +795,7 @@ pore_STI(PoreInlineContext *ctx, int32_t offset, int base, uint64_t imm) PGAS_OPCODE_STI, 0, offset, base, imm); } -static inline int +PORE_STATIC inline int pore_BSI(PoreInlineContext *ctx, int src, int32_t offset, int base, uint64_t imm) { @@ -791,7 +804,7 @@ pore_BSI(PoreInlineContext *ctx, PGAS_OPCODE_BSI, src, offset, base, imm); } -static inline int +PORE_STATIC inline int pore_BCI(PoreInlineContext *ctx, int src, int32_t offset, int base, uint64_t imm) { diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_inline_assembler.c b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_inline_assembler.c index 096595a78..492d25bd4 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_inline_assembler.c +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_inline_assembler.c @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: pore_inline_assembler.c,v 1.15 2012/11/12 19:54:15 bcbrock Exp $ +// $Id: pore_inline_assembler.c,v 1.18 2013/02/06 17:41:51 bcbrock Exp $ // ** WARNING : This file is maintained as part of the OCC firmware. Do ** // ** not edit this file in the PMX area or the hardware procedure area ** @@ -368,6 +368,9 @@ /// section will be disassembled as data. For complete information see the /// documentation for pore_inline_disassemble(). +#ifdef PPC_HYP +#include <HvPlicModule.H> +#endif #define __PORE_INLINE_ASSEMBLER_C__ #include "pore_inline.h" @@ -376,7 +379,7 @@ // Definitions of PORE register classes. These are predicates that return // 1 if the register is a member of the class, else 0. -static int +PORE_STATIC int pore_data(int reg) { return @@ -385,7 +388,7 @@ pore_data(int reg) } -static int +PORE_STATIC int pore_address(int reg) { return @@ -394,7 +397,7 @@ pore_address(int reg) } -static int +PORE_STATIC int pore_pervasive_chiplet_id(int reg) { return @@ -403,7 +406,7 @@ pore_pervasive_chiplet_id(int reg) } -static int +PORE_STATIC int pore_branch_compare_data(int reg) { return @@ -413,7 +416,7 @@ pore_branch_compare_data(int reg) } -static int +PORE_STATIC int pore_ls_destination(int reg) { return @@ -427,7 +430,7 @@ pore_ls_destination(int reg) } -static int +PORE_STATIC int pore_li_destination(int reg) { return @@ -441,7 +444,7 @@ pore_li_destination(int reg) } -static int +PORE_STATIC int pore_mr_source(int reg) { return @@ -459,7 +462,7 @@ pore_mr_source(int reg) (reg == EMR); } -static int +PORE_STATIC int pore_mr_destination(int reg) { return @@ -564,12 +567,11 @@ pore_inline_host64(unsigned long p) // 32-bit population count // -// This is a well-known divide-and-conquer algorithm, e.g. look on Wikipedia -// under "Hamming Weight". The idea is to compute sums of adjacent bit -// segments in parallel, in place. +// This is a well-known divide-and-conquer algorithm. The idea is to compute +// sums of adjacent bit segments in parallel, in place. -static int -popcount32(uint32_t x) +PORE_STATIC int +pore_popcount32(uint32_t x) { uint32_t m1 = 0x55555555; uint32_t m2 = 0x33333333; @@ -584,10 +586,10 @@ popcount32(uint32_t x) // 64-bit population count -static int -popcount64(uint64_t x) +PORE_STATIC int +pore_popcount64(uint64_t x) { - return popcount32(x & 0xffffffff) + popcount32(x >> 32); + return pore_popcount32(x & 0xffffffff) + pore_popcount32(x >> 32); } @@ -596,7 +598,7 @@ popcount64(uint64_t x) int pore_inline_parity(uint32_t instruction, uint64_t imd64) { - return (popcount32(instruction) + popcount64(imd64)) % 2; + return (pore_popcount32(instruction) + pore_popcount64(imd64)) % 2; } @@ -799,7 +801,7 @@ pore_inline_context_bump(PoreInlineContext *ctx, size_t bytes) // Allocation failure sets the context error code to either // PORE_INLINE_NO_MEMORY or PORE_INLINE_ALIGNMENT_ERROR. -static unsigned long +PORE_STATIC unsigned long pore_inline_allocate(PoreInlineContext *ctx, size_t bytes) { unsigned long p = 0; @@ -1229,7 +1231,7 @@ pore_LI(PoreInlineContext *ctx, int dest, uint64_t imm) // LD, LDANDI, STD, STI, BSI, BCI -static void +PORE_STATIC void pervasive_ima24(PoreInlineContext *ctx, int opcode, uint32_t offset, int base, uint64_t imm) { @@ -1254,7 +1256,7 @@ pervasive_ima24(PoreInlineContext *ctx, } -static void +PORE_STATIC void memory_ima24(PoreInlineContext *ctx, int opcode, uint32_t offset, int base, uint64_t imm) { @@ -1281,7 +1283,7 @@ memory_ima24(PoreInlineContext *ctx, } -static void +PORE_STATIC void ima24(PoreInlineContext *ctx, int opcode, uint32_t offset, int base, uint64_t imm) { @@ -1294,7 +1296,6 @@ ima24(PoreInlineContext *ctx, } } -#include <stdio.h> int pore_inline_load_store(PoreInlineContext *ctx, diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/sbe_xip_image.c b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/sbe_xip_image.c index 0160b7bd9..0e78bf540 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/sbe_xip_image.c +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/sbe_xip_image.c @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: sbe_xip_image.c,v 1.21 2012/09/18 20:16:49 bcbrock Exp $ +// $Id: sbe_xip_image.c,v 1.26 2013/03/13 23:28:17 cmolsen Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/sbe/sbe_xip_image.c,v $ //----------------------------------------------------------------------------- // *! (C) Copyright International Business Machines Corp. 2011 @@ -44,6 +44,10 @@ /// ensure that no memory outside of the putative bounds of the image is ever /// referenced during validation. +#ifdef PPC_HYP +#include <HvPlicModule.H> +#endif + #include <stddef.h> #include <stdint.h> #include <stdlib.h> @@ -55,6 +59,29 @@ // Local Functions //////////////////////////////////////////////////////////////////////////// +// PHYP has their own way of implementing the <string.h> functions. PHYP also +// does not allow static functions or data, so all of the XIP_STATIC functions +// defined here are global to PHYP. + +#ifdef PPC_HYP + +#ifndef _HVTYPES_H +#include <HvTypes.H> +#endif + +#define strcpy(dest, src) hvstrcpy(dest, src) +#define strlen(s) hvstrlen(s) +#define strcmp(s1, s2) hvstrcmp(s1, s2) + +#define XIP_STATIC + +#else // PPC_HYP + +#define XIP_STATIC static + +#endif // PPC_HYP + + #ifdef DEBUG_SBE_XIP_IMAGE // Debugging support, normally disabled. All of the formatted I/O you see in @@ -83,7 +110,7 @@ #define F0x016llx "0x%016" PRIx64 #define F0x012llx "0x%012" PRIx64 -static SBE_XIP_ERROR_STRINGS(sbe_xip_error_strings); +XIP_STATIC SBE_XIP_ERROR_STRINGS(sbe_xip_error_strings); #define TRACE_ERROR(x) \ ({ \ @@ -106,11 +133,11 @@ static SBE_XIP_ERROR_STRINGS(sbe_xip_error_strings); #if 0 -static uint32_t revle32(const uint32_t i_x); +XIP_STATIC uint32_t xipRevLe32(const uint32_t i_x); -static SBE_XIP_TYPE_STRINGS(type_strings); +XIP_STATIC SBE_XIP_TYPE_STRINGS(type_strings); -static void +XIP_STATIC void dumpToc(int index, SbeXipToc* toc) { printf("TOC entry %d @ %p\n" @@ -120,8 +147,8 @@ dumpToc(int index, SbeXipToc* toc) " iv_section = 0x%02x\n" " iv_elements = %d\n", index, toc, - revle32(toc->iv_id), - revle32(toc->iv_data), + xipRevLe32(toc->iv_id), + xipRevLe32(toc->iv_data), SBE_XIP_TYPE_STRING(type_strings, toc->iv_type), toc->iv_section, toc->iv_elements); @@ -131,7 +158,7 @@ dumpToc(int index, SbeXipToc* toc) #if 0 -static void +XIP_STATIC void dumpItem(SbeXipItem* item) { printf("SbeXipItem @ %p\n" @@ -153,7 +180,7 @@ dumpItem(SbeXipItem* item) #endif /* 0 */ -static void +XIP_STATIC void dumpSectionTable(const void* i_image) { int i, rc; @@ -193,8 +220,8 @@ dumpSectionTable(const void* i_image) /// Byte-reverse a 16-bit integer if on a little-endian machine -static uint16_t -revle16(const uint16_t i_x) +XIP_STATIC uint16_t +xipRevLe16(const uint16_t i_x) { uint16_t rx; @@ -214,8 +241,8 @@ revle16(const uint16_t i_x) /// Byte-reverse a 32-bit integer if on a little-endian machine -static uint32_t -revle32(const uint32_t i_x) +XIP_STATIC uint32_t +xipRevLe32(const uint32_t i_x) { uint32_t rx; @@ -237,8 +264,8 @@ revle32(const uint32_t i_x) /// Byte-reverse a 64-bit integer if on a little-endian machine -static uint64_t -revle64(const uint64_t i_x) +XIP_STATIC uint64_t +xipRevLe64(const uint64_t i_x) { uint64_t rx; @@ -264,52 +291,52 @@ revle64(const uint64_t i_x) /// What is the image link address? -static uint64_t -linkAddress(const void* i_image) +XIP_STATIC uint64_t +xipLinkAddress(const void* i_image) { - return revle64(((SbeXipHeader*)i_image)->iv_linkAddress); + return xipRevLe64(((SbeXipHeader*)i_image)->iv_linkAddress); } /// What is the image size? -static uint32_t -imageSize(const void* i_image) +XIP_STATIC uint32_t +xipImageSize(const void* i_image) { - return revle32(((SbeXipHeader*)i_image)->iv_imageSize); + return xipRevLe32(((SbeXipHeader*)i_image)->iv_imageSize); } /// Set the image size -static void -setImageSize(void* io_image, const size_t i_size) +XIP_STATIC void +xipSetImageSize(void* io_image, const size_t i_size) { - ((SbeXipHeader*)io_image)->iv_imageSize = revle32(i_size); + ((SbeXipHeader*)io_image)->iv_imageSize = xipRevLe32(i_size); } /// Re-establish the required final alignment -static void -finalAlignment(void* io_image) +XIP_STATIC void +xipFinalAlignment(void* io_image) { uint32_t size; - size = imageSize(io_image); + size = xipImageSize(io_image); if ((size % SBE_XIP_FINAL_ALIGNMENT) != 0) { - setImageSize(io_image, - size + (SBE_XIP_FINAL_ALIGNMENT - - (size % SBE_XIP_FINAL_ALIGNMENT))); + xipSetImageSize(io_image, + size + (SBE_XIP_FINAL_ALIGNMENT - + (size % SBE_XIP_FINAL_ALIGNMENT))); } } /// Compute a host address from an image address and offset -static void* -hostAddressFromOffset(const void* i_image, const uint32_t offset) +XIP_STATIC void* +xipHostAddressFromOffset(const void* i_image, const uint32_t offset) { return (void*)((unsigned long)i_image + offset); } @@ -317,29 +344,34 @@ hostAddressFromOffset(const void* i_image, const uint32_t offset) /// Convert a PORE address to a host address -static void* -pore2Host(const void* i_image, const uint64_t i_poreAddress) +XIP_STATIC void* +xipPore2Host(const void* i_image, const uint64_t i_poreAddress) { - return hostAddressFromOffset(i_image, - i_poreAddress - linkAddress(i_image)); + return xipHostAddressFromOffset(i_image, + i_poreAddress - xipLinkAddress(i_image)); } -static int -validatePoreAddress(const void* i_image, - const uint64_t i_poreAddress, - const uint32_t size) +XIP_STATIC int +xipValidatePoreAddress(const void* i_image, + const uint64_t i_poreAddress, + const uint32_t size) { int rc; - if ((i_poreAddress < linkAddress(i_image)) || - (i_poreAddress > (linkAddress(i_image) + imageSize(i_image) - size))) { + if ((i_poreAddress < xipLinkAddress(i_image)) || + (i_poreAddress > (xipLinkAddress(i_image) + + xipImageSize(i_image) - + size))) { rc = TRACE_ERRORX(SBE_XIP_INVALID_ARGUMENT, - "The PORE address " F0x012llx " is outside the bounds " - "of the image (" F0x012llx ":" F0x012llx ") for %u-byte access.\n", + "The PORE address " F0x012llx + " is outside the bounds " + "of the image (" + F0x012llx ":" F0x012llx + ") for %u-byte access.\n", i_poreAddress, - linkAddress(i_image), - linkAddress(i_image) + imageSize(i_image) - 1, + xipLinkAddress(i_image), + xipLinkAddress(i_image) + xipImageSize(i_image) - 1, size); } else { rc = 0; @@ -350,17 +382,17 @@ validatePoreAddress(const void* i_image, /// Get the magic number from the image -static uint64_t -magic(const void* i_image) +XIP_STATIC uint64_t +xipMagic(const void* i_image) { - return revle64(((SbeXipHeader*)i_image)->iv_magic); + return xipRevLe64(((SbeXipHeader*)i_image)->iv_magic); } /// Get the header version from the image -static uint8_t -headerVersion(const void* i_image) +XIP_STATIC uint8_t +xipHeaderVersion(const void* i_image) { return ((SbeXipHeader*)i_image)->iv_headerVersion; } @@ -368,8 +400,8 @@ headerVersion(const void* i_image) /// Has the image been normalized? -static uint8_t -normalized(const void* i_image) +XIP_STATIC uint8_t +xipNormalized(const void* i_image) { return ((SbeXipHeader*)i_image)->iv_normalized; } @@ -377,8 +409,8 @@ normalized(const void* i_image) /// Has the image TOC been sorted? -static uint8_t -sorted(const void* i_image) +XIP_STATIC uint8_t +xipSorted(const void* i_image) { return ((SbeXipHeader*)i_image)->iv_tocSorted; } @@ -387,8 +419,8 @@ sorted(const void* i_image) /// A quick check that the image exists, has the correct magic and header /// version, and optionally is normalized. -static int -quickCheck(const void* i_image, const int i_normalizationRequired) +XIP_STATIC int +xipQuickCheck(const void* i_image, const int i_normalizationRequired) { int rc; @@ -400,21 +432,22 @@ quickCheck(const void* i_image, const int i_normalizationRequired) "Image pointer is NULL (0)\n"); break; } - if ((magic(i_image) >> 32) != SBE_XIP_MAGIC) { + if ((xipMagic(i_image) >> 32) != SBE_XIP_MAGIC) { rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR, "Magic number mismatch; Found " "" F0x016llx ", expected 0x%08x........\n", - magic(i_image), SBE_XIP_MAGIC); + xipMagic(i_image), SBE_XIP_MAGIC); break; } - if ((headerVersion(i_image)) != SBE_XIP_HEADER_VERSION) { + if ((xipHeaderVersion(i_image)) != SBE_XIP_HEADER_VERSION) { rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR, "Header version mismatch; Expecting %d, " "found %d\n", - SBE_XIP_HEADER_VERSION, headerVersion(i_image)); + SBE_XIP_HEADER_VERSION, + xipHeaderVersion(i_image)); break; } - if (i_normalizationRequired && !normalized(i_image)) { + if (i_normalizationRequired && !xipNormalized(i_image)) { rc = TRACE_ERRORX(SBE_XIP_NOT_NORMALIZED, "Image not normalized\n"); break; @@ -427,17 +460,17 @@ quickCheck(const void* i_image, const int i_normalizationRequired) /// Convert a 32-bit relocatable offset to a full PORE 48-bit address -static uint64_t -fullAddress(const void* i_image, uint32_t offset) +XIP_STATIC uint64_t +xipFullAddress(const void* i_image, uint32_t offset) { - return (linkAddress(i_image) & 0x0000ffff00000000ull) + offset; + return (xipLinkAddress(i_image) & 0x0000ffff00000000ull) + offset; } /// Translate a section table entry -static void -translateSection(SbeXipSection* o_dest, const SbeXipSection* i_src) +XIP_STATIC void +xipTranslateSection(SbeXipSection* o_dest, const SbeXipSection* i_src) { #ifndef _BIG_ENDIAN @@ -445,8 +478,8 @@ translateSection(SbeXipSection* o_dest, const SbeXipSection* i_src) #error This code assumes the SBE-XIP header version 8 layout #endif - o_dest->iv_offset = revle32(i_src->iv_offset); - o_dest->iv_size = revle32(i_src->iv_size); + o_dest->iv_offset = xipRevLe32(i_src->iv_offset); + o_dest->iv_size = xipRevLe32(i_src->iv_size); o_dest->iv_alignment = i_src->iv_alignment; o_dest->iv_reserved8[0] = 0; o_dest->iv_reserved8[1] = 0; @@ -461,8 +494,8 @@ translateSection(SbeXipSection* o_dest, const SbeXipSection* i_src) /// Translate a TOC entry -static void -translateToc(SbeXipToc* o_dest, SbeXipToc* i_src) +XIP_STATIC void +xipTranslateToc(SbeXipToc* o_dest, SbeXipToc* i_src) { #ifndef _BIG_ENDIAN @@ -470,8 +503,8 @@ translateToc(SbeXipToc* o_dest, SbeXipToc* i_src) #error This code assumes the SBE-XIP header version 8 layout #endif - o_dest->iv_id = revle32(i_src->iv_id); - o_dest->iv_data = revle32(i_src->iv_data); + o_dest->iv_id = xipRevLe32(i_src->iv_id); + o_dest->iv_data = xipRevLe32(i_src->iv_data); o_dest->iv_type = i_src->iv_type; o_dest->iv_section = i_src->iv_section; o_dest->iv_elements = i_src->iv_elements; @@ -486,8 +519,8 @@ translateToc(SbeXipToc* o_dest, SbeXipToc* i_src) /// Find the final (highest-address) section of the image -static int -finalSection(const void* i_image, int* o_sectionId) +XIP_STATIC int +xipFinalSection(const void* i_image, int* o_sectionId) { int i, rc; uint32_t offset; @@ -514,10 +547,10 @@ finalSection(const void* i_image, int* o_sectionId) /// Return a pointer to an image-format section table entry -static int -getSectionPointer(const void* i_image, - const int i_sectionId, - SbeXipSection** o_imageSection) +XIP_STATIC int +xipGetSectionPointer(const void* i_image, + const int i_sectionId, + SbeXipSection** o_imageSection) { int rc; @@ -534,18 +567,18 @@ getSectionPointer(const void* i_image, /// Restore a section table entry from host format to image format. -static int -putSection(const void* i_image, - const int i_sectionId, - SbeXipSection* i_hostSection) +XIP_STATIC int +xipPutSection(const void* i_image, + const int i_sectionId, + SbeXipSection* i_hostSection) { int rc; SbeXipSection *imageSection; - rc = getSectionPointer(i_image, i_sectionId, &imageSection); + rc = xipGetSectionPointer(i_image, i_sectionId, &imageSection); if (!rc) { - translateSection(imageSection, i_hostSection); + xipTranslateSection(imageSection, i_hostSection); } return rc; @@ -554,15 +587,16 @@ putSection(const void* i_image, /// Set the offset of a section -static int -setSectionOffset(void* io_image, const int i_section, const uint32_t i_offset) +XIP_STATIC int +xipSetSectionOffset(void* io_image, const int i_section, + const uint32_t i_offset) { SbeXipSection* section; int rc; - rc = getSectionPointer(io_image, i_section, §ion); + rc = xipGetSectionPointer(io_image, i_section, §ion); if (!rc) { - section->iv_offset = revle32(i_offset); + section->iv_offset = xipRevLe32(i_offset); } return rc; } @@ -570,15 +604,15 @@ setSectionOffset(void* io_image, const int i_section, const uint32_t i_offset) /// Set the size of a section -static int -setSectionSize(void* io_image, const int i_section, const uint32_t i_size) +XIP_STATIC int +xipSetSectionSize(void* io_image, const int i_section, const uint32_t i_size) { SbeXipSection* section; int rc; - rc = getSectionPointer(io_image, i_section, §ion); + rc = xipGetSectionPointer(io_image, i_section, §ion); if (!rc) { - section->iv_size = revle32(i_size); + section->iv_size = xipRevLe32(i_size); } return rc; } @@ -591,11 +625,11 @@ setSectionSize(void* io_image, const int i_section, const uint32_t i_size) // section contains the address - if none then the image is corrupted. We can // (must) use the 32-bit offset form of the address here. -static int -pore2Section(const void* i_image, - const uint64_t i_poreAddress, - int* o_section, - uint32_t* o_offset) +XIP_STATIC int +xipPore2Section(const void* i_image, + const uint64_t i_poreAddress, + int* o_section, + uint32_t* o_offset) { int rc, sectionId; SbeXipSection section; @@ -604,19 +638,20 @@ pore2Section(const void* i_image, do { rc = 0; - if ((i_poreAddress < linkAddress(i_image)) || - (i_poreAddress > (linkAddress(i_image) + imageSize(i_image)))) { + if ((i_poreAddress < xipLinkAddress(i_image)) || + (i_poreAddress > + (xipLinkAddress(i_image) + xipImageSize(i_image)))) { rc = TRACE_ERRORX(SBE_XIP_INVALID_ARGUMENT, "pore2section: The i_poreAddress argument " "(" F0x016llx ")\nis outside the bounds of the " "image (" F0x016llx ":" F0x016llx ")\n", i_poreAddress, - linkAddress(i_image), - linkAddress(i_image) + imageSize(i_image)); + xipLinkAddress(i_image), + xipLinkAddress(i_image) + xipImageSize(i_image)); break; } - addressOffset = (i_poreAddress - linkAddress(i_image)) & 0xffffffff; + addressOffset = (i_poreAddress - xipLinkAddress(i_image)) & 0xffffffff; for (sectionId = 0; sectionId < SBE_XIP_SECTIONS; sectionId++) { rc = sbe_xip_get_section(i_image, sectionId, §ion); @@ -655,12 +690,12 @@ pore2Section(const void* i_image, /// /// All return values are optional. -static int -getToc(void* i_image, - SbeXipToc** o_toc, - size_t* o_entries, - int* o_sorted, - char** o_strings) +XIP_STATIC int +xipGetToc(void* i_image, + SbeXipToc** o_toc, + size_t* o_entries, + int* o_sorted, + char** o_strings) { int rc; SbeXipSection tocSection, stringsSection; @@ -670,7 +705,7 @@ getToc(void* i_image, if (rc) break; rc = sbe_xip_get_section(i_image, SBE_XIP_SECTION_STRINGS, - &stringsSection); + &stringsSection); if (rc) break; if (o_toc) { @@ -680,7 +715,7 @@ getToc(void* i_image, *o_entries = tocSection.iv_size / sizeof(SbeXipToc); } if (o_sorted) { - *o_sorted = sorted(i_image); + *o_sorted = xipSorted(i_image); } if (o_strings) { *o_strings = (char*)i_image + stringsSection.iv_offset; @@ -692,12 +727,12 @@ getToc(void* i_image, /// Compare two normalized TOC entries for sorting. -static int -compareToc(const SbeXipToc* i_a, const SbeXipToc* i_b, - const char* i_strings) +XIP_STATIC int +xipCompareToc(const SbeXipToc* i_a, const SbeXipToc* i_b, + const char* i_strings) { - return strcmp(i_strings + revle32(i_a->iv_id), - i_strings + revle32(i_b->iv_id)); + return strcmp(i_strings + xipRevLe32(i_a->iv_id), + i_strings + xipRevLe32(i_b->iv_id)); } @@ -705,9 +740,9 @@ compareToc(const SbeXipToc* i_a, const SbeXipToc* i_b, // Note: The stack requirement is limited to 256 bytes + minor local storage. -static void -quickSort(SbeXipToc* io_toc, int i_left, int i_right, - const char* i_strings) +XIP_STATIC void +xipQuickSort(SbeXipToc* io_toc, int i_left, int i_right, + const char* i_strings) { int i, j, left, right, sp; SbeXipToc pivot, temp; @@ -728,10 +763,10 @@ quickSort(SbeXipToc* io_toc, int i_left, int i_right, pivot = io_toc[(i + j) / 2]; while (i <= j) { - while (compareToc(&(io_toc[i]), &pivot, i_strings) < 0) { + while (xipCompareToc(&(io_toc[i]), &pivot, i_strings) < 0) { i++; } - while (compareToc(&(io_toc[j]), &pivot, i_strings) > 0) { + while (xipCompareToc(&(io_toc[j]), &pivot, i_strings) > 0) { j--; } if (i <= j) { @@ -756,8 +791,8 @@ quickSort(SbeXipToc* io_toc, int i_left, int i_right, /// TOC linear search -static int -linearSearch(void* i_image, const char* i_id, SbeXipToc** o_entry) +XIP_STATIC int +xipLinearSearch(void* i_image, const char* i_id, SbeXipToc** o_entry) { int rc; SbeXipToc *imageToc, hostToc; @@ -765,10 +800,10 @@ linearSearch(void* i_image, const char* i_id, SbeXipToc** o_entry) char* strings; *o_entry = 0; - rc = getToc(i_image, &imageToc, &entries, 0, &strings); + rc = xipGetToc(i_image, &imageToc, &entries, 0, &strings); if (!rc) { for (; entries; entries--, imageToc++) { - translateToc(&hostToc, imageToc); + xipTranslateToc(&hostToc, imageToc); if (strcmp(i_id, strings + hostToc.iv_id) == 0) { break; } @@ -787,8 +822,8 @@ linearSearch(void* i_image, const char* i_id, SbeXipToc** o_entry) /// A classic binary search of a (presumed) sorted array -static int -binarySearch(void* i_image, const char* i_id, SbeXipToc** o_entry) +XIP_STATIC int +xipBinarySearch(void* i_image, const char* i_id, SbeXipToc** o_entry) { int rc; SbeXipToc *imageToc; @@ -799,7 +834,7 @@ binarySearch(void* i_image, const char* i_id, SbeXipToc** o_entry) do { *o_entry = 0; - rc = getToc(i_image, &imageToc, &entries, &sorted, &strings); + rc = xipGetToc(i_image, &imageToc, &entries, &sorted, &strings); if (rc) break; if (!sorted) { @@ -811,7 +846,7 @@ binarySearch(void* i_image, const char* i_id, SbeXipToc** o_entry) right = entries - 1; while (left <= right) { next = (left + right) / 2; - sort = strcmp(i_id, strings + revle32(imageToc[next].iv_id)); + sort = strcmp(i_id, strings + xipRevLe32(imageToc[next].iv_id)); if (sort == 0) { *o_entry = &(imageToc[next]); break; @@ -835,8 +870,8 @@ binarySearch(void* i_image, const char* i_id, SbeXipToc** o_entry) /// The TOC is validated by searching for the entry, which will uncover /// duplicate entries or problems with sorting/searching. -static int -validateTocEntry(void* io_image, const SbeXipItem* i_item, void* io_arg) +XIP_STATIC int +xipValidateTocEntry(void* io_image, const SbeXipItem* i_item, void* io_arg) { int rc; SbeXipItem found; @@ -872,7 +907,7 @@ validateTocEntry(void* io_image, const SbeXipItem* i_item, void* io_arg) #define FNV_PRIME32 16777619u uint32_t -hash32(const char* s) +xipHash32(const char* s) { uint32_t hash; @@ -892,10 +927,10 @@ hash32(const char* s) // addresses in the TOC are actually 32-bit offsets in the address space named // in bits 16:31 of the link address of the image. -static int -normalizeToc(void* io_image, SbeXipToc *io_imageToc, - SbeXipHashedToc** io_fixedTocEntry, - size_t* io_fixedEntriesRemaining) +XIP_STATIC int +xipNormalizeToc(void* io_image, SbeXipToc *io_imageToc, + SbeXipHashedToc** io_fixedTocEntry, + size_t* io_fixedEntriesRemaining) { SbeXipToc hostToc; int idSection, dataSection; @@ -909,15 +944,16 @@ normalizeToc(void* io_image, SbeXipToc *io_imageToc, // sections/offsets of the Id string (which must be in .strings) and // the data. - translateToc(&hostToc, io_imageToc); + xipTranslateToc(&hostToc, io_imageToc); hostString = - (char*)pore2Host(io_image, fullAddress(io_image, hostToc.iv_id)); + (char*)xipPore2Host(io_image, + xipFullAddress(io_image, hostToc.iv_id)); - rc = pore2Section(io_image, - fullAddress(io_image, hostToc.iv_id), - &idSection, - &idOffset); + rc = xipPore2Section(io_image, + xipFullAddress(io_image, hostToc.iv_id), + &idSection, + &idOffset); if (rc) break; if (idSection != SBE_XIP_SECTION_STRINGS) { @@ -925,10 +961,10 @@ normalizeToc(void* io_image, SbeXipToc *io_imageToc, break; } - rc = pore2Section(io_image, - fullAddress(io_image, hostToc.iv_data), - &dataSection, - &dataOffset); + rc = xipPore2Section(io_image, + xipFullAddress(io_image, hostToc.iv_data), + &dataSection, + &dataOffset); if (rc) break; // Now replace the Id and data pointers with their offsets, and update @@ -953,8 +989,8 @@ normalizeToc(void* io_image, SbeXipToc *io_imageToc, break; } - (*io_fixedTocEntry)->iv_hash = revle32(hash32(hostString)); - (*io_fixedTocEntry)->iv_offset = revle16(hostToc.iv_data); + (*io_fixedTocEntry)->iv_hash = xipRevLe32(xipHash32(hostString)); + (*io_fixedTocEntry)->iv_offset = xipRevLe16(hostToc.iv_data); (*io_fixedTocEntry)->iv_type = hostToc.iv_type; (*io_fixedTocEntry)->iv_elements = hostToc.iv_elements; @@ -964,7 +1000,7 @@ normalizeToc(void* io_image, SbeXipToc *io_imageToc, // Finally update the TOC entry - translateToc(io_imageToc, &hostToc); + xipTranslateToc(io_imageToc, &hostToc); } while (0); @@ -975,8 +1011,8 @@ normalizeToc(void* io_image, SbeXipToc *io_imageToc, // Check for hash collisions in the .fixed mini-TOC. Note that endianness is // not an issue here, as we're comparing for equality. -static int -hashCollision(SbeXipHashedToc* i_fixedToc, size_t i_entries) +XIP_STATIC int +xipHashCollision(SbeXipHashedToc* i_fixedToc, size_t i_entries) { int rc; size_t i, j; @@ -1002,17 +1038,17 @@ hashCollision(SbeXipHashedToc* i_fixedToc, size_t i_entries) /// Decode a normalized image-format TOC entry into a host-format SbeXipItem /// structure -static int -decodeToc(void* i_image, - SbeXipToc* i_imageToc, - SbeXipItem* o_item) +XIP_STATIC int +xipDecodeToc(void* i_image, + SbeXipToc* i_imageToc, + SbeXipItem* o_item) { int rc; SbeXipToc hostToc; SbeXipSection dataSection, stringsSection; do { - if (!normalized(i_image)) { + if (!xipNormalized(i_image)) { rc = TRACE_ERROR(SBE_XIP_NOT_NORMALIZED); break; } @@ -1022,7 +1058,7 @@ decodeToc(void* i_image, // number of elements in the outgoing structure. The Id string is // always located in the TOC_STRINGS section. - translateToc(&hostToc, i_imageToc); + xipTranslateToc(&hostToc, i_imageToc); o_item->iv_toc = i_imageToc; o_item->iv_type = hostToc.iv_type; @@ -1051,7 +1087,7 @@ decodeToc(void* i_image, dataSection.iv_offset + hostToc.iv_data); o_item->iv_address = - linkAddress(i_image) + dataSection.iv_offset + hostToc.iv_data; + xipLinkAddress(i_image) + dataSection.iv_offset + hostToc.iv_data; o_item->iv_partial = 0; @@ -1062,8 +1098,8 @@ decodeToc(void* i_image, /// Sort the TOC -static int -sortToc(void* io_image) +XIP_STATIC int +xipSortToc(void* io_image) { int rc; SbeXipToc *hostToc; @@ -1071,15 +1107,15 @@ sortToc(void* io_image) char* strings; do { - rc = quickCheck(io_image, 1); + rc = xipQuickCheck(io_image, 1); if (rc) break; - if (sorted(io_image)) break; + if (xipSorted(io_image)) break; - rc = getToc(io_image, &hostToc, &entries, 0, &strings); + rc = xipGetToc(io_image, &hostToc, &entries, 0, &strings); if (rc) break; - quickSort(hostToc, 0, entries - 1, strings); + xipQuickSort(hostToc, 0, entries - 1, strings); ((SbeXipHeader*)io_image)->iv_tocSorted = 1; @@ -1093,9 +1129,9 @@ sortToc(void* io_image) // modified to reflect the pad, but the caller must modify the section size to // reflect the pad. -static int -padImage(void* io_image, uint32_t i_allocation, - uint32_t i_align, uint32_t* pad) +XIP_STATIC int +xipPadImage(void* io_image, uint32_t i_allocation, + uint32_t i_align, uint32_t* pad) { int rc; @@ -1110,18 +1146,18 @@ padImage(void* io_image, uint32_t i_allocation, break; } - *pad = imageSize(io_image) % i_align; + *pad = xipImageSize(io_image) % i_align; if (*pad != 0) { *pad = i_align - *pad; - if ((imageSize(io_image) + *pad) > i_allocation) { + if ((xipImageSize(io_image) + *pad) > i_allocation) { rc = TRACE_ERROR(SBE_XIP_WOULD_OVERFLOW); break; } - memset((void*)((unsigned long)io_image + imageSize(io_image)), + memset((void*)((unsigned long)io_image + xipImageSize(io_image)), 0, *pad); - setImageSize(io_image, imageSize(io_image) + *pad); + xipSetImageSize(io_image, xipImageSize(io_image) + *pad); } } while (0); @@ -1131,10 +1167,10 @@ padImage(void* io_image, uint32_t i_allocation, // Get the .fixed_toc section -static int -getFixedToc(void* io_image, - SbeXipHashedToc** o_imageToc, - size_t* o_entries) +XIP_STATIC int +xipGetFixedToc(void* io_image, + SbeXipHashedToc** o_imageToc, + size_t* o_entries) { int rc; SbeXipSection section; @@ -1157,8 +1193,8 @@ getFixedToc(void* io_image, // adequate. The TOC structures are also small so all byte-reversal is done // 'by hand' rather than with a translate-type API. -static int -fixedFind(void* i_image, const char* i_id, SbeXipItem* o_item) +XIP_STATIC int +xipFixedFind(void* i_image, const char* i_id, SbeXipItem* o_item) { int rc; SbeXipHashedToc* toc; @@ -1168,10 +1204,10 @@ fixedFind(void* i_image, const char* i_id, SbeXipItem* o_item) uint32_t offset; do { - rc = getFixedToc(i_image, &toc, &entries); + rc = xipGetFixedToc(i_image, &toc, &entries); if (rc) break; - for (hash = revle32(hash32(i_id)); entries != 0; entries--, toc++) { + for (hash = xipRevLe32(xipHash32(i_id)); entries != 0; entries--, toc++) { if (toc->iv_hash == hash) break; } @@ -1184,7 +1220,7 @@ fixedFind(void* i_image, const char* i_id, SbeXipItem* o_item) // The caller may have requested a lookup only (o_item == 0), in which // case we're done. Otherwise we create a partial SbeXipItem and - // populate the non-0 fields analogously to the decodeToc() + // populate the non-0 fields analogously to the xipDecodeToc() // routine. The data resides in the .fixed section in this case. if (o_item == 0) break; @@ -1204,10 +1240,104 @@ fixedFind(void* i_image, const char* i_id, SbeXipItem* o_item) break; } - offset = fixedSection.iv_offset + revle16(toc->iv_offset); + offset = fixedSection.iv_offset + xipRevLe16(toc->iv_offset); + + o_item->iv_imageData = (void*)((uint8_t*)i_image + offset); + o_item->iv_address = xipLinkAddress(i_image) + offset; + + } while (0); + + return rc; +} + + +// Search for an item in the special built-in TOC of header fields, and +// populate a partial TOC entry if requested. +// +// This facility was added to allow header data to be searched by name even +// when the TOC has been stripped. This API will only be used in the case of a +// stripped TOC since the header fields are also indexed in the main TOC. +// +// The table is allocated on the stack in order to make this code concurrently +// patchable in PHYP (although PHYP applications will never use this code). +// The table is small and unsorted so a linear search is adequate, and the +// stack requirememts are small. + +XIP_STATIC int +xipHeaderFind(void* i_image, const char* i_id, SbeXipItem* o_item) +{ + int rc; + unsigned i; + uint32_t offset; + SbeXipSection headerSection; + +#define HEADER_TOC(id, field, type) \ + {#id, offsetof(SbeXipHeader, field), type} + + struct HeaderToc { + + const char* iv_id; + uint16_t iv_offset; + uint8_t iv_type; + + } toc[] = { + + HEADER_TOC(magic, iv_magic, SBE_XIP_UINT64), + HEADER_TOC(entry_offset, iv_entryOffset, SBE_XIP_UINT64), + HEADER_TOC(link_address, iv_linkAddress, SBE_XIP_UINT64), + + HEADER_TOC(image_size, iv_imageSize, SBE_XIP_UINT32), + HEADER_TOC(build_date, iv_buildDate, SBE_XIP_UINT32), + HEADER_TOC(build_time, iv_buildTime, SBE_XIP_UINT32), + + HEADER_TOC(header_version, iv_headerVersion, SBE_XIP_UINT8), + HEADER_TOC(toc_normalized, iv_normalized, SBE_XIP_UINT8), + HEADER_TOC(toc_sorted, iv_tocSorted, SBE_XIP_UINT8), + + HEADER_TOC(build_user, iv_buildUser, SBE_XIP_STRING), + HEADER_TOC(build_host, iv_buildHost, SBE_XIP_STRING), + + }; + + do { + + rc = SBE_XIP_ITEM_NOT_FOUND; + for (i = 0; i < (sizeof(toc) / sizeof(struct HeaderToc)); i++) { + if (strcmp(i_id, toc[i].iv_id) == 0) { + rc = 0; + break; + } + } + + if (rc) break; + + // The caller may have requested a lookup only (o_item == 0), in which + // case we're done. Otherwise we create a partial SbeXipItem and + // populate the non-0 fields analogously to the xipDecodeToc() + // routine. The data resides in the .fixed section in this case. + + if (o_item == 0) break; + + o_item->iv_partial = 1; + o_item->iv_toc = 0; + o_item->iv_id = 0; + + o_item->iv_type = toc[i].iv_type; + o_item->iv_elements = 1; /* True for now... */ + + rc = sbe_xip_get_section(i_image, SBE_XIP_SECTION_HEADER, + &headerSection); + if (rc) break; + + if (headerSection.iv_size == 0) { + rc = TRACE_ERROR(SBE_XIP_DATA_NOT_PRESENT); + break; + } + + offset = headerSection.iv_offset + toc[i].iv_offset; o_item->iv_imageData = (void*)((uint8_t*)i_image + offset); - o_item->iv_address = linkAddress(i_image) + offset; + o_item->iv_address = xipLinkAddress(i_image) + offset; } while (0); @@ -1253,13 +1383,14 @@ sbe_xip_validate(void* i_image, const uint32_t i_size) rc = TRACE_ERRORX(SBE_XIP_BUG, "C/Assembler size mismatch(%d/%d) " "for SbeXipHashedToc\n", - sizeof(SbeXipHashedToc), SIZE_OF_SBE_XIP_HASHED_TOC); + sizeof(SbeXipHashedToc), + SIZE_OF_SBE_XIP_HASHED_TOC); break; } // Validate the image pointer and magic number - rc = quickCheck(i_image, 0); + rc = xipQuickCheck(i_image, 0); if (rc) break; // Validate the image size @@ -1335,8 +1466,135 @@ sbe_xip_validate(void* i_image, const uint32_t i_size) size = hostHeader.iv_section[SBE_XIP_SECTION_TOC].iv_size; if (size != 0) { - if (normalized(i_image)) { - rc = sbe_xip_map_toc(i_image, validateTocEntry, 0); + if (xipNormalized(i_image)) { + rc = sbe_xip_map_toc(i_image, xipValidateTocEntry, 0); + if (rc) break; + } + } + } while (0); + return rc; +} + + +int +sbe_xip_validate2(void* i_image, const uint32_t i_size, const uint32_t i_maskIgnores) +{ + SbeXipHeader hostHeader; + int rc = 0, i; + uint32_t linkAddress, imageSize, extent, offset, size; + uint8_t alignment; + + sbe_xip_translate_header(&hostHeader, (SbeXipHeader*)i_image); + + do { + + // Validate C/Assembler constraints. + + if (sizeof(SbeXipSection) != SIZE_OF_SBE_XIP_SECTION) { + rc = TRACE_ERRORX(SBE_XIP_BUG, + "C/Assembler size mismatch(%d/%d) " + "for SbeXipSection\n", + sizeof(SbeXipSection), SIZE_OF_SBE_XIP_SECTION); + break; + } + + if (sizeof(SbeXipToc) != SIZE_OF_SBE_XIP_TOC) { + rc = TRACE_ERRORX(SBE_XIP_BUG, + "C/Assembler size mismatch(%d/%d) " + "for SbeXipToc\n", + sizeof(SbeXipToc), SIZE_OF_SBE_XIP_TOC); + break; + } + + if (sizeof(SbeXipHashedToc) != SIZE_OF_SBE_XIP_HASHED_TOC) { + rc = TRACE_ERRORX(SBE_XIP_BUG, + "C/Assembler size mismatch(%d/%d) " + "for SbeXipHashedToc\n", + sizeof(SbeXipHashedToc), + SIZE_OF_SBE_XIP_HASHED_TOC); + break; + } + + // Validate the image pointer and magic number + + rc = xipQuickCheck(i_image, 0); + if (rc) break; + + // Validate the image size + + linkAddress = hostHeader.iv_linkAddress; + imageSize = hostHeader.iv_imageSize; + extent = linkAddress + imageSize; + + if (imageSize < sizeof(SbeXipHeader)) { + rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR, + "sbe_xip_validate2(%p, %u) : " + "The image size recorded in the image " + "(%u) is smaller than the header size.\n", + i_image, i_size, imageSize); + break; + } + if (imageSize != i_size && !(i_maskIgnores & SBE_XIP_IGNORE_FILE_SIZE)) { + rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR, + "sbe_xip_validate2(%p, %u) : " + "The image size recorded in the image " + "(%u) does not match the i_size parameter.\n", + i_image, i_size, imageSize); + break; + } + if (extent <= linkAddress) { + rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR, + "sbe_xip_validate2(%p, %u) : " + "Given the link address (%u) and the " + "image size, the image wraps the address space\n", + i_image, i_size, linkAddress); + break; + } + if ((imageSize % SBE_XIP_FINAL_ALIGNMENT) != 0) { + rc = TRACE_ERRORX(SBE_XIP_ALIGNMENT_ERROR, + "sbe_xip_validate2(%p, %u) : " + "The image size (%u) is not a multiple of %u\n", + i_image, i_size, imageSize, + SBE_XIP_FINAL_ALIGNMENT); + break; + } + + // Validate that all sections appear to be within the image + // bounds, and are aligned correctly. + + for (i = 0; i < SBE_XIP_SECTIONS; i++) { + + offset = hostHeader.iv_section[i].iv_offset; + size = hostHeader.iv_section[i].iv_size; + alignment = hostHeader.iv_section[i].iv_alignment; + + if ((offset > imageSize) || + ((offset + size) > imageSize) || + ((offset + size) < offset)) { + rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR, + "Section %d does not appear to be within " + "the bounds of the image\n" + "offset = %u, size = %u, image size = %u\n", + i, offset, size, imageSize); + break; + } + if ((offset % alignment) != 0) { + rc = TRACE_ERRORX(SBE_XIP_ALIGNMENT_ERROR, + "Section %d requires %d-byte initial " + "alignment but the section offset is %u\n", + i, alignment, offset); + break; + } + } + if (rc) break; + + // If the TOC exists and the image is normalized, validate each TOC + // entry. + + size = hostHeader.iv_section[SBE_XIP_SECTION_TOC].iv_size; + if (size != 0) { + if (xipNormalized(i_image)) { + rc = sbe_xip_map_toc(i_image, xipValidateTocEntry, 0); if (rc) break; } } @@ -1368,23 +1626,23 @@ sbe_xip_normalize(void* io_image) size_t tocEntries, fixedTocEntries, fixedEntriesRemaining; do { - rc = quickCheck(io_image, 0); + rc = xipQuickCheck(io_image, 0); if (rc) break; - if (!normalized(io_image)) { + if (!xipNormalized(io_image)) { - rc = getToc(io_image, &imageToc, &tocEntries, 0, 0); + rc = xipGetToc(io_image, &imageToc, &tocEntries, 0, 0); if (rc) break; - rc = getFixedToc(io_image, &fixedImageToc, &fixedTocEntries); + rc = xipGetFixedToc(io_image, &fixedImageToc, &fixedTocEntries); if (rc) break; fixedTocEntry = fixedImageToc; fixedEntriesRemaining = fixedTocEntries; for (; tocEntries--; imageToc++) { - rc = normalizeToc(io_image, imageToc, - &fixedTocEntry, &fixedEntriesRemaining); + rc = xipNormalizeToc(io_image, imageToc, + &fixedTocEntry, &fixedEntriesRemaining); if (rc) break; } @@ -1396,20 +1654,20 @@ sbe_xip_normalize(void* io_image) break; } - rc = hashCollision(fixedImageToc, fixedTocEntries); + rc = xipHashCollision(fixedImageToc, fixedTocEntries); if (rc) break; ((SbeXipHeader*)io_image)->iv_normalized = 1; } - rc = sortToc(io_image); + rc = xipSortToc(io_image); if (rc) break; for (i = 0; i < SBE_XIP_SECTIONS; i++) { rc = sbe_xip_get_section(io_image, i, §ion); if (rc) break; if (section.iv_size == 0) { - setSectionOffset(io_image, i, 0); + xipSetSectionOffset(io_image, i, 0); } } if (rc) break; @@ -1427,9 +1685,9 @@ sbe_xip_image_size(void* io_image, uint32_t* o_size) { int rc; - rc = quickCheck(io_image, 0); + rc = xipQuickCheck(io_image, 0); if (!rc) { - *o_size = imageSize(io_image); + *o_size = xipImageSize(io_image); } return rc; } @@ -1443,18 +1701,18 @@ sbe_xip_get_section(const void* i_image, int rc; SbeXipSection *imageSection; - rc = getSectionPointer(i_image, i_sectionId, &imageSection); + rc = xipGetSectionPointer(i_image, i_sectionId, &imageSection); if (!rc) { - translateSection(o_hostSection, imageSection); + xipTranslateSection(o_hostSection, imageSection); } return rc; } -// If the 'big' TOC is not present, search the mini-TOC that only indexes the -// fixed section. +// If the 'big' TOC is not present, search the mini-TOCs that only index the +// .fixed and .header sections. int sbe_xip_find(void* i_image, @@ -1467,21 +1725,24 @@ sbe_xip_find(void* i_image, SbeXipSection* tocSection; do { - rc = quickCheck(i_image, 1); + rc = xipQuickCheck(i_image, 1); if (rc) break; - rc = getSectionPointer(i_image, SBE_XIP_SECTION_TOC, &tocSection); + rc = xipGetSectionPointer(i_image, SBE_XIP_SECTION_TOC, &tocSection); if (rc) break; if (tocSection->iv_size == 0) { - rc = fixedFind(i_image, i_id, o_item); + rc = xipFixedFind(i_image, i_id, o_item); + if (rc) { + rc = xipHeaderFind(i_image, i_id, o_item); + } break; } - if (sorted(i_image)) { - rc = binarySearch(i_image, i_id, &toc); + if (xipSorted(i_image)) { + rc = xipBinarySearch(i_image, i_id, &toc); } else { - rc = linearSearch(i_image, i_id, &toc); + rc = xipLinearSearch(i_image, i_id, &toc); } if (rc) break; @@ -1490,7 +1751,7 @@ sbe_xip_find(void* i_image, } else { pitem = &item; } - rc = decodeToc(i_image, toc, pitem); + rc = xipDecodeToc(i_image, toc, pitem); if (rc) break; } while (0); @@ -1514,7 +1775,7 @@ sbe_xip_map_halt(void* io_image, uint32_t actualSize; do { - rc = quickCheck(io_image, 0); + rc = xipQuickCheck(io_image, 0); if (rc) break; rc = sbe_xip_get_section(io_image, SBE_XIP_SECTION_HALT, &haltSection); @@ -1526,7 +1787,7 @@ sbe_xip_map_halt(void* io_image, while (size) { rc = i_fn(io_image, - revle64(halt->iv_address), + xipRevLe64(halt->iv_address), halt->iv_string, io_arg); if (rc) break; @@ -1561,11 +1822,11 @@ typedef struct { } GetHaltStruct; -static int -getHaltMap(void* io_image, - const uint64_t i_poreAddress, - const char* i_rcString, - void* io_arg) +XIP_STATIC int +xipGetHaltMap(void* io_image, + const uint64_t i_poreAddress, + const char* i_rcString, + void* io_arg) { int rc; @@ -1592,10 +1853,10 @@ sbe_xip_get_halt(void* io_image, s.iv_address = i_poreAddress; do { - rc = quickCheck(io_image, 0); + rc = xipQuickCheck(io_image, 0); if (rc) break; - rc = sbe_xip_map_halt(io_image, getHaltMap, &s); + rc = sbe_xip_map_halt(io_image, xipGetHaltMap, &s); if (rc == 0) { rc = TRACE_ERRORX(SBE_XIP_ITEM_NOT_FOUND, "sbe_xip_get_halt: No HALT code is associated " @@ -1623,10 +1884,10 @@ sbe_xip_get_scalar(void *i_image, const char* i_id, uint64_t* o_data) *o_data = *((uint8_t*)(item.iv_imageData)); break; case SBE_XIP_UINT32: - *o_data = revle32(*((uint32_t*)(item.iv_imageData))); + *o_data = xipRevLe32(*((uint32_t*)(item.iv_imageData))); break; case SBE_XIP_UINT64: - *o_data = revle64(*((uint64_t*)(item.iv_imageData))); + *o_data = xipRevLe64(*((uint64_t*)(item.iv_imageData))); break; case SBE_XIP_ADDRESS: *o_data = item.iv_address; @@ -1663,10 +1924,10 @@ sbe_xip_get_element(void *i_image, *o_data = ((uint8_t*)(item.iv_imageData))[i_index]; break; case SBE_XIP_UINT32: - *o_data = revle32(((uint32_t*)(item.iv_imageData))[i_index]); + *o_data = xipRevLe32(((uint32_t*)(item.iv_imageData))[i_index]); break; case SBE_XIP_UINT64: - *o_data = revle64(((uint64_t*)(item.iv_imageData))[i_index]); + *o_data = xipRevLe64(((uint64_t*)(item.iv_imageData))[i_index]); break; default: rc = TRACE_ERROR(SBE_XIP_TYPE_ERROR); @@ -1708,10 +1969,10 @@ sbe_xip_read_uint64(const void *i_image, int rc; do { - rc = quickCheck(i_image, 0); + rc = xipQuickCheck(i_image, 0); if (rc) break; - rc = validatePoreAddress(i_image, i_poreAddress, 8); + rc = xipValidatePoreAddress(i_image, i_poreAddress, 8); if (rc) break; if (i_poreAddress % 8) { @@ -1720,7 +1981,7 @@ sbe_xip_read_uint64(const void *i_image, } *o_data = - revle64(*((uint64_t*)pore2Host(i_image, i_poreAddress))); + xipRevLe64(*((uint64_t*)xipPore2Host(i_image, i_poreAddress))); } while(0); @@ -1741,10 +2002,10 @@ sbe_xip_set_scalar(void* io_image, const char* i_id, const uint64_t i_data) *((uint8_t*)(item.iv_imageData)) = (uint8_t)i_data; break; case SBE_XIP_UINT32: - *((uint32_t*)(item.iv_imageData)) = revle32((uint32_t)i_data); + *((uint32_t*)(item.iv_imageData)) = xipRevLe32((uint32_t)i_data); break; case SBE_XIP_UINT64: - *((uint64_t*)(item.iv_imageData)) = revle64((uint64_t)i_data); + *((uint64_t*)(item.iv_imageData)) = xipRevLe64((uint64_t)i_data); break; default: rc = TRACE_ERROR(SBE_XIP_TYPE_ERROR); @@ -1779,11 +2040,11 @@ sbe_xip_set_element(void *i_image, break; case SBE_XIP_UINT32: ((uint32_t*)(item.iv_imageData))[i_index] = - revle32((uint32_t)i_data); + xipRevLe32((uint32_t)i_data); break; case SBE_XIP_UINT64: ((uint64_t*)(item.iv_imageData))[i_index] = - revle64((uint64_t)i_data); + xipRevLe64((uint64_t)i_data); break; default: rc = TRACE_ERROR(SBE_XIP_TYPE_ERROR); @@ -1832,10 +2093,10 @@ sbe_xip_write_uint64(void *io_image, int rc; do { - rc = quickCheck(io_image, 0); + rc = xipQuickCheck(io_image, 0); if (rc) break; - rc = validatePoreAddress(io_image, i_poreAddress, 8); + rc = xipValidatePoreAddress(io_image, i_poreAddress, 8); if (rc) break; if (i_poreAddress % 8) { @@ -1843,7 +2104,8 @@ sbe_xip_write_uint64(void *io_image, break; } - *((uint64_t*)pore2Host(io_image, i_poreAddress)) = revle64(i_data); + *((uint64_t*)xipPore2Host(io_image, i_poreAddress)) = + xipRevLe64(i_data); } while(0); @@ -1858,7 +2120,7 @@ sbe_xip_delete_section(void* io_image, const int i_sectionId) SbeXipSection section; do { - rc = quickCheck(io_image, 1); + rc = xipQuickCheck(io_image, 1); if (rc) break; rc = sbe_xip_get_section(io_image, i_sectionId, §ion); @@ -1871,7 +2133,7 @@ sbe_xip_delete_section(void* io_image, const int i_sectionId) if (section.iv_size == 0) break; - rc = finalSection(io_image, &final); + rc = xipFinalSection(io_image, &final); if (rc) break; if (final != i_sectionId) { @@ -1881,11 +2143,11 @@ sbe_xip_delete_section(void* io_image, const int i_sectionId) break; } - setImageSize(io_image, section.iv_offset); - setSectionOffset(io_image, i_sectionId, 0); - setSectionSize(io_image, i_sectionId, 0); + xipSetImageSize(io_image, section.iv_offset); + xipSetSectionOffset(io_image, i_sectionId, 0); + xipSetSectionSize(io_image, i_sectionId, 0); - finalAlignment(io_image); + xipFinalAlignment(io_image); } while (0); @@ -1893,6 +2155,11 @@ sbe_xip_delete_section(void* io_image, const int i_sectionId) } +#ifndef PPC_HYP + +// This API is not needed by PHYP procedures, and is elided since PHYP does +// not support malloc(). + int sbe_xip_duplicate_section(const void* i_image, const int i_sectionId, @@ -1905,7 +2172,7 @@ sbe_xip_duplicate_section(const void* i_image, *o_duplicate = 0; do { - rc = quickCheck(i_image, 0); + rc = xipQuickCheck(i_image, 0); if (rc) break; rc = sbe_xip_get_section(i_image, i_sectionId, §ion); @@ -1927,7 +2194,7 @@ sbe_xip_duplicate_section(const void* i_image, } memcpy(*o_duplicate, - hostAddressFromOffset(i_image, section.iv_offset), + xipHostAddressFromOffset(i_image, section.iv_offset), section.iv_size); @@ -1942,6 +2209,8 @@ sbe_xip_duplicate_section(const void* i_image, return rc; } +#endif // PPC_HYP + int sbe_xip_append(void* io_image, @@ -1957,7 +2226,7 @@ sbe_xip_append(void* io_image, uint32_t pad; do { - rc = quickCheck(io_image, 1); + rc = xipQuickCheck(io_image, 1); if (rc) break; rc = sbe_xip_get_section(io_image, i_sectionId, §ion); @@ -1971,16 +2240,17 @@ sbe_xip_append(void* io_image, // the image to the specified section alignment. Note that the // size of the previously final section does not change. - rc = padImage(io_image, i_allocation, section.iv_alignment, &pad); + rc = xipPadImage(io_image, i_allocation, section.iv_alignment, + &pad); if (rc) break; - section.iv_offset = imageSize(io_image); + section.iv_offset = xipImageSize(io_image); } else { // Otherwise, the section must be the final section in order to // continue. Remove any padding from the image. - rc = finalSection(io_image, &final); + rc = xipFinalSection(io_image, &final); if (rc) break; if (final != i_sectionId) { @@ -1989,7 +2259,7 @@ sbe_xip_append(void* io_image, "%d\n", i_sectionId); break; } - setImageSize(io_image, section.iv_offset + section.iv_size); + xipSetImageSize(io_image, section.iv_offset + section.iv_size); } @@ -1997,7 +2267,7 @@ sbe_xip_append(void* io_image, // parameter o_sectionOffset and copy the new data into the image (or // simply clear the space). - if ((imageSize(io_image) + i_size) > i_allocation) { + if ((xipImageSize(io_image) + i_size) > i_allocation) { rc = TRACE_ERROR(SBE_XIP_WOULD_OVERFLOW); break; } @@ -2005,7 +2275,8 @@ sbe_xip_append(void* io_image, *o_sectionOffset = section.iv_size; } - hostAddress = hostAddressFromOffset(io_image, imageSize(io_image)); + hostAddress = + xipHostAddressFromOffset(io_image, xipImageSize(io_image)); if (i_data == 0) { memset(hostAddress, 0, i_size); } else { @@ -2015,11 +2286,11 @@ sbe_xip_append(void* io_image, // Update the image size and section table. - setImageSize(io_image, imageSize(io_image) + i_size); - finalAlignment(io_image); + xipSetImageSize(io_image, xipImageSize(io_image) + i_size); + xipFinalAlignment(io_image); section.iv_size += i_size; - rc = putSection(io_image, i_sectionId, §ion); + rc = xipPutSection(io_image, i_sectionId, §ion); if (rc) break; @@ -2045,7 +2316,7 @@ sbe_xip_section2pore(const void* i_image, SbeXipSection section; do { - rc = quickCheck(i_image, 0); + rc = xipQuickCheck(i_image, 0); if (rc) break; rc = sbe_xip_get_section(i_image, i_sectionId, §ion); @@ -2061,7 +2332,7 @@ sbe_xip_section2pore(const void* i_image, break; } - *o_poreAddress = linkAddress(i_image) + section.iv_offset + i_offset; + *o_poreAddress = xipLinkAddress(i_image) + section.iv_offset + i_offset; if (*o_poreAddress % 4) { rc = TRACE_ERROR(SBE_XIP_ALIGNMENT_ERROR); @@ -2083,10 +2354,10 @@ sbe_xip_pore2section(const void* i_image, int rc; do { - rc = quickCheck(i_image, 0); + rc = xipQuickCheck(i_image, 0); if (rc) break; - rc = pore2Section(i_image, i_poreAddress, i_section, i_offset); + rc = xipPore2Section(i_image, i_poreAddress, i_section, i_offset); } while(0); @@ -2102,18 +2373,19 @@ sbe_xip_pore2host(const void* i_image, int rc; do { - rc = quickCheck(i_image, 0); + rc = xipQuickCheck(i_image, 0); if (rc) break; - if ((i_poreAddress < linkAddress(i_image)) || - (i_poreAddress > (linkAddress(i_image) + imageSize(i_image)))) { + if ((i_poreAddress < xipLinkAddress(i_image)) || + (i_poreAddress > + (xipLinkAddress(i_image) + xipImageSize(i_image)))) { rc = TRACE_ERROR(SBE_XIP_INVALID_ARGUMENT); break; } *o_hostAddress = - hostAddressFromOffset(i_image, - i_poreAddress - linkAddress(i_image)); + xipHostAddressFromOffset(i_image, + i_poreAddress - xipLinkAddress(i_image)); } while(0); return rc; @@ -2128,16 +2400,17 @@ sbe_xip_host2pore(const void* i_image, int rc; do { - rc = quickCheck(i_image, 0); + rc = xipQuickCheck(i_image, 0); if (rc) break; if ((i_hostAddress < i_image) || - (i_hostAddress > hostAddressFromOffset(i_image, imageSize(i_image)))) { + (i_hostAddress > + xipHostAddressFromOffset(i_image, xipImageSize(i_image)))) { rc = TRACE_ERROR(SBE_XIP_INVALID_ARGUMENT); break; } - *o_poreAddress = linkAddress(i_image) + + *o_poreAddress = xipLinkAddress(i_image) + ((unsigned long)i_hostAddress - (unsigned long)i_image); if (*o_poreAddress % 4) { rc = TRACE_ERROR(SBE_XIP_ALIGNMENT_ERROR); @@ -2161,9 +2434,9 @@ sbe_xip_translate_header(SbeXipHeader* o_dest, const SbeXipHeader* i_src) #error This code assumes the SBE-XIP header version 8 layout #endif - o_dest->iv_magic = revle64(i_src->iv_magic); - o_dest->iv_entryOffset = revle64(i_src->iv_entryOffset); - o_dest->iv_linkAddress = revle64(i_src->iv_linkAddress); + o_dest->iv_magic = xipRevLe64(i_src->iv_magic); + o_dest->iv_entryOffset = xipRevLe64(i_src->iv_entryOffset); + o_dest->iv_linkAddress = xipRevLe64(i_src->iv_linkAddress); for (i = 0; i < 5; i++) { o_dest->iv_reserved64[i] = 0; @@ -2173,12 +2446,12 @@ sbe_xip_translate_header(SbeXipHeader* o_dest, const SbeXipHeader* i_src) srcSection = i_src->iv_section; i < SBE_XIP_SECTIONS; i++, destSection++, srcSection++) { - translateSection(destSection, srcSection); + xipTranslateSection(destSection, srcSection); } - o_dest->iv_imageSize = revle32(i_src->iv_imageSize); - o_dest->iv_buildDate = revle32(i_src->iv_buildDate); - o_dest->iv_buildTime = revle32(i_src->iv_buildTime); + o_dest->iv_imageSize = xipRevLe32(i_src->iv_imageSize); + o_dest->iv_buildDate = xipRevLe32(i_src->iv_buildDate); + o_dest->iv_buildTime = xipRevLe32(i_src->iv_buildTime); for (i = 0; i < 5; i++) { o_dest->iv_reserved32[i] = 0; @@ -2220,14 +2493,14 @@ sbe_xip_map_toc(void* io_image, size_t entries; do { - rc = quickCheck(io_image, 0); + rc = xipQuickCheck(io_image, 0); if (rc) break; - rc = getToc(io_image, &imageToc, &entries, 0, 0); + rc = xipGetToc(io_image, &imageToc, &entries, 0, 0); if (rc) break; for (; entries--; imageToc++) { - rc = decodeToc(io_image, imageToc, &item); + rc = xipDecodeToc(io_image, imageToc, &item); if (rc) break; rc = i_fn(io_image, &item, io_arg); if (rc) break; @@ -2236,10 +2509,3 @@ sbe_xip_map_toc(void* io_image, return rc; } - - - - - - - diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/sbe_xip_image.h b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/sbe_xip_image.h index 3bf222ade..726113e73 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/sbe_xip_image.h +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/sbe_xip_image.h @@ -23,7 +23,7 @@ #ifndef __SBE_XIP_IMAGE_H #define __SBE_XIP_IMAGE_H -// $Id: sbe_xip_image.h,v 1.20 2013/02/06 04:48:45 bcbrock Exp $ +// $Id: sbe_xip_image.h,v 1.23 2013/03/20 21:41:53 cmolsen Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/sbe/sbe_xip_image.h,v $ //----------------------------------------------------------------------------- // *! (C) Copyright International Business Machines Corp. 2011 @@ -87,7 +87,7 @@ #define SBE_XIP_SECTION_STRINGS 8 #define SBE_XIP_SECTION_HALT 9 #define SBE_XIP_SECTION_PIBMEM0 10 -#define SBE_XIP_SECTION_PIBMEM1 11 +#define SBE_XIP_SECTION_DCRINGS 11 #define SBE_XIP_SECTION_RINGS 12 #define SBE_XIP_SECTION_SLW 13 #define SBE_XIP_SECTION_FIT 14 @@ -97,6 +97,23 @@ /// @} + +/// \defgroup sbe_xip_validate() ignore masks. +/// +/// These defines, when matched in sbe_xip_validate(), cause the validation +/// to skip the check of the corresponding property. The purpose is to more +/// effectively debug images that may be damaged and which have excess info +/// before or after the image. The latter will be the case when dumping the +/// image as a memory block without knowing where the image starts and ends. +/// +/// @{ + +#define SBE_XIP_IGNORE_FILE_SIZE (uint32_t)0x00000001 +#define SBE_XIP_IGNORE_ALL (uint32_t)0x80000000 + +/// @} + + #ifndef __ASSEMBLER__ /// Applications can expand this macro to create an array of section names. @@ -113,7 +130,7 @@ ".strings", \ ".halt", \ ".pibmem0", \ - ".pibmem1", \ + ".dcrings", \ ".rings", \ ".slw", \ ".fit", \ @@ -599,6 +616,9 @@ typedef struct { /// /// \param[in] i_size The putative size of the image /// +/// \param[in] i_maskIgnores Array of ignore bits representing which properties +/// should not be checked for in sbe_xip_validate2(). +/// /// This API should be called first by all applications that manipulate /// SBE-XIP images in host memory. The magic number is validated, and /// the image is checked for consistency of the section table and table of @@ -611,6 +631,9 @@ typedef struct { int sbe_xip_validate(void* i_image, const uint32_t i_size); +int +sbe_xip_validate2(void* i_image, const uint32_t i_size, const uint32_t i_maskIgnores); + /// Normalize the SBE-XIP image /// diff --git a/src/usr/hwpf/hwp/bus_training/io_run_training.C b/src/usr/hwpf/hwp/bus_training/io_run_training.C index 07ca1471d..a658a9cc0 100644 --- a/src/usr/hwpf/hwp/bus_training/io_run_training.C +++ b/src/usr/hwpf/hwp/bus_training/io_run_training.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: io_run_training.C,v 1.28 2013/01/28 20:19:06 jaswamin Exp $ +// $Id: io_run_training.C,v 1.32 2013/03/26 15:04:24 varkeykv Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -49,6 +49,190 @@ extern "C" { using namespace fapi; +// For clearing the FIR mask , used by io run training +ReturnCode clear_fir_mask_reg(const Target &i_target,fir_io_interface_t i_chip_interface){ + + ReturnCode rc; + uint64_t scom_address64=0; + ecmdDataBufferBase putscom_data64(64),temp(64); + FAPI_INF("io_run_training:In the Clear FIR MASK register function "); + //get the 64 bit data + temp.setDoubleWord(0,fir_clear_mask_reg_addr[i_chip_interface]); + scom_address64=temp.getDoubleWord(0); + + //do the putscom + rc=fapiPutScom( i_target, scom_address64, putscom_data64); + + return(rc); + +} + +// FIR Workaround Code -- Pre Training Section - HW205368 - procedure from Rob /Pete +ReturnCode fir_workaround_pre_training(const Target& master_target, io_interface_t master_interface,uint32_t master_group, const Target& slave_target, io_interface_t slave_interface,uint32_t slave_group, + ecmdDataBufferBase *slave_data_one_old,ecmdDataBufferBase *slave_data_two_old,ecmdDataBufferBase *master_data_one_old,ecmdDataBufferBase *master_data_two_old) +{ + ReturnCode rc; + //Start - Workaround Pre Training Section - HW205368 - procedure from Rob /Pete + + uint8_t max_group=1; + + if(master_interface==CP_FABRIC_X0){ + max_group=4; + } + + // Take backup of slave bad lane data restored by FW prior to training + FAPI_DBG("io_run_training: Saving Bad lane information for HW workaround "); + if(master_interface==CP_FABRIC_X0){ + for (int current_group = 0 ; current_group < max_group; current_group++){ + rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_0_15_pg, current_group, 0, slave_data_one_old[current_group]); + if(rc){return rc;} + rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_16_31_pg, current_group, 0, slave_data_two_old[current_group]); + if(rc){return rc;} + } + //Take backup of master bad lane data restored by FW prior to training + for (int current_group = 0 ; current_group < max_group; current_group++){ + rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_0_15_pg, current_group, 0, master_data_one_old[current_group]); + if(rc){return rc;} + rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_16_31_pg, current_group, 0, master_data_two_old[current_group]); + if(rc){return rc;} + } + }else{ + rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_0_15_pg, slave_group, 0, slave_data_one_old[0]); + if(rc){return rc;} + rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_16_31_pg, slave_group, 0, slave_data_two_old[0]); + if(rc){return rc;} + //Take backup of master bad lane data restored by FW prior to training + rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_0_15_pg, master_group, 0, master_data_one_old[0]); + if(rc){return rc;} + rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_16_31_pg, master_group, 0, master_data_two_old[0]); + if(rc){return rc;} + } + // End - Workaround HW205368 + return(rc); +} + +ReturnCode fir_workaround_post_training(const Target& master_target, io_interface_t master_interface,uint32_t master_group, const Target& slave_target, io_interface_t slave_interface,uint32_t slave_group, + ecmdDataBufferBase *slave_data_one_old,ecmdDataBufferBase *slave_data_two_old,ecmdDataBufferBase *master_data_one_old,ecmdDataBufferBase *master_data_two_old) +{ + ReturnCode rc; + //These buffers will store new bad lane info after training + ecmdDataBufferBase slave_data_one_new[4]; + ecmdDataBufferBase slave_data_two_new[4]; + ecmdDataBufferBase master_data_one_new[4]; + ecmdDataBufferBase master_data_two_new[4]; + fir_io_interface_t fir_master_interface=FIR_CP_IOMC0_P0; + fir_io_interface_t fir_slave_interface=FIR_CEN_DMI; + + uint8_t max_group=1; + + if(master_interface==CP_FABRIC_X0){ + max_group=4; + } + + FAPI_DBG("io_run_training : Starting post training HW workaround "); + // Start post training part of Workaround - HW205368 - procedure from Rob /Pete + // Read slave side bad lane data after training + if(master_interface==CP_FABRIC_X0){ + for (int current_group = 0 ; current_group < max_group; current_group++){ + rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_0_15_pg, current_group, 0, slave_data_one_new[current_group]); + if(rc){return rc;} + rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_16_31_pg, current_group, 0, slave_data_two_new[current_group]); + if(rc){return rc;} + } + //Take backup of master bad lane data restored by FW prior to training + for (int current_group = 0 ; current_group < max_group; current_group++){ + rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_0_15_pg, current_group, 0, master_data_one_new[current_group]); + if(rc){return rc;} + rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_16_31_pg, current_group, 0, master_data_two_new[current_group]); + if(rc){return rc;} + } + }else{ + rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_0_15_pg, slave_group, 0, slave_data_one_new[0]); + if(rc){return rc;} + rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_16_31_pg, slave_group, 0, slave_data_two_new[0]); + if(rc){return rc;} + //Take backup of master bad lane data restored by FW prior to training + rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_0_15_pg, master_group, 0, master_data_one_new[0]); + if(rc){return rc;} + rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_16_31_pg, master_group, 0, master_data_two_new[0]); + if(rc){return rc;} + } + // Now we will compare the old and new bad lane data and take appropriate action + if(master_interface==CP_FABRIC_X0) + { + for (int current_group = 0 ; current_group < max_group; current_group++){ + if(slave_data_one_new[current_group]==slave_data_one_old[current_group] && slave_data_two_new[current_group]==slave_data_two_old[current_group] ){ + // If old and new data is same , no need to present FIRs to PRD + if( !( slave_data_one_new[current_group].isBitClear(0,16) && slave_data_two_new[current_group].isBitClear(0,16) )){ + FAPI_DBG("io_run_training : Clear invalid FIRs on the slave side "); + // If all bad lane info is clear in new data then no need to clear ,this is a 0==0 case of both old and new empty vectors + io_clear_firs(slave_target); + } + } + if(master_data_one_new[current_group]==master_data_one_old[current_group] && master_data_two_new[current_group]==master_data_two_old[current_group] ){ + // If old and new data is same , no need to present FIRs to PRD + if( !( master_data_one_new[current_group].isBitClear(0,16) && master_data_two_new[current_group].isBitClear(0,16) )){ + FAPI_DBG("io_run_training : Clear invalid FIRs on the master side "); + // If all bad lane info is clear in new data then no need to clear ,this is a 0==0 case of both old and new empty vectors + io_clear_firs(master_target); + } + } + } + } + else + { + if(slave_data_one_new[0]==slave_data_one_old[0] && slave_data_two_new[0]==slave_data_two_old[0] ){ + // If old and new data is same , no need to present FIRs to PRD + if( !( slave_data_one_new[0].isBitClear(0,16) && slave_data_two_new[0].isBitClear(0,16) )){ + FAPI_DBG("io_run_training : Clear invalid FIRs on the slave side "); + // If all bad lane info is clear in new data then no need to clear ,this is a 0==0 case of both old and new empty vectors + io_clear_firs(slave_target); + } + } + if(master_data_one_new[0]==master_data_one_old[0] && master_data_two_new[0]==master_data_two_old[0] ){ + // If old and new data is same , no need to present FIRs to PRD + if( !( master_data_one_new[0].isBitClear(0,16) && master_data_two_new[0].isBitClear(0,16) )){ + FAPI_DBG("io_run_training : Clear invalid FIRs on the master side "); + // If all bad lane info is clear in new data then no need to clear ,this is a 0==0 case of both old and new empty vectors + io_clear_firs(master_target); + } + } + } + + // END post training part of Workaround - HW205368 - procedure from Rob /Pete + + //Translate some enums in training header to fir enums + if(master_interface==CP_FABRIC_X0){ + fir_master_interface=FIR_CP_FABRIC_X0; + } + else if(master_interface==CP_IOMC0_P0){ + fir_master_interface= FIR_CP_IOMC0_P0; + } + else if(master_interface== CEN_DMI){ + fir_master_interface=FIR_CEN_DMI; + } + else if(master_interface== CP_FABRIC_A0){ + fir_master_interface=FIR_CP_FABRIC_A0; + } + if(slave_interface==CP_FABRIC_X0){ + fir_slave_interface=FIR_CP_FABRIC_X0; + } + else if(slave_interface==CP_IOMC0_P0){ + fir_slave_interface= FIR_CP_IOMC0_P0; + } + else if(slave_interface== CEN_DMI){ + fir_slave_interface=FIR_CEN_DMI; + } + else if(slave_interface== CP_FABRIC_A0){ + fir_slave_interface=FIR_CP_FABRIC_A0; + } + FAPI_DBG("io_run_training : Clearing FIR masks now"); + //Finally Unmask the LFIR to let PRD take action post training + clear_fir_mask_reg(slave_target,fir_slave_interface); + clear_fir_mask_reg(master_target,fir_master_interface); + return(rc); +} + // These functions work on a pair of targets. One is the master side of the bus interface, the other the slave side. For eg; in EDI(DMI2)PU is the master and Centaur is the slave // In EI4 both sides have pu targets . After the talk with Dean , my understanding is that targets are configured down upto the endpoints of a particular bus. eg; pu 0 A0 --> pu 1 A3 could be a combination on EI4 // In a EDI(DMI) bus the targets are considered to be one pu and one centaur pair . The overall code is same for EDI and EI4 and the run_training function handles both bus types ( X ,A or MC ) . @@ -62,6 +246,15 @@ ReturnCode io_run_training(const Target &master_target,const Target &slave_targe edi_training init1(SELECTED,SELECTED,SELECTED, NOT_RUNNING, NOT_RUNNING); // Run WDE first edi_training init2( NOT_RUNNING, NOT_RUNNING, NOT_RUNNING,SELECTED,SELECTED); // Run RF next bool is_master=false; + + //FIR workaround buffers + //These buffers will store old bad lane info that was restored prior to training + ecmdDataBufferBase slave_data_one_old[4]; + ecmdDataBufferBase slave_data_two_old[4]; + ecmdDataBufferBase master_data_one_old[4]; + ecmdDataBufferBase master_data_two_old[4]; + + // This is a DMI/MC bus if( (master_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET )&& (slave_target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP)){ FAPI_DBG("This is a DMI bus using base DMI scom address"); @@ -69,12 +262,16 @@ ReturnCode io_run_training(const Target &master_target,const Target &slave_targe slave_interface=CEN_DMI; // Centaur scom base master_group=3; // Design requires us to do this as per scom map and layout slave_group=0; + fir_workaround_pre_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group, + slave_data_one_old,slave_data_two_old,master_data_one_old,master_data_two_old); // Workaround - HW 220654 -- Need to split WDERF into WDE + RF due to sync problem rc=init1.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group); - if(rc){ + if(!rc.ok()){ return rc; } rc=init2.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group); + fir_workaround_post_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group, + slave_data_one_old,slave_data_two_old,master_data_one_old,master_data_two_old); } //This is an X Bus else if( (master_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT )&& (slave_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT )){ @@ -88,14 +285,22 @@ ReturnCode io_run_training(const Target &master_target,const Target &slave_targe if(!is_master){ //Swap master and slave targets !! FAPI_DBG("X Bus ..target swap performed"); + fir_workaround_pre_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group, + slave_data_one_old,slave_data_two_old,master_data_one_old,master_data_two_old); rc=init1.run_training(slave_target,slave_interface,slave_group,master_target,master_interface,master_group); if(rc) return rc; rc=init2.run_training(slave_target,slave_interface,slave_group,master_target,master_interface,master_group); + fir_workaround_post_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group, + slave_data_one_old,slave_data_two_old,master_data_one_old,master_data_two_old); } else{ + fir_workaround_pre_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group, + slave_data_one_old,slave_data_two_old,master_data_one_old,master_data_two_old); rc=init1.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group); if(rc) return rc; rc=init2.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group); + fir_workaround_post_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group, + slave_data_one_old,slave_data_two_old,master_data_one_old,master_data_two_old); } } } @@ -111,15 +316,23 @@ ReturnCode io_run_training(const Target &master_target,const Target &slave_targe if(!is_master) { FAPI_DBG("A Bus ..target swap performed"); + fir_workaround_pre_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group, + slave_data_one_old,slave_data_two_old,master_data_one_old,master_data_two_old); rc=init1.run_training(slave_target,slave_interface,slave_group,master_target,master_interface,master_group); if(rc) return rc; rc=init2.run_training(slave_target,slave_interface,slave_group,master_target,master_interface,master_group); + fir_workaround_post_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group, + slave_data_one_old,slave_data_two_old,master_data_one_old,master_data_two_old); } else { + fir_workaround_pre_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group, + slave_data_one_old,slave_data_two_old,master_data_one_old,master_data_two_old); rc=init1.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group); if(rc) return rc; rc=init2.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group); + fir_workaround_post_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group, + slave_data_one_old,slave_data_two_old,master_data_one_old,master_data_two_old); } } } diff --git a/src/usr/hwpf/hwp/bus_training/io_run_training.H b/src/usr/hwpf/hwp/bus_training/io_run_training.H index 0ff1e9419..a0581aada 100644 --- a/src/usr/hwpf/hwp/bus_training/io_run_training.H +++ b/src/usr/hwpf/hwp/bus_training/io_run_training.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ diff --git a/src/usr/hwpf/hwp/centaur_ec_attributes.xml b/src/usr/hwpf/hwp/centaur_ec_attributes.xml index b5b1693ba..882f3d03b 100644 --- a/src/usr/hwpf/hwp/centaur_ec_attributes.xml +++ b/src/usr/hwpf/hwp/centaur_ec_attributes.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> <!-- --> <!-- p1 --> <!-- --> @@ -39,4 +39,37 @@ </chip> </chipEcFeature> </attribute> + + <attribute> + <id>ATTR_CENTAUR_EC_MSS_CONTINUE_ON_DP18_PLL_LOCK_FAIL</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description> +Controls the ddr_phy_reset procedure. When set to TRUE, the procedure will continue with processing other DP18 blocks, if one fails. In DD2, this attribute must be set to false so that the failing hardware (centaur) is marked as bad and not the DIMM. Set by firwmare using the EC level or by a MRW + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_CENTAUR</name> + <ec> + <value>0x10</value> + <test>EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + +<attribute> + <id>ATTR_CENTAUR_EC_MSS_READ_PHASE_SELECT_RESET</id> + <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <description>Set by the platform depending on DD1 vs DD2. If true, then training and periodic training needs to make adjustments to the read phase select. In DD2, we expect this to be fixed.</description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_CENTAUR</name> + <ec> + <value>0x10</value> + <test>EQUAL</test> + </ec> + </chip> + </chipEcFeature> +</attribute> + </attributes> diff --git a/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.C b/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.C index 8e56ec71c..0383e9eb9 100644 --- a/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.C +++ b/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_get_cen_ecid.C,v 1.13 2013/01/24 18:29:59 bellows Exp $ +// $Id: mss_get_cen_ecid.C,v 1.18 2013/03/27 13:20:55 bellows Exp $ //------------------------------------------------------------------------------ // *| // *! (C) Copyright International Business Machines Corp. 2012 @@ -31,7 +31,7 @@ // *! DESCRIPTION : Get ECID string from target using SCOM's // *! // *! OWNER NAME : Mark Bellows Email: bellows@us.ibm.com -// *! Copied From : Joe McGill's proc_cleanup code +// *! Copied From : Joe McGill's proc_cleanup code // *! //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ @@ -39,6 +39,11 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.18 | bellows |27-MAR-13| Fixes to rc handling from reviewer comments +// 1.17 | bellows |26-MAR-13| Additional reviewer comments +// 1.16 | bellows |26-MAR-13| Cleanup because of Firmware Gerrit Review Comments +// 1.15 | bellows |22-MAR-13| Changed name of ECID Attribute per Firmware request +// 1.14 | bellows |29-JAN-13| Getting sub version, setting NWELL Attribute // 1.13 | bellows |24-JAN-13| Cache Disable Valid bit is ecid_128, made bit // | | | number consistent // 1.12 | bellows |23-JAN-13| PSRO attriubute is available in cronus dev @@ -66,9 +71,9 @@ extern "C" { // HWP entry point fapi::ReturnCode mss_get_cen_ecid( const fapi::Target& i_target, - uint8_t & ddr_port_status, - uint8_t & cache_enable_o, - uint8_t & centaur_sub_revision_o + uint8_t & o_ddr_port_status, + uint8_t & o_cache_enable, + uint8_t & o_centaur_sub_revision ) { // return code @@ -86,7 +91,7 @@ fapi::ReturnCode mss_get_cen_ecid( return rc; } scom.reverse(); - data[0] = scom.getDoubleWord(0); + data[0] = scom.getDoubleWord(0); //gets the second part of the ecid and sets the attribute rc = fapiGetScom( i_target, ECID_PART_1_0x00010001, scom ); if (rc) @@ -96,10 +101,10 @@ fapi::ReturnCode mss_get_cen_ecid( } scom.reverse(); data[1] = scom.getDoubleWord(0); - rc = FAPI_ATTR_SET(ATTR_MSS_ECID, &i_target, data); + rc = FAPI_ATTR_SET(ATTR_ECID, &i_target, data); if (rc) { - FAPI_ERR("mss_get_cen_ecid: set ATTR_MSS_ECID" ); + FAPI_ERR("mss_get_cen_ecid: set ATTR_ECID" ); return rc; } @@ -130,29 +135,22 @@ fapi::ReturnCode mss_get_cen_ecid( else if(bit113_114 == 1) t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_HALF_A; else if(bit113_114 == 2) t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_HALF_B; else t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_OFF; - cache_enable_o = t; + o_cache_enable = t; } else { FAPI_INF("Cache Dissbled because eDRAM data bits are assumed to be bad"); - cache_enable_o = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_OFF; + o_cache_enable = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_OFF; } -// //sets the cache attribute and error checks -// rc = FAPI_ATTR_SET(ATTR_MSS_CACHE_ENABLE, &i_target, t); -// if (!rc.ok()) { -// FAPI_ERR("mss_get_cen_ecid: could not set ATTR_MSS_CACHE_ENABLE" ); -// return rc; -// } - //reads in the ECID info for whether a DDR port side is good or bad - rc_ecmd = scom.extract(&ddr_port_status,50,2); - ddr_port_status = ddr_port_status >> 6; + rc_ecmd = scom.extract(&o_ddr_port_status,50,2); + o_ddr_port_status = o_ddr_port_status >> 6; if(rc_ecmd) { FAPI_ERR("mss_get_cen_ecid: could not extract DDR status data" ); rc.setEcmdError(rc_ecmd); return rc; } - + //116..123 average PSRO from 85C wafer test uint8_t bit117_124=0; rc_ecmd = scom.extract(&bit117_124,52,8); @@ -177,7 +175,28 @@ fapi::ReturnCode mss_get_cen_ecid( rc.setEcmdError(rc_ecmd); return rc; } - centaur_sub_revision_o=bit125; + o_centaur_sub_revision=bit125; + // The ecid contains the chip's subrevision, changes in the subrevision should not + // change firmware behavior but for the exceptions, update attributes to indicate + // those behaviors + uint8_t ec; + uint8_t l_nwell_misplacement = 0; + rc = FAPI_ATTR_GET_PRIVILEGED(ATTR_EC, &i_target, ec); + if (!rc.ok()) { + FAPI_ERR("mss_get_cen_ecid: could not GET PRIVILEGED ATTR_EC" ); + return rc; + } + if ((ec == 0x10) && (o_centaur_sub_revision < 1)) + { + // For DD1.00, the transistor misplaced in the nwell needs some setting adjustments to get it to function + // after DD1.00, we no longer need to make that adjustment + l_nwell_misplacement = 1; + } + rc = FAPI_ATTR_SET(ATTR_MSS_NWELL_MISPLACEMENT, &i_target, l_nwell_misplacement); + if (!rc.ok()) { + FAPI_ERR("mss_get_cen_ecid: could not set ATTR_MSS_NWELL_MISPLACEMENT" ); + return rc; + } // mark HWP exit FAPI_IMP("Exiting mss_get_cen_ecid...."); diff --git a/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.H b/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.H index d2b9ae780..1c52667fc 100644 --- a/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.H +++ b/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_get_cen_ecid.H,v 1.6 2013/01/21 17:11:37 bellows Exp $ +// $Id: mss_get_cen_ecid.H,v 1.8 2013/03/26 15:53:59 bellows Exp $ //------------------------------------------------------------------------------ // *| // *! (C) Copyright International Business Machines Corp. 2012 @@ -41,6 +41,8 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.8 | bellows |26-MAR-13| Reviewer found updates +// 1.7 | bellows |22-MAR-13| Changed commented name of ECID Attribute per Firmware request // 1.6 | bellows |21-JAN-13| added in sub revision reader // 1.5 | bellows |15-JAN-13| moved Cache Enable Information to the caller // 1.1-1.4 | various |07-DEC-12| Original Program @@ -70,7 +72,7 @@ enum mss_get_cen_ecid_ddr_status // function pointer typedef definition for HWP call support typedef fapi::ReturnCode -(*mss_get_cen_ecid_FP_t)(const fapi::Target& i_target, uint8_t & ddr_port_status, uint8_t & cache_enable_o, uint8_t & centaur_sub_revision_o +(*mss_get_cen_ecid_FP_t)(const fapi::Target& i_target, uint8_t & o_ddr_port_status, uint8_t & o_cache_enable, uint8_t & o_centaur_sub_revision ); @@ -83,17 +85,19 @@ extern "C" // function: FAPI mss_get_cen_ecid HWP entry point // parameters: i_target => cen chip target -// &ddr_port_status => indicates if the MBA's are bad, with MBA 1 being the rightmost bit and MBA 0 being the next to right most bit -// &cache_enable_o => what it would have set the cache enable attribute to if it sets attributes +// &o_ddr_port_status => indicates if the MBA's are bad, with MBA 1 being the rightmost bit and MBA 0 being the next to right most bit +// &o_cache_enable => what it would have set the cache enable attribute to if it sets attributes +// &o_centaur_sub_revision => the sub revision indicator between DD1.0 and DD1.01 // returns: FAPI_RC_SUCCESS if FBC stop is deasserted at end of execution -// else FAPI getscom/putscom return code for failing operation -// Updates attributes: ATTR_MSS_ECID[2] -> bits 1-64 and 65-128 of the ECID -// ATTR_MSS_CACHE_ENABLE -> Stores which parts of the eDRAM are enabled +// else FAPI return code for failing operation +// Updates attributes: ATTR_ECID[2] -> bits 1-64 and 65-128 of the ECID +// ATTR_MSS_PSRO -> average PSRO from 85C wafer test +// ATTR_MSS_NWELL_MISPLACEMENT -> indicates if nwell defect in hardware fapi::ReturnCode mss_get_cen_ecid( const fapi::Target& i_target, - uint8_t & ddr_port_status, - uint8_t & cache_enable_o, - uint8_t & centaur_sub_revision_o + uint8_t & o_ddr_port_status, + uint8_t & o_cache_enable, + uint8_t & o_centaur_sub_revision ); diff --git a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.C b/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.C index 7a1251098..c55062091 100644 --- a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.C +++ b/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: cen_mem_pll_setup.C,v 1.23 2012/08/13 17:16:16 mfred Exp $ +// $Id: cen_mem_pll_setup.C,v 1.24 2013/03/04 17:56:26 mfred Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_mem_pll_setup.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -31,6 +31,7 @@ // *! DESCRIPTION : see additional comments below // *! OWNER NAME : Mark Fredrickson Email: mfred@us.ibm.com // *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com +// *! SCREEN : pervasive_screen // #! ADDITIONAL COMMENTS : // // The purpose of this procedure is to make sure the Centaur MEM PLL locks. @@ -133,6 +134,9 @@ fapi::ReturnCode cen_mem_pll_setup(const fapi::Target & i_target) This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: cen_mem_pll_setup.C,v $ +Revision 1.24 2013/03/04 17:56:26 mfred +Add some header comments for BACKUP and SCREEN. + Revision 1.23 2012/08/13 17:16:16 mfred Adding new hwp cen_mem_pll_initf. diff --git a/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C b/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C index d68bebeba..636077eba 100644 --- a/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C +++ b/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C @@ -1,27 +1,26 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ -// $Id: cen_mem_startclocks.C,v 1.9 2012/06/07 13:52:27 jmcgill Exp $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: cen_mem_startclocks.C,v 1.10 2013/03/04 17:56:29 mfred Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_mem_startclocks.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -32,6 +31,7 @@ // *! DESCRIPTION : see additional comments below // *! OWNER NAME : Mark Fredrickson Email: mfred@us.ibm.com // *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com +// *! SCREEN : pervasive_screen // #! ADDITIONAL COMMENTS : See below // // The purpose of this procedure is to drop the fences and release the tholds associated with the Centaur chip MEM PLL. @@ -393,6 +393,9 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target) This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: cen_mem_startclocks.C,v $ +Revision 1.10 2013/03/04 17:56:29 mfred +Add some header comments for BACKUP and SCREEN. + Revision 1.9 2012/06/07 13:52:27 jmcgill use independent data buffers for cfam/scom accesses diff --git a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C index a6429eb1c..9202268ff 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C +++ b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_ddr_phy_reset.C,v 1.17 2012/12/03 15:49:27 mfred Exp $ +// $Id: mss_ddr_phy_reset.C,v 1.18 2013/03/18 19:38:48 mfred Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_ddr_phy_reset.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -31,6 +31,7 @@ // *! DESCRIPTION : see additional comments below // *! OWNER NAME : Mark Fredrickson Email: mfred@us.ibm.com // *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com +// *! SCREEN : memory_screen // #! ADDITIONAL COMMENTS : // // The purpose of this procedure is to do a soft reset of the DDR PHY logic @@ -138,6 +139,8 @@ fapi::ReturnCode mss_ddr_phy_reset_cloned(const fapi::Target & i_target) uint8_t P1_DP2_reg_error = 0; uint8_t P1_DP3_reg_error = 0; uint8_t P1_DP4_reg_error = 0; + fapi::Target l_centaurTarget; + uint8_t continue_on_dp18_pll_lock_failure = 0; FAPI_INF("********* mss_ddr_phy_reset start *********"); @@ -163,13 +166,13 @@ fapi::ReturnCode mss_ddr_phy_reset_cloned(const fapi::Target & i_target) // Deassert Force_mclk_low signal // see CQ 216395 (HW217109) rc = mss_deassert_force_mclk_low(i_target); - if(rc) + if (rc) { FAPI_ERR(" deassert_force_mclk_low Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); break; } - + // // 1. Drive all control signals to the PHY to their inactive state, idle state, or inactive value. // (Note: The chip should already be in this state.) @@ -349,7 +352,7 @@ fapi::ReturnCode mss_ddr_phy_reset_cloned(const fapi::Target & i_target) // PC DP18 PLL Lock Status should be 0xF800: (SCOM Addr: 0x8000C0000301143F, 0x8001C0000301143F, 0x8000C0000301183F, 0x8001C0000301183F) // PC AD32S PLL Lock Status should be 0xC000: (SCOM Addr: 0x8000C0010301143F, 0x8001C0010301143F, 0x8000C0010301183F, 0x8001C0010301183F) //------------------------ - // 7a - Poll for lock bits + // 8a - Poll for lock bits FAPI_DBG("Step 8: Poll until DP18 and AD32S PLLs have locked....\n"); do { @@ -392,10 +395,33 @@ fapi::ReturnCode mss_ddr_phy_reset_cloned(const fapi::Target & i_target) } while ((done_polling == 0) && (poll_count < MAX_POLL_LOOPS)); // Poll until PLLs are locked. if (rc) break; // Go to end of proc if error found inside polling loop. + if (poll_count == MAX_POLL_LOOPS) { + //------------------------------- - // 7b - Check Port 0 DP lock bits + // Check to see if we should continue even if the DP18 PLL lock fails + rc = fapiGetParentChip(i_target, l_centaurTarget); + if (rc) + { + FAPI_ERR("Error getting Centaur parent target from the input MBA"); + break; + } + else + { + rc = FAPI_ATTR_GET( ATTR_CENTAUR_EC_MSS_CONTINUE_ON_DP18_PLL_LOCK_FAIL, &l_centaurTarget, continue_on_dp18_pll_lock_failure); + if (rc) + { + FAPI_ERR("Failed to get attribute: ATTR_CENTAUR_EC_MSS_CONTINUE_ON_DP18_PLL_LOCK_FAIL."); + break; + } + else + { + FAPI_DBG("Got attribute ATTR_CENTAUR_EC_MSS_CONTINUE_ON_DP18_PLL_LOCK_FAIL: value=%X.\n", continue_on_dp18_pll_lock_failure); + } + } + //------------------------------- + // 8b - Check Port 0 DP lock bits if ( dp_p0_lock_data.getHalfWord(3) != DP18_PLL_EXP_LOCK_STATUS ) { FAPI_ERR("One or more DP18 port 0 (0x0C000) PLL failed to lock! Lock Status = %04X",dp_p0_lock_data.getHalfWord(3)); @@ -405,10 +431,15 @@ fapi::ReturnCode mss_ddr_phy_reset_cloned(const fapi::Target & i_target) if ( dp_p0_lock_data.isBitClear(50) ) { FAPI_ERR("Port 0 DP 2 PLL failed to lock!");} if ( dp_p0_lock_data.isBitClear(51) ) { FAPI_ERR("Port 0 DP 3 PLL failed to lock!");} if ( dp_p0_lock_data.isBitClear(52) ) { FAPI_ERR("Port 0 DP 4 PLL failed to lock!");} - // break; // Don't break. Keep going to initialize any other channels that might be good. + if (!continue_on_dp18_pll_lock_failure) + { + FAPI_ERR("DP18 PLL lock failed and this chip does not have the known DP18 lock bug."); + break; + } + // for DD1 parts that have the DP18 lock bug - keep going to initialize any other channels that might be good. } //------------------------------- - // 7c - Check Port 1 DP lock bits + // 8c - Check Port 1 DP lock bits if ( dp_p1_lock_data.getHalfWord(3) != DP18_PLL_EXP_LOCK_STATUS ) { FAPI_ERR("One or more DP18 port 1 (0x1C000) PLL failed to lock! Lock Status = %04X",dp_p1_lock_data.getHalfWord(3)); @@ -418,10 +449,15 @@ fapi::ReturnCode mss_ddr_phy_reset_cloned(const fapi::Target & i_target) if ( dp_p1_lock_data.isBitClear(50) ) { FAPI_ERR("Port 1 DP 2 PLL failed to lock!");} if ( dp_p1_lock_data.isBitClear(51) ) { FAPI_ERR("Port 1 DP 3 PLL failed to lock!");} if ( dp_p1_lock_data.isBitClear(52) ) { FAPI_ERR("Port 1 DP 4 PLL failed to lock!");} - // break; // Don't break. Keep going to initialize any channels that might be good. + if (!continue_on_dp18_pll_lock_failure) + { + FAPI_ERR("DP18 PLL lock failed and this chip does not have the known DP18 lock bug."); + break; + } + // for DD1 parts that have the DP18 lock bug - keep going to initialize any other channels that might be good. } //------------------------------- - // 7d - Check Port 0 AD lock bits + // 8d - Check Port 0 AD lock bits if ( ad_p0_lock_data.getHalfWord(3) != AD32S_PLL_EXP_LOCK_STATUS ) { FAPI_ERR("One or more AD32S port 0 (0x0C001) PLL failed to lock! Lock Status = %04X",ad_p0_lock_data.getHalfWord(3)); @@ -429,7 +465,7 @@ fapi::ReturnCode mss_ddr_phy_reset_cloned(const fapi::Target & i_target) break; } //------------------------------- - // 7e - Check Port 1 AD lock bits + // 8e - Check Port 1 AD lock bits if ( ad_p1_lock_data.getHalfWord(3) != AD32S_PLL_EXP_LOCK_STATUS ) { FAPI_ERR("One or more AD32S port 1 (0x1C001) PLL failed to lock! Lock Status = %04X",ad_p1_lock_data.getHalfWord(3)); @@ -1079,6 +1115,9 @@ This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: mss_ddr_phy_reset.C,v $ +Revision 1.18 2013/03/18 19:38:48 mfred +Update to not continue if DP18 PLL fails to lock and EC is DD2. + Revision 1.17 2012/12/03 15:49:27 mfred Fixed bug to allow exit from loops in case of error. diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C index f1a1812f5..155f33f9e 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit_mc.C,v 1.33 2013/02/04 20:04:51 lapietra Exp $ +// $Id: mss_draminit_mc.C,v 1.34 2013/03/12 21:33:56 lapietra Exp $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -44,6 +44,7 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.34 | dcadiga |12-MAR-13| Added spare cke disable as step 0 // 1.33 | dcadiga |04-FEB-13| For some reason the main procedure call was commented out in the last commit... commenting it back in // 1.32 | gollub |31-JAN-13| Uncommenting mss_unmask_maint_errors and mss_unmask_inband_errors // 1.31 | dcadiga |21-JAN-13| Fixed variable name for memcal_interval (coded as memcal_iterval...) @@ -119,6 +120,7 @@ ReturnCode mss_set_iml_complete(Target& i_target); ReturnCode mss_enable_power_management(Target& i_target); ReturnCode mss_enable_control_bit_ecc(Target& i_target); ReturnCode mss_ccs_mode_reset(Target& i_target); +ReturnCode mss_spare_cke_disable(Target& i_target); ReturnCode mss_draminit_mc(Target& i_target) @@ -158,6 +160,22 @@ ReturnCode mss_draminit_mc_cloned(Target& i_target) rc=fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_MBA_CHIPLET, l_mbaChiplets); if (rc) return rc; + // Step Zero: Turn Off Spare CKE - This needs to be off before IML complete + FAPI_INF("+++ Disabling Spare CKE FIX +++"); + for (uint32_t i=0; i < l_mbaChiplets.size(); i++) + { + rc = mss_spare_cke_disable(l_mbaChiplets[i]); + if(rc) + { + FAPI_ERR("---Error During Spare CKE Disable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator()); + return rc; + } + + + + } + + // Step One: Set IML COMPLETE FAPI_INF( "+++ Setting IML Complete +++"); rc = mss_set_iml_complete(i_target); @@ -170,6 +188,7 @@ ReturnCode mss_draminit_mc_cloned(Target& i_target) // Loop through the 2 MBA's for (uint32_t i=0; i < l_mbaChiplets.size(); i++) { + // Step Two: Disable CCS address lines FAPI_INF( "+++ Disabling CCS Address Lines +++"); @@ -451,5 +470,30 @@ ReturnCode mss_ccs_mode_reset (Target& i_target) return rc; } +ReturnCode mss_spare_cke_disable (Target& i_target) +{ + + //Target MBA + //Selects address data from the mainline + //Variables + ReturnCode rc; + ReturnCode rc_buff; + uint32_t rc_num = 0; + ecmdDataBufferBase spare_cke_data_buffer_64(64); + + //Setup SPARE CKE enable bit + rc = fapiGetScom(i_target, MBA01_MBARPC0Q_0x03010434, spare_cke_data_buffer_64); + if(rc) return rc; + rc_num = rc_num | spare_cke_data_buffer_64.clearBit(42); + rc = fapiPutScom(i_target, MBA01_MBARPC0Q_0x03010434, spare_cke_data_buffer_64); + if(rc) return rc; + + + FAPI_INF("+++ disable_spare_cke complete +++"); + return rc; +} + + + } //end extern C diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C index 2c317afc3..e8ca570f0 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit_training_advanced.C,v 1.25 2013/01/31 15:54:58 sasethur Exp $ +// $Id: mss_draminit_training_advanced.C,v 1.26 2013/03/06 11:22:31 sasethur Exp $ /* File is created by SARAVANAN SETHURAMAN on Thur 29 Sept 2011. */ //------------------------------------------------------------------------------ @@ -65,6 +65,7 @@ // 1.23 | sasethur |14-Dec-12| Updated for FW review comments // 1.24 | sasethur |17-Jan-13| Updated for mss_mcbist_common.C include file // 1.25 | abhijsau |31-Jan-13| removed mss_mcbist_common.C include file , needs to be included while compiling +// 1.26 | abhijsau |06-Mar-13| fixed fw comment // This procedure Schmoo's DRV_IMP, SLEW, VREF (DDR, CEN), RCV_IMP based on attribute from effective config procedure @@ -321,7 +322,7 @@ fapi::ReturnCode mss_draminit_training_advanced_cloned(const fapi::Target & i_ta return rc; } } - if (((l_shmoo_param_valid & DELAY_REG) != 0) || (l_shmoo_type_valid != 0)) + if (((l_shmoo_param_valid & DELAY_REG) != 0) || (l_shmoo_type_valid != TEST_NONE)) { rc = delay_shmoo(i_target_mba, l_port, l_shmoo_type_valid, &l_left_margin, &l_right_margin,i_pattern,i_test_type); if (rc) diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H new file mode 100644 index 000000000..8016f3d1b --- /dev/null +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H @@ -0,0 +1,80 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// *!*************************************************************************** +// *! (C) Copyright International Business Machines Corp. 1997, 1998 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *!*************************************************************************** +// *! FILENAME : mss_mcbist_address.H +// *! TITLE : +// *! DESCRIPTION : MCBIST procedures +// *! CONTEXT : +// *! +// *! OWNER NAME : +// *! BACKUP : +// *!*************************************************************************** +// CHANGE HISTORY: +//------------------------------------------------------------------------------- +// Version:|Author: | Date: | Comment: +// --------|--------|---------|-------------------------------------------------- +//------------------------------------------------------------------------------ +#ifndef MSS_MCBIST_ADDRESS_H +#define MSS_MCBIST_ADDRESS_H + +/****************************************************************************************/ +/* mss_mcbist_address.H */ +/****************************************************************************************/ +#include <fapi.H> +#include <cen_scom_addresses.H> +#include <mss_access_delay_reg.H> +#include <mss_shmoo_common.H> +#include <mss_mcbist.H> +#include<string.h> +extern "C" +{ +using namespace fapi; + +/*enum address_mode +{ + SF, + SR, + RF, + RR +};*/ +enum interleave_type +{ + +BANK_RANK, +RANK_BANK, +BANK_ONLY, +RANK_ONLY, +RANKS_DIMM0, +RANKS_DIMM1, +USER_PATTERN +}; + +fapi::ReturnCode address_generation(const fapi:: Target & i_target_mba,uint8_t i_port,mcbist_addr_mode i_addr_type,interleave_type i_add_inter_type,uint8_t i_rank,uint64_t &io_start_address, uint64_t &io_end_address); +fapi::ReturnCode parse_addr(const fapi:: Target & i_target_mba, char addr_string[],uint8_t mr3_valid,uint8_t mr2_valid,uint8_t mr1_valid,uint8_t l_dram_rows,uint8_t l_dram_cols,uint8_t l_addr_inter); + +} +#endif diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_shmoo_common.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_shmoo_common.H index af6b2eac4..d6438580e 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_shmoo_common.H +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_shmoo_common.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_shmoo_common.H,v 1.10 2012/12/06 11:46:58 sasethur Exp $ +// $Id: mss_shmoo_common.H,v 1.12 2013/03/20 17:18:38 sasethur Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -58,6 +58,7 @@ const uint8_t MAX_NIBBLES=2; const uint8_t MAX_BITS=4; const uint8_t MAX_DQ=80; const uint8_t MAX_DQS=20; +const uint8_t SCHMOO_NIBBLES=20; const uint16_t read_counter_threshold=1000; const uint16_t error_threshold_count=400; const uint8_t MAX_PORT = 2; diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C index 1a2f3b8e6..08512d949 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit_training.C,v 1.55 2013/02/25 19:05:31 jdsloat Exp $ +// $Id: mss_draminit_training.C,v 1.56 2013/03/09 00:05:43 jdsloat Exp $ //------------------------------------------------------------------------------ // Don't forget to create CVS comments when you check in your changes! //------------------------------------------------------------------------------ @@ -28,6 +28,11 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|------------------------------------------------ +// 1.56 | jdsloat |27-FEB-13| Fixed rtt_nom and rtt_wr swap bug during condition of rtt_nom = diabled and rtt_wr = non-disabled +// | | | Added workaround on a per quad resolution +// | | | Added workaround as a seperate sub +// | | | Added framework of binning workaround based on timing reference +// | | | Added putscom to enable spare cke mirroring // 1.55 | jdsloat |25-FEB-13| Added MBA/Port info to debug messages. // 1.54 | jdsloat |22-FEB-13| Edited WRITE_READ workaround to also edit DQSCLK PHASE // 1.53 | jdsloat |14-FEB-13| Fixed WRITE_READ workaround so it will execute in a partial substep case @@ -158,6 +163,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target); ReturnCode mss_check_cal_status(Target& i_target, uint8_t i_port, uint8_t i_group, mss_draminit_training_result& io_status); ReturnCode mss_check_error_status(Target& i_target, uint8_t i_port, uint8_t i_group, mss_draminit_training_result& io_status); ReturnCode mss_rtt_nom_rtt_wr_swap( Target& i_target, uint32_t i_port_number, uint8_t i_rank, uint32_t i_rank_pair_group, uint32_t& io_ccs_inst_cnt, uint8_t& io_dram_rtt_nom_original); +ReturnCode mss_read_center_workaround(Target& i_target, uint8_t i_mbaPosition, uint32_t i_port, uint32_t i_rank_group); ReturnCode getC4dq2reg(const Target &i_mba, const uint8_t i_port, const uint8_t i_dimm, const uint8_t i_rank, ecmdDataBufferBase &o_reg); ReturnCode setC4dq2reg(const Target &i_mba, const uint8_t i_port, const uint8_t i_dimm, const uint8_t i_rank, ecmdDataBufferBase &o_reg); @@ -198,7 +204,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) INVALID = 255 }; - const uint32_t NUM_POLL = 100; + const uint32_t NUM_POLL = 10000; ReturnCode rc; uint32_t rc_num = 0; @@ -260,13 +266,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) uint8_t cal_steps = 0; uint8_t cur_cal_step = 0; ecmdDataBufferBase cal_steps_8(8); - uint64_t DQSCLK_RD_PHASE_ADDR_0 = 0; - uint64_t DQSCLK_RD_PHASE_ADDR_1 = 0; - uint64_t DQSCLK_RD_PHASE_ADDR_2 = 0; - uint64_t DQSCLK_RD_PHASE_ADDR_3 = 0; - uint64_t DQSCLK_RD_PHASE_ADDR_4 = 0; - uint8_t l_value_u8 = 0; - uint8_t l_new_value_u8 = 0; + uint8_t l_nwell_misplacement = 0; uint8_t dram_rtt_nom_original = 0; @@ -302,12 +302,21 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) return rc; } + + //Get which training steps we are to run rc = FAPI_ATTR_GET(ATTR_MSS_CAL_STEP_ENABLE, &i_target, cal_steps); if(rc) return rc; - rc_num = rc_num | cal_steps_8.insert(cal_steps, 0, 8, 0); + + //Setup SPARE CKE enable bit + rc = fapiGetScom(i_target, MBA01_MBARPC0Q_0x03010434, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.setBit(42); + rc = fapiPutScom(i_target, MBA01_MBARPC0Q_0x03010434, data_buffer_64); + if(rc) return rc; + //Set up CCS Mode Reg for Init cal rc = fapiGetScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer_64); if(rc) return rc; @@ -552,7 +561,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) // Before WR_LVL --- Change the RTT_NOM to RTT_WR pre-WR_LVL if (cur_cal_step == 1) { - dram_rtt_nom_original = 0; + dram_rtt_nom_original = 0xFF; rc = mss_rtt_nom_rtt_wr_swap(i_target, port, primary_ranks_array[group][port], @@ -650,172 +659,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) ( ( l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_TRUE ) ||( l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_FALSE ) ) ) { - FAPI_INF( "+++ Read Centering Workaround on rank group: %d +++", group); - FAPI_INF( "+++ Clearing values from RD PHASE SELECT regs. +++"); - FAPI_INF( "+++ Incrementing by 2 values from DQS CLK PHASE SELECT regs. +++"); - - if ( port == 0 ) - { - if ( group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; - - } - else if ( group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; - - } - else if ( group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; - - } - else if ( group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; - - } - } - else if (port == 1 ) - { - if ( group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; - - } - else if ( group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; - - - } - else if ( group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; - - } - else if ( group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; - - } - } - - // Set Read Phase to 0. - //Increment dqs clk 2. 4 is the limit, wrap around (IE 5 = 1, 6 = 2) - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(50, 2); - rc_num = rc_num | data_buffer_64.clearBit(54, 2); - rc_num = rc_num | data_buffer_64.clearBit(58, 2); - rc_num = rc_num | data_buffer_64.clearBit(62, 2); - - for ( uint8_t l_element_u8 = 0; l_element_u8 < 4; l_element_u8 += 1 ) { - l_value_u8 = 0; - data_buffer_64.extractToRight(&l_value_u8, (48 + (l_element_u8 * 4)), 2); - l_new_value_u8 = (l_value_u8 + 2) % 4; - data_buffer_64.insertFromRight(&l_new_value_u8, (48 + (l_element_u8 * 4)), 2); - } - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(50, 2); - rc_num = rc_num | data_buffer_64.clearBit(54, 2); - rc_num = rc_num | data_buffer_64.clearBit(58, 2); - rc_num = rc_num | data_buffer_64.clearBit(62, 2); - - for ( uint8_t l_element_u8 = 0; l_element_u8 < 4; l_element_u8 += 1 ) { - l_value_u8 = 0; - data_buffer_64.extractToRight(&l_value_u8, (48 + (l_element_u8 * 4)), 2); - l_new_value_u8 = (l_value_u8 + 2) % 4; - data_buffer_64.insertFromRight(&l_new_value_u8, (48 + (l_element_u8 * 4)), 2); - } - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(50, 2); - rc_num = rc_num | data_buffer_64.clearBit(54, 2); - rc_num = rc_num | data_buffer_64.clearBit(58, 2); - rc_num = rc_num | data_buffer_64.clearBit(62, 2); - - for ( uint8_t l_element_u8 = 0; l_element_u8 < 4; l_element_u8 += 1 ) { - l_value_u8 = 0; - data_buffer_64.extractToRight(&l_value_u8, (48 + (l_element_u8 * 4)), 2); - l_new_value_u8 = (l_value_u8 + 2) % 4; - data_buffer_64.insertFromRight(&l_new_value_u8, (48 + (l_element_u8 * 4)), 2); - } - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(50, 2); - rc_num = rc_num | data_buffer_64.clearBit(54, 2); - rc_num = rc_num | data_buffer_64.clearBit(58, 2); - rc_num = rc_num | data_buffer_64.clearBit(62, 2); - - for ( uint8_t l_element_u8 = 0; l_element_u8 < 4; l_element_u8 += 1 ) { - l_value_u8 = 0; - data_buffer_64.extractToRight(&l_value_u8, (48 + (l_element_u8 * 4)), 2); - l_new_value_u8 = (l_value_u8 + 2) % 4; - data_buffer_64.insertFromRight(&l_new_value_u8, (48 + (l_element_u8 * 4)), 2); - } - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(50, 2); - rc_num = rc_num | data_buffer_64.clearBit(54, 2); - rc_num = rc_num | data_buffer_64.clearBit(58, 2); - rc_num = rc_num | data_buffer_64.clearBit(62, 2); - - for ( uint8_t l_element_u8 = 0; l_element_u8 < 4; l_element_u8 += 1 ) { - l_value_u8 = 0; - data_buffer_64.extractToRight(&l_value_u8, (48 + (l_element_u8 * 4)), 2); - l_new_value_u8 = (l_value_u8 + 2) % 4; - data_buffer_64.insertFromRight(&l_new_value_u8, (48 + (l_element_u8 * 4)), 2); - } - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); - if (rc) return rc; - + mss_read_center_workaround(i_target, mbaPosition, port, group); } } @@ -980,6 +824,723 @@ ReturnCode mss_check_error_status( Target& i_target, return rc; } +ReturnCode mss_read_center_workaround( + Target& i_target, + uint8_t i_mbaPosition, + uint32_t i_port, + uint32_t i_rank_group + ) +{ + + ReturnCode rc; + uint32_t rc_num = 0; + ecmdDataBufferBase data_buffer_64(64); + + + uint64_t DQSCLK_RD_PHASE_ADDR_0 = 0; + uint64_t DQSCLK_RD_PHASE_ADDR_1 = 0; + uint64_t DQSCLK_RD_PHASE_ADDR_2 = 0; + uint64_t DQSCLK_RD_PHASE_ADDR_3 = 0; + uint64_t DQSCLK_RD_PHASE_ADDR_4 = 0; + uint64_t RD_TIMING_REF0_ADDR_0 = 0; + uint64_t RD_TIMING_REF0_ADDR_1 = 0; + uint64_t RD_TIMING_REF0_ADDR_2 = 0; + uint64_t RD_TIMING_REF0_ADDR_3 = 0; + uint64_t RD_TIMING_REF0_ADDR_4 = 0; + uint64_t RD_TIMING_REF1_ADDR_0 = 0; + uint64_t RD_TIMING_REF1_ADDR_1 = 0; + uint64_t RD_TIMING_REF1_ADDR_2 = 0; + uint64_t RD_TIMING_REF1_ADDR_3 = 0; + uint64_t RD_TIMING_REF1_ADDR_4 = 0; + uint8_t l_value_u8 = 0; + uint8_t l_new_value_u8 = 0; + uint8_t quad0_workaround_type = 2; + uint8_t quad1_workaround_type = 2; + uint8_t quad2_workaround_type = 2; + uint8_t quad3_workaround_type = 2; + uint8_t dqs_clk_increment_wa0 = 0; + uint8_t dqs_clk_increment_wa1 = 3; + uint8_t dqs_clk_increment_wa2 = 2; + uint8_t read_phase_value_wa0 = 0; + uint8_t read_phase_value_wa1 = 0; + uint8_t read_phase_value_wa2 = 0; + uint8_t dqs_clk_increment_quad0 = 2; + uint8_t dqs_clk_increment_quad1 = 2; + uint8_t dqs_clk_increment_quad2 = 2; + uint8_t dqs_clk_increment_quad3 = 2; + uint8_t read_phase_value_quad0 = 0; + uint8_t read_phase_value_quad1 = 0; + uint8_t read_phase_value_quad2 = 0; + uint8_t read_phase_value_quad3 = 0; + uint8_t l_timing_ref_quad0 = 0; + uint8_t l_timing_ref_quad1 = 0; + uint8_t l_timing_ref_quad2 = 0; + uint8_t l_timing_ref_quad3 = 0; + + FAPI_INF( "+++ Read Centering Workaround on MBA: %d Port: %d rank group: %d +++", i_mbaPosition, i_port, i_rank_group); + FAPI_INF( "+++ Choosing New RD PHASE SELECT values based on timing values. +++"); + FAPI_INF( "+++ Incrementing DQS CLK PHASE SELECT regs based on timing values. +++"); + + if ( i_port == 0 ) + { + + RD_TIMING_REF0_ADDR_0 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_0_0x800000700301143F; + RD_TIMING_REF0_ADDR_1 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_1_0x800004700301143F; + RD_TIMING_REF0_ADDR_2 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_2_0x800008700301143F; + RD_TIMING_REF0_ADDR_3 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_3_0x80000C700301143F; + RD_TIMING_REF0_ADDR_4 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_4_0x800010700301143F; + RD_TIMING_REF1_ADDR_0 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_0_0x800000710301143F; + RD_TIMING_REF1_ADDR_1 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_1_0x800004710301143F; + RD_TIMING_REF1_ADDR_2 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_2_0x800008710301143F; + RD_TIMING_REF1_ADDR_3 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_3_0x80000C710301143F; + RD_TIMING_REF1_ADDR_4 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_4_0x800010710301143F; + + if ( i_rank_group == 0 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; + + } + else if ( i_rank_group == 1 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; + + } + else if ( i_rank_group == 2 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; + + } + else if ( i_rank_group == 3 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; + + } + } + else if (i_port == 1 ) + { + + RD_TIMING_REF0_ADDR_0 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_0_0x800100700301143F; + RD_TIMING_REF0_ADDR_1 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_1_0x800104700301143F; + RD_TIMING_REF0_ADDR_2 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_2_0x800108700301143F; + RD_TIMING_REF0_ADDR_3 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_3_0x80010C700301143F; + RD_TIMING_REF0_ADDR_4 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_4_0x800110700301143F; + RD_TIMING_REF1_ADDR_0 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_0_0x800100710301143F; + RD_TIMING_REF1_ADDR_1 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_1_0x800104710301143F; + RD_TIMING_REF1_ADDR_2 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_2_0x800108710301143F; + RD_TIMING_REF1_ADDR_3 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_3_0x80010C710301143F; + RD_TIMING_REF1_ADDR_4 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_4_0x800110710301143F; + + if ( i_rank_group == 0 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; + + } + else if ( i_rank_group == 1 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; + + + } + else if ( i_rank_group == 2 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; + + } + else if ( i_rank_group == 3 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; + + } + } + + //Block 0 + rc = fapiGetScom(i_target, RD_TIMING_REF0_ADDR_0, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad0, 49, 7); + rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad1, 57, 7); + rc = fapiGetScom(i_target, RD_TIMING_REF1_ADDR_0, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad2, 49, 7); + rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad3, 57, 7); + + if ( quad0_workaround_type == 0 ) + { + dqs_clk_increment_quad0 = dqs_clk_increment_wa0; + read_phase_value_quad0 = read_phase_value_wa0; + } + else if ( quad0_workaround_type == 1 ) + { + dqs_clk_increment_quad0 = dqs_clk_increment_wa1; + read_phase_value_quad0 = read_phase_value_wa1; + } + else if ( quad0_workaround_type == 2 ) + { + dqs_clk_increment_quad0 = dqs_clk_increment_wa2; + read_phase_value_quad0 = read_phase_value_wa2; + } + FAPI_INF( "+++ Block 0 Quad 0 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad0, read_phase_value_quad0); + + if ( quad1_workaround_type == 0 ) + { + dqs_clk_increment_quad1 = dqs_clk_increment_wa0; + read_phase_value_quad1 = read_phase_value_wa0; + } + else if ( quad1_workaround_type == 1 ) + { + dqs_clk_increment_quad1 = dqs_clk_increment_wa1; + read_phase_value_quad1 = read_phase_value_wa1; + } + else if ( quad1_workaround_type == 2 ) + { + dqs_clk_increment_quad1 = dqs_clk_increment_wa2; + read_phase_value_quad1 = read_phase_value_wa2; + } + FAPI_INF( "+++ Block 0 Quad 1 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad1, read_phase_value_quad1); + + if ( quad2_workaround_type == 0 ) + { + dqs_clk_increment_quad2 = dqs_clk_increment_wa0; + read_phase_value_quad2 = read_phase_value_wa0; + } + else if ( quad2_workaround_type == 1 ) + { + dqs_clk_increment_quad2 = dqs_clk_increment_wa1; + read_phase_value_quad2 = read_phase_value_wa1; + } + else if ( quad2_workaround_type == 2 ) + { + dqs_clk_increment_quad2 = dqs_clk_increment_wa2; + read_phase_value_quad2 = read_phase_value_wa2; + } + FAPI_INF( "+++ Block 0 Quad 2 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad2, read_phase_value_quad2); + + if ( quad3_workaround_type == 0 ) + { + dqs_clk_increment_quad3 = dqs_clk_increment_wa0; + read_phase_value_quad3 = read_phase_value_wa0; + } + else if ( quad3_workaround_type == 1 ) + { + dqs_clk_increment_quad3 = dqs_clk_increment_wa1; + read_phase_value_quad3 = read_phase_value_wa1; + } + else if ( quad3_workaround_type == 2 ) + { + dqs_clk_increment_quad3 = dqs_clk_increment_wa2; + read_phase_value_quad3 = read_phase_value_wa2; + } + FAPI_INF( "+++ Block 0 Quad 3 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad3, read_phase_value_quad3); + + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); + if (rc) return rc; + + // Set Read Phase. + rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad0, 50, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad1, 54, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad2, 58, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad3, 62, 2); + + //Increment dqs clk. 4 is the limit, wrap around (IE 5 = 1, 6 = 2) + l_value_u8 = 0; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 48, 2); + l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad0) % 4; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 48, 2); + l_value_u8 = 0; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 52, 2); + l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad1) % 4; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 52, 2); + l_value_u8 = 0; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 56, 2); + l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad2) % 4; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 56, 2); + l_value_u8 = 0; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 60, 2); + l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad3) % 4; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 60, 2); + + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); + if (rc) return rc; + + //Block 1 + rc = fapiGetScom(i_target, RD_TIMING_REF0_ADDR_1, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad0, 49, 7); + rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad1, 57, 7); + rc = fapiGetScom(i_target, RD_TIMING_REF1_ADDR_1, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad2, 49, 7); + rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad3, 57, 7); + + + if ( quad0_workaround_type == 0 ) + { + dqs_clk_increment_quad0 = dqs_clk_increment_wa0; + read_phase_value_quad0 = read_phase_value_wa0; + } + else if ( quad0_workaround_type == 1 ) + { + dqs_clk_increment_quad0 = dqs_clk_increment_wa1; + read_phase_value_quad0 = read_phase_value_wa1; + } + else if ( quad0_workaround_type == 2 ) + { + dqs_clk_increment_quad0 = dqs_clk_increment_wa2; + read_phase_value_quad0 = read_phase_value_wa2; + } + FAPI_INF( "+++ Block 1 Quad 0 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad0, read_phase_value_quad0); + + if ( quad1_workaround_type == 0 ) + { + dqs_clk_increment_quad1 = dqs_clk_increment_wa0; + read_phase_value_quad1 = read_phase_value_wa0; + } + else if ( quad1_workaround_type == 1 ) + { + dqs_clk_increment_quad1 = dqs_clk_increment_wa1; + read_phase_value_quad1 = read_phase_value_wa1; + } + else if ( quad1_workaround_type == 2 ) + { + dqs_clk_increment_quad1 = dqs_clk_increment_wa2; + read_phase_value_quad1 = read_phase_value_wa2; + } + FAPI_INF( "+++ Block 1 Quad 1 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad1, read_phase_value_quad1); + + if ( quad2_workaround_type == 0 ) + { + dqs_clk_increment_quad2 = dqs_clk_increment_wa0; + read_phase_value_quad2 = read_phase_value_wa0; + } + else if ( quad2_workaround_type == 1 ) + { + dqs_clk_increment_quad2 = dqs_clk_increment_wa1; + read_phase_value_quad2 = read_phase_value_wa1; + } + else if ( quad2_workaround_type == 2 ) + { + dqs_clk_increment_quad2 = dqs_clk_increment_wa2; + read_phase_value_quad2 = read_phase_value_wa2; + } + FAPI_INF( "+++ Block 1 Quad 2 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad2, read_phase_value_quad2); + + if ( quad3_workaround_type == 0 ) + { + dqs_clk_increment_quad3 = dqs_clk_increment_wa0; + read_phase_value_quad3 = read_phase_value_wa0; + } + else if ( quad3_workaround_type == 1 ) + { + dqs_clk_increment_quad3 = dqs_clk_increment_wa1; + read_phase_value_quad3 = read_phase_value_wa1; + } + else if ( quad3_workaround_type == 2 ) + { + dqs_clk_increment_quad3 = dqs_clk_increment_wa2; + read_phase_value_quad3 = read_phase_value_wa2; + } + FAPI_INF( "+++ Block 1 Quad 3 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad3, read_phase_value_quad3); + + + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); + if (rc) return rc; + + // Set Read Phase. + rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad0, 50, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad1, 54, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad2, 58, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad3, 62, 2); + + //Increment dqs clk. 4 is the limit, wrap around (IE 5 = 1, 6 = 2) + l_value_u8 = 0; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 48, 2); + l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad0) % 4; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 48, 2); + l_value_u8 = 0; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 52, 2); + l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad1) % 4; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 52, 2); + l_value_u8 = 0; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 56, 2); + l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad2) % 4; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 56, 2); + l_value_u8 = 0; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 60, 2); + l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad3) % 4; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 60, 2); + + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); + if (rc) return rc; + + //Block 2 + rc = fapiGetScom(i_target, RD_TIMING_REF0_ADDR_2, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad0, 49, 7); + rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad1, 57, 7); + rc = fapiGetScom(i_target, RD_TIMING_REF1_ADDR_2, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad2, 49, 7); + rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad3, 57, 7); + + + if ( quad0_workaround_type == 0 ) + { + dqs_clk_increment_quad0 = dqs_clk_increment_wa0; + read_phase_value_quad0 = read_phase_value_wa0; + } + else if ( quad0_workaround_type == 1 ) + { + dqs_clk_increment_quad0 = dqs_clk_increment_wa1; + read_phase_value_quad0 = read_phase_value_wa1; + } + else if ( quad0_workaround_type == 2 ) + { + dqs_clk_increment_quad0 = dqs_clk_increment_wa2; + read_phase_value_quad0 = read_phase_value_wa2; + } + FAPI_INF( "+++ Block 2 Quad 0 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad0, read_phase_value_quad0); + + if ( quad1_workaround_type == 0 ) + { + dqs_clk_increment_quad1 = dqs_clk_increment_wa0; + read_phase_value_quad1 = read_phase_value_wa0; + } + else if ( quad1_workaround_type == 1 ) + { + dqs_clk_increment_quad1 = dqs_clk_increment_wa1; + read_phase_value_quad1 = read_phase_value_wa1; + } + else if ( quad1_workaround_type == 2 ) + { + dqs_clk_increment_quad1 = dqs_clk_increment_wa2; + read_phase_value_quad1 = read_phase_value_wa2; + } + FAPI_INF( "+++ Block 2 Quad 1 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad1, read_phase_value_quad1); + + if ( quad2_workaround_type == 0 ) + { + dqs_clk_increment_quad2 = dqs_clk_increment_wa0; + read_phase_value_quad2 = read_phase_value_wa0; + } + else if ( quad2_workaround_type == 1 ) + { + dqs_clk_increment_quad2 = dqs_clk_increment_wa1; + read_phase_value_quad2 = read_phase_value_wa1; + } + else if ( quad2_workaround_type == 2 ) + { + dqs_clk_increment_quad2 = dqs_clk_increment_wa2; + read_phase_value_quad2 = read_phase_value_wa2; + } + FAPI_INF( "+++ Block 2 Quad 2 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad2, read_phase_value_quad2); + + if ( quad3_workaround_type == 0 ) + { + dqs_clk_increment_quad3 = dqs_clk_increment_wa0; + read_phase_value_quad3 = read_phase_value_wa0; + } + else if ( quad3_workaround_type == 1 ) + { + dqs_clk_increment_quad3 = dqs_clk_increment_wa1; + read_phase_value_quad3 = read_phase_value_wa1; + } + else if ( quad3_workaround_type == 2 ) + { + dqs_clk_increment_quad3 = dqs_clk_increment_wa2; + read_phase_value_quad3 = read_phase_value_wa2; + } + FAPI_INF( "+++ Block 2 Quad 3 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad3, read_phase_value_quad3); + + + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); + if (rc) return rc; + + // Set Read Phase. + rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad0, 50, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad1, 54, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad2, 58, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad3, 62, 2); + + //Increment dqs clk. 4 is the limit, wrap around (IE 5 = 1, 6 = 2) + l_value_u8 = 0; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 48, 2); + l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad0) % 4; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 48, 2); + l_value_u8 = 0; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 52, 2); + l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad1) % 4; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 52, 2); + l_value_u8 = 0; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 56, 2); + l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad2) % 4; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 56, 2); + l_value_u8 = 0; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 60, 2); + l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad3) % 4; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 60, 2); + + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); + if (rc) return rc; + + //Block 3 + rc = fapiGetScom(i_target, RD_TIMING_REF0_ADDR_3, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad0, 49, 7); + rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad1, 57, 7); + rc = fapiGetScom(i_target, RD_TIMING_REF1_ADDR_3, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad2, 49, 7); + rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad3, 57, 7); + + if ( quad0_workaround_type == 0 ) + { + dqs_clk_increment_quad0 = dqs_clk_increment_wa0; + read_phase_value_quad0 = read_phase_value_wa0; + } + else if ( quad0_workaround_type == 1 ) + { + dqs_clk_increment_quad0 = dqs_clk_increment_wa1; + read_phase_value_quad0 = read_phase_value_wa1; + } + else if ( quad0_workaround_type == 2 ) + { + dqs_clk_increment_quad0 = dqs_clk_increment_wa2; + read_phase_value_quad0 = read_phase_value_wa2; + } + FAPI_INF( "+++ Block 3 Quad 0 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad0, read_phase_value_quad0); + + if ( quad1_workaround_type == 0 ) + { + dqs_clk_increment_quad1 = dqs_clk_increment_wa0; + read_phase_value_quad1 = read_phase_value_wa0; + } + else if ( quad1_workaround_type == 1 ) + { + dqs_clk_increment_quad1 = dqs_clk_increment_wa1; + read_phase_value_quad1 = read_phase_value_wa1; + } + else if ( quad1_workaround_type == 2 ) + { + dqs_clk_increment_quad1 = dqs_clk_increment_wa2; + read_phase_value_quad1 = read_phase_value_wa2; + } + FAPI_INF( "+++ Block 3 Quad 1 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad1, read_phase_value_quad1); + + if ( quad2_workaround_type == 0 ) + { + dqs_clk_increment_quad2 = dqs_clk_increment_wa0; + read_phase_value_quad2 = read_phase_value_wa0; + } + else if ( quad2_workaround_type == 1 ) + { + dqs_clk_increment_quad2 = dqs_clk_increment_wa1; + read_phase_value_quad2 = read_phase_value_wa1; + } + else if ( quad2_workaround_type == 2 ) + { + dqs_clk_increment_quad2 = dqs_clk_increment_wa2; + read_phase_value_quad2 = read_phase_value_wa2; + } + FAPI_INF( "+++ Block 3 Quad 2 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad2, read_phase_value_quad2); + + if ( quad3_workaround_type == 0 ) + { + dqs_clk_increment_quad3 = dqs_clk_increment_wa0; + read_phase_value_quad3 = read_phase_value_wa0; + } + else if ( quad3_workaround_type == 1 ) + { + dqs_clk_increment_quad3 = dqs_clk_increment_wa1; + read_phase_value_quad3 = read_phase_value_wa1; + } + else if ( quad3_workaround_type == 2 ) + { + dqs_clk_increment_quad3 = dqs_clk_increment_wa2; + read_phase_value_quad3 = read_phase_value_wa2; + } + FAPI_INF( "+++ Block 3 Quad 3 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad3, read_phase_value_quad3); + + + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); + if (rc) return rc; + + // Set Read Phase. + rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad0, 50, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad1, 54, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad2, 58, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad3, 62, 2); + + //Increment dqs clk. 4 is the limit, wrap around (IE 5 = 1, 6 = 2) + l_value_u8 = 0; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 48, 2); + l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad0) % 4; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 48, 2); + l_value_u8 = 0; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 52, 2); + l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad1) % 4; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 52, 2); + l_value_u8 = 0; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 56, 2); + l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad2) % 4; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 56, 2); + l_value_u8 = 0; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 60, 2); + l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad3) % 4; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 60, 2); + + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); + if (rc) return rc; + + //Block 4 + rc = fapiGetScom(i_target, RD_TIMING_REF0_ADDR_4, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad0, 49, 7); + rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad1, 57, 7); + rc = fapiGetScom(i_target, RD_TIMING_REF1_ADDR_4, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad2, 49, 7); + rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad3, 57, 7); + + + if ( quad0_workaround_type == 0 ) + { + dqs_clk_increment_quad0 = dqs_clk_increment_wa0; + read_phase_value_quad0 = read_phase_value_wa0; + } + else if ( quad0_workaround_type == 1 ) + { + dqs_clk_increment_quad0 = dqs_clk_increment_wa1; + read_phase_value_quad0 = read_phase_value_wa1; + } + else if ( quad0_workaround_type == 2 ) + { + dqs_clk_increment_quad0 = dqs_clk_increment_wa2; + read_phase_value_quad0 = read_phase_value_wa2; + } + FAPI_INF( "+++ Block 4 Quad 0 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad0, read_phase_value_quad0); + + if ( quad1_workaround_type == 0 ) + { + dqs_clk_increment_quad1 = dqs_clk_increment_wa0; + read_phase_value_quad1 = read_phase_value_wa0; + } + else if ( quad1_workaround_type == 1 ) + { + dqs_clk_increment_quad1 = dqs_clk_increment_wa1; + read_phase_value_quad1 = read_phase_value_wa1; + } + else if ( quad1_workaround_type == 2 ) + { + dqs_clk_increment_quad1 = dqs_clk_increment_wa2; + read_phase_value_quad1 = read_phase_value_wa2; + } + FAPI_INF( "+++ Block 4 Quad 1 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad1, read_phase_value_quad1); + + if ( quad2_workaround_type == 0 ) + { + dqs_clk_increment_quad2 = dqs_clk_increment_wa0; + read_phase_value_quad2 = read_phase_value_wa0; + } + else if ( quad2_workaround_type == 1 ) + { + dqs_clk_increment_quad2 = dqs_clk_increment_wa1; + read_phase_value_quad2 = read_phase_value_wa1; + } + else if ( quad2_workaround_type == 2 ) + { + dqs_clk_increment_quad2 = dqs_clk_increment_wa2; + read_phase_value_quad2 = read_phase_value_wa2; + } + FAPI_INF( "+++ Block 4 Quad 2 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad2, read_phase_value_quad2); + + if ( quad3_workaround_type == 0 ) + { + dqs_clk_increment_quad3 = dqs_clk_increment_wa0; + read_phase_value_quad3 = read_phase_value_wa0; + } + else if ( quad3_workaround_type == 1 ) + { + dqs_clk_increment_quad3 = dqs_clk_increment_wa1; + read_phase_value_quad3 = read_phase_value_wa1; + } + else if ( quad3_workaround_type == 2 ) + { + dqs_clk_increment_quad3 = dqs_clk_increment_wa2; + read_phase_value_quad3 = read_phase_value_wa2; + } + FAPI_INF( "+++ Block 4 Quad 3 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad3, read_phase_value_quad3); + + + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); + if (rc) return rc; + + // Set Read Phase. + rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad0, 50, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad1, 54, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad2, 58, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad3, 62, 2); + + //Increment dqs clk. 4 is the limit, wrap around (IE 5 = 1, 6 = 2) + l_value_u8 = 0; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 48, 2); + l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad0) % 4; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 48, 2); + l_value_u8 = 0; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 52, 2); + l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad1) % 4; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 52, 2); + l_value_u8 = 0; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 56, 2); + l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad2) % 4; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 56, 2); + l_value_u8 = 0; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 60, 2); + l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad3) % 4; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 60, 2); + + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); + if (rc) return rc; + + if(rc_num) + { + rc.setEcmdError(rc_num); + return rc; + } + + return rc; +} + ReturnCode mss_rtt_nom_rtt_wr_swap( Target& i_target, uint32_t i_port_number, @@ -992,9 +1553,9 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( // Target MBA level // This is a function written specifically for mss_draminit_training // Meant for placing RTT_WR into RTT_NOM within MR1 before wr_lvl - // If the function argument dram_rtt_nom_original is 0 it will put the original rtt_nom there + // If the function argument dram_rtt_nom_original has a value of 0xFF it will put the original rtt_nom there // and write rtt_wr to the rtt_nom value - // If the function argument dram_rtt_nom_original has a value it will write that value to rtt_nom. + // If the function argument dram_rtt_nom_original has any value besides 0xFF it will try to write that value to rtt_nom. ReturnCode rc; @@ -1046,6 +1607,7 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim); if(rc) return rc; + // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles rc_num = rc_num | csn_8.setBit(0,8); rc_num = rc_num | address_16.clearBit(0, 16); @@ -1324,7 +1886,7 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( if ( (mrs2_16.isBitClear(9)) && (mrs2_16.isBitClear(10)) ) { //RTT WR DISABLE - FAPI_INF( "DRAM_RTT_WR currently set to disable."); + FAPI_INF( "DRAM_RTT_WR currently set to Disable."); dram_rtt_wr = 0x00; //RTT NOM CODE FOR THIS VALUE IS @@ -1355,14 +1917,14 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( // If you have a 0 value in dram_rtt_nom_orignal // you will use dram_rtt_nom_original to save the original value - if (io_dram_rtt_nom_original == 0) + if (io_dram_rtt_nom_original == 0xFF) { io_dram_rtt_nom_original = dram_rtt_nom; dram_rtt_nom = dram_rtt_wr; if (dram_rtt_wr == 0x00) { - FAPI_INF( "DRAM_RTT_NOM to be set to DRAM_RTT_WR which is disable."); + FAPI_INF( "DRAM_RTT_NOM to be set to DRAM_RTT_WR which is Disable."); } else if (dram_rtt_wr == 0x80) { @@ -1373,7 +1935,7 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( FAPI_INF( "DRAM_RTT_NOM to be set to DRAM_RTT_WR which is 120 Ohm."); } } - else if (io_dram_rtt_nom_original != 0) + else if (io_dram_rtt_nom_original != 0xFF) { dram_rtt_nom = io_dram_rtt_nom_original; @@ -1408,6 +1970,11 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( // RTT_NOM set to 120 FAPI_INF( "DRAM_RTT_NOM being set back to 120 Ohm."); } + else + { + FAPI_INF( "Proposed DRAM_RTT_NOM value is a non-supported. Using Disabled."); + dram_rtt_nom = 0x00; + } } diff --git a/src/usr/hwpf/hwp/dram_training/mss_termination_control.C b/src/usr/hwpf/hwp/dram_training/mss_termination_control.C index f94aac915..c15ffa5ac 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_termination_control.C +++ b/src/usr/hwpf/hwp/dram_training/mss_termination_control.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_termination_control.C,v 1.16 2013/01/24 20:56:09 mwuu Exp $ +// $Id: mss_termination_control.C,v 1.18 2013/03/05 15:40:38 mwuu Exp $ /* File is created by SARAVANAN SETHURAMAN on Thur 29 Sept 2011. */ //------------------------------------------------------------------------------ @@ -43,6 +43,8 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.18 | mwuu |25-Feb-13| Added return code per port for config slew FN +// 1.17 | mwuu |07-Feb-13| Improved the debug and trace messages. // 1.16 | mwuu |24-Jan-13| Fixed cal_slew extraction of bits. // 1.15 | mwuu |14-Jan-13| Altered error message for unsupported slew rate // 1.14 | mwuu |14-Jan-13| Removed error messages from slew cal fail when @@ -178,7 +180,7 @@ fapi::ReturnCode config_drv_imp(const fapi::Target & i_target_mba, uint8_t i_por DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_4_0x800010790301143F, data_buffer); if(rc) return rc; } - else // Port = 1 + else // port = 1 { rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_0_0x800100780301143F, @@ -420,46 +422,45 @@ fapi::ReturnCode config_slew_rate(const fapi::Target & i_target_mba, if (i_port >= MAX_NUM_PORTS) { - FAPI_ERR("Slew port input(%u) out of bounds", i_port); - FAPI_SET_HWP_ERROR(rc, RC_MSS_INVALID_FN_INPUT_ERROR); - return rc; + FAPI_ERR("Slew port input(%u) out of bounds", i_port); + FAPI_SET_HWP_ERROR(rc, RC_MSS_INVALID_FN_INPUT_ERROR); + return rc; } if (i_slew_type >= MAX_NUM_SLEW_TYPES) { - FAPI_ERR("Slew type input(%u) out of bounds, (>= %u)", - i_slew_type, MAX_NUM_SLEW_TYPES); - FAPI_SET_HWP_ERROR(rc, RC_MSS_INVALID_FN_INPUT_ERROR); - return rc; + FAPI_ERR("Slew type input(%u) out of bounds, (>= %u)", + i_slew_type, MAX_NUM_SLEW_TYPES); + FAPI_SET_HWP_ERROR(rc, RC_MSS_INVALID_FN_INPUT_ERROR); + return rc; } switch (i_slew_rate) // get slew index { - case SLEW_MAXV_NS: // max slew - FAPI_INF("Slew rate is set to MAX, using bypass mode"); - slew_cal_value = 0; // slew cal value for bypass mode - break; - case SLEW_6V_NS: - slew_idx = 3; - break; - case SLEW_5V_NS: - slew_idx = 2; - break; - case SLEW_4V_NS: - slew_idx = 1; - break; - case SLEW_3V_NS: - slew_idx = 0; - break; - default: - FAPI_ERR("Slew rate input(%u) out of bounds", i_slew_rate); - FAPI_SET_HWP_ERROR(rc, RC_MSS_INVALID_FN_INPUT_ERROR); - return rc; + case SLEW_MAXV_NS: // max slew + FAPI_INF("Slew rate is set to MAX, using bypass mode"); + slew_cal_value = 0; // slew cal value for bypass mode + break; + case SLEW_6V_NS: + slew_idx = 3; + break; + case SLEW_5V_NS: + slew_idx = 2; + break; + case SLEW_4V_NS: + slew_idx = 1; + break; + case SLEW_3V_NS: + slew_idx = 0; + break; + default: + FAPI_ERR("Slew rate input(%u) out of bounds", i_slew_rate); + FAPI_SET_HWP_ERROR(rc, RC_MSS_INVALID_FN_INPUT_ERROR); + return rc; } if (i_slew_type == SLEW_TYPE_DATA) { - FAPI_INF("Setting data (dq/dqs) slew"); switch (i_slew_imp) // get impedance index for data { case OHM40: @@ -481,205 +482,219 @@ fapi::ReturnCode config_slew_rate(const fapi::Target & i_target_mba, return rc; } - if (i_slew_rate != SLEW_MAXV_NS) - { - rc = FAPI_ATTR_GET(ATTR_MSS_SLEW_RATE_DATA, &i_target_mba, - calibrated_slew_rate_table); if(rc) return rc; + if (i_slew_rate != SLEW_MAXV_NS) + { + rc = FAPI_ATTR_GET(ATTR_MSS_SLEW_RATE_DATA, &i_target_mba, + calibrated_slew_rate_table); if(rc) return rc; - slew_cal_value = - calibrated_slew_rate_table[i_port][imp_idx][slew_idx]; - } + slew_cal_value = + calibrated_slew_rate_table[i_port][imp_idx][slew_idx]; + } - FAPI_DBG("port%u type=%u imp_idx=%u slew_idx=%u cal_slew=%u", + if (slew_cal_value > MAX_SLEW_VALUE) + { + FAPI_INF("WARNING: Slew rate(0x%02x) unsupported, " + "but continuing... !!", slew_cal_value); + slew_cal_value = slew_cal_value & 0x0F; + } + + FAPI_INF("Setting DATA (dq/dqs) slew register, imped=%i, slewrate=%i, " + "reg_val=0x%X", i_slew_imp, i_slew_rate, slew_cal_value); + + FAPI_DBG("port%u type=%u imp_idx=%u slew_idx=%u cal_slew=%u", i_port, i_slew_type, imp_idx, slew_idx, slew_cal_value); - if (slew_cal_value > MAX_SLEW_VALUE) - { - FAPI_INF("!! Slew rate(0x%02x) unsupported, but continuing... !!", - slew_cal_value); - slew_cal_value = slew_cal_value & 0x0F; - } + if (i_port == 0) // port dq/dqs slew + { + rc = fapiGetScom(i_target_mba, + DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_0_0x800000750301143F, + data_buffer); if(rc) return rc; - if (i_port == 0) // port dq/dqs slew - { - rc = fapiGetScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_0_0x800000750301143F, - data_buffer); if(rc) return rc; + rc_num |= data_buffer.insertFromRight(slew_cal_value, 56, 4); + if (rc_num) + { + FAPI_ERR("Error in setting up DATA slew buffer"); + rc.setEcmdError(rc_num); + return rc; + } + // switch this later to use broadcast address, 0x80003C750301143F P0_[0:4] + rc = fapiPutScom(i_target_mba, + DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_0_0x800000750301143F, + data_buffer); if(rc) return rc; + rc = fapiPutScom(i_target_mba, + DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_1_0x800004750301143F, + data_buffer); if(rc) return rc; + rc = fapiPutScom(i_target_mba, + DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_2_0x800008750301143F, + data_buffer); if(rc) return rc; + rc = fapiPutScom(i_target_mba, + DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_3_0x80000C750301143F, + data_buffer); if(rc) return rc; + rc = fapiPutScom(i_target_mba, + DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_4_0x800010750301143F, + data_buffer); if(rc) return rc; + } + else // port 1 dq/dqs slew + { + rc = fapiGetScom(i_target_mba, + DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_0_0x800100750301143F, + data_buffer); if(rc) return rc; - rc_num = rc_num | data_buffer.insertFromRight(slew_cal_value, 56, 4); - if (rc_num) - { - FAPI_ERR("Error in setting up DATA slew buffer"); + rc_num |= data_buffer.insertFromRight(slew_cal_value, 56, 4); + if (rc_num) + { + FAPI_ERR("Error in setting up DATA slew buffer"); rc.setEcmdError(rc_num); return rc; - } + } + // switch this later to use broadcast address, 0x80013C750301143F P1_[0:4] + rc = fapiPutScom(i_target_mba, + DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_0_0x800100750301143F, + data_buffer); if(rc) return rc; + rc = fapiPutScom(i_target_mba, + DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_1_0x800104750301143F, + data_buffer); if(rc) return rc; + rc = fapiPutScom(i_target_mba, + DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_2_0x800108750301143F, + data_buffer); if(rc) return rc; + rc = fapiPutScom(i_target_mba, + DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_3_0x80010C750301143F, + data_buffer); if(rc) return rc; + rc = fapiPutScom(i_target_mba, + DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_4_0x800110750301143F, + data_buffer); if(rc) return rc; + } // end port 1 DATA + } // end DATA + else // Slew type = ADR + { + uint8_t adr_pos = 48; // SLEW_CTL0(48:51) of reg for ADR command slew - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_0_0x800000750301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_1_0x800004750301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_2_0x800008750301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_3_0x80000C750301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_4_0x800010750301143F, - data_buffer); if(rc) return rc; - } - else // port 1 dq/dqs slew - { - rc = fapiGetScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_0_0x800100750301143F, - data_buffer); if(rc) return rc; + for(uint8_t i=0; i < MAX_NUM_IMP; i++) // find ADR imp index + { + if (adr_imp_array[i] == i_slew_imp) + { + imp_idx = i; + break; + } + } + if ((i_slew_imp == OHM24) || (i_slew_imp == OHM34) || + (imp_idx >= MAX_NUM_IMP)) + { + FAPI_ERR("Slew impedance input(%u) out of bounds", i_slew_imp); + FAPI_SET_HWP_ERROR(rc, RC_MSS_IMP_INPUT_ERROR); + return rc; + } - rc_num = rc_num | data_buffer.insertFromRight(slew_cal_value,56,4); - if (rc_num) - { - FAPI_ERR( "Error in setting up DATA slew buffer"); - rc.setEcmdError(rc_num); - return rc; - } + if (i_slew_rate == SLEW_MAXV_NS) + { + slew_cal_value = 0; + } + else + { + rc = FAPI_ATTR_GET(ATTR_MSS_SLEW_RATE_ADR, &i_target_mba, + calibrated_slew_rate_table); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_0_0x800100750301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_1_0x800104750301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_2_0x800108750301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_3_0x80010C750301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_4_0x800110750301143F, - data_buffer); if(rc) return rc; - } - } - else // Slew type = ADR - { - uint8_t adr_pos = 48; // SLEW_CTL0(48:51) of reg for ADR command slew - - switch (i_slew_type) // get impedance index for data - { - case SLEW_TYPE_ADR_ADDR: - // CTL0 for command slew (A0:15, BA0:3, ACT, PAR, CAS, RAS, WE) - FAPI_INF("Setting ADR command/address slew in CTL0 register"); - adr_pos = 48; - break; - case SLEW_TYPE_ADR_CNTL: - // CTL1 for control slew (CKE0:1, CKE4:5, ODT0:3, CSN0:3) - FAPI_INF("Setting ADR control slew in CTL1 register"); - adr_pos = 52; - break; - case SLEW_TYPE_ADR_CLK: - // CTL2 for clock slew (CLK0:3) - FAPI_INF("Setting ADR clock slew in CTL2 register"); - adr_pos = 56; - break; - case SLEW_TYPE_ADR_SPCKE: - // CTL3 for spare clock slew (CKE2:3) - FAPI_INF("Setting ADR Spare clock in CTL3 register"); - adr_pos = 60; - break; - } - for(uint8_t i=0; i < MAX_NUM_IMP; i++) // find ADR imp index - { - if (adr_imp_array[i] == i_slew_imp) + slew_cal_value = + calibrated_slew_rate_table[i_port][imp_idx][slew_idx]; + } + + if (slew_cal_value > MAX_SLEW_VALUE) { - imp_idx = i; - break; + FAPI_INF("!! Slew rate(0x%02x) unsupported, but continuing... !!", + slew_cal_value); + slew_cal_value = slew_cal_value & 0x0F; } - } - if ((i_slew_imp == OHM24) || (i_slew_imp == OHM34) || - (imp_idx >= MAX_NUM_IMP)) - { - FAPI_ERR("Slew impedance input(%u) out of bounds", i_slew_imp); - FAPI_SET_HWP_ERROR(rc, RC_MSS_IMP_INPUT_ERROR); - return rc; - } - if (i_slew_rate == SLEW_MAXV_NS) - { - slew_cal_value = 0; - } - else - { - rc = FAPI_ATTR_GET(ATTR_MSS_SLEW_RATE_ADR, &i_target_mba, - calibrated_slew_rate_table); if(rc) return rc; + switch (i_slew_type) // get impedance index for data + { + case SLEW_TYPE_ADR_ADDR: + // CTL0 for command slew (A0:15, BA0:3, ACT, PAR, CAS, RAS, WE) + FAPI_INF("Setting ADR command/address slew in CTL0 register " + "imped=%i, slewrate=%i, reg_val=0x%X", i_slew_imp, + i_slew_rate, slew_cal_value); + adr_pos = 48; + break; + case SLEW_TYPE_ADR_CNTL: + // CTL1 for control slew (CKE0:1, CKE4:5, ODT0:3, CSN0:3) + FAPI_INF("Setting ADR control slew in CTL1 register " + "imped=%i, slewrate=%i, reg_val=0x%X", i_slew_imp, + i_slew_rate, slew_cal_value); + adr_pos = 52; + break; + case SLEW_TYPE_ADR_CLK: + // CTL2 for clock slew (CLK0:3) + FAPI_INF("Setting ADR clock slew in CTL2 register " + "imped=%i, slewrate=%i, reg_val=0x%X", i_slew_imp, + i_slew_rate, slew_cal_value); + adr_pos = 56; + break; + case SLEW_TYPE_ADR_SPCKE: + // CTL3 for spare clock slew (CKE2:3) + FAPI_INF("Setting ADR Spare clock in CTL3 register " + "imped=%i, slewrate=%i, reg_val=0x%X", i_slew_imp, + i_slew_rate, slew_cal_value); + adr_pos = 60; + break; + } - slew_cal_value = - calibrated_slew_rate_table[i_port][imp_idx][slew_idx]; - } - FAPI_DBG("port%u type=%u slew_idx=%u imp_idx=%u cal_slew=%u", + FAPI_DBG("port%u type=%u slew_idx=%u imp_idx=%u cal_slew=%u", i_port, i_slew_type, slew_idx, imp_idx, slew_cal_value); - if (slew_cal_value > MAX_SLEW_VALUE) - { - FAPI_INF("!! Slew rate(0x%02x) unsupported, but continuing... !!", - slew_cal_value); - slew_cal_value = slew_cal_value & 0x0F; - } + if (i_port == 0) + { + rc = fapiGetScom(i_target_mba, + DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR0_0x8000401A0301143F, + data_buffer); if(rc) return rc; - if (i_port == 0) - { - rc = fapiGetScom(i_target_mba, + rc_num |= data_buffer.insertFromRight(slew_cal_value, adr_pos, 4); + if (rc_num) + { + FAPI_ERR( "Error in setting up ADR slew buffer"); + rc.setEcmdError(rc_num); + return rc; + } + // switch this later to use broadcast address, 0x80007C1A0301143f ADR[0:3] + rc = fapiPutScom(i_target_mba, DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR0_0x8000401A0301143F, data_buffer); if(rc) return rc; + rc = fapiPutScom(i_target_mba, + DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR1_0x8000441A0301143F, + data_buffer); if(rc) return rc; + rc = fapiPutScom(i_target_mba, + DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR2_0x8000481A0301143F, + data_buffer); if(rc) return rc; + rc = fapiPutScom(i_target_mba, + DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR3_0x80004C1A0301143F, + data_buffer); if(rc) return rc; + } + else // port 1 ADR slew + { + rc = fapiGetScom(i_target_mba, + DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR0_0x8001401A0301143F, + data_buffer); if(rc) return rc; - rc_num |= data_buffer.insertFromRight(slew_cal_value, adr_pos, 4); - if (rc_num) - { - FAPI_ERR( "Error in setting up ADR slew buffer"); - rc.setEcmdError(rc_num); - return rc; - } - - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR0_0x8000401A0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR1_0x8000441A0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR2_0x8000481A0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR3_0x80004C1A0301143F, - data_buffer); if(rc) return rc; - } - else // port 1 ADR slew - { - rc = fapiGetScom(i_target_mba, - DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR0_0x8001401A0301143F, - data_buffer); if(rc) return rc; - - rc_num |= data_buffer.insertFromRight(slew_cal_value, adr_pos, 4); - if (rc_num) - { - FAPI_ERR( "Error in setting up ADR slew buffer"); - rc.setEcmdError(rc_num); - return rc; - } - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR0_0x8001401A0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR1_0x8001441A0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR2_0x8001481A0301143F, - data_buffer); if(rc) return rc; - rc = fapiPutScom(i_target_mba, - DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR3_0x80014C1A0301143F, - data_buffer); if(rc) return rc; - } - } + rc_num |= data_buffer.insertFromRight(slew_cal_value, adr_pos, 4); + if (rc_num) + { + FAPI_ERR( "Error in setting up ADR slew buffer"); + rc.setEcmdError(rc_num); + return rc; + } + // switch this later to use broadcast address, 0x80017C1A0301143f ADR[0:3] + rc = fapiPutScom(i_target_mba, + DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR0_0x8001401A0301143F, + data_buffer); if(rc) return rc; + rc = fapiPutScom(i_target_mba, + DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR1_0x8001441A0301143F, + data_buffer); if(rc) return rc; + rc = fapiPutScom(i_target_mba, + DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR2_0x8001481A0301143F, + data_buffer); if(rc) return rc; + rc = fapiPutScom(i_target_mba, + DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR3_0x80014C1A0301143F, + data_buffer); if(rc) return rc; + } // end port 1 ADR + } // end ADR return rc; } @@ -879,7 +894,8 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target_mba) ecmdDataBufferBase ctl_reg(64); ecmdDataBufferBase stat_reg(64); - + + // DD level 1.0-1.1, Version 1.0 // [ddr3/4][dq/adr][speed][impedance][slew_rate] // note: Assumes standard voltage for DDR3(1.35V), DDR4(1.2V), // little endian, if >=128, lab only debug. @@ -1014,7 +1030,7 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target_mba) uint8_t port_val = (ports_valid & (0xF0 >> (4 * l_port))); if (port_val == 0) { - FAPI_INF("WARNING: Port %u is invalid from " + FAPI_INF("WARNING: port %u is invalid from " "ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR (0x%02x), skipping.", l_port, ports_valid); continue; @@ -1038,9 +1054,9 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target_mba) return rc; } - FAPI_INF("%s: Enabling slew calibration engine on Port %i: DDR%i(%u) " - "%u(%u)", i_target_mba.toEcmdString(), l_port, (ddr_type+2), - ddr_idx, ddr_freq, freq_idx); + FAPI_INF("Enabling slew calibration engine on port %i: DDR%i(%u) " + "%u(%u) in %s", l_port, (ddr_type+2), ddr_idx, ddr_freq, + freq_idx, i_target_mba.toEcmdString()); // DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_0x800080390301143F + port rc = fapiPutScom(i_target_mba, slew_cal_cntl[l_port], ctl_reg); @@ -1087,7 +1103,7 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target_mba) } else { - FAPI_DBG("polling finished in %i loops (%u ns)", + FAPI_DBG("polling finished in %i loops (%u ns)\n", poll_count, (100*poll_count)); } @@ -1097,6 +1113,8 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target_mba) // slew(4) 3V/ns=0, 4V/ns=1, 5V/ns=2, 6V/ns=3 for (uint8_t data_adr=0; data_adr < 2; data_adr++) { + FAPI_INF("Starting %s(%i) slew calibration...", + (data_adr ? "ADR" : "DATA"), data_adr); for (uint8_t imp=0; imp < MAX_NUM_IMP; imp++) { uint8_t cal_slew; @@ -1111,9 +1129,6 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target_mba) rc_ecmd |= ctl_reg.insertFromRight(cal_slew, 59, 5); rc_ecmd |= ctl_reg.setBit(START_BIT); // set start bit(48) - FAPI_DBG("%s Slew cntl_reg(48:63)=0x%04X, i_slew=%i,0x%02x " - "(59:63)", (data_adr ? "ADR" : "DATA"), - ctl_reg.getHalfWord(3), cal_slew, cal_slew); if (rc_ecmd) { FAPI_ERR("Error setting start bit or cal input value."); @@ -1121,10 +1136,12 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target_mba) return rc; } + FAPI_DBG("Slew data_adr=%i, imp_idx=%i, slewrate=%i, " + "i_slew=%i,0x%02X (59:63) cntl_reg(48:63)=0x%04X", + data_adr, imp, (slew+3), cal_slew, cal_slew, + ctl_reg.getHalfWord(3)); + // DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_0x800080390301143F + port - FAPI_INF("Starting slew calibration, ddr_idx=%i, " - "data_adr=%i, imp=%i, slewrate=%i", ddr_idx, data_adr, - imp, (slew+3)); rc = fapiPutScom(i_target_mba, slew_cal_cntl[l_port], ctl_reg); if (rc) { @@ -1153,7 +1170,6 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target_mba) rc.setEcmdError(rc_ecmd); return rc; } - FAPI_DBG("cal_status = %i",cal_status); if (cal_status != 0) break; // wait (1020 mclks / MAX_POLL_LOOPS) @@ -1175,13 +1191,20 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target_mba) else if (cal_status == 2) { FAPI_INF("WARNING: occurred during slew " - "calibration, imp=%i, slew=%i, input=0x%x " - "continuing...", imp, slew, (cal_slew & 0x1F)); + "calibration, imped=%i, slewrate=%i \n\t %s " + "\t\t\t [%i][%i][%i][%i][%i], input=0x%02X, " + "ctrl=0x%04X, status=0x%04X continuing...", + (data_adr ? adr_imp_array[imp] : + drv_imp_array[(4-imp)]), (slew+3), + i_target_mba.toEcmdString(), ddr_idx, data_adr, + freq_idx, imp, slew, (cal_slew & 0x1F), + ctl_reg.getHalfWord(3), + stat_reg.getHalfWord(3)); } cal_slew = cal_slew & 0x80; // clear bits 6:0 rc_ecmd = stat_reg.extractPreserve(&cal_slew, 60, 4, 4); FAPI_DBG("MSS_SLEW_RATE_%s port[%i]imp[%i]slew[%i] = " - "0x%02x", (data_adr ? "ADR" : "DATA"), l_port, + "0x%02x\n", (data_adr ? "ADR" : "DATA"), l_port, imp, slew, (cal_slew & 0xF)); if (rc_ecmd) { @@ -1207,19 +1230,24 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target_mba) { if (cal_status == 1) { - FAPI_ERR("Error occurred during slew calibration"); + FAPI_ERR("Error occurred during slew " + "calibration"); } else { FAPI_ERR("Slew calibration timed out, loop=%i", poll_count); } - FAPI_ERR("Slew calibration failed on %s slew: imp_idx=" - "%d, slew_idx=%d, slew_table=0x%02X, " - "status=0x%04X on %s!", - (data_adr ? "ADR" : "DATA"), imp, slew, - cal_slew, stat_reg.getHalfWord(3), - i_target_mba.toEcmdString()); + FAPI_ERR("Slew calibration failed on %s slew: " + "imp_idx=%d(%i ohms), slew_idx=%d(%i V/ns), " + "slew_table=0x%02X,\n\t\t\t ctl_reg=0x%04X, " + "status=0x%04X on %s!", + (data_adr ? "ADR" : "DATA"), imp, + (data_adr ? adr_imp_array[imp] : + drv_imp_array[(4-imp)]), slew, (slew+3), + cal_slew, stat_reg.getHalfWord(3), + ctl_reg.getHalfWord(3), + i_target_mba.toEcmdString()); FAPI_SET_HWP_ERROR(rc, RC_MSS_SLEW_CAL_ERROR); //return rc; @@ -1240,6 +1268,11 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target_mba) "DDRPHY_ADR_SLEW_CAL_CNTL register."); return rc; } + else + { + FAPI_INF("Finished slew calibration on port %i: " + "disabling cal engine\n", l_port); + } } // end port loop for (uint8_t rn=0; rn < MAX_NUM_PORTS; rn++) @@ -1250,7 +1283,7 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target_mba) return array_rcs[rn]; } } - FAPI_INF("Setting output slew tables ATTR_MSS_SLEW_RATE_DATA/ADR"); + FAPI_INF("Setting output slew tables ATTR_MSS_SLEW_RATE_DATA/ADR\n"); // ATTR_MSS_SLEW_RATE_DATA [2][4][4] port, imped, slew_rate rc = FAPI_ATTR_SET(ATTR_MSS_SLEW_RATE_DATA, &i_target_mba, calibrated_slew[0]); if (rc) @@ -1291,9 +1324,9 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target_mba) // convert enum value to actual ohms. for (uint8_t j=0; j < MAX_NUM_PORTS; j++) { - FAPI_INF("DQ_DQS IMP Attribute[%i] = %u", j, - slew_imp_val[SLEW_TYPE_DATA][IMP][j]); - +// FAPI_INF("DQ_DQS IMP Attribute[%i] = %u", j, +// slew_imp_val[SLEW_TYPE_DATA][IMP][j]); + switch (slew_imp_val[SLEW_TYPE_DATA][IMP][j]) { case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM24_FFE0: @@ -1326,8 +1359,8 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target_mba) // FAPI_SET_HWP_ERROR(rc, RC_MSS_IMP_INPUT_ERROR); // return rc; } - FAPI_DBG("switched imp to value of %u", - slew_imp_val[SLEW_TYPE_DATA][IMP][j]); +// FAPI_DBG("switched imp to value of %u", +// slew_imp_val[SLEW_TYPE_DATA][IMP][j]); } // Get desired ADR control slew rate & impedance from attribute rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_CNTL, &i_target_mba, @@ -1397,22 +1430,28 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target_mba) if (port_val == 0) { - FAPI_INF("WARNING: Port %u is invalid from " + FAPI_INF("WARNING: port %u is invalid from " "ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR, 0x%02x " "skipping configuration of slew rate on this port", l_port, ports_valid); continue; } + FAPI_INF("Setting slew registers for port %i", l_port); for (uint8_t slew_type=0; slew_type < MAX_NUM_SLEW_TYPES; slew_type++) { - FAPI_DBG("slew_imp_val imp=%u, slew=%u", - slew_imp_val[slew_type][IMP][l_port], - slew_imp_val[slew_type][SLEW][l_port]); - - config_slew_rate(i_target_mba, l_port, slew_type, + array_rcs[l_port]=config_slew_rate(i_target_mba, l_port, slew_type, slew_imp_val[slew_type][IMP][l_port], slew_imp_val[slew_type][SLEW][l_port]); } } + + for (uint8_t rn=0; rn < MAX_NUM_PORTS; rn++) + { + if (array_rcs[rn] != fapi::FAPI_RC_SUCCESS) + { + FAPI_ERR("Returning ERROR RC for port %u",rn); + return array_rcs[rn]; + } + } return rc; } diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.C b/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.C index 7c2bd969d..48a6bbaef 100644 --- a/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.C +++ b/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_fab_iovalid.C,v 1.9 2013/01/21 01:42:45 jmcgill Exp $ +// $Id: proc_fab_iovalid.C,v 1.10 2013/03/05 02:53:19 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_fab_iovalid.C,v $ //------------------------------------------------------------------------------ // *| @@ -51,26 +51,24 @@ extern "C" //------------------------------------------------------------------------------ -// function: utility subroutine which writes chiplet GP0 register to -// set/clear desired iovalid bits -// parameters: i_target => chip target -// i_active_link_mask => bit mask defining active links to act on -// i_set_not_clear => define desired operation -// (true=set, false=clear) -// i_gp0_and_mask_addr => SCOM address for chiplet GP0 AND -// mask register -// i_gp0_or_mask_addr => SCOM address for chiplet GP0 OR -// mask register +// function: utility subroutine which writes AND/OR mask register to +// set/clear desired bits +// parameters: i_target => target +// i_active_mask => bit mask defining active bits to act on +// i_set_not_clear => define desired operation +// (true=set, false=clear) +// i_and_mask_addr => SCOM address for AND mask register +// i_or_mask_addr => SCOM address for OR mask register // returns: FAPI_RC_SUCCESS if operation was successful, else error //------------------------------------------------------------------------------ -fapi::ReturnCode proc_fab_iovalid_write_gp0_mask( +fapi::ReturnCode proc_fab_iovalid_write_active_mask( const fapi::Target& i_target, - ecmdDataBufferBase& i_active_link_mask, + ecmdDataBufferBase& i_active_mask, bool i_set_not_clear, - const uint32_t& i_gp0_and_mask_addr, - const uint32_t& i_gp0_or_mask_addr) + const uint32_t& i_and_mask_addr, + const uint32_t& i_or_mask_addr) { - // data buffer to hold final iovalid bit mask + // data buffer to hold final bit mask ecmdDataBufferBase mask(64); // return codes @@ -78,16 +76,16 @@ fapi::ReturnCode proc_fab_iovalid_write_gp0_mask( fapi::ReturnCode rc; // mark function entry - FAPI_DBG("proc_fab_iovalid_write_gp0_mask: Start"); + FAPI_DBG("proc_fab_iovalid_write_active_mask: Start"); do { // copy input mask - rc_ecmd = i_active_link_mask.copy(mask); + rc_ecmd = i_active_mask.copy(mask); // form final mask based on desired operation (set/clear) if (!i_set_not_clear) { - FAPI_DBG("proc_fab_iovalid_write_gp0_mask: Inverting active link mask"); + FAPI_DBG("proc_fab_iovalid_write_active_mask: Inverting active mask"); rc_ecmd |= mask.invert(); } @@ -95,27 +93,27 @@ fapi::ReturnCode proc_fab_iovalid_write_gp0_mask( rc.setEcmdError(rc_ecmd); if (!rc.ok()) { - FAPI_ERR("proc_fab_iovalid_write_gp0_mask: Error 0x%x setting up iovalid mask data buffer", + FAPI_ERR("proc_fab_iovalid_write_active_mask: Error 0x%x setting up active mask data buffer", rc_ecmd); break; } - // write GP0 register (use OR mask address for set operation, + // write register (use OR mask address for set operation, // AND mask address for clear operation) rc = fapiPutScom(i_target, - i_set_not_clear?i_gp0_or_mask_addr:i_gp0_and_mask_addr, + i_set_not_clear?i_or_mask_addr:i_and_mask_addr, mask); if (!rc.ok()) { - FAPI_ERR("proc_fab_iovalid_write_gp0_mask: fapiPutScom error (GP0 Register 0x%08X)", - i_set_not_clear?i_gp0_or_mask_addr:i_gp0_and_mask_addr); + FAPI_ERR("proc_fab_iovalid_write_active_mask: fapiPutScom error (0x%08X)", + i_set_not_clear?i_or_mask_addr:i_and_mask_addr); break; } } while (0); // mark function exit - FAPI_DBG("proc_fab_iovalid_write_gp0_mask: End"); + FAPI_DBG("proc_fab_iovalid_write_active_mask: End"); return rc; } @@ -133,85 +131,57 @@ fapi::ReturnCode proc_fab_iovalid_manage_x_links( proc_fab_iovalid_proc_chip& i_proc_chip, bool i_set_not_clear) { - // data buffer to hold iovalid bit mask - ecmdDataBufferBase active_link_mask(64); + ecmdDataBufferBase gp0_iovalid_active(64); // return codes uint32_t rc_ecmd = 0; fapi::ReturnCode rc; - // partial good attribute - uint8_t xbus_enable_attr; - // mark function entry FAPI_DBG("proc_fab_iovalid_manage_x_links: Start"); do { - // set mask bit for each link to act on - if (i_proc_chip.x0 || - i_proc_chip.x1 || - i_proc_chip.x2 || - i_proc_chip.x3) + if (i_proc_chip.x0) { - // query XBUS partial good attribute - rc = FAPI_ATTR_GET(ATTR_PROC_X_ENABLE, - &(i_proc_chip.this_chip), - xbus_enable_attr); - if (!rc.ok()) - { - FAPI_ERR("proc_fab_iovalid_manage_x_links: Error querying ATTR_PROC_X_ENABLE"); - break; - } - - if (xbus_enable_attr != fapi::ENUM_ATTR_PROC_X_ENABLE_ENABLE) - { - FAPI_ERR("proc_fab_iovalid_manage_x_links: Partial good attribute error"); - FAPI_SET_HWP_ERROR(rc, RC_PROC_FAB_IOVALID_X_PARTIAL_GOOD_ERR); - break; - } - - if (i_proc_chip.x0) - { - FAPI_DBG("proc_fab_iovalid_manage_x_links: Adding link X0 to active link mask"); - rc_ecmd |= active_link_mask.setBit(X_GP0_X0_IOVALID_BIT); - } - if (i_proc_chip.x1) - { - FAPI_DBG("proc_fab_iovalid_manage_x_links: Adding link X1 to active link mask"); - rc_ecmd |= active_link_mask.setBit(X_GP0_X1_IOVALID_BIT); - } - if (i_proc_chip.x2) - { - FAPI_DBG("proc_fab_iovalid_manage_x_links: Adding link X2 to active link mask"); - rc_ecmd |= active_link_mask.setBit(X_GP0_X2_IOVALID_BIT); - } - if (i_proc_chip.x3) - { - FAPI_DBG("proc_fab_iovalid_manage_x_links: Adding link X3 to active link mask"); - rc_ecmd |= active_link_mask.setBit(X_GP0_X3_IOVALID_BIT); - } + FAPI_DBG("proc_fab_iovalid_manage_x_links: Adding link X0 to active link mask"); + rc_ecmd |= gp0_iovalid_active.setBit(X_GP0_X0_IOVALID_BIT); + } + if (i_proc_chip.x1) + { + FAPI_DBG("proc_fab_iovalid_manage_x_links: Adding link X1 to active link mask"); + rc_ecmd |= gp0_iovalid_active.setBit(X_GP0_X1_IOVALID_BIT); + } + if (i_proc_chip.x2) + { + FAPI_DBG("proc_fab_iovalid_manage_x_links: Adding link X2 to active link mask"); + rc_ecmd |= gp0_iovalid_active.setBit(X_GP0_X2_IOVALID_BIT); + } + if (i_proc_chip.x3) + { + FAPI_DBG("proc_fab_iovalid_manage_x_links: Adding link X3 to active link mask"); + rc_ecmd |= gp0_iovalid_active.setBit(X_GP0_X3_IOVALID_BIT); + } - // check aggregate return code from buffer manipulation operations - rc.setEcmdError(rc_ecmd); - if (!rc.ok()) - { - FAPI_ERR("proc_fab_iovalid_manage_x_links: Error 0x%x setting up active link mask data buffer", - rc_ecmd); - break; - } + // check aggregate return code from buffer manipulation operations + rc.setEcmdError(rc_ecmd); + if (!rc.ok()) + { + FAPI_ERR("proc_fab_iovalid_manage_x_links: Error 0x%x setting up active link mask data buffer", + rc_ecmd); + break; + } - // write appropriate GP0 mask register to perform desired operation - rc = proc_fab_iovalid_write_gp0_mask(i_proc_chip.this_chip, - active_link_mask, - i_set_not_clear, - X_GP0_AND_0x04000004, - X_GP0_OR_0x04000005); - if (!rc.ok()) - { - FAPI_ERR("proc_fab_iovalid_manage_x_links: Error from proc_fab_iovalid_write_gp0_mask"); - break; - } + // write appropriate GP0 mask register to perform desired operation + rc = proc_fab_iovalid_write_active_mask(i_proc_chip.this_chip, + gp0_iovalid_active, + i_set_not_clear, + X_GP0_AND_0x04000004, + X_GP0_OR_0x04000005); + if (!rc.ok()) + { + FAPI_ERR("proc_fab_iovalid_manage_x_links: Error from proc_fab_iovalid_write_active_mask"); + break; } } while(0); @@ -234,77 +204,106 @@ fapi::ReturnCode proc_fab_iovalid_manage_a_links( proc_fab_iovalid_proc_chip& i_proc_chip, bool i_set_not_clear) { - // data buffer to hold iovalid bit mask - ecmdDataBufferBase active_link_mask(64); + ecmdDataBufferBase gp0_iovalid_active(64); + ecmdDataBufferBase secure_iovalid_data(64); + ecmdDataBufferBase secure_iovalid_mask(64); // return codes uint32_t rc_ecmd = 0; fapi::ReturnCode rc; - // partial good attribute - uint8_t abus_enable_attr; + // secure iovalid attribute + uint8_t secure_iovalid_present_attr = 1; // mark function entry FAPI_DBG("proc_fab_iovalid_manage_a_links: Start"); do { - // set mask bit for each link to act on - if (i_proc_chip.a0 || - i_proc_chip.a1 || - i_proc_chip.a2) + // query secure iovalid attribute + rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_SECURE_IOVALID_PRESENT, + &(i_proc_chip.this_chip), + secure_iovalid_present_attr); + if (!rc.ok()) { - // query ABUS partial good attribute - rc = FAPI_ATTR_GET(ATTR_PROC_A_ENABLE, - &(i_proc_chip.this_chip), - abus_enable_attr); - if (!rc.ok()) - { - FAPI_ERR("proc_fab_iovalid_manage_a_links: Error querying ATTR_PROC_A_ENABLE"); - break; - } - - if (abus_enable_attr != fapi::ENUM_ATTR_PROC_A_ENABLE_ENABLE) - { - FAPI_ERR("proc_fab_iovalid_manage_a_links: Partial good attribute error"); - FAPI_SET_HWP_ERROR(rc, RC_PROC_FAB_IOVALID_A_PARTIAL_GOOD_ERR); - break; - } + FAPI_ERR("proc_fab_iovalid_manage_a_links: Error querying ATTR_CHIP_EC_FEATURE_SECURE_IOVALID_PRESENT"); + break; + } - if (i_proc_chip.a0) + if (i_proc_chip.a0) + { + FAPI_DBG("proc_fab_iovalid_manage_a_links: Adding link A0 to active link mask"); + rc_ecmd |= gp0_iovalid_active.setBit(A_GP0_A0_IOVALID_BIT); + if (secure_iovalid_present_attr) { - FAPI_DBG("proc_fab_iovalid_manage_a_links: Adding link A0 to active link mask"); - rc_ecmd |= active_link_mask.setBit(A_GP0_A0_IOVALID_BIT); + FAPI_DBG("proc_fab_iovalid_manage_a_links: Adding link A0 to active link mask (secure)"); + if (i_set_not_clear) + { + rc_ecmd |= secure_iovalid_data.setBit(ADU_IOS_LINK_EN_A0_IOVALID_BIT); + } + rc_ecmd |= secure_iovalid_mask.setBit(ADU_IOS_LINK_EN_A0_IOVALID_BIT); } - if (i_proc_chip.a1) + } + if (i_proc_chip.a1) + { + FAPI_DBG("proc_fab_iovalid_manage_a_links: Adding link A1 to active link mask"); + rc_ecmd |= gp0_iovalid_active.setBit(A_GP0_A1_IOVALID_BIT); + if (secure_iovalid_present_attr) { - FAPI_DBG("proc_fab_iovalid_manage_a_links: Adding link A1 to active link mask"); - rc_ecmd |= active_link_mask.setBit(A_GP0_A1_IOVALID_BIT); + FAPI_DBG("proc_fab_iovalid_manage_a_links: Adding link A1 to active link mask (secure)"); + if (i_set_not_clear) + { + rc_ecmd |= secure_iovalid_data.setBit(ADU_IOS_LINK_EN_A1_IOVALID_BIT); + } + rc_ecmd |= secure_iovalid_mask.setBit(ADU_IOS_LINK_EN_A1_IOVALID_BIT); } - if (i_proc_chip.a2) + } + if (i_proc_chip.a2) + { + FAPI_DBG("proc_fab_iovalid_manage_a_links: Adding link A2 to active link mask"); + rc_ecmd |= gp0_iovalid_active.setBit(A_GP0_A2_IOVALID_BIT); + if (secure_iovalid_present_attr) { - FAPI_DBG("proc_fab_iovalid_manage_a_links: Adding link A2 to active link mask"); - rc_ecmd |= active_link_mask.setBit(A_GP0_A2_IOVALID_BIT); + FAPI_DBG("proc_fab_iovalid_manage_a_links: Adding link A2 to active link mask (secure)"); + if (i_set_not_clear) + { + rc_ecmd |= secure_iovalid_data.setBit(ADU_IOS_LINK_EN_A2_IOVALID_BIT); + } + rc_ecmd |= secure_iovalid_mask.setBit(ADU_IOS_LINK_EN_A2_IOVALID_BIT); } + } - // check aggregate return code from buffer manipulation operations - rc.setEcmdError(rc_ecmd); - if (!rc.ok()) - { - FAPI_ERR("proc_fab_iovalid_manage_a_links: Error 0x%x setting up active link mask data buffer", - rc_ecmd); - break; - } + // check aggregate return code from buffer manipulation operations + rc.setEcmdError(rc_ecmd); + if (!rc.ok()) + { + FAPI_ERR("proc_fab_iovalid_manage_a_links: Error 0x%x setting up active link mask data buffersa", + rc_ecmd); + break; + } - // write appropriate GP0 mask register to perform desired operation - rc = proc_fab_iovalid_write_gp0_mask(i_proc_chip.this_chip, - active_link_mask, - i_set_not_clear, - A_GP0_AND_0x08000004, - A_GP0_OR_0x08000005); + // write appropriate GP0 mask register to perform desired operation + rc = proc_fab_iovalid_write_active_mask(i_proc_chip.this_chip, + gp0_iovalid_active, + i_set_not_clear, + A_GP0_AND_0x08000004, + A_GP0_OR_0x08000005); + if (!rc.ok()) + { + FAPI_ERR("proc_fab_iovalid_manage_a_links: Error from proc_fab_iovalid_write_active_mask"); + break; + } + + // adjust secure iovalids if present + if (secure_iovalid_present_attr) + { + rc = fapiPutScomUnderMask(i_proc_chip.this_chip, + ADU_IOS_LINK_EN_0x02020019, + secure_iovalid_data, + secure_iovalid_mask); if (!rc.ok()) { - FAPI_ERR("proc_fab_iovalid_manage_a_links: Error from proc_fab_iovalid_write_gp0_mask"); + FAPI_ERR("proc_fab_iovalid_manage_a_links: fapiPutScomUnderMask error (ADU_IOS_LINK_EN_0x02020019)"); break; } } @@ -317,6 +316,125 @@ fapi::ReturnCode proc_fab_iovalid_manage_a_links( //------------------------------------------------------------------------------ +// function: utility subroutine to manage PB RAS FIR setup +// parameters: i_proc_chip => structure providing: +// o target for this chip +// o A/X busses to act on +// i_set_not_clear => define desired iovalid operation (true=set, +// false=clear) +// returns: FAPI_RC_SUCCESS if operation was successful, else error +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_fab_iovalid_manage_ras_fir( + proc_fab_iovalid_proc_chip& i_proc_chip, + bool i_set_not_clear) +{ + ecmdDataBufferBase mask_active(64); + ecmdDataBufferBase zero_data(64); + ecmdDataBufferBase action_mask(64); + + // return codes + uint32_t rc_ecmd = 0; + fapi::ReturnCode rc; + + + // mark function entry + FAPI_DBG("proc_fab_iovalid_manage_ras_fir: Start"); + + do + { + if (i_proc_chip.x0) + { + FAPI_DBG("proc_fab_iovalid_manage_ras_fir: Configuring RAS FIR for link X0"); + rc_ecmd |= mask_active.setBit(PB_RAS_FIR_X0_BIT); + rc_ecmd |= action_mask.setBit(PB_RAS_FIR_X0_BIT); + } + if (i_proc_chip.x1) + { + FAPI_DBG("proc_fab_iovalid_manage_ras_fir: Configuring RAS FIR for link X1"); + rc_ecmd |= mask_active.setBit(PB_RAS_FIR_X1_BIT); + rc_ecmd |= action_mask.setBit(PB_RAS_FIR_X1_BIT); + } + if (i_proc_chip.x2) + { + FAPI_DBG("proc_fab_iovalid_manage_ras_fir: Configuring RAS FIR for link X2"); + rc_ecmd |= mask_active.setBit(PB_RAS_FIR_X2_BIT); + rc_ecmd |= action_mask.setBit(PB_RAS_FIR_X2_BIT); + } + if (i_proc_chip.x3) + { + FAPI_DBG("proc_fab_iovalid_manage_ras_fir: Configuring RAS FIR for link X3"); + rc_ecmd |= mask_active.setBit(PB_RAS_FIR_X3_BIT); + rc_ecmd |= action_mask.setBit(PB_RAS_FIR_X3_BIT); + } + if (i_proc_chip.a0) + { + FAPI_DBG("proc_fab_iovalid_manage_ras_fir: Configuring RAS FIR for link A0"); + rc_ecmd |= mask_active.setBit(PB_RAS_FIR_A0_BIT); + rc_ecmd |= action_mask.setBit(PB_RAS_FIR_A0_BIT); + } + if (i_proc_chip.a1) + { + FAPI_DBG("proc_fab_iovalid_manage_ras_fir: Configuring RAS FIR for link A1"); + rc_ecmd |= mask_active.setBit(PB_RAS_FIR_A1_BIT); + rc_ecmd |= action_mask.setBit(PB_RAS_FIR_A1_BIT); + } + if (i_proc_chip.a2) + { + FAPI_DBG("proc_fab_iovalid_manage_ras_fir: Configuring RAS FIR for link A2"); + rc_ecmd |= mask_active.setBit(PB_RAS_FIR_A2_BIT); + rc_ecmd |= action_mask.setBit(PB_RAS_FIR_A2_BIT); + } + + // check aggregate return code from buffer manipulation operations + rc.setEcmdError(rc_ecmd); + if (!rc.ok()) + { + FAPI_ERR("proc_fab_iovalid_manage_ras_fir: Error 0x%x setting up active link mask data buffers", + rc_ecmd); + break; + } + + // write appropriate RAS FIR mask register to perform desired operation + rc = proc_fab_iovalid_write_active_mask(i_proc_chip.this_chip, + mask_active, + !i_set_not_clear, + PB_RAS_FIR_MASK_AND_0x02010C72, + PB_RAS_FIR_MASK_OR_0x02010C73); + if (!rc.ok()) + { + FAPI_ERR("proc_fab_iovalid_manage_ras_fir: Error from proc_fab_iovalid_write_active_mask"); + break; + } + + // set RAS FIR action registers (action0=0b0, action1=0b0 for checkstop) + rc = fapiPutScomUnderMask(i_proc_chip.this_chip, + PB_RAS_FIR_ACTION0_0x02010C74, + zero_data, + action_mask); + if (!rc.ok()) + { + FAPI_ERR("proc_fab_iovalid_manage_ras_fir: fapiPutScomUnderMask error (PB_RAS_FIR_ACTION0_0x02010C74)"); + break; + } + + rc = fapiPutScomUnderMask(i_proc_chip.this_chip, + PB_RAS_FIR_ACTION1_0x02010C75, + zero_data, + action_mask); + if (!rc.ok()) + { + FAPI_ERR("proc_fab_iovalid_manage_ras_fir: fapiPutScomUnderMask error (PB_RAS_FIR_ACTION1_0x02010C75)"); + break; + } + } while(0); + + // mark function exit + FAPI_DBG("proc_fab_iovalid_manage_ras_fir: End"); + return rc; +} + + +//------------------------------------------------------------------------------ // HWP entry point //------------------------------------------------------------------------------ fapi::ReturnCode proc_fab_iovalid( @@ -328,6 +446,12 @@ fapi::ReturnCode proc_fab_iovalid( // iterator for HWP input vector std::vector<proc_fab_iovalid_proc_chip>::iterator iter; + // partial good attributes + uint8_t abus_enable_attr; + uint8_t xbus_enable_attr; + bool x_changed = false; + bool a_changed = false; + // mark HWP entry FAPI_IMP("proc_fab_iovalid: Entering ..."); @@ -338,18 +462,79 @@ fapi::ReturnCode proc_fab_iovalid( iter != i_proc_chips.end(); iter++) { - rc = proc_fab_iovalid_manage_x_links(*iter, i_set_not_clear); - if (!rc.ok()) + // process X links + if (iter->x0 || + iter->x1 || + iter->x2 || + iter->x3) { - FAPI_ERR("proc_fab_iovalid: Error from proc_fab_iovalid_manage_x_links"); - break; + // query XBUS partial good attribute + rc = FAPI_ATTR_GET(ATTR_PROC_X_ENABLE, + &(iter->this_chip), + xbus_enable_attr); + if (!rc.ok()) + { + FAPI_ERR("proc_fab_iovalid_manage_x_links: Error querying ATTR_PROC_X_ENABLE"); + break; + } + + if (xbus_enable_attr != fapi::ENUM_ATTR_PROC_X_ENABLE_ENABLE) + { + FAPI_ERR("proc_fab_iovalid_manage_x_links: Partial good attribute error"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_FAB_IOVALID_X_PARTIAL_GOOD_ERR); + break; + } + + rc = proc_fab_iovalid_manage_x_links(*iter, i_set_not_clear); + if (!rc.ok()) + { + FAPI_ERR("proc_fab_iovalid: Error from proc_fab_iovalid_manage_x_links"); + break; + } + + x_changed = true; } - rc = proc_fab_iovalid_manage_a_links(*iter, i_set_not_clear); - if (!rc.ok()) + // process A links + if (iter->a0 || + iter->a1 || + iter->a2) { - FAPI_ERR("proc_fab_iovalid: Error from proc_fab_iovalid_manage_a_links"); - break; + // query ABUS partial good attribute + rc = FAPI_ATTR_GET(ATTR_PROC_A_ENABLE, + &(iter->this_chip), + abus_enable_attr); + if (!rc.ok()) + { + FAPI_ERR("proc_fab_iovalid: Error querying ATTR_PROC_A_ENABLE"); + break; + } + + if (abus_enable_attr != fapi::ENUM_ATTR_PROC_A_ENABLE_ENABLE) + { + FAPI_ERR("proc_fab_iovalid: Partial good attribute error"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_FAB_IOVALID_A_PARTIAL_GOOD_ERR); + break; + } + + rc = proc_fab_iovalid_manage_a_links(*iter, i_set_not_clear); + if (!rc.ok()) + { + FAPI_ERR("proc_fab_iovalid: Error from proc_fab_iovalid_manage_a_links"); + break; + } + + a_changed = true; + } + + if (x_changed || a_changed) + { + rc = proc_fab_iovalid_manage_ras_fir(*iter, i_set_not_clear); + if (!rc.ok()) + { + FAPI_ERR("proc_fab_iovalid: Error from proc_fab_iovalid_manage_ras_fir"); + break; + } } } } while(0); diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.H b/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.H index bcc195a31..fb489930e 100644 --- a/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.H +++ b/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.H @@ -1,27 +1,26 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.H $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ -// $Id: proc_fab_iovalid.H,v 1.8 2012/07/23 14:15:54 jmcgill Exp $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_fab_iovalid.H,v 1.9 2013/03/05 02:53:21 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_fab_iovalid.H,v $ //------------------------------------------------------------------------------ // *| @@ -100,6 +99,20 @@ const uint8_t A_GP0_A0_IOVALID_BIT = 48; const uint8_t A_GP0_A1_IOVALID_BIT = 49; const uint8_t A_GP0_A2_IOVALID_BIT = 50; +// ADU Secure Iovalid register bit/field definitions +const uint8_t ADU_IOS_LINK_EN_A0_IOVALID_BIT = 0; +const uint8_t ADU_IOS_LINK_EN_A1_IOVALID_BIT = 1; +const uint8_t ADU_IOS_LINK_EN_A2_IOVALID_BIT = 2; + +// PB RAS FIR register bit/field definitions +const uint8_t PB_RAS_FIR_X0_BIT = 0; +const uint8_t PB_RAS_FIR_X1_BIT = 1; +const uint8_t PB_RAS_FIR_X2_BIT = 2; +const uint8_t PB_RAS_FIR_X3_BIT = 3; +const uint8_t PB_RAS_FIR_A0_BIT = 4; +const uint8_t PB_RAS_FIR_A1_BIT = 5; +const uint8_t PB_RAS_FIR_A2_BIT = 6; + extern "C" { diff --git a/src/usr/hwpf/hwp/include/p8_istep_num.H b/src/usr/hwpf/hwp/include/p8_istep_num.H index bc91d666c..b18cf9c4e 100644 --- a/src/usr/hwpf/hwp/include/p8_istep_num.H +++ b/src/usr/hwpf/hwp/include/p8_istep_num.H @@ -23,7 +23,7 @@ #ifndef __P8_ISTEP_NUM_H #define __P8_ISTEP_NUM_H -// $Id: p8_istep_num.H,v 1.22 2013/02/06 04:15:38 jmcgill Exp $ +// $Id: p8_istep_num.H,v 1.24 2013/02/25 14:59:03 jeshua Exp $ /// Istep number encoding for all SEEPROM and PNOR procedures. Used to update /// the SBEVITAL register to record procedure progress and to create unique @@ -80,9 +80,22 @@ CONST_UINT64_T(proc_sbe_instruct_start_istep_num, ULL(0x0502)); CONST_UINT64_T(proc_sbe_trigger_winkle_istep_num, ULL(0x0F01)); +// The following record progress through the SLW process and only are +// logged in the virtual SBEVITAL in the OCC SRAM; these are not recorded +// in the real SBEVITAL as they are not executed during the master core IPL. +CONST_UINT64_T(slw_fast_sleep_enter_istep_num, ULL(0x0F80)); +CONST_UINT64_T(slw_fast_sleep_exit_istep_num, ULL(0x0F81)); +CONST_UINT64_T(slw_fast_winkle_enter_istep_num, ULL(0x0F82)); +CONST_UINT64_T(slw_fast_winkle_exit_istep_num, ULL(0x0F83)); +CONST_UINT64_T(slw_deep_sleep_enter_istep_num, ULL(0x0F84)); +CONST_UINT64_T(slw_deep_sleep_exit_istep_num, ULL(0x0F85)); +CONST_UINT64_T(slw_deep_winkle_enter_istep_num, ULL(0x0F86)); +CONST_UINT64_T(slw_deep_winkle_exit_istep_num, ULL(0x0F87)); + #define PROC_SBE_TRIGGER_WINKLE_ISTEP_NUM proc_sbe_trigger_winkle_istep_num #define PROC_SBE_CHECK_MASTER_ISTEP_NUM proc_sbe_check_master_istep_num #define PROC_SBE_ENABLE_PNOR_ISTEP_NUM proc_sbe_enable_pnor_istep_num #define PROC_SBE_EX_HOST_RUNTIME_SCOM_ISTEP_NUM proc_sbe_ex_host_runtime_scom_istep_num +#define PROC_SBE_TP_LD_IMAGE_ISTEP_NUM proc_sbe_tp_ld_image_istep_num #endif // __P8_ISTEP_NUM_H diff --git a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile index 3cb9706d8..6b7744182 100755 --- a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile +++ b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile @@ -1,9 +1,10 @@ -#-- $Id: cen_ddrphy.initfile,v 1.20 2013/01/16 21:07:47 mwuu Exp $ +#-- $Id: cen_ddrphy.initfile,v 1.21 2013/02/08 00:32:24 mwuu Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- -#-- 1.20|mwuu |01/16/12|Updated TWTR & TRTP define for FW_WR_RD field in +#-- 1.21|mwuu |02/07/13|Updated PC_CSID register to default CS to high +#-- 1.20|mwuu |01/16/13|Updated TWTR & TRTP define for FW_WR_RD field in # | | |WC_CONFIG0 and FW_RD_WR in WC_CONFIG2 in 0W spec. # | | |Thin Oxide hibernation disabled in ATEST & BIT_DIR1 # | | |registers. @@ -812,7 +813,7 @@ scom 0x80013C7B0301143f { # PFET_TERM_P1_[0:4] broadcast # --------------------------------------------------------------------------------------- # Output(DQ/DQS) driver impedance settings # -# ATTR_EFF_CEN_DRV_IMP_DQ_DQS 24, 30, 34, 40 +# ATTR_EFF_CEN_DRV_IMP_DQ_DQS 24, 30, 34, 40 + FFE differences... # # [01:23] [N:P] [0:1][0:4] # DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_0 0x078 0x800000780301143f @@ -2586,10 +2587,6 @@ scom 0x8001c0150301143f { # --------------------------------------------------------------------------------------- # SEQ Read/Write Data {0-1} Register default=0x5555 !! need to set to custom mode # for DDR3 -# !! Anuwat says for WLC pattern get from SN, doesn't look like its only for WLC -# -# For DDRPHY_DP18_RX_PEAK_AMP:Read_Centering_Mode -# # Attributes # Read/Write via programming interface. Two registers. These two registers are used to # create eight beats of data by repeating every fourth bit of data within a beat. @@ -2840,6 +2837,12 @@ scom 0x8001C40D0301143F { # # DPHY01_DDRPHY_PC_CSID_CFG_P0 0x033 0x8000c0330301143f # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG51_L2 +scom 0x800(0,1)c0330301143f { + bits , scom_data ; +# 0:47 , 0x000000000000 ; # reserved + 48:55 , 0xFF ; # CS[0:7] level + 56:63 , 0x00 ; # reserved +} # --------------------------------------------------------------------------------------- # DP18 DQSCLK offset default=0x0200 needed for SIM @@ -3388,10 +3391,9 @@ scom 0x8000c0090301143f { # asking Ken... # --------------------------------------------------------------------------------------- -# PC Rank Group Register no need to set since using RDIMMs +# PC Rank Group Register set in the mss_draminit procedure # -# This register provides control of mirrored address bits. Mainly? used for -# UDIMMs? +# This register provides control of mirrored address bits. # # DPHY01_DDRPHY_PC_RANK_GROUP_P0 0x11 0x8000c0110301143f # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG17_L2 @@ -3406,7 +3408,7 @@ scom 0x8000c0090301143f { # 53 , 0b0 , any ; # ADDR_MIRROR_RP2_SEC # 54 , 0b0 , any ; # ADDR_MIRROR_RP3_PRI # 55 , 0b0 , any ; # ADDR_MIRROR_RP3_SEC -# 56:57 , 0b0 , any ; # RANK_GROUPING +# 56:57 , 0b0 , any ; # RANK_GROUPING # reserved # 58 , 0b0 , any ; # ADDR_MIRROR_A3_A4 # 59 , 0b0 , any ; # ADDR_MIRROR_A5_A6 # 60 , 0b0 , any ; # ADDR_MIRROR_A7_A8 @@ -3762,7 +3764,7 @@ scom 0x800(0,1)C8070301143F { # _P[0:1] # # --------------------------------------------------------------------------------------- -# SEQ Configuration 0 Register default=0 !! need to review settings +# SEQ Configuration 0 Register default=0 # # DPHY01.DDRPHY_SEQ_CONFIG0_P0 # DPHY01.DDRPHY_SEQ_CONFIG0_P1 @@ -3773,7 +3775,7 @@ scom 0x800(0,1)C4020301143F { # _P[0:1] bits , scom_data ; # 0:47 , 0x000000000000 ; # reserved 48 , 0b0 ; # MPR_PATTERN_BIT - 49 , 0b0 ; # TWO_CYCLE_ADDR_EN (must be set to 0), need 1 in sim ? 2N + 49 , 0b0 ; # TWO_CYCLE_ADDR_EN (must be set to 0?) 50:53 , 0b0000 ; # MR_MASK_EN (mode register[0:3] mask during calibration) 54 , 0b0 ; # DELAYED_PARITY (only for DDR4, DDR3 don't care) 55 , 0b0 ; # LRDIMM_CONTEXT @@ -4004,23 +4006,26 @@ scom 0x800(0,1)CC000301143F { # _P[0:1] # 0:47 , 0x000000000000 , any ; # reserved # !! need to review # = 12 + max(tWLDQSEN-tMOD,tWLO+tWLOE) + (longest DQS wire delay in CKs) + (longest DQ wire delay in CKs) - 48:55 , 0x10 , any ; # TWLO_TWLOE = 16 (same as DD0) - # @ 1600, = 12 + max(13,3) + ldqs + ldq = 25 + ldqs + ldq - #48:55 , 0x1B , any ; # TWLO_TWLOE = 27 + 48:55 , 0x10 , (def_is_sim) ; # TWLO_TWLOE = 16 (same as DD0) + # @ 1600, = 12 + max(13,8) + ldqs + ldq = 25 + ldqs + ldq + # @ 1866, = 12 + max(13,9) + ldqs + ldq = 25 + ldqs + ldq + 48:55 , 0x1B , any ; # TWLO_TWLOE = 27 #48:55 , (25+ldqs+ldq) , (CEN.ATTR_MSS_FREQ > 1460) ; # TWLO_TWLOE (> 1333) - 56 , 0b1 , any ; # WL_ONE_DQS_PULSE = enable - # FW_WR_RD = max(tWTR+11,AL+tRTP+3), ATTR_EFF_DRAM_AL(0,1,2) - 57:62 , 0b000000 , (def_is_sim) ; - 57:62 , 0b010001 , any ; # same as dd0 + 56 , 0b1 , any ; # WL_ONE_DQS_PULSE = enable (one pulse) +# 56 , 0b0 , any ; # WL_ONE_DQS_PULSE = disable (many pulses) + + # FW_WR_RD [same formula as RD_WR? max(tWTR+11,AL+tRTP+3), ATTR_EFF_DRAM_AL(0,1,2)] + 57:62 , 0b000000 , (def_is_sim) ; # is this max? + 57:62 , 0b010001 , any ; # same as dd0, 17 clocks # AL={1,2}; max (TWTR + 11, TRTP + AL + 3) - 57:62 , (def_TWTR_PLUS_OFF) , (def_AL_ena && (def_TWTR_PLUS_OFF >= def_TRTP_PLUS_AL) ) ; # TWTR + 11 - 57:62 , (def_TRTP_PLUS_AL) , (def_AL_ena && (def_TWTR_PLUS_OFF < def_TRTP_PLUS_AL) ) ; # TRTP + AL + 3 +# 57:62 , (def_TWTR_PLUS_OFF) , (def_AL_ena && (def_TWTR_PLUS_OFF >= def_TRTP_PLUS_AL) ) ; # TWTR + 11 +# 57:62 , (def_TRTP_PLUS_AL) , (def_AL_ena && (def_TWTR_PLUS_OFF < def_TRTP_PLUS_AL) ) ; # TRTP + AL + 3 # AL=0, max (TWTR + 11, TRTP + 3) - 57:62 , (def_TWTR_PLUS_OFF) , (def_AL_dis && (def_TWTR_PLUS_OFF >= def_TRTP_PLUS_NOAL) ) ; # TWTR + 11 - 57:62 , (def_TRTP_PLUS_NOAL), (def_AL_dis && (def_TWTR_PLUS_OFF < def_TRTP_PLUS_NOAL) ) ; # TRTP + 3 +# 57:62 , (def_TWTR_PLUS_OFF) , (def_AL_dis && (def_TWTR_PLUS_OFF >= def_TRTP_PLUS_NOAL) ) ; # TWTR + 11 +# 57:62 , (def_TRTP_PLUS_NOAL), (def_AL_dis && (def_TWTR_PLUS_OFF < def_TRTP_PLUS_NOAL) ) ; # TRTP + 3 63 , 0b0 , any ; # CUSTOM_INIT_WRITE } @@ -4254,6 +4259,7 @@ scom 0x800108000301143f { # # Procedure function to set this register, pulling data from the SPD. # 1 = disable dq bit +# !! Note only affects calibrations. # # DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0 0x07C 0x8000007c0301143f # PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_L2 diff --git a/src/usr/hwpf/hwp/initfiles/mba_def.initfile b/src/usr/hwpf/hwp/initfiles/mba_def.initfile index 2001dc78b..eed536f27 100644 --- a/src/usr/hwpf/hwp/initfiles/mba_def.initfile +++ b/src/usr/hwpf/hwp/initfiles/mba_def.initfile @@ -1,9 +1,12 @@ -#-- $Id: mba_def.initfile,v 1.30 2013/03/05 17:01:22 yctschan Exp $ +#-- $Id: mba_def.initfile,v 1.33 2013/03/18 21:22:56 yctschan Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.33|tschang | 3/12/13|RWDM_dly margin increased by 1 to match other RW dlys - HW243893 +#-- 1.32|tschang | 3/12/13|Def_margin_rdtag set it to 4 - increased by 2 +#-- 1.31|tschang | 3/11/13|Defined new def_margin_rdtag and set it to 2 to increase it from figtree values #-- 1.30|tschang | 3/05/13|Set def_margin2 to 0 to decrease timing parmeters for performance and added def_margin1 for RW parms #-- 1.29|tschang | 2/27/13|Set def_margin to 1 to decrease timing parmeters for performance #-- 1.28|tschang | 2/11/13|Set WR ODT start to 1 and end to 5 (HW239026) @@ -237,8 +240,9 @@ define def_equal_test = (SYS.ATTR_SCRATCH_UINT32_1 == SYS.ATTR_SCRATCH_UINT # mba tmr0 register timings are added to the value below -define def_margin1 = (1); -define def_margin2 = (0); +define def_margin1 = (1); +define def_margin2 = (0); +define def_margin_rdtag = (4); define def_no_spare = (SYS.ATTR_IS_SIMULATION==1) ; @@ -1925,15 +1929,15 @@ scom 0x0301040B { 16:19 , 0b1101 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys13 == 1); # RWSMDR_dly 5 16:19 , 0b1110 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys14 == 1); # RWSMDR_dly 5 16:19 , 0b1111 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys15 == 1); # RWSMDR_dly 5 - 20:23 , 0b0001 + def_margin2 , 1 , (def_mba_tmr0q_RW_dlys7 == 1); # RWDM_dly 6 - 20:23 , 0b1000 + def_margin2 , 1 , (def_mba_tmr0q_RW_dlys8 == 1); # RWDM_dly 6 - 20:23 , 0b1001 + def_margin2 , 1 , (def_mba_tmr0q_RW_dlys9 == 1); # RWDM_dly 6 - 20:23 , 0b1010 + def_margin2 , 1 , (def_mba_tmr0q_RW_dlys10 == 1); # RWDM_dly 6 - 20:23 , 0b1011 + def_margin2 , 1 , (def_mba_tmr0q_RW_dlys11 == 1); # RWDM_dly 6 - 20:23 , 0b1100 + def_margin2 , 1 , (def_mba_tmr0q_RW_dlys12 == 1); # RWDM_dly 6 - 20:23 , 0b1101 + def_margin2 , 1 , (def_mba_tmr0q_RW_dlys13 == 1); # RWDM_dly 6 - 20:23 , 0b1110 + def_margin2 , 1 , (def_mba_tmr0q_RW_dlys14 == 1); # RWDM_dly 6 - 20:23 , 0b1111 + def_margin2 , 1 , (def_mba_tmr0q_RW_dlys15 == 1); # RWDM_dly 6 + 20:23 , 0b0001 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys7 == 1); # RWDM_dly 6 + 20:23 , 0b1000 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys8 == 1); # RWDM_dly 6 + 20:23 , 0b1001 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys9 == 1); # RWDM_dly 6 + 20:23 , 0b1010 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys10 == 1); # RWDM_dly 6 + 20:23 , 0b1011 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys11 == 1); # RWDM_dly 6 + 20:23 , 0b1100 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys12 == 1); # RWDM_dly 6 + 20:23 , 0b1101 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys13 == 1); # RWDM_dly 6 + 20:23 , 0b1110 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys14 == 1); # RWDM_dly 6 + 20:23 , 0b1111 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys15 == 1); # RWDM_dly 6 24:29 , 0b010011 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys19 == 1); # WRSMSR_dly 7 24:29 , 0b010100 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys20 == 1); # WRSMSR_dly 7 24:29 , 0b010101 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys21 == 1); # WRSMSR_dly 7 @@ -2093,26 +2097,31 @@ scom 0x0301040A { # 30:35 , 0b010001 , 1 , (def_mba_dsm0q_cfg_wrdata_dly17 == 1); # wrdata_dly 26 # 30:35 , 0b010010 , 1 , (def_mba_dsm0q_cfg_wrdata_dly18 == 1); # wrdata_dly 26 # 30:35 , 0b010011 , 1 , (def_mba_dsm0q_cfg_wrdata_dly19 == 1); # wrdata_dly 26 -# 36:41 , 0b001100 , 1 , (def_mba_dsm0q_cfg_rdtag_dly12 == 1); # rdtag_dly 27 -# 36:41 , 0b001101 , 1 , (def_mba_dsm0q_cfg_rdtag_dly13 == 1); # rdtag_dly 27 -# 36:41 , 0b001110 , 1 , (def_mba_dsm0q_cfg_rdtag_dly14 == 1); # rdtag_dly 27 -# 36:41 , 0b001111 , 1 , (def_mba_dsm0q_cfg_rdtag_dly15 == 1); # rdtag_dly 27 -# 36:41 , 0b010000 , 1 , (def_mba_dsm0q_cfg_rdtag_dly16 == 1); # rdtag_dly 27 -# 36:41 , 0b010001 , 1 , (def_mba_dsm0q_cfg_rdtag_dly17 == 1); # rdtag_dly 27 -# 36:41 , 0b010010 , 1 , (def_mba_dsm0q_cfg_rdtag_dly18 == 1); # rdtag_dly 27 -# 36:41 , 0b010011 , 1 , (def_mba_dsm0q_cfg_rdtag_dly19 == 1); # rdtag_dly 27 -# 36:41 , 0b010100 , 1 , (def_mba_dsm0q_cfg_rdtag_dly20 == 1); # rdtag_dly 27 -# 36:41 , 0b010101 , 1 , (def_mba_dsm0q_cfg_rdtag_dly21 == 1); # rdtag_dly 27 -# 36:41 , 0b010110 , 1 , (def_mba_dsm0q_cfg_rdtag_dly22 == 1); # rdtag_dly 27 -# 36:41 , 0b010111 , 1 , (def_mba_dsm0q_cfg_rdtag_dly23 == 1); # rdtag_dly 27 -# 36:41 , 0b011000 , 1 , (def_mba_dsm0q_cfg_rdtag_dly24 == 1); # rdtag_dly 27 -# 36:41 , 0b011001 , 1 , (def_mba_dsm0q_cfg_rdtag_dly25 == 1); # rdtag_dly 27 -# 36:41 , 0b011010 , 1 , (def_mba_dsm0q_cfg_rdtag_dly26 == 1); # rdtag_dly 27 -# 36:41 , 0b011011 , 1 , (def_mba_dsm0q_cfg_rdtag_dly27 == 1); # rdtag_dly 27 -# 36:41 , 0b011100 , 1 , (def_mba_dsm0q_cfg_rdtag_dly28 == 1); # rdtag_dly 27 -# 36:41 , 0b011101 , 1 , (def_mba_dsm0q_cfg_rdtag_dly29 == 1); # rdtag_dly 27 + 36:41 , 0b001100 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly12 == 1); # rdtag_dly 27 + 36:41 , 0b001101 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly13 == 1); # rdtag_dly 27 + 36:41 , 0b001110 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly14 == 1); # rdtag_dly 27 + 36:41 , 0b001111 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly15 == 1); # rdtag_dly 27 + 36:41 , 0b010000 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly16 == 1); # rdtag_dly 27 + 36:41 , 0b010001 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly17 == 1); # rdtag_dly 27 + 36:41 , 0b010010 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly18 == 1); # rdtag_dly 27 + 36:41 , 0b010011 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly19 == 1); # rdtag_dly 27 + 36:41 , 0b010100 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly20 == 1); # rdtag_dly 27 + 36:41 , 0b010101 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly21 == 1); # rdtag_dly 27 + 36:41 , 0b010110 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly22 == 1); # rdtag_dly 27 + 36:41 , 0b010111 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly23 == 1); # rdtag_dly 27 + 36:41 , 0b011000 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly24 == 1); # rdtag_dly 27 + 36:41 , 0b011001 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly25 == 1); # rdtag_dly 27 + 36:41 , 0b011010 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly26 == 1); # rdtag_dly 27 + 36:41 , 0b011011 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly27 == 1); # rdtag_dly 27 + 36:41 , 0b011100 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly28 == 1); # rdtag_dly 27 + 36:41 , 0b011101 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly29 == 1); # rdtag_dly 27 # 36:41 , 0b100100 , 1 , any ; # rdtag_dly 36 temporary fix for testfloor - 36:41 , 0b011000 , 1 , any ; # rdtag_dly 24 temporary fix for testfloor +# 36:41 , 0b011000 , 1 , any ; # rdtag_dly 24 temporary fix for testfloor +# 36:41 , 0b010111 , 1 , any ; # rdtag_dly 23 temporary fix for testfloor +# setting 22 works for 1600 11-11-11 +# 36:41 , 0b010110 , 1 , any ; # rdtag_dly 22 temporary fix for testfloor +# setting 21 failed +# 36:41 , 0b010101 , 1 , any ; # rdtag_dly 21 temporary fix for testfloor 43:48 , 0b000101 , 1 , (def_mba_dsm0q_CFG_RODT_BC4_END_DLY5 == 1); # CFG_RODT_BC4_END_DLY 28 43:48 , 0b000110 , 1 , (def_mba_dsm0q_CFG_RODT_BC4_END_DLY6 == 1); # CFG_RODT_BC4_END_DLY 28 43:48 , 0b000111 , 1 , (def_mba_dsm0q_CFG_RODT_BC4_END_DLY7 == 1); # CFG_RODT_BC4_END_DLY 28 diff --git a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile index bf6bd970d..a83c5cd20 100644 --- a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile +++ b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile @@ -1,8 +1,9 @@ -#-- $Id: mbs_def.initfile,v 1.25 2013/01/17 15:41:30 yctschan Exp $ +#-- $Id: mbs_def.initfile,v 1.28 2013/03/15 16:59:48 jmcgill Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.26 |tschang |03/13/13| changed cache interleave mode to have ATTR_MSS_CACHE_ENABLE as a condition #-- 1.25 |tschang |01/17/13| cache enabled when (ATTR_MSS_CACHE_ENABLE != 0) - enabled cache when 1/2 cache mode is choosen #-- 1.21 |tschang |10/23/12| disable interleaving when one or both MBA are disabled (partial good tests) #-- 1.20 |tschang |09/27/12| added partial good support for the SCOM write using ATTR_FUNCTIONAL @@ -442,8 +443,8 @@ scom 0x0201140F { 0 , 0b1 , (ATTR_MSS_CACHE_ENABLE != 0); # MBCCFGQ_cache_enable # 1 , 0b0 , any ; # -MW match dials 1 , 0b0 , any ; # MBCCFGQ_cfg_dyn_whap_en - 2 , 0b0 , (SYS.ATTR_MSS_CLEANER_ENABLE == 0); # MBCCFGQ_cleaner_enable - 2 , 0b1 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1); # MBCCFGQ_cleaner_enable + 2 , 0b0 , ((SYS.ATTR_MSS_CLEANER_ENABLE == 0) || (ATTR_MSS_CACHE_ENABLE != 1)); # MBCCFGQ_cleaner_enable + 2 , 0b1 , ((SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (ATTR_MSS_CACHE_ENABLE == 1)); # MBCCFGQ_cleaner_enable 3 , 0b0 , any ; # MBCCFGQ_cache_only_enable 4 , 0b0 , any ; # MBCCFGQ_lru_dmap_en 5 , 0b0 , any ; # MBCCFGQ_lru_random_en @@ -456,15 +457,12 @@ scom 0x0201140F { 11 , 0b1 , (SYS.ATTR_MSS_PREFETCH_ENABLE == 0); # MBCCFGQ_srw_prefetch_dis 12 , 0b0 , (SYS.ATTR_MSS_PREFETCH_ENABLE == 1); # MBCCFGQ_prq_prefetch_dis 12 , 0b1 , (SYS.ATTR_MSS_PREFETCH_ENABLE == 0); # MBCCFGQ_prq_prefetch_dis -# 12 , 0b0 , any ; # -MW match dials -# 12 , 0b0 , (SYS.ATTR_MSS_PREFETCH_ENABLE == 1) && (SYS.ATTR_MSS_CACHE_ENABLE == 1); -# 12 , 0b1 , (SYS.ATTR_MSS_PREFETCH_ENABLE == 0); -#13:16 , 0xF , any ; # MBCCFGQ_cln_page_mode_bundle_max_cnt_0_3 -#17:22 , 0x10 , any ; # MBCCFGQ_cln_wrq_tgt_alloc_0_5 -#23:28 , 0x7 , any ; # MBCCFGQ_cln_wr_priority_wrq_hwmark_0_5 -#29:34 , 0x6 , any ; # MBCCFGQ_cln_wr_priority_wrq_lwmark_0_5 -#35:48 , 0x400 , any ; # MBCCFGQ_cln_wr_priority_dv_hwmark_0_13 -#49:62 , 0x300 , any ; # MBCCFGQ_cln_wr_priority_dv_lwmark_0_13 + 13:16 , 0xE , any ; # MBCCFGQ_cln_page_mode_bundle_max_cnt_0_3 + 17:22 , 0x1F , any ; # MBCCFGQ_cln_wrq_tgt_alloc_0_5 + 23:28 , 0x7 , any ; # MBCCFGQ_cln_wr_priority_wrq_hwmark_0_5 + 29:34 , 0x6 , any ; # MBCCFGQ_cln_wr_priority_wrq_lwmark_0_5 + 35:48 , 0x1000 , any ; # MBCCFGQ_cln_wr_priority_dv_hwmark_0_13 + 49:62 , 0x0FC0 , any ; # MBCCFGQ_cln_wr_priority_dv_lwmark_0_13 } @@ -555,8 +553,10 @@ scom 0x0201140B { 10:11 , 0b01 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 1); # MBAXCR01Q_MBA01_Hash_Mode 10:11 , 0b10 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 2); # MBAXCR01Q_MBA01_Hash_Mode # 12 , 0b0 , 1 , any; # -MW match dials # MBAXCR01Q_MBA01_Interleave_Mode - 12 , 0b0 , 1 , (SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 0); # MBAXCR01Q_MBA01_Interleave_Mode - 12 , 0b1 , 1 , (SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 1); # MBAXCR01Q_MBA01_Interleave_Mode +# 12 , 0b0 , 1 , (SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 0); # MBAXCR01Q_MBA01_Interleave_Mode +# 12 , 0b1 , 1 , (SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 1); # MBAXCR01Q_MBA01_Interleave_Mode + 12 , 0b0 , 1 , ((SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 0) || (ATTR_MSS_CACHE_ENABLE != 1)); # MBAXCR01Q_MBA01_Interleave_Mode + 12 , 0b1 , 1 , ((SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 1) && (ATTR_MSS_CACHE_ENABLE == 1)); # MBAXCR01Q_MBA01_Interleave_Mod } diff --git a/src/usr/hwpf/hwp/mc_config/mc_config.C b/src/usr/hwpf/hwp/mc_config/mc_config.C index 35c2a30f3..173824391 100644 --- a/src/usr/hwpf/hwp/mc_config/mc_config.C +++ b/src/usr/hwpf/hwp/mc_config/mc_config.C @@ -378,7 +378,8 @@ errlHndl_t call_opt_memmap() l_fapi_procs.push_back(l_fapi_target); } - FAPI_INVOKE_HWP(l_err, opt_memmap, l_fapi_procs); + bool l_initProcMemBaseAttr = false; + FAPI_INVOKE_HWP(l_err, opt_memmap, l_fapi_procs, l_initProcMemBaseAttr); if ( l_err ) { diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C index 6a2547e9e..340bd6f7d 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_config.C,v 1.20 2013/02/28 21:36:08 asaetow Exp $ +// $Id: mss_eff_config.C,v 1.21 2013/03/22 21:57:25 asaetow Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/ // centaur/working/procedures/ipl/fapi/mss_eff_config.C,v $ //------------------------------------------------------------------------------ @@ -44,7 +44,9 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- -// 1.21 | | | +// 1.22 | | | +// 1.21 | asaetow |22-Mar-13| Changed ATTR_EFF_ZQCAL_INTERVAL and ATTR_EFF_MEMCAL_INTERVAL back to enable. +// | | | NOTE: Need mba_def.initfile v1.27 or newer // 1.20 | asaetow |28-Feb-13| Changed temporary ATTR_EFF_ZQCAL_INTERVAL and ATTR_EFF_MEMCAL_INTERVAL to disable. // | | | NOTE: Temporary until we get timeout error fixed. // 1.19 | sauchadh |26-Feb-13| Added MCBIST related attributes @@ -1526,15 +1528,15 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( // ------------------------------ = 13.333ms // (1.5 * 10) + (0.15 * 150) - p_o_atts->eff_zqcal_interval = 0; - //p_o_atts->eff_zqcal_interval = ( 13333 * - // p_i_mss_eff_config_data->mss_freq) / 2; + //p_o_atts->eff_zqcal_interval = 0; + p_o_atts->eff_zqcal_interval = ( 13333 * + p_i_mss_eff_config_data->mss_freq) / 2; //------------------------------------------------------------------------------ // Calculate MEMCAL Interval based on 1sec interval across all bits per DP18 - p_o_atts->eff_memcal_interval = 0; - //p_o_atts->eff_memcal_interval = (62500 * - // p_i_mss_eff_config_data->mss_freq) / 2; + //p_o_atts->eff_memcal_interval = 0; + p_o_atts->eff_memcal_interval = (62500 * + p_i_mss_eff_config_data->mss_freq) / 2; //------------------------------------------------------------------------------ // Calculate tRFI p_o_atts->eff_dram_trfi = (3900 * diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C index 616c9388b..dc5a8cba0 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_config_termination.C,v 1.11 2012/12/23 02:29:44 asaetow Exp $ +// $Id: mss_eff_config_termination.C,v 1.15 2013/03/14 13:23:58 lapietra Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_termination.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -29,7 +29,7 @@ //------------------------------------------------------------------------------ // *! TITLE : mss_eff_config_termination // *! DESCRIPTION : see additional comments below -// *! OWNER NAME : Anuwat Saetow Email: asaetow@us.ibm.com +// *! OWNER NAME : Dave Cadigan Email: dcadiga@us.ibm.com // *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com // *! ADDITIONAL COMMENTS : // @@ -42,7 +42,10 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- -// 1.12 | | | +// 1.15 | dcadiga |14-MAR-13| Fixed simulation issue +// 1.14 | dcadiga |12-MAR-13| Code re-write for new dimms. Confirmed working on all systems +// 1.13 | asaetow |19-FEB-12| Changed default SI value for CDIMM, turned of Rtt_NOM and disabled Rtt_WR for DIMM1. +// 1.12 | asaetow |07-FEB-12| Added check for Centaur EC10 ADR Centerlane NWELL workaround. // 1.11 | asaetow |22-DEC-12| Added CDIMM workaround for EC10 ADR Centerlane race condition, subtract 32ticks. // | | | NOTE: Need EC check for Centaur EC10 ADR Centerlane NWELL workaround. // 1.10 | asaetow |22-DEC-12| Added Centaur EC10 ADR Centerlane PR=0x7F workaround for NWELL LVS issue. @@ -51,7 +54,7 @@ // 1.9 | bellows |12-DEC-12| Changed phase rotators for sim to 0x40 for clocks // 1.8 | bellows |06-DEC-12| Added sim leg for rotator values // 1.7 | asaetow |18-NOV-12| Changed ATTR_MSS_CAL_STEP_ENABLE from 0x7F back to 0xFF. -// 1.6 | asaetow |17-NOV-12| Fixed ATTR_EFF_ODT_WR for 4R RDIMMs. +// 1.6 | asaetow |17-NOV-12| Fixed uint8_t attr_eff_odt_wr for 4R RDIMMs. // 1.5 | asaetow |17-NOV-12| Added PR settings. // | | | Fixed RCD settings for RDIMM. // 1.4 | asaetow |17-NOV-12| Changed ATTR_MSS_CAL_STEP_ENABLE from 0xFF to 0x7F. @@ -81,108 +84,439 @@ // Define attribute array size const uint8_t PORT_SIZE = 2; -const uint8_t PR_TYPE_SIZE = 48; -const uint8_t TOPO_SIZE = 25; - -const uint8_t PR_VALUE_U8ARRAY[PORT_SIZE][PR_TYPE_SIZE][TOPO_SIZE] = { - {{0,95,100,63,67,66,63,63,63,90,95,69,71,73,77,69,71,69,73,76,77,81,73,78,74}, - {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, - {0,103,109,0,0,0,0,0,0,98,104,0,0,0,0,0,0,0,69,71,72,77,69,71,68}, - {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, - {0,6,9,2,1,2,2,2,2,11,14,12,15,12,15,12,14,10,18,21,17,21,16,20,15}, - {0,7,9,3,2,3,2,3,3,11,14,11,13,11,13,10,13,9,17,20,16,19,14,18,14}, - {0,7,9,2,2,2,2,2,2,10,13,12,15,12,15,12,15,10,18,22,18,21,16,20,15}, - {0,3,3,5,4,5,4,5,4,5,6,11,14,11,14,11,14,9,17,20,17,20,15,19,14}, - {0,0,0,0,0,0,0,0,1,4,5,8,10,8,10,8,10,7,14,17,14,16,12,15,12}, - {0,0,0,1,1,1,1,1,1,5,6,12,15,12,15,11,14,10,18,21,17,21,16,20,15}, - {0,3,3,4,3,4,3,4,4,6,8,13,16,13,16,13,16,11,19,23,18,22,17,21,16}, - {0,2,2,3,2,3,2,3,3,6,8,13,17,13,17,13,17,11,19,23,19,23,17,22,16}, - {0,4,4,6,5,6,5,6,5,9,11,16,21,16,21,16,21,14,22,27,22,27,21,26,19}, - {0,6,8,2,2,2,2,2,2,10,13,12,15,12,15,12,15,10,18,22,18,22,16,21,15}, - {0,11,14,8,6,8,6,8,7,8,11,9,11,9,11,9,11,7,15,18,15,17,12,16,12}, - {0,8,10,3,3,3,3,3,3,11,14,12,15,12,15,12,15,10,18,22,18,21,16,21,15}, - {0,8,10,4,3,4,3,4,4,10,12,11,13,11,13,10,13,9,17,20,16,19,14,18,14}, - {0,7,10,3,3,3,3,3,3,13,16,14,18,14,18,14,17,12,20,24,19,23,18,23,17}, - {0,7,9,3,2,3,2,3,3,11,14,12,15,12,15,12,15,10,18,21,17,21,16,20,15}, - {0,11,14,8,7,8,6,8,7,8,10,7,9,7,9,7,9,6,13,15,13,15,10,14,11}, - {0,6,7,8,7,8,7,8,7,3,3,9,11,9,11,9,11,7,15,18,14,17,12,16,12}, - {0,6,6,8,7,8,7,8,7,4,5,10,13,10,13,10,13,8,16,20,16,19,14,18,14}, - {0,11,14,8,6,8,6,8,7,7,9,7,8,7,8,7,8,5,13,15,12,14,10,13,10}, - {0,12,15,9,8,9,8,9,8,7,9,8,10,8,10,8,10,7,14,17,14,16,12,15,12}, - {0,11,14,8,6,8,6,8,7,11,13,11,14,11,14,11,14,9,17,20,17,20,15,19,14}, - {0,12,15,9,7,9,7,9,8,7,9,6,7,6,7,6,7,5,12,14,11,13,9,12,9}, - {0,0,0,8,7,8,7,8,7,0,0,9,11,9,11,9,11,7,15,18,14,17,12,16,12}, - {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, - {0,31,37,3,2,3,2,3,3,38,44,8,10,8,9,8,10,7,11,14,12,13,12,16,12}, - {0,0,0,12,10,12,10,12,11,0,0,1,2,1,1,1,1,1,5,6,5,5,6,8,7}, - {0,24,29,0,0,0,0,0,0,34,40,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, - {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, - {0,12,14,0,0,0,0,0,1,21,25,10,13,10,13,10,13,9,14,17,14,16,15,20,15}, - {0,0,0,12,10,12,10,12,11,0,0,1,2,1,2,1,2,1,5,6,5,5,6,8,7}, - {0,0,0,2,2,2,2,2,3,0,0,10,12,10,12,10,12,8,13,17,14,15,14,19,14}, - {0,0,0,12,10,12,10,12,11,0,0,4,5,4,5,4,5,3,7,10,8,8,8,12,9}, - {0,14,16,3,2,3,2,3,3,14,16,3,4,3,4,3,4,3,7,9,7,7,8,11,9}, - {0,0,0,11,9,11,9,11,10,0,0,1,2,1,1,1,1,1,5,6,5,5,6,8,7}, - {0,31,37,0,0,0,0,0,0,41,47,0,0,0,0,0,0,0,11,13,11,13,11,14,9}, - {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,2,2,2,2,2,1}, - {0,34,40,0,0,0,0,0,0,34,41,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, - {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, - {0,19,23,0,0,0,0,0,0,13,15,0,0,0,0,0,0,0,3,4,3,4,3,4,3}, - {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,3,3,3,3,3,2}, - {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,5,5,5,5,5,6,4}, - {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,3,3,3,3,3,3}, - {0,15,17,0,0,0,0,0,0,21,24,0,0,0,0,0,0,0,8,10,8,10,8,10,7}, - {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,3,2,2,2,3,2}}, - - {{0,90,95,70,71,75,68,70,71,91,96,69,71,73,77,69,71,69,73,76,77,81,73,78,74}, - {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, - {0,99,105,0,0,0,0,0,0,99,104,0,0,0,0,0,0,0,69,71,72,77,69,71,68}, - {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, - {0,11,13,8,7,8,7,8,7,7,9,10,12,10,12,10,12,8,16,19,16,19,14,17,13}, - {0,9,11,6,5,6,5,6,5,8,10,10,13,10,13,10,13,8,16,20,16,19,14,18,14}, - {0,12,14,9,7,9,7,9,7,10,12,13,16,13,16,13,16,11,19,23,19,23,17,22,16}, - {0,2,3,4,3,4,3,4,3,2,2,10,13,11,13,10,13,8,16,20,16,19,14,18,14}, - {0,0,0,2,2,2,2,2,2,2,3,11,13,11,13,10,13,9,17,20,16,19,14,18,14}, - {0,0,0,0,0,0,0,0,0,4,4,13,16,13,16,13,16,10,19,23,18,22,17,21,16}, - {0,1,2,3,2,3,2,3,2,4,5,13,16,13,16,13,16,11,19,23,19,23,17,22,16}, - {0,0,0,2,1,2,1,2,1,3,4,12,15,12,15,12,15,10,18,22,18,21,16,20,15}, - {0,7,8,10,8,10,8,10,8,5,5,13,16,13,16,13,16,11,19,23,19,23,17,22,16}, - {0,5,7,1,1,1,1,1,1,10,12,13,17,13,17,13,16,11,19,23,19,23,17,22,16}, - {0,12,15,9,8,9,8,9,8,5,7,9,11,9,11,8,10,7,15,17,14,17,12,15,12}, - {0,6,8,3,2,3,2,3,2,10,12,13,16,13,16,13,16,11,19,23,18,22,17,21,16}, - {0,10,13,7,6,7,6,7,6,7,8,10,12,10,13,10,12,8,16,19,16,19,14,17,13}, - {0,9,11,6,5,6,5,6,5,9,11,12,15,12,15,12,15,10,18,22,18,21,16,20,15}, - {0,7,9,3,3,3,3,3,3,10,12,13,17,13,17,13,17,11,19,23,19,23,17,22,16}, - {0,10,13,6,5,6,5,6,5,7,9,10,12,10,12,10,12,8,16,19,16,19,13,17,13}, - {0,4,5,6,5,6,5,6,5,1,1,10,12,10,12,9,12,8,16,19,15,18,13,17,13}, - {0,4,4,5,4,5,4,5,4,2,2,10,13,10,13,10,12,8,16,19,16,19,14,17,13}, - {0,11,14,7,6,8,6,8,6,6,8,9,11,9,11,9,11,7,15,18,15,18,13,16,12}, - {0,12,15,9,7,9,7,9,7,7,9,10,12,10,12,10,12,8,16,19,16,19,14,17,13}, - {0,15,18,11,9,11,9,11,9,5,7,8,9,8,9,8,9,6,14,16,13,16,11,14,11}, - {0,13,16,10,9,11,9,11,9,5,7,8,10,8,10,8,9,6,14,16,13,16,11,14,11}, - {0,0,0,4,3,4,3,4,3,0,0,12,15,12,15,12,15,10,18,22,18,22,16,21,15}, - {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, - {0,32,38,3,1,3,2,3,2,31,37,4,4,4,4,4,4,3,7,9,8,7,8,11,9}, - {0,0,0,5,3,5,4,5,4,0,0,11,14,11,14,11,14,10,15,19,15,17,16,21,15}, - {0,27,32,0,0,0,0,0,0,36,42,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, - {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, - {0,14,16,4,3,4,4,5,4,14,15,4,4,4,4,4,4,3,7,9,8,8,8,11,9}, - {0,0,0,10,7,10,8,10,8,0,0,12,15,12,15,12,15,10,15,20,16,18,17,22,16}, - {0,0,0,3,2,3,3,3,3,0,0,4,4,4,4,4,4,3,7,9,8,8,8,11,9}, - {0,0,0,12,9,12,10,12,10,0,0,11,13,11,13,11,13,9,14,18,15,16,15,20,15}, - {0,14,16,3,1,3,2,3,3,13,15,3,4,3,3,3,4,2,6,8,7,7,7,10,8}, - {0,0,0,12,10,12,10,13,11,0,0,9,12,9,11,9,12,8,13,16,13,15,14,18,14}, - {0,33,39,0,0,0,0,0,0,31,36,0,0,0,0,0,0,0,4,4,4,4,4,4,3}, - {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,12,15,12,15,12,15,10}, - {0,33,40,0,0,0,0,0,0,32,38,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, - {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, - {0,15,18,0,0,0,0,0,0,19,21,0,0,0,0,0,0,0,9,11,9,11,9,11,8}, - {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,14,17,14,17,14,17,12}, - {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,9,10,9,10,9,11,7}, - {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,11,13,11,13,11,13,9}, - {0,12,14,0,0,0,0,0,0,13,15,0,0,0,0,0,0,0,4,5,4,5,4,5,3}, - {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,11,13,11,13,10,13,9}}}; +const uint8_t DIMM_SIZE = 2; +const uint8_t RANK_SIZE = 4; + +//Declare all Static Arrays + +uint32_t attr_eff_dimm_rcd_ibt[PORT_SIZE][DIMM_SIZE]; +uint8_t attr_eff_dimm_rcd_mirror_mode[PORT_SIZE][DIMM_SIZE]; +uint8_t attr_eff_dram_ron[PORT_SIZE][DIMM_SIZE]; +uint8_t attr_eff_dram_rtt_nom[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; +uint8_t attr_eff_dram_rtt_wr[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; +uint8_t attr_eff_odt_rd[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; +uint8_t attr_eff_odt_wr[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; +uint32_t attr_eff_cen_rd_vref[PORT_SIZE]; +uint32_t attr_eff_dram_wr_vref[PORT_SIZE]; +//uint8_t attr_eff_dram_wrddr4_vref[PORT_SIZE]; +uint8_t attr_eff_cen_rcv_imp_dq_dqs[PORT_SIZE]; +uint8_t attr_eff_cen_drv_imp_dq_dqs[PORT_SIZE]; +uint8_t attr_eff_cen_drv_imp_cntl[PORT_SIZE]; +uint8_t attr_eff_cen_drv_imp_addr[PORT_SIZE]; +uint8_t attr_eff_cen_drv_imp_clk[PORT_SIZE]; +uint8_t attr_eff_cen_drv_imp_spcke[PORT_SIZE]; +uint8_t attr_eff_cen_slew_rate_dq_dqs[PORT_SIZE]; +uint8_t attr_eff_cen_slew_rate_cntl[PORT_SIZE]; +uint8_t attr_eff_cen_slew_rate_addr[PORT_SIZE]; +uint8_t attr_eff_cen_slew_rate_clk[PORT_SIZE]; +uint8_t attr_eff_cen_slew_rate_spcke[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m0_clk_p0[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m0_clk_p1[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m1_clk_p0[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m1_clk_p1[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_cmd_a0[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_cmd_a1[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_cmd_a2[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_cmd_a3[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_cmd_a4[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_cmd_a5[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_cmd_a6[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_cmd_a7[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_cmd_a8[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_cmd_a9[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_cmd_a10[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_cmd_a11[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_cmd_a12[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_cmd_a13[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_cmd_a14[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_cmd_a15[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_cmd_bA0[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_cmd_bA1[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_cmd_bA2[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_cmd_casn[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_cmd_rasn[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_cmd_wen[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_par[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m_actn[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m0_cntl_cke0[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m0_cntl_cke1[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m0_cntl_cke2[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m0_cntl_cke3[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m0_cntl_csn0[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m0_cntl_csn1[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m0_cntl_csn2[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m0_cntl_csn3[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m0_cntl_odt0[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m0_cntl_odt1[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m1_cntl_cke0[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m1_cntl_cke1[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m1_cntl_cke2[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m1_cntl_cke3[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m1_cntl_csn0[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m1_cntl_csn1[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m1_cntl_csn2[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m1_cntl_csn3[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m1_cntl_odt0[PORT_SIZE]; +uint8_t attr_eff_cen_phase_rot_m1_cntl_odt1[PORT_SIZE]; + +/* +const uint8_t valid_attrs[200] = { +attr_eff_dimm_rcd_ibt[0][0], +attr_eff_dimm_rcd_ibt[0][1], +attr_eff_dimm_rcd_ibt[1][0], +attr_eff_dimm_rcd_ibt[1][1], +attr_eff_dimm_rcd_mirror_mode[0][0], +attr_eff_dimm_rcd_mirror_mode[0][1], +attr_eff_dimm_rcd_mirror_mode[1][0], +attr_eff_dimm_rcd_mirror_mode[1][1], +attr_eff_dram_ron[0][0], +attr_eff_dram_ron[0][1], +attr_eff_dram_ron[1][0], +attr_eff_dram_ron[1][1], +attr_eff_dram_rtt_nom[0][0][0], +attr_eff_dram_rtt_nom[0][0][1], +attr_eff_dram_rtt_nom[0][0][2], +attr_eff_dram_rtt_nom[0][0][3], +attr_eff_dram_rtt_nom[0][1][0], +attr_eff_dram_rtt_nom[0][1][1], +attr_eff_dram_rtt_nom[0][1][2], +attr_eff_dram_rtt_nom[0][1][3], +attr_eff_dram_rtt_nom[1][0][0], +attr_eff_dram_rtt_nom[1][0][1], +attr_eff_dram_rtt_nom[1][0][2], +attr_eff_dram_rtt_nom[1][0][3], +attr_eff_dram_rtt_nom[1][1][0], +attr_eff_dram_rtt_nom[1][1][1], +attr_eff_dram_rtt_nom[1][1][2], +attr_eff_dram_rtt_nom[1][1][3], +attr_eff_dram_rtt_wr[0][0][0], +attr_eff_dram_rtt_wr[0][0][1], +attr_eff_dram_rtt_wr[0][0][2], +attr_eff_dram_rtt_wr[0][0][3], +attr_eff_dram_rtt_wr[0][1][0], +attr_eff_dram_rtt_wr[0][1][1], +attr_eff_dram_rtt_wr[0][1][2], +attr_eff_dram_rtt_wr[0][1][3], +attr_eff_dram_rtt_wr[1][0][0], +attr_eff_dram_rtt_wr[1][0][1], +attr_eff_dram_rtt_wr[1][0][2], +attr_eff_dram_rtt_wr[1][0][3], +attr_eff_dram_rtt_wr[1][1][0], +attr_eff_dram_rtt_wr[1][1][1], +attr_eff_dram_rtt_wr[1][1][2], +attr_eff_dram_rtt_wr[1][1][3], +attr_eff_odt_rd[0][0][0], +attr_eff_odt_rd[0][0][1], +attr_eff_odt_rd[0][0][2], +attr_eff_odt_rd[0][0][3], +attr_eff_odt_rd[0][1][0], +attr_eff_odt_rd[0][1][1], +attr_eff_odt_rd[0][1][2], +attr_eff_odt_rd[0][1][3], +attr_eff_odt_rd[1][0][0], +attr_eff_odt_rd[1][0][1], +attr_eff_odt_rd[1][0][2], +attr_eff_odt_rd[1][0][3], +attr_eff_odt_rd[1][1][0], +attr_eff_odt_rd[1][1][1], +attr_eff_odt_rd[1][1][2], +attr_eff_odt_rd[1][1][3], +attr_eff_odt_wr[0][0][0], +attr_eff_odt_wr[0][0][1], +attr_eff_odt_wr[0][0][2], +attr_eff_odt_wr[0][0][3], +attr_eff_odt_wr[0][1][0], +attr_eff_odt_wr[0][1][1], +attr_eff_odt_wr[0][1][2], +attr_eff_odt_wr[0][1][3], +attr_eff_odt_wr[1][0][0], +attr_eff_odt_wr[1][0][1], +attr_eff_odt_wr[1][0][2], +attr_eff_odt_wr[1][0][3], +attr_eff_odt_wr[1][1][0], +attr_eff_odt_wr[1][1][1], +attr_eff_odt_wr[1][1][2], +attr_eff_odt_wr[1][1][3], +attr_eff_cen_rd_vref[0], +attr_eff_cen_rd_vref[1], +attr_eff_dram_wr_vref[0], +attr_eff_dram_wr_vref[1], +//attr_eff_dram_wrddr4_vref[0], +//attr_eff_dram_wrddr4_vref[1], +attr_eff_cen_rcv_imp_dq_dqs[0], +attr_eff_cen_rcv_imp_dq_dqs[1], +attr_eff_cen_drv_imp_dq_dqs[0], +attr_eff_cen_drv_imp_dq_dqs[1], +attr_eff_cen_drv_imp_cntl[0], +attr_eff_cen_drv_imp_cntl[1], +attr_eff_cen_drv_imp_addr[0], +attr_eff_cen_drv_imp_addr[1], +attr_eff_cen_drv_imp_clk[0], +attr_eff_cen_drv_imp_clk[1], +attr_eff_cen_drv_imp_spcke[0], +attr_eff_cen_drv_imp_spcke[1], +attr_eff_cen_slew_rate_dq_dqs[0], +attr_eff_cen_slew_rate_dq_dqs[1], +attr_eff_cen_slew_rate_cntl[0], +attr_eff_cen_slew_rate_cntl[1], +attr_eff_cen_slew_rate_addr[0], +attr_eff_cen_slew_rate_addr[1], +attr_eff_cen_slew_rate_clk[0], +attr_eff_cen_slew_rate_clk[1], +attr_eff_cen_slew_rate_spcke[0], +attr_eff_cen_slew_rate_spcke[1], +attr_eff_cen_phase_rot_m0_clk_p0[0], +attr_eff_cen_phase_rot_m0_clk_p1[0], +attr_eff_cen_phase_rot_m1_clk_p0[0], +attr_eff_cen_phase_rot_m1_clk_p1[0], +attr_eff_cen_phase_rot_m_cmd_a0[0], +attr_eff_cen_phase_rot_m_cmd_a1[0], +attr_eff_cen_phase_rot_m_cmd_a2[0], +attr_eff_cen_phase_rot_m_cmd_a3[0], +attr_eff_cen_phase_rot_m_cmd_a4[0], +attr_eff_cen_phase_rot_m_cmd_a5[0], +attr_eff_cen_phase_rot_m_cmd_a6[0], +attr_eff_cen_phase_rot_m_cmd_a7[0], +attr_eff_cen_phase_rot_m_cmd_a8[0], +attr_eff_cen_phase_rot_m_cmd_a9[0], +attr_eff_cen_phase_rot_m_cmd_a10[0], +attr_eff_cen_phase_rot_m_cmd_a11[0], +attr_eff_cen_phase_rot_m_cmd_a12[0], +attr_eff_cen_phase_rot_m_cmd_a13[0], +attr_eff_cen_phase_rot_m_cmd_a14[0], +attr_eff_cen_phase_rot_m_cmd_a15[0], +attr_eff_cen_phase_rot_m_cmd_bA0[0], +attr_eff_cen_phase_rot_m_cmd_bA1[0], +attr_eff_cen_phase_rot_m_cmd_bA2[0], +attr_eff_cen_phase_rot_m_cmd_casn[0], +attr_eff_cen_phase_rot_m_cmd_rasn[0], +attr_eff_cen_phase_rot_m_cmd_wen[0], +attr_eff_cen_phase_rot_m_par[0], +attr_eff_cen_phase_rot_m_actn[0], +attr_eff_cen_phase_rot_m0_cntl_cke0[0], +attr_eff_cen_phase_rot_m0_cntl_cke1[0], +attr_eff_cen_phase_rot_m0_cntl_cke2[0], +attr_eff_cen_phase_rot_m0_cntl_cke3[0], +attr_eff_cen_phase_rot_m0_cntl_csn0[0], +attr_eff_cen_phase_rot_m0_cntl_csn1[0], +attr_eff_cen_phase_rot_m0_cntl_csn2[0], +attr_eff_cen_phase_rot_m0_cntl_csn3[0], +attr_eff_cen_phase_rot_m0_cntl_odt0[0], +attr_eff_cen_phase_rot_m0_cntl_odt1[0], +attr_eff_cen_phase_rot_m1_cntl_cke0[0], +attr_eff_cen_phase_rot_m1_cntl_cke1[0], +attr_eff_cen_phase_rot_m1_cntl_cke2[0], +attr_eff_cen_phase_rot_m1_cntl_cke3[0], +attr_eff_cen_phase_rot_m1_cntl_csn0[0], +attr_eff_cen_phase_rot_m1_cntl_csn1[0], +attr_eff_cen_phase_rot_m1_cntl_csn2[0], +attr_eff_cen_phase_rot_m1_cntl_csn3[0], +attr_eff_cen_phase_rot_m1_cntl_odt0[0], +attr_eff_cen_phase_rot_m1_cntl_odt1[0], +attr_eff_cen_phase_rot_m0_clk_p0[1], +attr_eff_cen_phase_rot_m0_clk_p1[1], +attr_eff_cen_phase_rot_m1_clk_p0[1], +attr_eff_cen_phase_rot_m1_clk_p1[1], +attr_eff_cen_phase_rot_m_cmd_a0[1], +attr_eff_cen_phase_rot_m_cmd_a1[1], +attr_eff_cen_phase_rot_m_cmd_a2[1], +attr_eff_cen_phase_rot_m_cmd_a3[1], +attr_eff_cen_phase_rot_m_cmd_a4[1], +attr_eff_cen_phase_rot_m_cmd_a5[1], +attr_eff_cen_phase_rot_m_cmd_a6[1], +attr_eff_cen_phase_rot_m_cmd_a7[1], +attr_eff_cen_phase_rot_m_cmd_a8[1], +attr_eff_cen_phase_rot_m_cmd_a9[1], +attr_eff_cen_phase_rot_m_cmd_a10[1], +attr_eff_cen_phase_rot_m_cmd_a11[1], +attr_eff_cen_phase_rot_m_cmd_a12[1], +attr_eff_cen_phase_rot_m_cmd_a13[1], +attr_eff_cen_phase_rot_m_cmd_a14[1], +attr_eff_cen_phase_rot_m_cmd_a15[1], +attr_eff_cen_phase_rot_m_cmd_bA0[1], +attr_eff_cen_phase_rot_m_cmd_bA1[1], +attr_eff_cen_phase_rot_m_cmd_bA2[1], +attr_eff_cen_phase_rot_m_cmd_casn[1], +attr_eff_cen_phase_rot_m_cmd_rasn[1], +attr_eff_cen_phase_rot_m_cmd_wen[1], +attr_eff_cen_phase_rot_m_par[1], +attr_eff_cen_phase_rot_m_actn[1], +attr_eff_cen_phase_rot_m0_cntl_cke0[1], +attr_eff_cen_phase_rot_m0_cntl_cke1[1], +attr_eff_cen_phase_rot_m0_cntl_cke2[1], +attr_eff_cen_phase_rot_m0_cntl_cke3[1], +attr_eff_cen_phase_rot_m0_cntl_csn0[1], +attr_eff_cen_phase_rot_m0_cntl_csn1[1], +attr_eff_cen_phase_rot_m0_cntl_csn2[1], +attr_eff_cen_phase_rot_m0_cntl_csn3[1], +attr_eff_cen_phase_rot_m0_cntl_odt0[1], +attr_eff_cen_phase_rot_m0_cntl_odt1[1], +attr_eff_cen_phase_rot_m1_cntl_cke0[1], +attr_eff_cen_phase_rot_m1_cntl_cke1[1], +attr_eff_cen_phase_rot_m1_cntl_cke2[1], +attr_eff_cen_phase_rot_m1_cntl_cke3[1], +attr_eff_cen_phase_rot_m1_cntl_csn0[1], +attr_eff_cen_phase_rot_m1_cntl_csn1[1], +attr_eff_cen_phase_rot_m1_cntl_csn2[1], +attr_eff_cen_phase_rot_m1_cntl_csn3[1], +attr_eff_cen_phase_rot_m1_cntl_odt0[1], +attr_eff_cen_phase_rot_m1_cntl_odt1[1] +}; +*/ +//Declare the different dimms here: +//Cdimm rc_A +uint32_t cdimm_rca_1r_1333_mba0[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,89,0,91,0,13,13,13,8,5,6,8,7,9,13,17,14,14,14,13,17,12,11,17,18,17,18,0,0,19,0,21,0,0,0,0,0,2,0,19,0,0,0,7,0,0,0,3,0,86,0,92,0,17,15,18,8,6,5,7,6,12,12,18,12,16,15,13,16,10,9,17,18,21,19,0,0,19,0,24,0,2,0,0,0,2,0,20,0,0,0,3,0,0,0,0,0 +}; + +uint32_t cdimm_rca_1r_1333_mba1[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,87,0,92,0,18,18,18,11,11,11,13,13,15,18,16,18,17,20,18,15,9,11,14,15,18,14,0,0,26,0,32,0,11,0,0,0,3,0,29,0,0,0,2,0,0,0,10,0,86,0,91,0,12,13,15,6,7,9,9,8,9,15,11,15,12,14,15,12,6,7,12,12,11,11,0,0,17,0,31,0,1,0,0,0,0,0,17,0,0,0,6,0,0,0,1,0 +}; + +uint32_t cdimm_rca_1r_1600_mba0[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,93,0,96,0,15,16,15,10,7,7,10,9,11,15,20,16,17,16,16,20,14,13,21,22,21,21,0,0,24,0,27,0,0,0,0,0,2,0,24,0,0,0,9,0,0,0,4,0,90,0,98,0,20,18,21,10,7,7,9,7,15,14,22,15,20,18,16,20,12,11,21,22,25,23,0,0,24,0,30,0,3,0,0,0,2,0,25,0,0,0,4,0,0,0,0,0 +}; + +uint32_t cdimm_rca_1r_1600_mba1[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,91,0,97,0,22,22,21,14,13,14,16,15,19,21,19,22,21,24,22,18,11,13,17,18,22,17,0,0,32,0,39,0,13,0,0,0,3,0,35,0,0,0,3,0,0,0,12,0,90,0,96,0,15,16,18,8,9,10,11,10,11,18,13,18,15,17,18,15,8,8,14,15,13,13,0,0,22,0,38,0,1,0,0,0,0,0,22,0,0,0,7,0,0,0,1,0 +}; + +uint32_t cdimm_rca_2r_1333_mba0[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,95,0,103,0,6,7,7,3,0,0,3,2,4,6,11,8,8,7,7,11,6,6,11,12,11,12,0,0,31,0,24,0,12,0,0,0,14,0,31,0,34,0,19,0,0,0,15,0,90,0,99,0,11,9,12,2,0,0,1,0,7,5,12,6,10,9,7,10,4,4,11,12,15,13,0,0,32,0,27,0,14,0,0,0,14,0,33,0,33,0,15,0,0,0,12,0 +}; + +uint32_t cdimm_rca_2r_1333_mba1[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,90,0,98,0,11,11,10,5,4,5,6,6,9,10,8,11,10,13,11,8,3,4,7,7,11,7,0,0,38,0,34,0,21,0,0,0,14,0,41,0,34,0,13,0,0,0,21,0,91,0,99,0,7,8,10,2,2,4,4,3,5,10,5,10,7,9,10,7,1,2,6,7,5,5,0,0,31,0,36,0,14,0,0,0,13,0,31,0,32,0,19,0,0,0,13,0 +}; + +uint32_t cdimm_rca_2r_1600_mba0[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,100,0,109,0,9,9,9,3,0,0,3,2,4,8,14,10,10,10,9,14,7,6,14,15,14,15,0,0,37,0,29,0,14,0,0,0,16,0,37,0,40,0,23,0,0,0,17,0,95,0,105,0,13,11,14,3,0,0,2,0,8,7,15,8,13,11,9,13,5,4,14,15,18,16,0,0,38,0,32,0,16,0,0,0,16,0,39,0,40,0,18,0,0,0,14,0 +}; + +uint32_t cdimm_rca_2r_1600_mba1[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,95,0,104,0,14,14,13,6,5,6,8,8,11,13,11,14,12,16,14,10,3,5,9,9,13,9,0,0,44,0,40,0,25,0,0,0,16,0,47,0,41,0,15,0,0,0,24,0,96,0,104,0,9,10,12,2,3,4,5,4,5,12,7,12,8,11,12,9,1,2,8,9,7,7,0,0,37,0,42,0,15,0,0,0,15,0,36,0,38,0,21,0,0,0,15,0 +}; + +//Cdimm rc_A DD1.0 +uint32_t cdimm_rca_1r_1333_mba0_DD10[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,57,0,59,0,64,0,0,0,0,0,0,0,0,0,0,0,64,64,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,54,0,60,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,64,0,64,0,0,0,0,0,0,0,0,0,0,0 +}; + +uint32_t cdimm_rca_1r_1333_mba1_DD10[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,55,0,60,0,0,64,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,54,0,59,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,64,0,0,0,0,0,0,0,64,0,0,0 +}; + +uint32_t cdimm_rca_1r_1600_mba0_DD10[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,61,0,64,0,64,0,0,0,0,0,0,0,0,0,0,0,64,64,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,58,0,66,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,64,0,64,0,0,0,0,0,0,0,0,0,0,0 +}; + +uint32_t cdimm_rca_1r_1600_mba1_DD10[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,59,0,65,0,0,64,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,7,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,0,64,58,0,64,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,6,0,64,0,0,0,64,0,0,0,0,0,0,0,64,0,0,0 +}; + +uint32_t cdimm_rca_2r_1333_mba0_DD10[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,71,0,64,0,0,0,0,0,0,0,0,0,0,0,64,64,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,58,0,67,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,64,0,64,0,1,0,1,0,0,0,0,0,0,0 +}; +uint32_t cdimm_rca_2r_1333_mba1_DD10[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,58,0,66,0,0,64,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,6,0,2,0,0,0,0,0,0,0,9,0,2,0,0,0,0,0,0,64,59,0,67,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4,0,64,0,0,0,64,0,0,0,0,0,0,0,64,0,0,0 +}; + +uint32_t cdimm_rca_2r_1600_mba0_DD10[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,68,0,77,0,64,0,0,0,0,0,0,0,0,0,0,0,64,64,0,0,64,0,0,0,0,0,0,0,5,0,0,0,0,0,0,0,0,0,5,0,8,0,0,0,0,0,0,0,63,0,73,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,64,0,64,0,7,0,8,0,0,0,0,0,0,0 +}; + +uint32_t cdimm_rca_2r_1600_mba1_DD10[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,72,0,0,64,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,12,0,8,0,0,0,0,0,0,0,15,0,9,0,0,0,0,0,0,64,64,0,72,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,5,0,10,0,64,0,0,0,64,0,4,0,6,0,0,0,64,0,0,0 +}; + + +//RDIMM A/B Ports MBA0 Glacier +uint32_t rdimm_glacier_1600_r10_mba0[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,70,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,7,9,11,10,4,0,3,5,0,0,4,10,3,12,3,12,0,0,0,0,0,0,0,0,0,0 +}; + +uint32_t rdimm_glacier_1333_r20e_mba0[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,67,0,0,0,1,2,2,4,0,1,3,2,5,2,6,3,3,3,2,7,7,7,6,8,6,7,7,0,2,10,0,0,0,10,2,10,2,9,0,0,0,0,0,0,0,0,0,0,71,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,1,3,0,0,3,7,2,9,1,10,0,0,0,0,0,0,0,0,0,0 +}; + +uint32_t rdimm_glacier_1600_r20e_mba0[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,66,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,75,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,8,9,11,11,4,0,3,5,0,0,4,10,3,12,3,12,0,0,0,0,0,0,0,0,0,0 +}; + +uint32_t rdimm_glacier_1333_r20b_mba0[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,2,2,4,0,1,3,2,5,2,6,3,3,3,2,6,7,7,6,8,6,7,7,0,2,10,0,0,0,10,2,10,2,9,0,0,0,0,0,0,0,0,0,0,68,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,2,4,0,0,4,8,3,10,2,10,0,0,0,0,0,0,0,0,0,0 +}; + +uint32_t rdimm_glacier_1600_r20b_mba0[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,70,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,8,9,11,11,4,0,3,5,0,0,5,10,3,12,3,13,0,0,0,0,0,0,0,0,0,0 +}; +uint32_t rdimm_glacier_1333_r40_mba0[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,4,1,1,4,3,5,2,7,3,4,3,3,7,7,7,7,8,7,8,7,0,3,11,0,0,1,11,3,11,3,10,0,0,0,0,0,0,0,0,0,0,71,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,2,4,0,0,4,8,3,10,3,11,0,0,0,0,0,0,0,0,0,0 +}; + +//RDIMM C/D Ports MBA1 Glacier + +uint32_t rdimm_glacier_1333_r10_mba1[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,12,11,12,11,8,12,13,13,16,12,9,12,11,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,10,10,13,10,11,13,13,12,13,13,9,13,10,12,13,10,10,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0 +}; + +uint32_t rdimm_glacier_1600_r10_mba1[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,15,13,15,14,10,15,16,17,21,15,11,15,13,18,15,9,11,13,8,10,14,7,11,0,10,2,0,0,13,2,12,5,4,2,0,0,0,0,0,0,0,0,0,0,71,0,0,0,12,13,16,13,13,16,16,15,16,17,11,16,12,15,17,12,12,13,11,12,9,10,15,0,4,14,0,0,4,15,4,13,4,12,0,0,0,0,0,0,0,0,0,0 +}; + +uint32_t rdimm_glacier_1333_r20e_mba1[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,0,0,12,11,12,11,8,12,13,13,16,12,9,12,11,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,73,0,0,0,10,10,13,11,11,13,13,12,13,13,9,13,10,12,13,10,10,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0 +}; + +uint32_t rdimm_glacier_1600_r20e_mba1[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,77,0,0,0,15,13,15,14,10,15,16,17,21,15,11,15,13,18,15,9,11,13,8,10,14,7,11,0,9,1,0,0,13,2,12,5,4,1,0,0,0,0,0,0,0,0,0,0,77,0,0,0,12,13,16,13,13,16,16,15,16,17,11,16,13,15,17,12,12,13,11,12,9,10,15,0,4,14,0,0,4,15,4,13,3,11,0,0,0,0,0,0,0,0,0,0 +}; + +uint32_t rdimm_glacier_1333_r20b_mba1[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,12,10,12,11,8,11,13,13,16,12,9,12,10,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,10,10,13,10,10,13,13,12,13,13,8,13,10,12,13,10,9,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0 +}; + +uint32_t rdimm_glacier_1600_r20b_mba1[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,14,13,15,14,10,14,16,17,21,15,11,15,13,17,15,9,11,13,8,10,14,7,11,0,10,1,0,0,13,2,12,5,4,1,0,0,0,0,0,0,0,0,0,0,71,0,0,0,12,13,16,13,13,16,16,15,16,16,10,16,12,15,17,12,12,12,11,12,9,9,15,0,4,14,0,0,4,15,4,13,4,12,0,0,0,0,0,0,0,0,0,0 +}; + +uint32_t rdimm_glacier_1066_r40_mba1[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,10,9,10,9,7,10,11,11,14,10,7,10,9,12,10,6,7,8,5,7,9,5,7,0,7,1,0,0,9,1,8,3,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,8,8,11,8,9,10,11,10,11,11,7,11,8,10,11,8,8,8,7,8,6,6,10,0,3,10,0,0,3,10,3,9,2,8,0,0,0,0,0,0,0,0,0,0 +}; + +uint32_t rdimm_glacier_1333_r11_mba1[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,69,0,18,17,18,17,14,18,19,19,22,18,15,18,17,20,18,13,15,16,13,14,17,12,15,0,11,5,0,0,14,5,13,7,7,5,11,2,0,0,3,3,5,3,8,2,73,0,69,0,16,16,19,16,17,19,19,18,19,19,15,19,16,18,19,16,16,16,15,16,14,14,18,0,7,15,0,0,7,15,7,14,6,13,4,12,0,0,9,14,9,11,4,11 +}; + +uint32_t rdimm_glacier_1600_r11_mba1[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,76,0,71,0,21,20,22,20,17,21,23,23,27,22,18,22,20,24,21,15,18,20,15,17,20,14,18,0,14,6,0,0,17,6,17,10,9,6,13,2,0,0,4,3,5,3,10,3,76,0,71,0,19,20,23,20,20,23,23,22,23,23,17,23,19,22,23,19,19,19,18,19,16,16,22,0,9,19,0,0,9,20,9,18,8,16,4,15,0,0,11,17,10,13,5,13 +}; + +uint32_t rdimm_glacier_1333_r22e_mba1[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,77,0,72,0,17,16,18,17,14,17,18,19,22,18,15,18,16,19,17,13,14,16,12,14,17,11,14,0,12,5,0,0,14,5,14,8,7,5,11,2,0,0,3,3,5,3,8,2,77,0,72,0,16,16,19,16,16,18,19,18,19,19,14,18,16,18,19,16,15,16,15,16,13,13,18,0,8,15,0,0,8,16,8,15,7,13,4,12,0,0,9,14,9,11,4,11 +}; + +uint32_t rdimm_glacier_1600_r22e_mba1[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,81,0,77,0,21,19,21,20,16,21,22,23,27,22,17,21,19,23,21,15,17,19,14,16,20,13,17,0,13,5,0,0,16,5,15,8,7,5,13,2,0,0,4,3,5,3,10,2,81,0,77,0,19,19,23,19,19,22,23,21,23,23,17,22,19,21,23,19,18,19,18,19,16,16,22,0,7,17,0,0,8,18,8,16,7,15,4,15,0,0,11,17,10,13,5,13 +}; + +uint32_t rdimm_glacier_1333_r22b_mba1[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,69,0,16,14,16,15,12,16,17,17,21,16,12,16,14,18,16,10,12,14,10,12,15,9,12,0,12,6,0,0,15,6,14,8,8,6,11,2,0,0,3,3,5,3,8,2,73,0,69,0,14,14,17,14,14,17,17,16,17,17,12,17,14,16,17,13,13,14,13,14,11,11,16,0,8,16,0,0,8,17,8,15,7,14,4,12,0,0,9,14,9,11,4,10 +}; + +uint32_t rdimm_glacier_1600_r22b_mba1[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,78,0,71,0,20,18,20,19,15,20,21,22,26,21,16,21,18,23,20,14,16,18,13,15,19,12,16,0,16,8,0,0,20,8,19,12,11,8,14,2,0,0,4,3,6,3,10,3,78,0,71,0,17,18,22,18,18,21,22,20,22,22,15,21,17,20,22,17,17,17,16,17,14,14,21,0,11,21,0,0,11,22,11,20,10,18,4,15,0,0,11,17,11,13,5,13 +}; + +uint32_t rdimm_glacier_1066_r44_mba1[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,0x20,0x20,0x20,0x20,0x80,0x80,0x80,0x80,0x20,0x20,0x20,0x20,0x80,0x80,0x80,0x80,0xA0,0x20,0x60,0x20,0xA0,0x80,0x90,0x80,0xA0,0x20,0x60,0x20,0xA0,0x80,0x90,0x80,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,74,0,68,0,15,14,15,14,12,15,16,16,19,15,12,15,14,17,15,11,12,14,10,12,14,9,12,0,12,7,0,0,15,7,14,9,9,7,9,1,0,0,3,2,4,3,7,2,74,0,68,0,13,14,16,14,14,16,16,15,16,16,12,16,13,15,16,13,13,13,12,13,11,11,15,0,9,15,0,0,9,16,9,15,8,14,3,10,0,0,8,12,7,9,3,9 +}; + + + +//Base Array Which Is Used For Looper To Setup Data +uint32_t base_var_array[200]; extern "C" { @@ -196,28 +530,25 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS; const char * const PROCEDURE_NAME = "mss_eff_config_termination"; FAPI_INF("*** Running %s on %s ... ***", PROCEDURE_NAME, i_target_mba.toEcmdString()); - - - // Define attribute array size - const uint8_t DIMM_SIZE = 2; - const uint8_t RANK_SIZE = 4; - - // Fetch dependent attributes uint8_t l_target_mba_pos = 0; uint32_t l_mss_freq = 0; uint32_t l_mss_volt = 0; + uint8_t l_nwell_misplacement = 0; uint8_t l_num_ranks_per_dimm_u8array[PORT_SIZE][DIMM_SIZE]; // ATTR_EFF_DRAM_GEN: EMPTY = 0, DDR3 = 1, DDR4 = 2, uint8_t l_dram_gen_u8; // ATTR_EFF_DIMM_TYPE: CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3, uint8_t l_dimm_type_u8; + uint8_t l_dimm_custom_u8; uint8_t l_num_drops_per_port; + uint8_t l_dram_width_u8; rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_target_mba_pos); fapi::Target l_target_centaur; rc = fapiGetParentChip(i_target_mba, l_target_centaur); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_mss_freq); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_mss_volt); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_MSS_NWELL_MISPLACEMENT, &l_target_centaur, l_nwell_misplacement); if(rc) return rc; if (l_mss_freq <= 0) { FAPI_ERR("Invalid ATTR_MSS_FREQ = %d on %s!", l_mss_freq, i_target_mba.toEcmdString()); FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; @@ -225,7 +556,9 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm_u8array); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target_mba, l_dram_gen_u8); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, l_dimm_type_u8); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, l_dimm_custom_u8); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba, l_num_drops_per_port); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width_u8); if(rc) return rc; // Fetch impacted attributes @@ -239,469 +572,561 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { // Define local attribute variables uint8_t l_attr_mss_cal_step_enable = 0xFF; + + + //Now, Determine The Type Of Dimm We Are Using + //l_target_mba_pos == 0,1 - MBA POS + //l_num_drops_per_port == drops / port + //if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM ) + //if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) + if(l_attr_is_simulation != 0) { + FAPI_INF("In Sim Detected %s on %s value is %d", PROCEDURE_NAME, i_target_mba.toEcmdString(), l_attr_is_simulation); + if((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM) || (l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) ){ + memcpy(base_var_array,cdimm_rca_1r_1600_mba1,200*sizeof(uint32_t)); + + } + else if(l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM){ + memcpy(base_var_array,rdimm_glacier_1600_r22e_mba1,200*sizeof(uint32_t)); + + } + else{ + FAPI_ERR("Invalid Dimm SIM This Should Never Happen!\n"); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + + } + + + } + else if( (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM) ){ + if((l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM) ){ + //This is a CDIMM! + if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ + //1R Cdimm + if ( l_mss_freq <= 1466 ) { // 1333Mbps + if((l_target_mba_pos == 0) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_FALSE)){ + memcpy(base_var_array,cdimm_rca_1r_1333_mba0,200*sizeof(uint32_t)); + FAPI_INF("CDIMM rca_1r_1333 MBA0\n"); + } + else if ((l_target_mba_pos == 0) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_TRUE)){ + //memcpy(base_var_array,cdimm_rca_1r_1333_mba0_DD10,200*sizeof(uint32_t)); //PAULS SETTINGS + memcpy(base_var_array,cdimm_rca_1r_1333_mba0,200*sizeof(uint32_t)); + FAPI_INF("CDIMM rca_1r_1333 MBA0 DD10\n"); + + } + else if ((l_target_mba_pos == 1) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_FALSE)){ + memcpy(base_var_array,cdimm_rca_1r_1333_mba1,200*sizeof(uint32_t)); + FAPI_INF("CDIMM rca_1r_1333 MBA1\n"); + + } + else if ((l_target_mba_pos == 1) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_TRUE)){ + //memcpy(base_var_array,cdimm_rca_1r_1333_mba1_DD10,200*sizeof(uint32_t)); //PAULS SETTINGS + memcpy(base_var_array,cdimm_rca_1r_1333_mba1,200*sizeof(uint32_t)); + FAPI_INF("CDIMM rca_1r_1333 MBA1 DD10\n"); + + } + else{ + FAPI_ERR("Invalid Dimm Type CDIMM FREQ %d\n",l_mss_freq); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + } else if ( l_mss_freq <= 1733 ) { // 1600Mbps + if((l_target_mba_pos == 0) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_FALSE)){ + memcpy(base_var_array,cdimm_rca_1r_1600_mba0,200*sizeof(uint32_t)); + FAPI_INF("CDIMM rca_1r_1600 MBA0\n"); + } + else if ((l_target_mba_pos == 0) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_TRUE)){ + //memcpy(base_var_array,cdimm_rca_1r_1600_mba0_DD10,200*sizeof(uint32_t)); //PAULS SETTINGS + memcpy(base_var_array,cdimm_rca_1r_1600_mba0,200*sizeof(uint32_t)); + FAPI_INF("CDIMM rca_1r_1600 MBA0 DD10\n"); + + } + else if ((l_target_mba_pos == 1) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_FALSE)){ + memcpy(base_var_array,cdimm_rca_1r_1600_mba1,200*sizeof(uint32_t)); + FAPI_INF("CDIMM rca_1r_1600 MBA1\n"); + + } + else if ((l_target_mba_pos == 1) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_TRUE)){ + //memcpy(base_var_array,cdimm_rca_1r_1600_mba1_DD10,200*sizeof(uint32_t)); //PAULS SETTINGS + memcpy(base_var_array,cdimm_rca_1r_1600_mba1,200*sizeof(uint32_t)); + FAPI_INF("CDIMM rca_1r_1600 MBA1 DD10\n"); + + } + else{ + FAPI_ERR("Invalid Dimm Type CDIMM FREQ %d\n",l_mss_freq); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + + }//1600 1R + + }//1R CDIMM + else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){ + //2R Cdimm + if ( l_mss_freq <= 1466 ) { // 1333Mbps + if((l_target_mba_pos == 0) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_FALSE)){ + memcpy(base_var_array,cdimm_rca_2r_1333_mba0,200*sizeof(uint32_t)); + FAPI_INF("CDIMM rca_2r_1333 MBA0\n"); + } + else if ((l_target_mba_pos == 0) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_TRUE)){ + //memcpy(base_var_array,cdimm_rca_2r_1333_mba0_DD10,200*sizeof(uint32_t)); //PAULS SETTINGS + memcpy(base_var_array,cdimm_rca_2r_1333_mba0,200*sizeof(uint32_t)); + FAPI_INF("CDIMM rca_2r_1333 MBA0 DD10\n"); + + } + else if ((l_target_mba_pos == 1) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_FALSE)){ + memcpy(base_var_array,cdimm_rca_2r_1333_mba1,200*sizeof(uint32_t)); + FAPI_INF("CDIMM rca_2r_1333 MBA1\n"); + + } + else if ((l_target_mba_pos == 1) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_TRUE)){ + //memcpy(base_var_array,cdimm_rca_2r_1333_mba1_DD10,200*sizeof(uint32_t)); //PAULS SETTINGS + memcpy(base_var_array,cdimm_rca_2r_1333_mba1,200*sizeof(uint32_t)); + FAPI_INF("CDIMM rca_2r_1333 MBA1 DD10\n"); + + } + else{ + FAPI_ERR("Invalid Dimm Type CDIMM FREQ %d\n",l_mss_freq); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + } else if ( l_mss_freq <= 1733 ) { // 1600Mbps + if((l_target_mba_pos == 0) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_FALSE)){ + memcpy(base_var_array,cdimm_rca_2r_1600_mba0,200*sizeof(uint32_t)); + FAPI_INF("CDIMM rca_2r_1600 MBA0\n"); + } + else if ((l_target_mba_pos == 0) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_TRUE)){ + //memcpy(base_var_array,cdimm_rca_2r_1600_mba0_DD10,200*sizeof(uint32_t)); //PAULS SETTINGS + memcpy(base_var_array,cdimm_rca_2r_1600_mba0,200*sizeof(uint32_t)); + FAPI_INF("CDIMM rca_2r_1600 MBA0 DD10\n"); + + } + else if ((l_target_mba_pos == 1) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_FALSE)){ + memcpy(base_var_array,cdimm_rca_2r_1600_mba1,200*sizeof(uint32_t)); + FAPI_INF("CDIMM rca_2r_1600 MBA1\n"); + + } + else if ((l_target_mba_pos == 1) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_TRUE)){ + //memcpy(base_var_array,cdimm_rca_1r_1600_mba1_DD10,200*sizeof(uint32_t)); //PAULS SETTINGS + memcpy(base_var_array,cdimm_rca_2r_1600_mba1,200*sizeof(uint32_t)); + FAPI_INF("CDIMM rca_2r_1600 MBA1 DD10\n"); - uint32_t l_attr_eff_dimm_rcd_ibt[PORT_SIZE][DIMM_SIZE]; - l_attr_eff_dimm_rcd_ibt[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF; - l_attr_eff_dimm_rcd_ibt[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF; - l_attr_eff_dimm_rcd_ibt[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF; - l_attr_eff_dimm_rcd_ibt[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF; - uint8_t l_attr_eff_dimm_rcd_mirror_mode[PORT_SIZE][DIMM_SIZE]; - l_attr_eff_dimm_rcd_mirror_mode[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF; - l_attr_eff_dimm_rcd_mirror_mode[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF; - l_attr_eff_dimm_rcd_mirror_mode[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF; - l_attr_eff_dimm_rcd_mirror_mode[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF; - - uint32_t l_attr_eff_cen_rd_vref[PORT_SIZE]; - l_attr_eff_cen_rd_vref[0] = fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000; - l_attr_eff_cen_rd_vref[1] = fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000; - uint32_t l_attr_eff_dram_wr_vref[PORT_SIZE]; - l_attr_eff_dram_wr_vref[0] = fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500; - l_attr_eff_dram_wr_vref[1] = fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500; - - uint8_t l_attr_eff_cen_rcv_imp_dq_dqs[PORT_SIZE]; - l_attr_eff_cen_rcv_imp_dq_dqs[0] = fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60; - l_attr_eff_cen_rcv_imp_dq_dqs[1] = fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60; - uint8_t l_attr_eff_cen_drv_imp_dq_dqs[PORT_SIZE]; - l_attr_eff_cen_drv_imp_dq_dqs[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0; - l_attr_eff_cen_drv_imp_dq_dqs[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0; - uint8_t l_attr_eff_cen_drv_imp_cntl[PORT_SIZE]; - l_attr_eff_cen_drv_imp_cntl[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30; - l_attr_eff_cen_drv_imp_cntl[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30; - uint8_t l_attr_eff_cen_drv_imp_addr[PORT_SIZE]; - l_attr_eff_cen_drv_imp_addr[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30; - l_attr_eff_cen_drv_imp_addr[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30; - uint8_t l_attr_eff_cen_drv_imp_clk[PORT_SIZE]; - l_attr_eff_cen_drv_imp_clk[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30; - l_attr_eff_cen_drv_imp_clk[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30; - uint8_t l_attr_eff_cen_drv_imp_spcke[PORT_SIZE]; - l_attr_eff_cen_drv_imp_spcke[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40; - l_attr_eff_cen_drv_imp_spcke[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40; - - uint8_t l_attr_eff_cen_slew_rate_dq_dqs[PORT_SIZE]; - l_attr_eff_cen_slew_rate_dq_dqs[0] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS; - l_attr_eff_cen_slew_rate_dq_dqs[1] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS; - uint8_t l_attr_eff_cen_slew_rate_cntl[PORT_SIZE]; - l_attr_eff_cen_slew_rate_cntl[0] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS; - l_attr_eff_cen_slew_rate_cntl[1] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS; - uint8_t l_attr_eff_cen_slew_rate_addr[PORT_SIZE]; - l_attr_eff_cen_slew_rate_addr[0] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS; - l_attr_eff_cen_slew_rate_addr[1] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS; - uint8_t l_attr_eff_cen_slew_rate_clk[PORT_SIZE]; - l_attr_eff_cen_slew_rate_clk[0] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS; - l_attr_eff_cen_slew_rate_clk[1] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS; - uint8_t l_attr_eff_cen_slew_rate_spcke[PORT_SIZE]; - l_attr_eff_cen_slew_rate_spcke[0] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS; - l_attr_eff_cen_slew_rate_spcke[1] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS; - - uint8_t l_attr_eff_dram_ron[PORT_SIZE][DIMM_SIZE]; - l_attr_eff_dram_ron[0][0] = fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34; - l_attr_eff_dram_ron[0][1] = fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34; - l_attr_eff_dram_ron[1][0] = fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34; - l_attr_eff_dram_ron[1][1] = fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34; - uint8_t l_attr_eff_dram_rtt_nom[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; - l_attr_eff_dram_rtt_nom[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE; - l_attr_eff_dram_rtt_nom[0][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE; - l_attr_eff_dram_rtt_nom[0][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE; - l_attr_eff_dram_rtt_nom[0][0][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE; - l_attr_eff_dram_rtt_nom[0][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE; - l_attr_eff_dram_rtt_nom[0][1][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE; - l_attr_eff_dram_rtt_nom[0][1][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE; - l_attr_eff_dram_rtt_nom[0][1][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE; - l_attr_eff_dram_rtt_nom[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE; - l_attr_eff_dram_rtt_nom[1][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE; - l_attr_eff_dram_rtt_nom[1][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE; - l_attr_eff_dram_rtt_nom[1][0][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE; - l_attr_eff_dram_rtt_nom[1][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE; - l_attr_eff_dram_rtt_nom[1][1][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE; - l_attr_eff_dram_rtt_nom[1][1][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE; - l_attr_eff_dram_rtt_nom[1][1][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE; - uint8_t l_attr_eff_dram_rtt_wr[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; - l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE; - l_attr_eff_dram_rtt_wr[0][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE; - l_attr_eff_dram_rtt_wr[0][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE; - l_attr_eff_dram_rtt_wr[0][0][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE; - l_attr_eff_dram_rtt_wr[0][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE; - l_attr_eff_dram_rtt_wr[0][1][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE; - l_attr_eff_dram_rtt_wr[0][1][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE; - l_attr_eff_dram_rtt_wr[0][1][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE; - l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE; - l_attr_eff_dram_rtt_wr[1][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE; - l_attr_eff_dram_rtt_wr[1][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE; - l_attr_eff_dram_rtt_wr[1][0][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE; - l_attr_eff_dram_rtt_wr[1][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE; - l_attr_eff_dram_rtt_wr[1][1][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE; - l_attr_eff_dram_rtt_wr[1][1][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE; - l_attr_eff_dram_rtt_wr[1][1][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE; - - uint8_t l_attr_eff_odt_rd[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; - l_attr_eff_odt_rd[0][0][0] = 0x0; - l_attr_eff_odt_rd[0][0][1] = 0x0; - l_attr_eff_odt_rd[0][0][2] = 0x0; - l_attr_eff_odt_rd[0][0][3] = 0x0; - l_attr_eff_odt_rd[0][1][0] = 0x0; - l_attr_eff_odt_rd[0][1][1] = 0x0; - l_attr_eff_odt_rd[0][1][2] = 0x0; - l_attr_eff_odt_rd[0][1][3] = 0x0; - l_attr_eff_odt_rd[1][0][0] = 0x0; - l_attr_eff_odt_rd[1][0][1] = 0x0; - l_attr_eff_odt_rd[1][0][2] = 0x0; - l_attr_eff_odt_rd[1][0][3] = 0x0; - l_attr_eff_odt_rd[1][1][0] = 0x0; - l_attr_eff_odt_rd[1][1][1] = 0x0; - l_attr_eff_odt_rd[1][1][2] = 0x0; - l_attr_eff_odt_rd[1][1][3] = 0x0; - uint8_t l_attr_eff_odt_wr[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; - l_attr_eff_odt_wr[0][0][0] = 0x0; - l_attr_eff_odt_wr[0][0][1] = 0x0; - l_attr_eff_odt_wr[0][0][2] = 0x0; - l_attr_eff_odt_wr[0][0][3] = 0x0; - l_attr_eff_odt_wr[0][1][0] = 0x0; - l_attr_eff_odt_wr[0][1][1] = 0x0; - l_attr_eff_odt_wr[0][1][2] = 0x0; - l_attr_eff_odt_wr[0][1][3] = 0x0; - l_attr_eff_odt_wr[1][0][0] = 0x0; - l_attr_eff_odt_wr[1][0][1] = 0x0; - l_attr_eff_odt_wr[1][0][2] = 0x0; - l_attr_eff_odt_wr[1][0][3] = 0x0; - l_attr_eff_odt_wr[1][1][0] = 0x0; - l_attr_eff_odt_wr[1][1][1] = 0x0; - l_attr_eff_odt_wr[1][1][2] = 0x0; - l_attr_eff_odt_wr[1][1][3] = 0x0; - - - if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) { - // IMP - l_attr_eff_cen_drv_imp_dq_dqs[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0; - l_attr_eff_cen_drv_imp_dq_dqs[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0; - l_attr_eff_cen_drv_imp_cntl[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30; - l_attr_eff_cen_drv_imp_cntl[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30; - l_attr_eff_cen_drv_imp_addr[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30; - l_attr_eff_cen_drv_imp_addr[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30; - l_attr_eff_cen_drv_imp_clk[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30; - l_attr_eff_cen_drv_imp_clk[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30; - // SLEW - l_attr_eff_cen_slew_rate_cntl[0] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS; - l_attr_eff_cen_slew_rate_cntl[1] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS; - l_attr_eff_cen_slew_rate_addr[0] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS; - l_attr_eff_cen_slew_rate_addr[1] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS; - l_attr_eff_cen_slew_rate_clk[0] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS; - l_attr_eff_cen_slew_rate_clk[1] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS; - // RTT and ODT - l_attr_eff_dram_rtt_nom[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40; - l_attr_eff_dram_rtt_nom[0][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40; - l_attr_eff_dram_rtt_nom[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40; - l_attr_eff_dram_rtt_nom[1][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40; - l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[0][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_odt_wr[0][0][0] = 0x80; - l_attr_eff_odt_wr[1][0][0] = 0x80; - } else if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM ) { - // IMP - l_attr_eff_cen_drv_imp_dq_dqs[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0; - l_attr_eff_cen_drv_imp_dq_dqs[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0; - l_attr_eff_cen_drv_imp_cntl[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40; - l_attr_eff_cen_drv_imp_cntl[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40; - l_attr_eff_cen_drv_imp_addr[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40; - l_attr_eff_cen_drv_imp_addr[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40; - l_attr_eff_cen_drv_imp_clk[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40; - l_attr_eff_cen_drv_imp_clk[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40; - // SLEW - l_attr_eff_cen_slew_rate_cntl[0] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS; - l_attr_eff_cen_slew_rate_cntl[1] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS; - l_attr_eff_cen_slew_rate_addr[0] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS; - l_attr_eff_cen_slew_rate_addr[1] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS; - l_attr_eff_cen_slew_rate_clk[0] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS; - l_attr_eff_cen_slew_rate_clk[1] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS; - // Check DPHY01 or DHPY23 - if ( l_target_mba_pos == 0 ) { - if ( l_num_ranks_per_dimm_u8array[0][0] == 4 ) { - // RCD TERM - l_attr_eff_dimm_rcd_ibt[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100; - l_attr_eff_dimm_rcd_ibt[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100; - l_attr_eff_dimm_rcd_mirror_mode[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - l_attr_eff_dimm_rcd_mirror_mode[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - // RTT and ODT - l_attr_eff_dram_rtt_nom[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30; - l_attr_eff_dram_rtt_nom[0][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30; - l_attr_eff_dram_rtt_nom[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30; - l_attr_eff_dram_rtt_nom[1][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30; - l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[0][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[0][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[0][0][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][0][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_odt_rd[0][0][0] = 0x40; - l_attr_eff_odt_rd[0][0][1] = 0x40; - l_attr_eff_odt_rd[0][0][2] = 0x80; - l_attr_eff_odt_rd[0][0][3] = 0x80; - l_attr_eff_odt_rd[1][0][0] = 0x40; - l_attr_eff_odt_rd[1][0][1] = 0x40; - l_attr_eff_odt_rd[1][0][2] = 0x80; - l_attr_eff_odt_rd[1][0][3] = 0x80; - l_attr_eff_odt_wr[0][0][0] = 0xC0; - l_attr_eff_odt_wr[0][0][1] = 0x40; - l_attr_eff_odt_wr[0][0][2] = 0xC0; - l_attr_eff_odt_wr[0][0][3] = 0x40; - l_attr_eff_odt_wr[1][0][0] = 0xC0; - l_attr_eff_odt_wr[1][0][1] = 0x40; - l_attr_eff_odt_wr[1][0][2] = 0xC0; - l_attr_eff_odt_wr[1][0][3] = 0x40; - } else if ( l_num_ranks_per_dimm_u8array[0][0] == 2 ) { - // RCD TERM - l_attr_eff_dimm_rcd_ibt[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100; - l_attr_eff_dimm_rcd_ibt[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100; - l_attr_eff_dimm_rcd_mirror_mode[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - l_attr_eff_dimm_rcd_mirror_mode[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - l_attr_eff_dimm_rcd_mirror_mode[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - l_attr_eff_dimm_rcd_mirror_mode[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - // RTT and ODT - l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60; - l_attr_eff_dram_rtt_wr[0][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60; - l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60; - l_attr_eff_dram_rtt_wr[1][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60; - l_attr_eff_odt_wr[0][0][0] = 0x80; - l_attr_eff_odt_wr[0][0][1] = 0x40; - l_attr_eff_odt_wr[1][0][0] = 0x80; - l_attr_eff_odt_wr[1][0][1] = 0x40; - } else if ( l_num_ranks_per_dimm_u8array[0][0] == 1 ) { - // RCD TERM - l_attr_eff_dimm_rcd_ibt[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100; - l_attr_eff_dimm_rcd_ibt[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100; - l_attr_eff_dimm_rcd_mirror_mode[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - l_attr_eff_dimm_rcd_mirror_mode[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - l_attr_eff_dimm_rcd_mirror_mode[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - l_attr_eff_dimm_rcd_mirror_mode[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - // RTT and ODT - l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60; - l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60; - l_attr_eff_odt_wr[0][0][0] = 0x80; - l_attr_eff_odt_wr[1][0][0] = 0x80; + } + else{ + FAPI_ERR("Invalid Dimm Type CDIMM FREQ %d\n",l_mss_freq); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + + }//1600 2R + }//2R CDIMM + else{ + FAPI_ERR("Invalid Dimm Type CDIMM FREQ %d\n",l_mss_freq); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; } - } else if ( l_target_mba_pos == 1 ) { - // Check SINGLE or DUAL Drop - if ( l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE ) { - if ( l_num_ranks_per_dimm_u8array[0][0] == 4 ) { - // RCD TERM - l_attr_eff_dimm_rcd_ibt[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100; - l_attr_eff_dimm_rcd_ibt[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100; - l_attr_eff_dimm_rcd_mirror_mode[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - l_attr_eff_dimm_rcd_mirror_mode[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - // RTT and ODT - l_attr_eff_dram_rtt_nom[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30; - l_attr_eff_dram_rtt_nom[0][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30; - l_attr_eff_dram_rtt_nom[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30; - l_attr_eff_dram_rtt_nom[1][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30; - l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[0][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[0][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[0][0][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][0][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_odt_rd[0][0][0] = 0x40; - l_attr_eff_odt_rd[0][0][1] = 0x40; - l_attr_eff_odt_rd[0][0][2] = 0x80; - l_attr_eff_odt_rd[0][0][3] = 0x80; - l_attr_eff_odt_rd[1][0][0] = 0x40; - l_attr_eff_odt_rd[1][0][1] = 0x40; - l_attr_eff_odt_rd[1][0][2] = 0x80; - l_attr_eff_odt_rd[1][0][3] = 0x80; - l_attr_eff_odt_wr[0][0][0] = 0xC0; - l_attr_eff_odt_wr[0][0][1] = 0x40; - l_attr_eff_odt_wr[0][0][2] = 0xC0; - l_attr_eff_odt_wr[0][0][3] = 0x40; - l_attr_eff_odt_wr[1][0][0] = 0xC0; - l_attr_eff_odt_wr[1][0][1] = 0x40; - l_attr_eff_odt_wr[1][0][2] = 0xC0; - l_attr_eff_odt_wr[1][0][3] = 0x40; - } else if ( l_num_ranks_per_dimm_u8array[0][0] == 2 ) { - // RCD TERM - l_attr_eff_dimm_rcd_ibt[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100; - l_attr_eff_dimm_rcd_ibt[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100; - l_attr_eff_dimm_rcd_mirror_mode[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - l_attr_eff_dimm_rcd_mirror_mode[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - l_attr_eff_dimm_rcd_mirror_mode[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - l_attr_eff_dimm_rcd_mirror_mode[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - // RTT and ODT - l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40; - l_attr_eff_dram_rtt_wr[0][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40; - l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40; - l_attr_eff_dram_rtt_wr[1][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40; - l_attr_eff_odt_wr[0][0][0] = 0x40; - l_attr_eff_odt_wr[0][0][1] = 0x80; - l_attr_eff_odt_wr[1][0][0] = 0x40; - l_attr_eff_odt_wr[1][0][1] = 0x80; - } else if ( l_num_ranks_per_dimm_u8array[0][0] == 1 ) { - // RCD TERM - l_attr_eff_dimm_rcd_ibt[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100; - l_attr_eff_dimm_rcd_ibt[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100; - l_attr_eff_dimm_rcd_mirror_mode[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - l_attr_eff_dimm_rcd_mirror_mode[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - l_attr_eff_dimm_rcd_mirror_mode[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - l_attr_eff_dimm_rcd_mirror_mode[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - // RTT and ODT - l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60; - l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60; - l_attr_eff_odt_wr[0][0][0] = 0x80; - l_attr_eff_odt_wr[1][0][0] = 0x80; + }//End CDIMM + else{ + //This is a UDIMM! + FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA0\n",l_mss_freq); + FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA1\n",l_mss_freq); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + + + }//End UDIMM + } + else if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM ){ + if( l_target_mba_pos == 0){ + if ( l_mss_freq <= 1466 ) { // 1333Mbps + if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 4)){ + memcpy(base_var_array,rdimm_glacier_1333_r20e_mba0,200*sizeof(uint32_t)); + FAPI_INF("RDIMM r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } - } else if ( l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL ) { - if ( l_num_ranks_per_dimm_u8array[0][0] == 4 ) { - // RCD TERM - l_attr_eff_dimm_rcd_ibt[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200; - l_attr_eff_dimm_rcd_ibt[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200; - l_attr_eff_dimm_rcd_ibt[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200; - l_attr_eff_dimm_rcd_ibt[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200; - l_attr_eff_dimm_rcd_mirror_mode[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF; - l_attr_eff_dimm_rcd_mirror_mode[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF; - l_attr_eff_dimm_rcd_mirror_mode[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF; - l_attr_eff_dimm_rcd_mirror_mode[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF; - // RTT and ODT - l_attr_eff_dram_rtt_nom[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20; - l_attr_eff_dram_rtt_nom[0][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20; - l_attr_eff_dram_rtt_nom[0][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20; - l_attr_eff_dram_rtt_nom[0][1][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20; - l_attr_eff_dram_rtt_nom[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20; - l_attr_eff_dram_rtt_nom[1][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20; - l_attr_eff_dram_rtt_nom[1][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20; - l_attr_eff_dram_rtt_nom[1][1][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20; - l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[0][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[0][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[0][0][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[0][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[0][1][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[0][1][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[0][1][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][0][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][1][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][1][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][1][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_odt_rd[0][0][0] = 0x20; - l_attr_eff_odt_rd[0][0][1] = 0x20; - l_attr_eff_odt_rd[0][0][2] = 0x20; - l_attr_eff_odt_rd[0][0][3] = 0x20; - l_attr_eff_odt_rd[0][1][0] = 0x80; - l_attr_eff_odt_rd[0][1][1] = 0x80; - l_attr_eff_odt_rd[0][1][2] = 0x80; - l_attr_eff_odt_rd[0][1][3] = 0x80; - l_attr_eff_odt_rd[1][0][0] = 0x20; - l_attr_eff_odt_rd[1][0][1] = 0x20; - l_attr_eff_odt_rd[1][0][2] = 0x20; - l_attr_eff_odt_rd[1][0][3] = 0x20; - l_attr_eff_odt_rd[1][1][0] = 0x80; - l_attr_eff_odt_rd[1][1][1] = 0x80; - l_attr_eff_odt_rd[1][1][2] = 0x80; - l_attr_eff_odt_rd[1][1][3] = 0x80; - l_attr_eff_odt_wr[0][0][0] = 0xA0; - l_attr_eff_odt_wr[0][0][1] = 0x20; - l_attr_eff_odt_wr[0][0][2] = 0x60; - l_attr_eff_odt_wr[0][0][3] = 0x20; - l_attr_eff_odt_wr[0][1][0] = 0xA0; - l_attr_eff_odt_wr[0][1][1] = 0x80; - l_attr_eff_odt_wr[0][1][2] = 0x90; - l_attr_eff_odt_wr[0][1][3] = 0x80; - l_attr_eff_odt_wr[1][0][0] = 0xA0; - l_attr_eff_odt_wr[1][0][1] = 0x20; - l_attr_eff_odt_wr[1][0][2] = 0x60; - l_attr_eff_odt_wr[1][0][3] = 0x20; - l_attr_eff_odt_wr[1][1][0] = 0xA0; - l_attr_eff_odt_wr[1][1][1] = 0x80; - l_attr_eff_odt_wr[1][1][2] = 0x90; - l_attr_eff_odt_wr[1][1][3] = 0x80; - } else if ( l_num_ranks_per_dimm_u8array[0][0] == 2 ) { - // RCD TERM - l_attr_eff_dimm_rcd_ibt[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200; - l_attr_eff_dimm_rcd_ibt[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200; - l_attr_eff_dimm_rcd_ibt[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200; - l_attr_eff_dimm_rcd_ibt[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200; - l_attr_eff_dimm_rcd_mirror_mode[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - l_attr_eff_dimm_rcd_mirror_mode[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - l_attr_eff_dimm_rcd_mirror_mode[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - l_attr_eff_dimm_rcd_mirror_mode[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - // RTT and ODT - l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40; - l_attr_eff_dram_rtt_wr[0][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40; - l_attr_eff_dram_rtt_wr[0][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40; - l_attr_eff_dram_rtt_wr[0][1][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40; - l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40; - l_attr_eff_dram_rtt_wr[1][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40; - l_attr_eff_dram_rtt_wr[1][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40; - l_attr_eff_dram_rtt_wr[1][1][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40; - l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[0][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[0][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[0][1][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][1][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_odt_rd[0][0][0] = 0x20; - l_attr_eff_odt_rd[0][0][1] = 0x20; - l_attr_eff_odt_rd[0][1][0] = 0x80; - l_attr_eff_odt_rd[0][1][1] = 0x80; - l_attr_eff_odt_rd[1][0][0] = 0x20; - l_attr_eff_odt_rd[1][0][1] = 0x20; - l_attr_eff_odt_rd[1][1][0] = 0x80; - l_attr_eff_odt_rd[1][1][1] = 0x80; - l_attr_eff_odt_wr[0][0][0] = 0xA0; - l_attr_eff_odt_wr[0][0][1] = 0x60; - l_attr_eff_odt_wr[0][1][0] = 0xA0; - l_attr_eff_odt_wr[0][1][1] = 0x60; - l_attr_eff_odt_wr[1][0][0] = 0xA0; - l_attr_eff_odt_wr[1][0][1] = 0x60; - l_attr_eff_odt_wr[1][1][0] = 0xA0; - l_attr_eff_odt_wr[1][1][1] = 0x60; - } else if ( l_num_ranks_per_dimm_u8array[0][0] == 1 ) { - // RCD TERM - l_attr_eff_dimm_rcd_ibt[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200; - l_attr_eff_dimm_rcd_ibt[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200; - l_attr_eff_dimm_rcd_ibt[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200; - l_attr_eff_dimm_rcd_ibt[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200; - l_attr_eff_dimm_rcd_mirror_mode[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - l_attr_eff_dimm_rcd_mirror_mode[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - l_attr_eff_dimm_rcd_mirror_mode[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - l_attr_eff_dimm_rcd_mirror_mode[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON; - // RTT and ODT - l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30; - l_attr_eff_dram_rtt_wr[0][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30; - l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30; - l_attr_eff_dram_rtt_wr[1][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30; - l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[0][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_dram_rtt_wr[1][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120; - l_attr_eff_odt_rd[0][0][0] = 0x20; - l_attr_eff_odt_rd[0][1][0] = 0x80; - l_attr_eff_odt_rd[1][0][0] = 0x20; - l_attr_eff_odt_rd[1][1][0] = 0x80; - l_attr_eff_odt_wr[0][0][0] = 0xA0; - l_attr_eff_odt_wr[0][1][0] = 0xA0; - l_attr_eff_odt_wr[1][0][0] = 0xA0; - l_attr_eff_odt_wr[1][1][0] = 0xA0; + else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 8)){ + memcpy(base_var_array,rdimm_glacier_1333_r20b_mba0,200*sizeof(uint32_t)); + FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } - } - } else { - FAPI_ERR("Invalid MBA on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } - } else { - FAPI_ERR("Currently unsupported DIMM_TYPE on %s!", i_target_mba.toEcmdString()); + else if((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 8)){ + memcpy(base_var_array,rdimm_glacier_1333_r40_mba0,200*sizeof(uint32_t)); + FAPI_INF("RDIMM r40 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else{ + FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d MBA0\n",l_mss_freq); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + + } else if ( l_mss_freq <= 1733 ) { // 1600Mbps + if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 8)){ + memcpy(base_var_array,rdimm_glacier_1600_r10_mba0,200*sizeof(uint32_t)); + FAPI_INF("RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 4)){ + memcpy(base_var_array,rdimm_glacier_1600_r20e_mba0,200*sizeof(uint32_t)); + FAPI_INF("RDIMM r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 8)){ + memcpy(base_var_array,rdimm_glacier_1600_r20b_mba0,200*sizeof(uint32_t)); + FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else{ + FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d MBA0\n",l_mss_freq); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + }//1600 + }//MBA0 + else{ + if ( l_mss_freq <= 1200 ) { // 1066Mbps + if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 4)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 4)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){ + memcpy(base_var_array,rdimm_glacier_1066_r44_mba1,200*sizeof(uint32_t)); + FAPI_INF("RDIMM r44 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ + memcpy(base_var_array,rdimm_glacier_1066_r40_mba1,200*sizeof(uint32_t)); + FAPI_INF("RDIMM r44 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else{ + FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d MBA1\n",l_mss_freq); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + + } else if ( l_mss_freq <= 1466 ) { // 1333Mbps + if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ + memcpy(base_var_array,rdimm_glacier_1333_r10_mba1,200*sizeof(uint32_t)); + FAPI_INF("RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){ + memcpy(base_var_array,rdimm_glacier_1333_r11_mba1,200*sizeof(uint32_t)); + FAPI_INF("RDIMM r11 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 4)){ + memcpy(base_var_array,rdimm_glacier_1333_r20e_mba1,200*sizeof(uint32_t)); + FAPI_INF("RDIMM r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 8)){ + memcpy(base_var_array,rdimm_glacier_1333_r20b_mba1,200*sizeof(uint32_t)); + FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 4)){ + memcpy(base_var_array,rdimm_glacier_1333_r22e_mba1,200*sizeof(uint32_t)); + FAPI_INF("RDIMM r22e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 8)){ + memcpy(base_var_array,rdimm_glacier_1333_r22b_mba1,200*sizeof(uint32_t)); + FAPI_INF("RDIMM r22b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else{ + FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d HERE MBA1\n",l_mss_freq); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + } else if ( l_mss_freq <= 1733 ) { // 1600Mbps + + if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ + memcpy(base_var_array,rdimm_glacier_1600_r10_mba1,200*sizeof(uint32_t)); + FAPI_INF("RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){ + memcpy(base_var_array,rdimm_glacier_1600_r11_mba1,200*sizeof(uint32_t)); + FAPI_INF("RDIMM r11 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 4)){ + memcpy(base_var_array,rdimm_glacier_1600_r20e_mba1,200*sizeof(uint32_t)); + FAPI_INF("RDIMM r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 8)){ + memcpy(base_var_array,rdimm_glacier_1600_r20b_mba1,200*sizeof(uint32_t)); + FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 4)){ + memcpy(base_var_array,rdimm_glacier_1600_r22e_mba1,200*sizeof(uint32_t)); + FAPI_INF("RDIMM r22e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 8)){ + memcpy(base_var_array,rdimm_glacier_1600_r22b_mba1,200*sizeof(uint32_t)); + FAPI_INF("RDIMM r22b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else{ + FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d MBA1\n",l_mss_freq); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + }//1600 + }//MBA1 + }//End RDIMM + else if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ){ + FAPI_ERR("Invalid Dimm Type LRDIMM FREQ %d MBA0\n",l_mss_freq); + FAPI_ERR("Invalid Dimm Type LRDIMM FREQ %d MBA1\n",l_mss_freq); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + + } + else{ + FAPI_ERR("Invalid Dimm Type"); FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; } + //SIM Mode + if(l_attr_is_simulation != 0) { + FAPI_INF("In Sim Detected %s on %s value is %d", PROCEDURE_NAME, i_target_mba.toEcmdString(), l_attr_is_simulation); + for( int l_array_offset = 102; l_array_offset < 198;l_array_offset++){ + if( (l_array_offset == 102) || + (l_array_offset == 103) || + (l_array_offset == 104) || + (l_array_offset == 105) || + (l_array_offset == 150) || + (l_array_offset == 151) || + (l_array_offset == 152) || + (l_array_offset == 153) ) + { + base_var_array[l_array_offset] = 0x40; + }//end if + else{ + base_var_array[l_array_offset] = 0x00; + }//end else + + + }//end for + + }//end if + + //DD1.0 N_WELL WORKAROUND + // Check for Centaur EC10 ADR Centerlane NWELL LVS issue PR=0x7F workaround. + if ( l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_TRUE && (l_attr_is_simulation == 0) ) { + for( int l_array_offset = 102; l_array_offset < 198;l_array_offset++){ + if ((((l_target_mba_pos == 0) && (l_array_offset == 118)) || // MA_CMD_A<12> + ((l_target_mba_pos == 0) && (l_array_offset == 106)) || // MA_CMS_A<0> + ((l_target_mba_pos == 0) && (l_array_offset == 119)) || // MA_CMD_A<13> + ((l_target_mba_pos == 0) && (l_array_offset == 122)) || // MA_CMD_BA<0> + ((l_target_mba_pos == 0) && (l_array_offset == 184)) || // MB0_CNTL_CSN<2> + ((l_target_mba_pos == 0) && (l_array_offset == 186)) || // MB0_CNTL_ODT<0> + ((l_target_mba_pos == 0) && (l_array_offset == 165)) || // MB_CMD_A<11> + ((l_target_mba_pos == 0) && (l_array_offset == 178)) || // MB0_CNTL_CKE<0> + ((l_target_mba_pos == 1) && (l_array_offset == 107)) || // MC_CMD_A<1> + ((l_target_mba_pos == 1) && (l_array_offset == 112)) || // MC_CMD_A<6> + ((l_target_mba_pos == 1) && (l_array_offset == 128)) || // MC_CMD_PAR + ((l_target_mba_pos == 1) && (l_array_offset == 149)) || // MC1_CNTL_ODT<1> + ((l_target_mba_pos == 1) && (l_array_offset == 182)) || // MD0_CNTL_CSN<0> + ((l_target_mba_pos == 1) && (l_array_offset == 164)) || // MD_CMD_A<10> + ((l_target_mba_pos == 1) && (l_array_offset == 194)) || // MD1_CNTL_CSN<2> + ((l_target_mba_pos == 1) && (l_array_offset == 186))) && // MD0_CNTL_ODT<0> + (l_attr_is_simulation == 0)) { + FAPI_INF("WARNING: Centaur EC10 ADR Centerlane PR=0x7F workaround for NWELL LVS issue on CmdLaneIndex %d MBA %s!", l_array_offset, i_target_mba.toEcmdString()); + base_var_array[l_array_offset] = 0x7F; + } else { + if (((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM) && (l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM)) { + if ((base_var_array[l_array_offset] - 32) > base_var_array[l_array_offset] ) { + base_var_array[l_array_offset] = 0; + } else { + FAPI_INF("OFFSET %d Value %d Value-32 %d\n",l_array_offset,base_var_array[l_array_offset],base_var_array[l_array_offset]-32); + base_var_array[l_array_offset] = base_var_array[l_array_offset] - 32; + + } + }//End IS CDIMM + }//END ELSE + + }//END FOR + }//END IF DD1.0 + + + + + + // Now Set All The Attributes + uint8_t i = 0; + attr_eff_dimm_rcd_ibt[0][0] = base_var_array[i++]; + attr_eff_dimm_rcd_ibt[0][1] = base_var_array[i++]; + attr_eff_dimm_rcd_ibt[1][0] = base_var_array[i++]; + attr_eff_dimm_rcd_ibt[1][1] = base_var_array[i++]; + attr_eff_dimm_rcd_mirror_mode[0][0] = base_var_array[i++]; + attr_eff_dimm_rcd_mirror_mode[0][1] = base_var_array[i++]; + attr_eff_dimm_rcd_mirror_mode[1][0] = base_var_array[i++]; + attr_eff_dimm_rcd_mirror_mode[1][1] = base_var_array[i++]; + attr_eff_dram_ron[0][0] = base_var_array[i++]; + attr_eff_dram_ron[0][1] = base_var_array[i++]; + attr_eff_dram_ron[1][0] = base_var_array[i++]; + attr_eff_dram_ron[1][1] = base_var_array[i++]; + attr_eff_dram_rtt_nom[0][0][0] = base_var_array[i++]; + attr_eff_dram_rtt_nom[0][0][1] = base_var_array[i++]; + attr_eff_dram_rtt_nom[0][0][2] = base_var_array[i++]; + attr_eff_dram_rtt_nom[0][0][3] = base_var_array[i++]; + attr_eff_dram_rtt_nom[0][1][0] = base_var_array[i++]; + attr_eff_dram_rtt_nom[0][1][1] = base_var_array[i++]; + attr_eff_dram_rtt_nom[0][1][2] = base_var_array[i++]; + attr_eff_dram_rtt_nom[0][1][3] = base_var_array[i++]; + attr_eff_dram_rtt_nom[1][0][0] = base_var_array[i++]; + attr_eff_dram_rtt_nom[1][0][1] = base_var_array[i++]; + attr_eff_dram_rtt_nom[1][0][2] = base_var_array[i++]; + attr_eff_dram_rtt_nom[1][0][3] = base_var_array[i++]; + attr_eff_dram_rtt_nom[1][1][0] = base_var_array[i++]; + attr_eff_dram_rtt_nom[1][1][1] = base_var_array[i++]; + attr_eff_dram_rtt_nom[1][1][2] = base_var_array[i++]; + attr_eff_dram_rtt_nom[1][1][3] = base_var_array[i++]; + attr_eff_dram_rtt_wr[0][0][0] = base_var_array[i++]; + attr_eff_dram_rtt_wr[0][0][1] = base_var_array[i++]; + attr_eff_dram_rtt_wr[0][0][2] = base_var_array[i++]; + attr_eff_dram_rtt_wr[0][0][3] = base_var_array[i++]; + attr_eff_dram_rtt_wr[0][1][0] = base_var_array[i++]; + attr_eff_dram_rtt_wr[0][1][1] = base_var_array[i++]; + attr_eff_dram_rtt_wr[0][1][2] = base_var_array[i++]; + attr_eff_dram_rtt_wr[0][1][3] = base_var_array[i++]; + attr_eff_dram_rtt_wr[1][0][0] = base_var_array[i++]; + attr_eff_dram_rtt_wr[1][0][1] = base_var_array[i++]; + attr_eff_dram_rtt_wr[1][0][2] = base_var_array[i++]; + attr_eff_dram_rtt_wr[1][0][3] = base_var_array[i++]; + attr_eff_dram_rtt_wr[1][1][0] = base_var_array[i++]; + attr_eff_dram_rtt_wr[1][1][1] = base_var_array[i++]; + attr_eff_dram_rtt_wr[1][1][2] = base_var_array[i++]; + attr_eff_dram_rtt_wr[1][1][3] = base_var_array[i++]; + attr_eff_odt_rd[0][0][0] = base_var_array[i++]; + attr_eff_odt_rd[0][0][1] = base_var_array[i++]; + attr_eff_odt_rd[0][0][2] = base_var_array[i++]; + attr_eff_odt_rd[0][0][3] = base_var_array[i++]; + attr_eff_odt_rd[0][1][0] = base_var_array[i++]; + attr_eff_odt_rd[0][1][1] = base_var_array[i++]; + attr_eff_odt_rd[0][1][2] = base_var_array[i++]; + attr_eff_odt_rd[0][1][3] = base_var_array[i++]; + attr_eff_odt_rd[1][0][0] = base_var_array[i++]; + attr_eff_odt_rd[1][0][1] = base_var_array[i++]; + attr_eff_odt_rd[1][0][2] = base_var_array[i++]; + attr_eff_odt_rd[1][0][3] = base_var_array[i++]; + attr_eff_odt_rd[1][1][0] = base_var_array[i++]; + attr_eff_odt_rd[1][1][1] = base_var_array[i++]; + attr_eff_odt_rd[1][1][2] = base_var_array[i++]; + attr_eff_odt_rd[1][1][3] = base_var_array[i++]; + attr_eff_odt_wr[0][0][0] = base_var_array[i++]; + attr_eff_odt_wr[0][0][1] = base_var_array[i++]; + attr_eff_odt_wr[0][0][2] = base_var_array[i++]; + attr_eff_odt_wr[0][0][3] = base_var_array[i++]; + attr_eff_odt_wr[0][1][0] = base_var_array[i++]; + attr_eff_odt_wr[0][1][1] = base_var_array[i++]; + attr_eff_odt_wr[0][1][2] = base_var_array[i++]; + attr_eff_odt_wr[0][1][3] = base_var_array[i++]; + attr_eff_odt_wr[1][0][0] = base_var_array[i++]; + attr_eff_odt_wr[1][0][1] = base_var_array[i++]; + attr_eff_odt_wr[1][0][2] = base_var_array[i++]; + attr_eff_odt_wr[1][0][3] = base_var_array[i++]; + attr_eff_odt_wr[1][1][0] = base_var_array[i++]; + attr_eff_odt_wr[1][1][1] = base_var_array[i++]; + attr_eff_odt_wr[1][1][2] = base_var_array[i++]; + attr_eff_odt_wr[1][1][3] = base_var_array[i++]; + attr_eff_cen_rd_vref[0] = base_var_array[i++]; + attr_eff_cen_rd_vref[1] = base_var_array[i++]; + attr_eff_dram_wr_vref[0] = base_var_array[i++]; + attr_eff_dram_wr_vref[1] = base_var_array[i++]; + //attr_eff_dram_wrddr4_vref[0] = base_var_array[i++]; + //attr_eff_dram_wrddr4_vref[1] = base_var_array[i++]; + attr_eff_cen_rcv_imp_dq_dqs[0] = base_var_array[i++]; + attr_eff_cen_rcv_imp_dq_dqs[1] = base_var_array[i++]; + attr_eff_cen_drv_imp_dq_dqs[0] = base_var_array[i++]; + attr_eff_cen_drv_imp_dq_dqs[1] = base_var_array[i++]; + attr_eff_cen_drv_imp_cntl[0] = base_var_array[i++]; + attr_eff_cen_drv_imp_cntl[1] = base_var_array[i++]; + attr_eff_cen_drv_imp_addr[0] = base_var_array[i++]; + attr_eff_cen_drv_imp_addr[1] = base_var_array[i++]; + attr_eff_cen_drv_imp_clk[0] = base_var_array[i++]; + attr_eff_cen_drv_imp_clk[1] = base_var_array[i++]; + attr_eff_cen_drv_imp_spcke[0] = base_var_array[i++]; + attr_eff_cen_drv_imp_spcke[1] = base_var_array[i++]; + attr_eff_cen_slew_rate_dq_dqs[0] = base_var_array[i++]; + attr_eff_cen_slew_rate_dq_dqs[1] = base_var_array[i++]; + attr_eff_cen_slew_rate_cntl[0] = base_var_array[i++]; + attr_eff_cen_slew_rate_cntl[1] = base_var_array[i++]; + attr_eff_cen_slew_rate_addr[0] = base_var_array[i++]; + attr_eff_cen_slew_rate_addr[1] = base_var_array[i++]; + attr_eff_cen_slew_rate_clk[0] = base_var_array[i++]; + attr_eff_cen_slew_rate_clk[1] = base_var_array[i++]; + attr_eff_cen_slew_rate_spcke[0] = base_var_array[i++]; + attr_eff_cen_slew_rate_spcke[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_clk_p0[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_clk_p1[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_clk_p0[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_clk_p1[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a0[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a1[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a2[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a3[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a4[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a5[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a6[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a7[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a8[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a9[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a10[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a11[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a12[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a13[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a14[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a15[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_bA0[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_bA1[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_bA2[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_casn[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_rasn[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_wen[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_par[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_actn[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_cntl_cke0[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_cntl_cke1[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_cntl_cke2[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_cntl_cke3[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_cntl_csn0[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_cntl_csn1[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_cntl_csn2[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_cntl_csn3[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_cntl_odt0[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_cntl_odt1[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_cntl_cke0[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_cntl_cke1[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_cntl_cke2[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_cntl_cke3[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_cntl_csn0[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_cntl_csn1[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_cntl_csn2[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_cntl_csn3[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_cntl_odt0[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_cntl_odt1[0] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_clk_p0[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_clk_p1[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_clk_p0[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_clk_p1[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a0[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a1[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a2[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a3[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a4[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a5[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a6[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a7[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a8[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a9[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a10[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a11[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a12[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a13[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a14[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_a15[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_bA0[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_bA1[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_bA2[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_casn[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_rasn[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_cmd_wen[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_par[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m_actn[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_cntl_cke0[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_cntl_cke1[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_cntl_cke2[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_cntl_cke3[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_cntl_csn0[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_cntl_csn1[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_cntl_csn2[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_cntl_csn3[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_cntl_odt0[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m0_cntl_odt1[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_cntl_cke0[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_cntl_cke1[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_cntl_cke2[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_cntl_cke3[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_cntl_csn0[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_cntl_csn1[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_cntl_csn2[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_cntl_csn3[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_cntl_odt0[1] = base_var_array[i++]; + attr_eff_cen_phase_rot_m1_cntl_odt1[1] = base_var_array[i++]; + + //Now Setup the RCD - Done Here to Steal Code From Anuwats Version Of Eff Config Termination - // Modify impacted attributes if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM ) { for( int l_port = 0; l_port < PORT_SIZE; l_port += 1 ) { for( int l_dimm = 0; l_dimm < DIMM_SIZE; l_dimm += 1 ) { @@ -742,23 +1167,23 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { FAPI_ERR("Invalid RDIMM ATTR_MSS_VOLT = %d on %s!", l_mss_volt, i_target_mba.toEcmdString()); FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; } - if ( l_attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF ) { + if ( attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF ) { l_rcd_ibt_mask = 0x0000000070000000LL; - } else if ( l_attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100 ) { + } else if ( attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100 ) { l_rcd_ibt_mask = 0x0000000000000000LL; - } else if ( l_attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_150 ) { + } else if ( attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_150 ) { l_rcd_ibt_mask = 0x0040000000000000LL; - } else if ( l_attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200 ) { + } else if ( attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200 ) { l_rcd_ibt_mask = 0x0000000020000000LL; - } else if ( l_attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_300 ) { + } else if ( attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_300 ) { l_rcd_ibt_mask = 0x0000000040000000LL; } else { FAPI_ERR("Invalid DIMM_RCD_IBT on %s!", i_target_mba.toEcmdString()); FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; } - if ( l_attr_eff_dimm_rcd_mirror_mode[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF ) { + if ( attr_eff_dimm_rcd_mirror_mode[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF ) { l_rcd_mirror_mode_mask = 0x0000000000000000LL; - } else if ( l_attr_eff_dimm_rcd_mirror_mode[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON ) { + } else if ( attr_eff_dimm_rcd_mirror_mode[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON ) { l_rcd_mirror_mode_mask = 0x0000000080000000LL; } else { FAPI_ERR("Invalid DIMM_RCD_MIRROR_MODE on %s!", i_target_mba.toEcmdString()); @@ -773,297 +1198,106 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { } - // PR_VALUE_U8ARRAY[PORT_SIZE][PR_TYPE_SIZE][TOPO_SIZE] - uint8_t l_attr_eff_cen_phase_rot[PR_TYPE_SIZE][PORT_SIZE]; - uint8_t l_topo_index = 0; - if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) { - if ( l_target_mba_pos == 0 ) { - if ( l_mss_freq <= 933 ) { // 800Mbps - l_topo_index = 0; - } else if ( l_mss_freq <= 1200 ) { // 1066Mbps - l_topo_index = 1; - } else if ( l_mss_freq <= 1466 ) { // 1333Mbps - l_topo_index = 1; - } else if ( l_mss_freq <= 1733 ) { // 1600Mbps - l_topo_index = 2; - } else { // 1866Mbps - l_topo_index = 2; - } - } else if ( l_target_mba_pos == 1 ) { - if ( l_mss_freq <= 933 ) { // 800Mbps - l_topo_index = 0; - } else if ( l_mss_freq <= 1200 ) { // 1066Mbps - l_topo_index = 9; - } else if ( l_mss_freq <= 1466 ) { // 1333Mbps - l_topo_index = 9; - } else if ( l_mss_freq <= 1733 ) { // 1600Mbps - l_topo_index = 10; - } else { // 1866Mbps - l_topo_index = 10; - } - } else { - FAPI_ERR("Invalid MBA on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } - } else { - if ( l_target_mba_pos == 0 ) { - if ( l_num_ranks_per_dimm_u8array[0][0] == 4 ) { - l_topo_index = 8; - } else if ( l_num_ranks_per_dimm_u8array[0][0] == 2 ) { - if ( l_mss_freq <= 933 ) { // 800Mbps - l_topo_index = 0; - } else if ( l_mss_freq <= 1200 ) { // 1066Mbps - l_topo_index = 4; - } else if ( l_mss_freq <= 1466 ) { // 1333Mbps - l_topo_index = 4; - } else if ( l_mss_freq <= 1733 ) { // 1600Mbps - l_topo_index = 5; - } else { // 1866Mbps - l_topo_index = 5; - } - } else if ( l_num_ranks_per_dimm_u8array[0][0] == 1 ) { - l_topo_index = 3; - } else { - l_topo_index = 0; - } - } else if ( l_target_mba_pos == 1 ) { - if ( l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE ) { - if ( l_num_ranks_per_dimm_u8array[0][0] == 4 ) { - l_topo_index = 17; - } else if ( l_num_ranks_per_dimm_u8array[0][0] == 2 ) { - if ( l_mss_freq <= 933 ) { // 800Mbps - l_topo_index = 0; - } else if ( l_mss_freq <= 1200 ) { // 1066Mbps - l_topo_index = 13; - } else if ( l_mss_freq <= 1466 ) { // 1333Mbps - l_topo_index = 13; - } else if ( l_mss_freq <= 1733 ) { // 1600Mbps - l_topo_index = 14; - } else { // 1866Mbps - l_topo_index = 14; - } - } else if ( l_num_ranks_per_dimm_u8array[0][0] == 1 ) { - if ( l_mss_freq <= 933 ) { // 800Mbps - l_topo_index = 0; - } else if ( l_mss_freq <= 1200 ) { // 1066Mbps - l_topo_index = 11; - } else if ( l_mss_freq <= 1466 ) { // 1333Mbps - l_topo_index = 11; - } else if ( l_mss_freq <= 1733 ) { // 1600Mbps - l_topo_index = 12; - } else { // 1866Mbps - l_topo_index = 12; - } - } else { - l_topo_index = 0; - } - } else if ( l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL ) { - if ( l_num_ranks_per_dimm_u8array[0][0] == 4 ) { - l_topo_index = 24; - } else if ( l_num_ranks_per_dimm_u8array[0][0] == 2 ) { - if ( l_mss_freq <= 933 ) { // 800Mbps - l_topo_index = 0; - } else if ( l_mss_freq <= 1200 ) { // 1066Mbps - l_topo_index = 20; - } else if ( l_mss_freq <= 1466 ) { // 1333Mbps - l_topo_index = 20; - } else if ( l_mss_freq <= 1733 ) { // 1600Mbps - l_topo_index = 21; - } else { // 1866Mbps - l_topo_index = 21; - } - } else if ( l_num_ranks_per_dimm_u8array[0][0] == 1 ) { - if ( l_mss_freq <= 933 ) { // 800Mbps - l_topo_index = 0; - } else if ( l_mss_freq <= 1200 ) { // 1066Mbps - l_topo_index = 18; - } else if ( l_mss_freq <= 1466 ) { // 1333Mbps - l_topo_index = 18; - } else if ( l_mss_freq <= 1733 ) { // 1600Mbps - l_topo_index = 19; - } else { // 1866Mbps - l_topo_index = 19; - } - } else { - l_topo_index = 0; - } - } else { - l_topo_index = 0; - } - } else { - FAPI_ERR("Invalid MBA on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; - } - } - for( int l_port = 0; l_port < PORT_SIZE; l_port += 1 ) { - for( int l_pr_type_index = 0; l_pr_type_index < PR_TYPE_SIZE; l_pr_type_index += 1 ) { - l_attr_eff_cen_phase_rot[l_pr_type_index][l_port] = PR_VALUE_U8ARRAY[l_port][l_pr_type_index][l_topo_index]; - // AST HERE: Need EC check here for Centaur EC10 ADR Centerlane NWELL LVS issue PR=0x7F workaround. - if ((((l_target_mba_pos == 0) && (l_port == 0) && (l_pr_type_index == 16)) || // MA_CMD_A<12> - ((l_target_mba_pos == 0) && (l_port == 0) && (l_pr_type_index == 4)) || // MA_CMS_A<0> - ((l_target_mba_pos == 0) && (l_port == 0) && (l_pr_type_index == 17)) || // MA_CMD_A<13> - ((l_target_mba_pos == 0) && (l_port == 0) && (l_pr_type_index == 20)) || // MA_CMD_BA<0> - ((l_target_mba_pos == 0) && (l_port == 1) && (l_pr_type_index == 34)) || // MB0_CNTL_CSN<2> - ((l_target_mba_pos == 0) && (l_port == 1) && (l_pr_type_index == 36)) || // MB0_CNTL_ODT<0> - ((l_target_mba_pos == 0) && (l_port == 1) && (l_pr_type_index == 15)) || // MB_CMD_A<11> - ((l_target_mba_pos == 0) && (l_port == 1) && (l_pr_type_index == 28)) || // MB0_CNTL_CKE<0> - ((l_target_mba_pos == 1) && (l_port == 0) && (l_pr_type_index == 5)) || // MC_CMD_A<1> - ((l_target_mba_pos == 1) && (l_port == 0) && (l_pr_type_index == 10)) || // MC_CMD_A<6> - ((l_target_mba_pos == 1) && (l_port == 0) && (l_pr_type_index == 26)) || // MC_CMD_PAR - ((l_target_mba_pos == 1) && (l_port == 0) && (l_pr_type_index == 47)) || // MC1_CNTL_ODT<1> - ((l_target_mba_pos == 1) && (l_port == 1) && (l_pr_type_index == 32)) || // MD0_CNTL_CSN<0> - ((l_target_mba_pos == 1) && (l_port == 1) && (l_pr_type_index == 14)) || // MD_CMD_A<10> - ((l_target_mba_pos == 1) && (l_port == 1) && (l_pr_type_index == 44)) || // MD1_CNTL_CSN<2> - ((l_target_mba_pos == 1) && (l_port == 1) && (l_pr_type_index == 36))) && // MD0_CNTL_ODT<0> - (l_attr_is_simulation == 0)) { - FAPI_INF("WARNING: Centaur EC10 ADR Centerlane PR=0x7F workaround for NWELL LVS issue on CmdLaneIndex %d Port %d %s!", l_pr_type_index, l_port, i_target_mba.toEcmdString()); - l_attr_eff_cen_phase_rot[l_pr_type_index][l_port] = 0x7F; - } else { - if (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM) { - if ((l_attr_eff_cen_phase_rot[l_pr_type_index][l_port] - 32) >= 0) { - l_attr_eff_cen_phase_rot[l_pr_type_index][l_port] = l_attr_eff_cen_phase_rot[l_pr_type_index][l_port] - 32; - } else { - l_attr_eff_cen_phase_rot[l_pr_type_index][l_port] = 0; - } - } - } - } - } // Set attributes rc = FAPI_ATTR_SET(ATTR_MSS_CAL_STEP_ENABLE, &i_target_mba, l_attr_mss_cal_step_enable); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_IBT, &i_target_mba, l_attr_eff_dimm_rcd_ibt); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_MIRROR_MODE, &i_target_mba, l_attr_eff_dimm_rcd_mirror_mode); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, l_attr_eff_cen_rd_vref); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, l_attr_eff_dram_wr_vref); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, l_attr_eff_cen_rcv_imp_dq_dqs); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, l_attr_eff_cen_drv_imp_dq_dqs); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_CNTL, &i_target_mba, l_attr_eff_cen_drv_imp_cntl); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_ADDR, &i_target_mba, l_attr_eff_cen_drv_imp_addr); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_CLK, &i_target_mba, l_attr_eff_cen_drv_imp_clk); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_SPCKE, &i_target_mba, l_attr_eff_cen_drv_imp_spcke); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, l_attr_eff_cen_slew_rate_dq_dqs); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CNTL, &i_target_mba, l_attr_eff_cen_slew_rate_cntl); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_ADDR, &i_target_mba, l_attr_eff_cen_slew_rate_addr); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CLK, &i_target_mba, l_attr_eff_cen_slew_rate_clk); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_SPCKE, &i_target_mba, l_attr_eff_cen_slew_rate_spcke); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RON, &i_target_mba, l_attr_eff_dram_ron); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RTT_NOM, &i_target_mba, l_attr_eff_dram_rtt_nom); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RTT_WR, &i_target_mba, l_attr_eff_dram_rtt_wr); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_ODT_RD, &i_target_mba, l_attr_eff_odt_rd); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_ODT_WR, &i_target_mba, l_attr_eff_odt_wr); if(rc) return rc; - - if(l_attr_is_simulation != 0) { - FAPI_INF("In Sim Detected %s on %s value is %d", PROCEDURE_NAME, i_target_mba.toEcmdString(), l_attr_is_simulation); - - for(int i=0;i<2;i++) { - l_attr_eff_cen_phase_rot[0][i]=0x40; - l_attr_eff_cen_phase_rot[1][i]=0x40; - l_attr_eff_cen_phase_rot[2][i]=0x40; - l_attr_eff_cen_phase_rot[3][i]=0x40; - l_attr_eff_cen_phase_rot[4][i]=0; - l_attr_eff_cen_phase_rot[5][i]=0; - l_attr_eff_cen_phase_rot[6][i]=0; - l_attr_eff_cen_phase_rot[7][i]=0; - l_attr_eff_cen_phase_rot[8][i]=0; - l_attr_eff_cen_phase_rot[9][i]=0; - l_attr_eff_cen_phase_rot[10][i]=0; - l_attr_eff_cen_phase_rot[11][i]=0; - l_attr_eff_cen_phase_rot[12][i]=0; - l_attr_eff_cen_phase_rot[13][i]=0; - l_attr_eff_cen_phase_rot[14][i]=0; - l_attr_eff_cen_phase_rot[15][i]=0; - l_attr_eff_cen_phase_rot[16][i]=0; - l_attr_eff_cen_phase_rot[17][i]=0; - l_attr_eff_cen_phase_rot[18][i]=0; - l_attr_eff_cen_phase_rot[19][i]=0; - l_attr_eff_cen_phase_rot[20][i]=0; - l_attr_eff_cen_phase_rot[21][i]=0; - l_attr_eff_cen_phase_rot[22][i]=0; - l_attr_eff_cen_phase_rot[23][i]=0; - l_attr_eff_cen_phase_rot[24][i]=0; - l_attr_eff_cen_phase_rot[25][i]=0; - l_attr_eff_cen_phase_rot[26][i]=0; - l_attr_eff_cen_phase_rot[27][i]=0; - l_attr_eff_cen_phase_rot[28][i]=0; - l_attr_eff_cen_phase_rot[29][i]=0; - l_attr_eff_cen_phase_rot[30][i]=0; - l_attr_eff_cen_phase_rot[31][i]=0; - l_attr_eff_cen_phase_rot[32][i]=0; - l_attr_eff_cen_phase_rot[33][i]=0; - l_attr_eff_cen_phase_rot[34][i]=0; - l_attr_eff_cen_phase_rot[35][i]=0; - l_attr_eff_cen_phase_rot[36][i]=0; - l_attr_eff_cen_phase_rot[37][i]=0; - l_attr_eff_cen_phase_rot[38][i]=0; - l_attr_eff_cen_phase_rot[39][i]=0; - l_attr_eff_cen_phase_rot[40][i]=0; - l_attr_eff_cen_phase_rot[41][i]=0; - l_attr_eff_cen_phase_rot[42][i]=0; - l_attr_eff_cen_phase_rot[43][i]=0; - l_attr_eff_cen_phase_rot[44][i]=0; - l_attr_eff_cen_phase_rot[45][i]=0; - l_attr_eff_cen_phase_rot[46][i]=0; - l_attr_eff_cen_phase_rot[47][i]=0; - } - } - - - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0, &i_target_mba, l_attr_eff_cen_phase_rot[0]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1, &i_target_mba, l_attr_eff_cen_phase_rot[1]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0, &i_target_mba, l_attr_eff_cen_phase_rot[2]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1, &i_target_mba, l_attr_eff_cen_phase_rot[3]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0, &i_target_mba, l_attr_eff_cen_phase_rot[4]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1, &i_target_mba, l_attr_eff_cen_phase_rot[5]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2, &i_target_mba, l_attr_eff_cen_phase_rot[6]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3, &i_target_mba, l_attr_eff_cen_phase_rot[7]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4, &i_target_mba, l_attr_eff_cen_phase_rot[8]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5, &i_target_mba, l_attr_eff_cen_phase_rot[9]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6, &i_target_mba, l_attr_eff_cen_phase_rot[10]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7, &i_target_mba, l_attr_eff_cen_phase_rot[11]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8, &i_target_mba, l_attr_eff_cen_phase_rot[12]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9, &i_target_mba, l_attr_eff_cen_phase_rot[13]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10, &i_target_mba, l_attr_eff_cen_phase_rot[14]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11, &i_target_mba, l_attr_eff_cen_phase_rot[15]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12, &i_target_mba, l_attr_eff_cen_phase_rot[16]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13, &i_target_mba, l_attr_eff_cen_phase_rot[17]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14, &i_target_mba, l_attr_eff_cen_phase_rot[18]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15, &i_target_mba, l_attr_eff_cen_phase_rot[19]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0, &i_target_mba, l_attr_eff_cen_phase_rot[20]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1, &i_target_mba, l_attr_eff_cen_phase_rot[21]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2, &i_target_mba, l_attr_eff_cen_phase_rot[22]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN, &i_target_mba, l_attr_eff_cen_phase_rot[23]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN, &i_target_mba, l_attr_eff_cen_phase_rot[24]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN, &i_target_mba, l_attr_eff_cen_phase_rot[25]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_PAR, &i_target_mba, l_attr_eff_cen_phase_rot[26]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_ACTN, &i_target_mba, l_attr_eff_cen_phase_rot[27]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0, &i_target_mba, l_attr_eff_cen_phase_rot[28]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1, &i_target_mba, l_attr_eff_cen_phase_rot[29]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2, &i_target_mba, l_attr_eff_cen_phase_rot[30]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3, &i_target_mba, l_attr_eff_cen_phase_rot[31]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0, &i_target_mba, l_attr_eff_cen_phase_rot[32]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1, &i_target_mba, l_attr_eff_cen_phase_rot[33]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2, &i_target_mba, l_attr_eff_cen_phase_rot[34]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3, &i_target_mba, l_attr_eff_cen_phase_rot[35]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0, &i_target_mba, l_attr_eff_cen_phase_rot[36]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1, &i_target_mba, l_attr_eff_cen_phase_rot[37]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0, &i_target_mba, l_attr_eff_cen_phase_rot[38]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1, &i_target_mba, l_attr_eff_cen_phase_rot[39]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2, &i_target_mba, l_attr_eff_cen_phase_rot[40]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3, &i_target_mba, l_attr_eff_cen_phase_rot[41]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0, &i_target_mba, l_attr_eff_cen_phase_rot[42]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1, &i_target_mba, l_attr_eff_cen_phase_rot[43]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2, &i_target_mba, l_attr_eff_cen_phase_rot[44]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3, &i_target_mba, l_attr_eff_cen_phase_rot[45]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0, &i_target_mba, l_attr_eff_cen_phase_rot[46]); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1, &i_target_mba, l_attr_eff_cen_phase_rot[47]); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_IBT, &i_target_mba, attr_eff_dimm_rcd_ibt); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_MIRROR_MODE, &i_target_mba, attr_eff_dimm_rcd_mirror_mode); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, attr_eff_cen_rd_vref); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, attr_eff_dram_wr_vref); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, attr_eff_cen_rcv_imp_dq_dqs); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, attr_eff_cen_drv_imp_dq_dqs); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_CNTL, &i_target_mba, attr_eff_cen_drv_imp_cntl); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_ADDR, &i_target_mba, attr_eff_cen_drv_imp_addr); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_CLK, &i_target_mba, attr_eff_cen_drv_imp_clk); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_SPCKE, &i_target_mba, attr_eff_cen_drv_imp_spcke); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, attr_eff_cen_slew_rate_dq_dqs); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CNTL, &i_target_mba, attr_eff_cen_slew_rate_cntl); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_ADDR, &i_target_mba, attr_eff_cen_slew_rate_addr); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CLK, &i_target_mba, attr_eff_cen_slew_rate_clk); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_SPCKE, &i_target_mba, attr_eff_cen_slew_rate_spcke); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RON, &i_target_mba, attr_eff_dram_ron); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RTT_NOM, &i_target_mba, attr_eff_dram_rtt_nom); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RTT_WR, &i_target_mba, attr_eff_dram_rtt_wr); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_ODT_RD, &i_target_mba, attr_eff_odt_rd); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_ODT_WR, &i_target_mba, attr_eff_odt_wr); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0, &i_target_mba, attr_eff_cen_phase_rot_m0_clk_p0); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1, &i_target_mba, attr_eff_cen_phase_rot_m0_clk_p1); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0, &i_target_mba, attr_eff_cen_phase_rot_m1_clk_p0); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1, &i_target_mba, attr_eff_cen_phase_rot_m1_clk_p1); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a0); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a1); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a2); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a3); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a4); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a5); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a6); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a7); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a8); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a9); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a10); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a11); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a12); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a13); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a14); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_a15); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_bA0); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_bA1); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_bA2); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_casn); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_rasn); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN, &i_target_mba, attr_eff_cen_phase_rot_m_cmd_wen); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_PAR, &i_target_mba, attr_eff_cen_phase_rot_m_par); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_ACTN, &i_target_mba, attr_eff_cen_phase_rot_m_actn); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0, &i_target_mba, attr_eff_cen_phase_rot_m0_cntl_cke0); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1, &i_target_mba, attr_eff_cen_phase_rot_m0_cntl_cke1); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2, &i_target_mba, attr_eff_cen_phase_rot_m0_cntl_cke2); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3, &i_target_mba, attr_eff_cen_phase_rot_m0_cntl_cke3); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0, &i_target_mba, attr_eff_cen_phase_rot_m0_cntl_csn0); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1, &i_target_mba, attr_eff_cen_phase_rot_m0_cntl_csn1); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2, &i_target_mba, attr_eff_cen_phase_rot_m0_cntl_csn2); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3, &i_target_mba, attr_eff_cen_phase_rot_m0_cntl_csn3); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0, &i_target_mba, attr_eff_cen_phase_rot_m0_cntl_odt0); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1, &i_target_mba, attr_eff_cen_phase_rot_m0_cntl_odt1); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_cke0); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_cke1); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_cke2); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_cke3); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_csn0); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_csn1); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_csn2); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_csn3); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_odt0); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_odt1); if(rc) return rc; FAPI_INF("%s on %s COMPLETE", PROCEDURE_NAME, i_target_mba.toEcmdString()); return rc; + } } // extern "C" + + + + + + + + + + + + + + + + + + + + + diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C index fe3123344..6a9027c70 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_config_thermal.C,v 1.14 2012/12/12 20:10:33 pardeik Exp $ +// $Id: mss_eff_config_thermal.C,v 1.15 2013/02/11 18:42:45 pardeik Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/ // centaur/working/procedures/ipl/fapi/mss_eff_config_thermal.C,v $ //------------------------------------------------------------------------------ @@ -53,6 +53,8 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.15 | pardeik |11-FEB-13| set safemode throttles to unthrottled value +// | | | for lab until fw sets runtime throttles // 1.14 | pardeik |03-DEC-12| update lines to have a max width of 80 chars // | | | added FAPI_ERR before return code lines // | | | made trace statements for procedures FAPI_IMP @@ -449,8 +451,24 @@ extern "C" { } */ // TODO: Get Safemode throttles from MRW (platinit), hardcode until available - safemode_throttle_n_per_mba = 96; - safemode_throttle_n_per_chip = 32; +// Do not use safe mode throttles until firmware programs runtime throttles (ie. don't impact lab with throttles) + if (dimm_type == CDIMM) + { + safemode_throttle_n_per_mba = 96; + } + else + { + safemode_throttle_n_per_mba = 96; + } +// safemode_throttle_n_per_chip = 32; + if (dimm_type == CDIMM) + { + safemode_throttle_n_per_chip = 192; + } + else + { + safemode_throttle_n_per_chip = 96; + } safemode_throttle_d = 512; /* rc = FAPI_ATTR_GET(ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA, diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_error_support.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_error_support.H new file mode 100644 index 000000000..9d1143079 --- /dev/null +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_error_support.H @@ -0,0 +1,65 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_error_support.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: mss_error_support.H,v 1.1 2013/03/21 19:04:22 bellows Exp $ + +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : mss_error_support.H +// *! DESCRIPTION : Tools +// *! OWNER NAME : bellows@us.ibm.com +// *! BACKUP NAME : +// #! ADDITIONAL COMMENTS : +// + +//------------------------------------------------------------------------------ +// Don't forget to create CVS comments when you check in your changes! +//------------------------------------------------------------------------------ +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version:| Author: | Date: | Comment: +//---------|----------|---------|----------------------------------------------- +// 1.0 | 03/08/13 | bellows | First version + +#ifndef _MSS_ERROR_SUPPORT_H +#define _MSS_ERROR_SUPPORT_H + +#include <fapi.H> + +typedef fapi::ReturnCode (*hwpCollectMemGrouping_FP_t)(const fapi::Target&, fapi::ReturnCode &); + +extern "C" +{ + + +fapi::ReturnCode hwpCollectMemGrouping(const fapi::Target & i_target,fapi::ReturnCode & o_rc); +fapi::ReturnCode hwpCollectMemFIRs(const fapi::Target & i_target,fapi::ReturnCode & o_rc); + + + +} // extern "C" + +#endif /* _MSS_ERROR_SUPPORT_H */ + diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.C index 96b14d9a2..9725ece00 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,8 +20,9 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ +// $Id: opt_memmap.C,v 1.6 2013/02/22 22:27:34 vanlee Exp $ //------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2012 +// *! (C) Copyright International Business Machines Corp. 2012, 2013 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //------------------------------------------------------------------------------ @@ -38,18 +39,21 @@ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- // 1.1 | vanlee | 12/01/12| First drop +// 1.4 | vanlee | 01/04/13| Added version string +// 1.5 | vanlee | 02/20/13| Add init paramter +// 1.6 | vanlee | 02/22/13| Update sort logic of ProcBase class //------------------------------------------------------------------------------ // Design flow // -// opt_memmap() is run in between two mss_eff_grouping() calls. +// opt_memmap() is run alternatively between two mss_eff_grouping() calls. // -// 1) Before First mss_eff_grouping() call +// 1) Call opt_memmap() with i_init = true // - Each proc's ATTR_PROC_MEM_BASE attribute is set to 0 // - Each proc's ATTR_PROC_MIRROR_BASE attribute is set to 512TB // 2) First mss_eff_grouping() call // - The HWP updates each proc's ATTR_PROC_MEM_BASES and ATTR_PROC_MEM_SIZES // attributes based on installed memory behind each proc -// 3) Call opt_memmap() +// 3) Call opt_memmap() with i_init = false // - Get "effective stackable" size (EffSize) of each proc. Due to (1), // (a) EffSize = highest ATTR_PROC_MEM_BASES + // its corresponding ATTR_PROC_MEM_SIZES @@ -89,7 +93,7 @@ extern "C" { public: uint64_t iv_base; uint64_t iv_size; - bool operator<(MemRegion rhs) + bool operator<(MemRegion rhs) const { bool l_lt = true; if (iv_base > rhs.iv_base || @@ -107,23 +111,41 @@ extern "C" { public: fapi::Target *iv_tgt; uint64_t iv_size; - bool operator<(ProcBase rhs) { return iv_size < rhs.iv_size; } - ProcBase(fapi::Target* t, uint64_t s) : iv_tgt(t), iv_size(s) {} + uint32_t iv_pos; + // sorting in increasing size, and decreasing proc position + // e.g. proc0 and proc2 have same size, then the order will be + // proc2 then proc0 + bool operator<(ProcBase rhs) const + { + bool l_lt = true; + if (iv_size > rhs.iv_size || + (iv_size == rhs.iv_size && iv_pos < rhs.iv_pos)) + { + l_lt = false; + } + return l_lt; + } + ProcBase(fapi::Target* t, uint64_t s, uint32_t p) : + iv_tgt(t), iv_size(s), iv_pos(p) {} }; inline uint64_t PowerOf2Roundedup( uint64_t i_number ) { if (i_number) { - uint64_t leading0s = 0; - asm volatile("cntlzd %0, %1" : "=r"(leading0s) : "r"(i_number)); - uint64_t mask = ( 1ULL << (63 - leading0s) ); - i_number = mask << ((mask ^ i_number) ? 1 : 0); + --i_number; + i_number |= i_number >> 1; + i_number |= i_number >> 2; + i_number |= i_number >> 4; + i_number |= i_number >> 8; + i_number |= i_number >> 16; + i_number |= i_number >> 32; + ++i_number; } return i_number; } - - ReturnCode opt_memmap(std::vector<fapi::Target> & i_procs) + + ReturnCode opt_memmap(std::vector<fapi::Target> & i_procs, bool i_init) { ReturnCode rc; std::vector<ProcBase> l_procBases; @@ -135,6 +157,18 @@ extern "C" { for (std::vector<fapi::Target>::iterator l_iter = i_procs.begin(); l_iter != i_procs.end(); ++l_iter) { + // If request to initialize MEM_BASE, just do it for each proc + if (i_init) + { + uint64_t l_base = 0; + rc = FAPI_ATTR_SET(ATTR_PROC_MEM_BASE, &(*l_iter), l_base); + if (rc) + { + break; + } + continue; + } + rc = FAPI_ATTR_GET(ATTR_POS, &(*l_iter), l_pos); if (rc) { @@ -157,7 +191,7 @@ extern "C" { { for(size_t i = 0; i < l_MCS_per_proc; i++) { - FAPI_INF(" l_bases[%d] = %016X", i, l_bases[i]); + FAPI_INF(" l_bases[%d] = %016llX", i, l_bases[i]); } } @@ -171,7 +205,7 @@ extern "C" { { for(size_t i = 0; i < l_MCS_per_proc; i++) { - FAPI_INF(" l_sizes[%d] = %016X", i, l_sizes[i]); + FAPI_INF(" l_sizes[%d] = %016llX", i, l_sizes[i]); } } @@ -189,31 +223,27 @@ extern "C" { round_size += l_regions[l_regions.size()-1].iv_size; round_size = PowerOf2Roundedup( round_size ); - FAPI_INF(" round_size = %016X", round_size); + FAPI_INF(" round_size = %016llX", round_size); // save the proc's target and effective size - ProcBase l_procBase(&(*l_iter), round_size); + ProcBase l_procBase(&(*l_iter), round_size, l_pos); l_procBases.push_back(l_procBase); } - while (rc.ok()) + while (rc.ok() && !i_init) { std::sort(l_procBases.begin(), l_procBases.end()); uint64_t cur_mem_base = 0; - uint64_t cur_mir_base = 0x0002000000000000; // 512TB + uint64_t cur_mir_base = 0x0002000000000000LL; // 512TB for (size_t i = l_procBases.size(); i != 0; --i) { fapi::Target * l_tgt = l_procBases[i-1].iv_tgt; uint64_t size = l_procBases[i-1].iv_size; + l_pos = l_procBases[i-1].iv_pos; - uint32_t l_pos = 0; - rc = FAPI_ATTR_GET(ATTR_POS, l_tgt, l_pos); - if (rc.ok()) - { - FAPI_INF("proc%d MEM_BASE = %016X", l_pos, cur_mem_base); - FAPI_INF("proc%d MIRROR_BASE = %016X", l_pos, cur_mir_base); - } + FAPI_INF("proc%d MEM_BASE = %016llX", l_pos, cur_mem_base); + FAPI_INF("proc%d MIRROR_BASE = %016llX", l_pos, cur_mir_base); rc = FAPI_ATTR_SET(ATTR_PROC_MEM_BASE, l_tgt, cur_mem_base); if (rc) diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.H index 1b0522e76..db8e96cba 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.H +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,6 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ +// $Id: opt_memmap.H,v 1.3 2013/02/20 23:13:30 vanlee Exp $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 // *! All Rights Reserved -- Property of IBM @@ -41,18 +42,23 @@ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- // 1.1 | vanlee | 12/01/12| Initial version +// 1.2 | vanlee | 01/04/13| Added version string +// 1.3 | vanlee | 02/20/13| Added i_init parameter #ifndef MSS_OPT_MEMMAP_H_ #define MSS_OPT_MEMMAP_H_ #include <fapi.H> -typedef fapi::ReturnCode (*opt_memmap_FP_t)(std::vector<fapi::Target> & i_procs ); +typedef fapi::ReturnCode (*opt_memmap_FP_t)(std::vector<fapi::Target> & i_procs, + bool i_init); extern "C" { -fapi::ReturnCode opt_memmap(std::vector<fapi::Target> & i_procs); +// i_init = true : initialize all ATTR_PROC_MEM_BASE attributes to 0 +// = false : perform memory map optimization +fapi::ReturnCode opt_memmap(std::vector<fapi::Target> & i_procs, bool i_init); } // extern "C" diff --git a/src/usr/hwpf/hwp/mc_config/mss_freq/mss_freq.C b/src/usr/hwpf/hwp/mc_config/mss_freq/mss_freq.C index 887428dff..89e5e80f5 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_freq/mss_freq.C +++ b/src/usr/hwpf/hwp/mc_config/mss_freq/mss_freq.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_freq.C,v 1.20 2013/02/12 15:20:47 jdsloat Exp $ +// $Id: mss_freq.C,v 1.21 2013/02/13 00:23:34 jdsloat Exp $ /* File mss_volt.C created by JEFF SABROWSKI on Fri 21 Oct 2011. */ //------------------------------------------------------------------------------ @@ -60,6 +60,7 @@ // 1.18 | jdsloat | 09/07/12 | Added FTB offset to TAA and TCK // 1.19 | jdsloat | 01/30/13 | Added Check for l_spd_min_tck_max // 1.20 | jdsloat | 02/12/13 | Added path for freq_override +// 1.21 | jdsloat | 02/12/13 | Added Debug messages // // This procedure takes CENTAUR as argument. for each DIMM (under each MBA) // DIMM SPD attributes are read to determine optimal DRAM frequency @@ -280,7 +281,9 @@ fapi::ReturnCode mss_freq(const fapi::Target &i_target_memb) break; } l_dimm_freq_calc = 2000000 / l_spd_min_tck; - + + FAPI_INF( "TAA(ps): %d TCK(ps): %d Calc'ed Freq for this dimm: %d", l_spd_min_taa, l_spd_min_tck, l_dimm_freq_calc); + //is this the slowest dimm? if (l_dimm_freq_calc < l_dimm_freq_min) { @@ -316,6 +319,9 @@ fapi::ReturnCode mss_freq(const fapi::Target &i_target_memb) } } + FAPI_INF( "Highest Supported Frequency amongst DIMMs: %d", l_dimm_freq_min); + FAPI_INF( "Minimum TAA(ps) amongst DIMMs: %d Minimum TCK(ps) amongst DIMMs: %d", l_spd_min_taa_max, l_spd_min_tck_max); + //Determining the cnfg for imposing any cnfg speed limitations if ((cur_dimm_spd_valid_u8array[0][0] == MSS_FREQ_VALID) && (cur_dimm_spd_valid_u8array[0][1] == MSS_FREQ_VALID)) { @@ -330,36 +336,44 @@ fapi::ReturnCode mss_freq(const fapi::Target &i_target_memb) plug_config = MSS_FREQ_EMPTY; } + + FAPI_INF( "PLUG CONFIG(from SPD): %d Type of Dimm(from SPD): 0x%02X Num Ranks(from SPD): %d", plug_config, module_type, num_ranks); + // Impose configuration limitations // Single Drop RDIMMs Cnfgs cannot run faster than 1333 unless it only has 1 rank if ((module_type_all == ENUM_ATTR_SPD_MODULE_TYPE_RDIMM)&&(plug_config == MSS_FREQ_SINGLE_DROP)&&(num_ranks_total > 1)&&(l_dimm_freq_min > 1333)) { l_dimm_freq_min = 1333; l_spd_min_tck_max = 1500; + FAPI_INF( "Single Drop RDIMM with more than 1 Rank Cnfg limitation. New Freq: %d", l_dimm_freq_min); } // Double Drop RDIMMs Cnfgs cannot run faster than 1333 with 4 ranks total else if ((module_type_all == ENUM_ATTR_SPD_MODULE_TYPE_RDIMM)&&(plug_config == MSS_FREQ_DUAL_DROP)&&(num_ranks_total == 4)&&(l_dimm_freq_min > 1333)) { l_dimm_freq_min = 1333; l_spd_min_tck_max = 1500; + FAPI_INF( "Dual Drop RDIMM with more than 4 Rank Cnfg limitation. New Freq: %d", l_dimm_freq_min); } // Double Drop RDIMMs Cnfgs cannot run faster than 1066 with 8 ranks total else if ((module_type_all == ENUM_ATTR_SPD_MODULE_TYPE_RDIMM)&&(plug_config == MSS_FREQ_DUAL_DROP)&&(num_ranks_total == 8)&&(l_dimm_freq_min > 1066)) { l_dimm_freq_min = 1066; l_spd_min_tck_max = 1875; + FAPI_INF( "Dual Drop RDIMM with more than 8 Rank Cnfg limitation. New Freq: %d", l_dimm_freq_min); } // Single Drop LRDIMMs Cnfgs cannot run faster than 1333 with greater than 2 ranks else if ((module_type_all == ENUM_ATTR_SPD_MODULE_TYPE_LRDIMM)&&(plug_config == MSS_FREQ_SINGLE_DROP)&&(num_ranks_total > 2)&&(l_dimm_freq_min > 1333)) { l_dimm_freq_min = 1333; l_spd_min_tck_max = 1500; + FAPI_INF( "Single Drop LRDIMM with more than 2 Rank Cnfg limitation. New Freq: %d", l_dimm_freq_min); } // Dual Drop LRDIMMs Cnfgs cannot run faster than 1333 else if ((module_type_all == ENUM_ATTR_SPD_MODULE_TYPE_LRDIMM)&&(plug_config == MSS_FREQ_DUAL_DROP)&&(l_dimm_freq_min > 1333)) { l_dimm_freq_min = 1333; l_spd_min_tck_max = 1500; + FAPI_INF( "Dual Drop LRDIMM Cnfg limitation. New Freq: %d", l_dimm_freq_min); } if ( l_spd_min_tck_max == 0) @@ -368,9 +382,6 @@ fapi::ReturnCode mss_freq(const fapi::Target &i_target_memb) FAPI_SET_HWP_ERROR(l_rc, RC_MSS_UNSUPPORTED_SPD_DATA); } - FAPI_INF( "PLUG CONFIG: %d Type O' Dimm: 0x%02X Num Ranks: %d", plug_config, module_type, num_ranks); - - l_rc = FAPI_ATTR_GET(ATTR_MSS_FREQ_OVERRIDE, &i_target_memb, l_freq_override); if ( l_freq_override != 0) { @@ -400,7 +411,7 @@ fapi::ReturnCode mss_freq(const fapi::Target &i_target_memb) l_dimm_freq_min = 1066; l_spd_min_tck_max = 1875; } - + FAPI_INF( "Override Frequency Detected: %d", l_dimm_freq_min); } if ((l_spd_cas_lat_supported_all == 0) && (!l_rc)) @@ -414,10 +425,16 @@ fapi::ReturnCode mss_freq(const fapi::Target &i_target_memb) //Determine a proposed CAS latency l_cas_latency = l_spd_min_taa_max / l_spd_min_tck_max; + + FAPI_INF( "CL = TAA / TCK ... TAA(ps): %d TCK(ps): %d", l_spd_min_taa_max, l_spd_min_tck_max); + FAPI_INF( "Calculated CL: %d", l_cas_latency); + if ( l_spd_min_taa_max % l_spd_min_tck_max) { l_cas_latency++; - } + FAPI_INF( "After rounding up ... CL: %d", l_cas_latency); + } + l_cl_mult_tck = l_cas_latency * l_spd_min_tck_max; // If the CL proposed is not supported or the TAA exceeds TAA max @@ -427,6 +444,9 @@ fapi::ReturnCode mss_freq(const fapi::Target &i_target_memb) while ( ( (!( l_spd_cas_lat_supported_all & (0x00000001<<(l_cas_latency-4)))) || (l_cl_mult_tck > 20000) ) && ( l_override_path = 0 ) ) { + + FAPI_INF( "Warning calculated CL is not supported in VPD. Searching for a new CL."); + // If not supported, increment the CL up to 18 (highest supported CL) looking for Supported CL while ((!( l_spd_cas_lat_supported_all & (0x00000001<<(l_cas_latency-4))))&&(l_cas_latency < 18)) { @@ -440,6 +460,8 @@ fapi::ReturnCode mss_freq(const fapi::Target &i_target_memb) if ( ( (!( l_spd_cas_lat_supported_all & (0x00000001<<(l_cas_latency-4)))) || (l_cl_mult_tck > 20000) ) && ( l_freq_override == 0) ) { + FAPI_INF( "No Supported CL works for calculating frequency. Lowering frequency and trying CL Algorithm again."); + if (l_spd_min_tck_max < 1500) { //1600 to 1333 @@ -479,6 +501,8 @@ fapi::ReturnCode mss_freq(const fapi::Target &i_target_memb) if ( ( (!( l_spd_cas_lat_supported_all & (0x00000001<<(l_cas_latency-4)))) || (l_cl_mult_tck > 20000) ) && ( l_freq_override == 1) ) { + + FAPI_INF( "No Supported CL works for override frequency. Using override frequency with an unsupported CL."); l_override_path = 1; } } @@ -532,8 +556,8 @@ fapi::ReturnCode mss_freq(const fapi::Target &i_target_memb) { return l_rc; } - FAPI_INF( "Successfully Calculated Frequency: %d ", l_selected_dimm_freq); - FAPI_INF( "Successfully Calculated CL: %d ", l_cas_latency); + FAPI_INF( "Final Chosen Frequency: %d ", l_selected_dimm_freq); + FAPI_INF( "Final Chosen CL: %d ", l_cas_latency); for (uint32_t k=0; k < l_mbaChiplets.size(); k++) { l_rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_CL, &l_mbaChiplets[k], l_cas_latency); diff --git a/src/usr/hwpf/hwp/memory_attributes.xml b/src/usr/hwpf/hwp/memory_attributes.xml index 25b2d0f4f..2f11e18c4 100644 --- a/src/usr/hwpf/hwp/memory_attributes.xml +++ b/src/usr/hwpf/hwp/memory_attributes.xml @@ -19,8 +19,8 @@ <!-- --> <!-- Origin: 30 --> <!-- --> -<attributes> <!-- IBM_PROLOG_END_TAG --> +<attributes> <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB --> <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP --> <!-- *********************************************************************** --> @@ -37,7 +37,7 @@ firmware notes: none</description> <odmVisable/> </attribute> - <attribute> +<attribute> <id>ATTR_MSS_FREQ_OVERRIDE</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> <description>FOR LAB USE ONLY: Frequency override of this memory channel in MHz, comprising of up to three DIMMs. Set by config file or an attribute writing program. Consumed by mss_freq. The default of AUTO means mss_freq will find the best frequencies given the DIMMs plugged in and other rules. Otherwise, this is the system frequency. @@ -407,9 +407,9 @@ firmware notes: none</description> <attribute> <id>ATTR_EFF_ODT_RD</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Read ODT. Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: mss_eff_cnfg_termination -consumer: various + <description>Read ODT. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: VPD(MT),mss_eff_cnfg_termination +consumer: various.C files and initfiles firmware notes: none</description> <valueType>uint8</valueType> <writeable/> @@ -421,9 +421,9 @@ firmware notes: none</description> <attribute> <id>ATTR_EFF_ODT_WR</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Write ODT. Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: mss_eff_cnfg_termination -consumer: various + <description>Write ODT. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +Creator: VPD(MT)/ mss_eff_cnfg_termination +consumer: various.C and initfile firmware notes: none</description> <valueType>uint8</valueType> <writeable/> @@ -469,12 +469,13 @@ firmware notes: none</description> <attribute> <id>ATTR_EFF_DRAM_RON</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>DRAM Ron. Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: mss_eff_cnfg_termination -consumer: various + <description>DRAM Ron. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +OHM48 is for DDR4. +creator: VPD(MT)/mss_eff_cnfg_termination +consumer: various.C files (no initfile) firmware notes: none</description> <valueType>uint8</valueType> - <enum>OHM34 = 34, OHM40 = 40</enum> + <enum>OHM34 = 34, OHM40 = 40, OHM48 = 48</enum> <writeable/> <odmVisable/> <odmChangeable/> @@ -484,9 +485,9 @@ firmware notes: none</description> <attribute> <id>ATTR_EFF_DRAM_RTT_NOM</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>DRAM Rtt_Nom. Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: mss_eff_cnfg_termination -consumer: various + <description>DRAM Rtt_Nom. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: VPD(MT),mss_eff_cnfg_termination +consumer: various.C files (no initfiles) firmware notes: none</description> <valueType>uint8</valueType> <enum>DISABLE = 0, OHM20 = 20, OHM30 = 30, OHM34 = 34, OHM40 = 40, OHM48 = 48, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM240 = 240</enum> @@ -499,9 +500,9 @@ firmware notes: none</description> <attribute> <id>ATTR_EFF_DRAM_RTT_WR</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>DRAM Rtt_WR. Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: mss_eff_cnfg_termination -consumer: various + <description>DRAM Rtt_WR. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +Creator: VPD(MT), mss_eff_cnfg_termination +consumer: various.C files (no initfiles) firmware notes: none</description> <valueType>uint8</valueType> <enum>DISABLE = 0, OHM60 = 60, OHM120 = 120</enum> @@ -514,9 +515,9 @@ firmware notes: none</description> <attribute> <id>ATTR_EFF_DRAM_WR_VREF</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>DRAM Write Vref. Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: mss_eff_cnfg_termination -consumer: various + <description>DRAM Write Vref. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: VPD(MT) or mss_eff_cnfg_termination +consumer: various.C and initfile firmware notes: none This is the nominal value This is for DDR3</description> @@ -531,8 +532,8 @@ This is for DDR3</description> <attribute> <id>ATTR_EFF_DRAM_WRDDR4_VREF</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>DRAM Write Vref. Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: mss_eff_cnfg_termination + <description>DRAM Write Vref. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: VPD(MT) or mss_eff_cnfg_termination consumer: various firmware notes: none This is the nominal value @@ -570,9 +571,9 @@ The value is from 0 to 50</description> <attribute> <id>ATTR_EFF_CEN_DRV_IMP_DQ_DQS</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Centaur DQ and DQS Drive Impedance Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: mss_eff_cnfg_termination -consumer: various + <description>Centaur DQ and DQS Drive Impedance Used in various locations and comes from the MT Keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: VPD(MT)/mss_eff_cnfg_termination +consumer: initfile,various.C files firmware notes: none This is the nominal value</description> <valueType>uint8</valueType> @@ -587,9 +588,9 @@ OHM30_FFE480, OHM30_FFE240, OHM30_FFE160, OHM30_FFE120, OHM34_FFE0, OHM34_FFE480 <attribute> <id>ATTR_EFF_CEN_DRV_IMP_ADDR</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Centaur Address Drive Impedance Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. + <description>Centaur Address Drive Impedance Used in various locations andcomes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_termination -consumer: various +consumer: initfile and various.C firmware notes: none This is the nominal value</description> <valueType>uint8</valueType> @@ -603,9 +604,9 @@ This is the nominal value</description> <attribute> <id>ATTR_EFF_CEN_DRV_IMP_CNTL</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Centaur Control Drive Impedance Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: mss_eff_cnfg_termination -consumer: various + <description>Centaur Control Drive Impedance Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: VPD(MT)/mss_eff_cnfg_termination +consumer: initfile,various .C firmware notes: none This is the nominal value</description> <valueType>uint8</valueType> @@ -619,9 +620,9 @@ This is the nominal value</description> <attribute> <id>ATTR_EFF_CEN_DRV_IMP_CLK</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Centaur Clock Drive Impedance Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: mss_eff_cnfg_termination -consumer: various + <description>Centaur Clock Drive Impedance Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: VPD(MT),mss_eff_cnfg_termination +consumer: initfiles,various firmware notes: none This is the nominal value</description> <valueType>uint8</valueType> @@ -635,9 +636,9 @@ This is the nominal value</description> <attribute> <id>ATTR_EFF_CEN_DRV_IMP_SPCKE</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Centaur Spare Clock Drive Impedance Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: mss_eff_cnfg_termination -consumer: various + <description>Centaur Spare Clock Drive Impedance Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: VPD(MT) , mss_eff_cnfg_termination +consumer: initfiles, various.C firmware notes: none This is the nominal value</description> <valueType>uint8</valueType> @@ -697,9 +698,9 @@ This is the nominal value</description> <attribute> <id>ATTR_EFF_CEN_RCV_IMP_DQ_DQS</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Centaur DQ and DQS Receiver Impedance Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: mss_eff_cnfg_termination -consumer: various + <description>Centaur DQ and DQS Receiver Impedance Used in various locations and it comes from the VPD MT keyword for custom DIMMs or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: VPD, mss_eff_cnfg_termination +Consumer: initfile + C code firmware notes: none This is the nominal value</description> <valueType>uint8</valueType> @@ -724,9 +725,9 @@ This is the nominal value</description> <attribute> <id>ATTR_EFF_CEN_SLEW_RATE_DQ_DQS</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Centaur DQ and DQS Slew Rate Used in various locations and is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: mss_eff_cnfg_termination -consumer: various + <description>Centaur DQ and DQS Slew Rate Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: VPD(MT), mss_eff_cnfg_termination +consumer: initfiles,various.C firmware notes: none This is the nominal value</description> <valueType>uint8</valueType> @@ -744,9 +745,9 @@ SLEW_MAXV_NS = 7</enum> <attribute> <id>ATTR_EFF_CEN_SLEW_RATE_ADDR</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Centaur Address Slew Rate Used in various locations and is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: mss_eff_cnfg_termination -consumer: various + <description>Centaur Address Slew Rate Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: VPD(MT),mss_eff_cnfg_termination +consumer: initfile,various .C files firmware notes: none This is the nominal value</description> <valueType>uint8</valueType> @@ -764,9 +765,9 @@ SLEW_MAXV_NS = 7</enum> <attribute> <id>ATTR_EFF_CEN_SLEW_RATE_CLK</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Centaur Clock Slew Rate Used in various locations and is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: mss_eff_cnfg_termination -consumer: various + <description>Centaur Clock Slew Rate Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: VPD(MT)mss_eff_cnfg_termination +consumer: initfile,various.C files firmware notes: none This is the nominal value</description> <valueType>uint8</valueType> @@ -784,9 +785,9 @@ SLEW_MAXV_NS = 7</enum> <attribute> <id>ATTR_EFF_CEN_SLEW_RATE_SPCKE</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Centaur Spare Clock Slew Rate Used in various locations and is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: mss_eff_cnfg_termination -consumer: various + <description>Centaur Spare Clock Slew Rate Used in various locations and comes from the MT keyword or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: VPD(MT) or mss_eff_cnfg_termination +consumer: initfile,various.C firmware notes: none This is the nominal value</description> <valueType>uint8</valueType> @@ -805,9 +806,9 @@ SLEW_MAXV_NS = 7 <attribute> <id>ATTR_EFF_CEN_SLEW_RATE_CNTL</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Centaur Control Slew Rate Used in various locations and is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: mss_eff_cnfg_termination -consumer: various + <description>Centaur Control Slew Rate Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +creator: VPD(MT),mss_eff_cnfg_termination +consumer:initfile, various .C files firmware notes: none This is the nominal value</description> <valueType>uint8</valueType> @@ -881,9 +882,9 @@ SLEW_MAXV_NS = 7 <attribute> <id>ATTR_EFF_CEN_RD_VREF</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Centaur Read Vref. Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. -creator: mss_eff_cnfg_termination -consumer: various + <description>Centaur Read Vref. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. +Creator: VPD(MT) or mss_eff_cnfg_termination +consumer: various.C and initfiles firmware notes: none This is the nominal value</description> <valueType>uint32</valueType> @@ -1819,8 +1820,6 @@ firmware notes: none</description> <persistRuntime/> </attribute> - -<!-- Comment out until HWP integrated that uses these attributes. Platform needs to initialize <attribute> <id>ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA</id> <targetType>TARGET_TYPE_SYSTEM</targetType> @@ -1860,8 +1859,6 @@ firmware notes: none</description> <odmVisable/> </attribute> ---> - <attribute> <id>ATTR_MSS_INTERLEAVE_ENABLE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -1988,6 +1985,440 @@ This factors in functionality</description> </attribute> <attribute> + <id>ATTR_EFF_DRAM_LPASR</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description> Low Power Auto Self-Refresh. This is for DDR4 MRS2. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>MANUAL_NORMAL =0, MANUAL_REDUCED = 1, MANUAL_EXTENDED = 2, ASR = 3</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_MPR_PAGE</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>MPR Page Selection This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_GEARDOWN_MODE</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Gear Down Mode. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>HALF =0, QUARTER=1</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_PER_DRAM_ACCESS</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Per DRAM accessibility. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>ENABLE = 0, DISABLE = 1</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_TEMP_READOUT</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Temperature sensor readout. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>ENABLE = 0, DISABLE = 1</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_FINE_REFRESH_MODE</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Fine refresh mode. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>FIXED_2X = 0, FIXED_4X = 1, FLY_2X = 2, FLY_4X = 3, NORMAL = 4</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_CRC_WR_LATENCY</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>write latency for CRC and DM. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>4NCK = 0, 5NCK = 2, 6NCK = 3</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_MPR_RD_FORMAT</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>MPR READ FORMAT. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>SERIAL = 0, PARALLEL = 1, STAGGERED = 2, RESERVED_TEMP= 3</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_MAX_POWERDOWN_MODE</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Max Power down mode. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>ENABLE = 0, DISABLE = 1</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_TEMP_REF_RANGE</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Temp ref range. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>NORMAL = 0, EXTEND = 1</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_TEMP_REF_MODE</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Temp controlled ref mode. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>ENABLE = 0, DISABLE = 1</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_INT_VREF_MON</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Internal Vref Monitor.. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>ENABLE = 0, DISABLE = 1</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_CS_CMD_LATENCY</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>CS to CMD/ADDR Latency. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_SELF_REF_ABORT</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Self Refresh Abort. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>ENABLE = 0, DISABLE = 1</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_RD_PREAMBLE_TRAIN</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Read Pre amble Training Mode. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>ENABLE = 0, DISABLE = 1</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_RD_PREAMBLE</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Read Pre amble. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>1NCLK = 0, 2NCLK = 1</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_WR_PREAMBLE</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Write Pre amble. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>1NCLK = 0, 2NCLK = 1</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_CA_PARITY_LATENCY</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>C/A Parity Latency Mode. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>DISABLE = 0</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_CRC_ERROR_CLEAR</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>CRC Error Clear. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>ERROR = 0, CLEAR = 1</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_CA_PARITY_ERROR_STATUS</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>C/A Parity Error Status. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>ERROR = 0, CLEAR = 1</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_ODT_INPUT_BUFF</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>ODT Input Buffer during power down. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>ACTIVATED = 0, DEACTIVATED = 1</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_RTT_PARK</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>RTT_Park value. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>DISABLE = 0, 60OHM = 1, 40OHM = 2, 120OHM = 3, 240OHM = 4, 48OHM = 5, 80OHM = 6, 34OHM = 7</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2 4</array> +</attribute> + +<attribute> + <id>ATTR_EFF_CA_PARITY</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>CA Parity Persistance Error. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>ENABLE = 0, DISABLE = 1</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_DATA_MASK</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Data Mask. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>DISABLE = 0, ENABLE = 1</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_WRITE_DBI</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Write DBI. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>DISABLE = 0, ENABLE = 1</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_READ_DBI</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Read DBI. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. +creator: mss_eff_cnfg +consumer: various +firmware notes: none</description> + <valueType>uint8</valueType> + <enum>DISABLE = 0, ENABLE = 1</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_VREF_DQ_TRAIN_VALUE</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>vrefdq_train value. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value. +Creator: mss_eff_cnfg +Consumer:various +Firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2 4</array> +</attribute> + +<attribute> + <id>ATTR_VREF_DQ_TRAIN_RANGE</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>vrefdq_train range. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value. +Creator: mss_eff_cnfg +Consumer:various +Firmware notes: none</description> + <valueType>uint8</valueType> + <enum>RANGE1 = 0, RANGE2 = 1</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2 4</array> +</attribute> + +<attribute> + <id>ATTR_VREF_DQ_TRAIN_ENABLE</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>vrefdq_train enable. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value. +Creator: mss_eff_cnfg +Consumer:various +Firmware notes: none</description> + <valueType>uint8</valueType> + <enum>ENABLE = 0, DISABLE = 1</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2 2 4</array> +</attribute> + +<attribute> + <id>ATTR_TCCD_L</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>tccd_l. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value. +Creator: mss_eff_cnfg +Consumer:various +Firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> + <id>ATTR_EFF_WRITE_CRC</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Write CRC control for DDR4. Set in mss_eff_cnfg. Each memory channel will have a value. +Creator: mss_eff_cnfg +Consumer:various +Firmware notes: none</description> + <valueType>uint8</valueType> + <enum>ENABLE = 0, DISABLE = 1</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> + +<attribute> <id>ATTR_MSS_CAL_STEP_ENABLE</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> <description>A bit vector denoting valid cal steps to run during dram_init_train. [0] EXT_ZQCAL @@ -2040,10 +2471,11 @@ bits6:7 will be consumed together to form COARSE_LVL. </description> </attribute> <attribute> - <id>ATTR_MSS_ECID</id> + <id>ATTR_ECID</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> <description>Bits 0 to 63 of the ECID in array entry 0 and bits 64 to 127 in ECID array entry 1 -Created from running the mss_get_cen_ecid.C</description> +Created from running the mss_get_cen_ecid.C +Firmware shares some code with the processor, so the attribute is named so they can point at a target and have common function.</description> <valueType>uint64</valueType> <writeable/> <odmVisable/> @@ -2063,27 +2495,10 @@ Created from running the mss_get_cen_ecid.C</description> <odmChangeable/> </attribute> -<!-- Comment out until HWP integrated that uses this attribute. Platform needs to initialize - At first glance, this looks like it could be a Chip EC Feature Attribute - -<attribute> - <id>ATTR_MSS_CONTINUE_ON_DP18_PLL_LOCK_FAIL</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Controls the ddr_phy_reset procedure. When set to TRUE, the procedure will continue with processing other DP18 blocks, if one fails. In DD2, this attribute must be set to false so that the failing hardware (centaur) is marked as bad and not the DIMM. Set by firwmare using the EC level or by a MRW</description> - <valueType>uint8</valueType> - <enum>FALSE = 0, TRUE = 1</enum> - <platInit/> - <writeable/> - <odmVisable/> - <odmChangeable/> -</attribute> - ---> - <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M0_CLK_P0</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CLK_P0</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2095,7 +2510,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M0_CLK_P1</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CLK_P1</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2107,7 +2522,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M1_CLK_P0</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CLK_P0</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2119,7 +2534,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M1_CLK_P1</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CLK_P1</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2131,7 +2546,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_CMD_A0</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A0</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2143,7 +2558,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_CMD_A1</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A1</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2155,7 +2570,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_CMD_A2</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A2</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2167,7 +2582,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_CMD_A3</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A3</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2179,7 +2594,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_CMD_A4</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A4</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2191,7 +2606,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_CMD_A5</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A5</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2203,7 +2618,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_CMD_A6</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A6</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2215,7 +2630,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_CMD_A7</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A7</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2227,7 +2642,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_CMD_A8</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A8</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2239,7 +2654,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_CMD_A9</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A9</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2251,7 +2666,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_CMD_A10</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A10</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2263,7 +2678,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_CMD_A11</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A11</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2275,7 +2690,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_CMD_A12</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A12</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2287,7 +2702,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_CMD_A13</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A13</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2299,7 +2714,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_CMD_A14</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A14</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2311,7 +2726,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_CMD_A15</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A15</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2323,7 +2738,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_CMD_BA0</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_BA0</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2335,7 +2750,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_CMD_BA1</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_BA1</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2347,7 +2762,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_CMD_BA2</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_BA2</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2359,7 +2774,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_CMD_CASN</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_CASN</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2371,7 +2786,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_CMD_RASN</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_RASN</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2383,7 +2798,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_CMD_WEN</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_WEN</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2395,7 +2810,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_PAR</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_PAR</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_PAR</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2407,7 +2822,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M_ACTN</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M_ACTN</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_ACTN</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2419,7 +2834,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M0_CNTL_CKE0</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CKE0</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2431,7 +2846,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M0_CNTL_CKE1</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CKE1</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2443,7 +2858,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M0_CNTL_CKE2</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CKE2</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2455,7 +2870,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M0_CNTL_CKE3</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CKE3</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2467,7 +2882,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M0_CNTL_CSN0</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CSN0</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2479,7 +2894,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M0_CNTL_CSN1</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CSN1</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2491,7 +2906,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M0_CNTL_CSN2</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CSN2</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2503,7 +2918,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M0_CNTL_CSN3</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CSN3</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2515,7 +2930,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M0_CNTL_ODT0</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_ODT0</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2527,7 +2942,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M0_CNTL_ODT1</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_ODT1</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2539,7 +2954,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M1_CNTL_CKE0</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CKE0</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2551,7 +2966,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M1_CNTL_CKE1</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CKE1</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2563,7 +2978,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M1_CNTL_CKE2</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CKE2</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2575,7 +2990,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M1_CNTL_CKE3</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CKE3</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2587,7 +3002,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M1_CNTL_CSN0</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CSN0</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2599,7 +3014,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M1_CNTL_CSN1</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CSN1</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2611,7 +3026,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M1_CNTL_CSN2</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CSN2</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2623,7 +3038,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M1_CNTL_CSN3</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CSN3</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2635,7 +3050,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M1_CNTL_ODT0</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_ODT0</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2647,7 +3062,7 @@ Created from running the mss_get_cen_ecid.C</description> <attribute> <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>Phase rotator value that comes from termination on the CDIMM VPD. This controls the IO M1_CNTL_ODT1</description> + <description>Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_ODT1</description> <valueType>uint8</valueType> <platInit/> <writeable/> @@ -2692,24 +3107,33 @@ Created from running the mss_get_cen_ecid.C</description> <description>Set by the platform depending on DD1 vs DD1.01. If true, then SI settings affected by the NWELL problem are adjusted. Used in eff_config</description> <valueType>uint8</valueType> <enum>FALSE = 0, TRUE = 1</enum> - <platInit/> + <writeable/> <odmVisable/> </attribute> -<!-- Comment out until HWP integrated that uses these attributes. Platform needs to initialize +<attribute> + <id>ATTR_EFF_DRAM_2N_MODE_ENABLED</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Describes if this MBA is in 2N address mode. The DIMM attributes associated with this MBA describes if this mode is needed for SI. The MR Keyword of the VPD gives and indication of the value needed. Set by eff_config and consumed in the mba_def.initfile.</description> + <valueType>uint8</valueType> + <enum>FALSE = 0, TRUE = 1</enum> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> <attribute> - <id>ATTR_MSS_READ_PHASE_SELECT</id> + <id>ATTR_MSS_DIMM_POWER_TEST_REV</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> - <description>Set by the platform depending on DD1 vs DD1.01. If true, then training and periodic training needs to make adjustments to the read phase select.</description> + <description>The power test revision number that is saved when data is saved on an ISDIMM. If the power test changes, then a difference indicates that the power test needs to be rerun. This attribute needs to stick around between IPLs</description> <valueType>uint8</valueType> - <enum>FALSE =0, TRUE = 1</enum> <platInit/> + <writeable/> <odmVisable/> + <odmChangeable/> + <persistent/> </attribute> ---> - <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB --> <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP --> </attributes> diff --git a/src/usr/hwpf/hwp/proc_chip_ec_feature.xml b/src/usr/hwpf/hwp/proc_chip_ec_feature.xml new file mode 100644 index 000000000..8edceccf9 --- /dev/null +++ b/src/usr/hwpf/hwp/proc_chip_ec_feature.xml @@ -0,0 +1,130 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/proc_chip_ec_feature.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<attributes> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW_BUG_PIBSLVRESET</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_MURANO</name> + <ec> + <value>0x10</value> + <test>EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW_BUG_PLLINIT</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_MURANO</name> + <ec> + <value>0x11</value> + <test>LESS_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_SECURE_IOVALID_PRESENT</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Returns if a chip contains secure iovalid controls for the ABUS. True if either: + Murano EC 0x20 or greater + Venice EC 0x10 or greater + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_MURANO</name> + <ec> + <value>0x20</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_VENICE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_NOT_SUPPORT_SBE_CFAM_START</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Returns if a chip does not support SBE cfam start. True if: + Murano EC less than 0x20 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_MURANO</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_NOT_SUPPORT_SBE_AUTO_START</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Returns if a chip does not support SBE auto start. True if: + Murano EC less than 0x20 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_MURANO</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_32_PCIE_LANES</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Returns if a chip contains 32 lanes of PCIE I/O. True if: + Venice EC 0x10 or greater + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_VENICE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> +</attributes> diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_check_slave_sbe_seeprom_complete.C b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_check_slave_sbe_seeprom_complete.C index af5863924..001bc7427 100644 --- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_check_slave_sbe_seeprom_complete.C +++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_check_slave_sbe_seeprom_complete.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -21,7 +21,7 @@ /* */ /* IBM_PROLOG_END_TAG */ // -*- mode: C++; c-file-style: "linux"; -*- -// $Id: proc_check_slave_sbe_seeprom_complete.C,v 1.5 2012/11/13 21:00:34 jeshua Exp $ +// $Id: proc_check_slave_sbe_seeprom_complete.C,v 1.6 2013/02/06 04:14:57 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_check_slave_sbe_seeprom_complete.C,v $ //------------------------------------------------------------------------------ // *| @@ -309,7 +309,8 @@ extern "C" //Did it stop in the correct istep? if(( istep_num != PROC_SBE_CHECK_MASTER_ISTEP_NUM ) && - ( istep_num != PROC_SBE_ENABLE_PNOR_ISTEP_NUM )) + ( istep_num != PROC_SBE_ENABLE_PNOR_ISTEP_NUM ) && + ( istep_num != PROC_SBE_EX_HOST_RUNTIME_SCOM_ISTEP_NUM )) { FAPI_ERR( "SBE halted in wrong istep (istep 0x%X, substep %i)", diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C index a38d121f7..cb8597118 100644 --- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C +++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -21,7 +21,7 @@ /* */ /* IBM_PROLOG_END_TAG */ // -*- mode: C++; c-file-style: "linux"; -*- -// $Id: proc_extract_sbe_rc.C,v 1.3 2012/10/29 22:06:08 jeshua Exp $ +// $Id: proc_extract_sbe_rc.C,v 1.4 2012/11/13 21:00:34 jeshua Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_sbe_rc.C,v $ //------------------------------------------------------------------------------ // *| @@ -149,7 +149,7 @@ extern "C" i_use_secondary = true; } - FAPI_PLAT_EXEC_HWP(rc, proc_read_seeprom, i_target, + FAPI_EXEC_HWP(rc, proc_read_seeprom, i_target, i_start_addr, i_length, i_ecc_disable, &error_code_64, i_use_secondary); @@ -175,7 +175,7 @@ extern "C" // uint32_t i_length = 8; // //JDS TODO - figure out how to get ECC status // bool i_ecc_disable = false; -// FAPI_PLAT_EXEC_HWP(rc, proc_read_pibmem, i_target, +// FAPI_EXEC_HWP(rc, proc_read_pibmem, i_target, // i_start_addr, i_length, // i_ecc_disable, &error_code_64); // if(rc) @@ -198,7 +198,7 @@ extern "C" // uint32_t i_length = 8; // //JDS TODO - figure out how to get ECC status // bool i_ecc_disable = false; -// FAPI_PLAT_EXEC_HWP(rc, proc_read_otprom, i_target, +// FAPI_EXEC_HWP(rc, proc_read_otprom, i_target, // i_start_addr, i_length, // i_ecc_disable, &error_code_64); // if(rc) @@ -228,7 +228,7 @@ extern "C" // JDS TODO - replace this with the official FAPI call // once it exists ////////////////////////////////////////// - FAPI_PLAT_EXEC_HWP(rc, proc_sbe_error, i_target, error_code); + FAPI_EXEC_HWP(rc, proc_sbe_error, i_target, error_code); } while(0); //Make sure the code doesn't return SUCCESS diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_read_seeprom.C b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_read_seeprom.C index d2b715b5a..05c9c4b33 100644 --- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_read_seeprom.C +++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_read_seeprom.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -22,7 +22,7 @@ /* IBM_PROLOG_END_TAG */ // -*- mode: C++; c-file-style: "linux"; -*- -// $Id: proc_read_seeprom.C,v 1.8 2012/10/22 15:28:41 szhong Exp $ +// $Id: proc_read_seeprom.C,v 1.9 2012/11/16 23:44:55 szhong Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/utils/proc_read_seeprom.C,v $ //------------------------------------------------------------------------------ // *| @@ -48,6 +48,17 @@ //------------------------------------------------------------------------------ #include "proc_read_seeprom.H" #include <fapi.H> + +//******************************************************* +//Experiments on s1_e8052 wafer model shows first read takes 29*200000 cycles +//other normal reads takes 19*200000 cycles. +//******************************************************* + +#define TIMEOUT_LIMIT 40 //total time_out: TIMEOUT_LIMIT*LOOP_DELAY_CYCLE or TIMEOUT_LIMIT*LOOP_DELAY_TIME +#define LOOP_DELAY_CYCLE 200000 +#define LOOP_DELAY_TIME 200000 //!!!this number should be rechecked!!! + + //------------------------------------------------------------------------------ // Function definitions //------------------------------------------------------------------------------ @@ -270,8 +281,14 @@ extern "C" //ECC Buffer ecmdDataBufferBase ecc_buff = ecmdDataBufferBase (64); ecmdDataBufferBase vital_reg_buff=ecmdDataBufferBase(64); + + + + + uint64_t ecc_value; + //uint64_t fix_offset=0;//read from logic address of 2000 uint32_t rc_ecmd=0; do { @@ -438,8 +455,11 @@ extern "C" } //Wait until the value is ready to be collected bool is_not_complete = true; + uint16_t counter=0; while(is_not_complete) { + counter++; + //printf( "counter: %d\n",counter); rc = fapiGetScom(i_target, PORE_ECCB_STATUS_REGISTER_READ_0x000C0002, is_ready); if(rc) { @@ -458,6 +478,15 @@ extern "C" break; } } + rc=fapiDelay(LOOP_DELAY_TIME,LOOP_DELAY_CYCLE); + if (rc) break; + + if(counter>TIMEOUT_LIMIT) + { + FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_I2C_COMMAND_COMPLETE_TIME_OUT); + FAPI_ERR("ERROR: I2C_COMMAND_COMPLETE not set, TIME OUT"); + break; + } } if(rc) { diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_read_seeprom_errors.xml b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_read_seeprom_errors.xml index cc6f01fe1..5480ecff0 100644 --- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_read_seeprom_errors.xml +++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_read_seeprom_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> <!-- --> <!-- p1 --> <!-- --> @@ -89,6 +89,11 @@ </hwpError> <!-- *********************************************************************** --> <hwpError> + <rc>RC_PROC_READ_SEEPROM_I2C_COMMAND_COMPLETE_TIME_OUT</rc> + <description>Bit 52 of status register not set and time out after certain time</description> + </hwpError> +<!-- *********************************************************************** --> + <hwpError> <rc>RC_PROC_READ_SEEPROM_I2C_STOP_ERR_BIT_SET</rc> <description>Bit 53 of status register set</description> </hwpError> diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile index dfa61f7f3..484c6929c 100644 --- a/src/usr/hwpf/makefile +++ b/src/usr/hwpf/makefile @@ -113,7 +113,8 @@ HWP_ATTR_XML_FILES = hwp/memory_attributes.xml \ hwp/mcbist_attributes.xml \ hwp/proc_winkle_scan_override_attributes.xml \ hwp/erepair_thresholds.xml \ - hwp/dram_training/mem_pll_setup/memb_pll_ring_attributes.xml + hwp/dram_training/mem_pll_setup/memb_pll_ring_attributes.xml \ + hwp/proc_chip_ec_feature.xml #------------------------------------------------------------------------------ # Initfiles diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index 4462ecbb4..00ed8177e 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -8410,7 +8410,7 @@ bits6:7 will be consumed together to form COARSE_LVL. </description> </attribute> <attribute> - <id>MSS_ECID</id> + <id>ECID</id> <description>Bits 0 to 63 of the ECID in array entry 0 and bits 64 to 127 in ECID array entry 1 Created from running the mss_get_cen_ecid.C</description> <simpleType> @@ -8423,7 +8423,7 @@ Created from running the mss_get_cen_ecid.C</description> <readable/> <writeable/> <hwpfToHbAttrMap> - <id>ATTR_MSS_ECID</id> + <id>ATTR_ECID</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> </attribute> @@ -11324,4 +11324,651 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </hwpfToHbAttrMap> </attribute> +<attribute> + <id>MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA</id> + <description>Machine Readable Workbook safe mode throttle value for numerator cfg_nm_n_per_mba</description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MRW_SAFEMODE_MEM_THROTTLE_DENOMINATOR</id> + <description>Machine Readable Workbook safe mode throttle value for denominator cfg_nm_m</description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_MRW_SAFEMODE_MEM_THROTTLE_DENOMINATOR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP</id> + <description>Machine Readable Workbook safe mode throttle value for numerator cfg_nm_n_per_chip</description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MRW_THERMAL_MEMORY_POWER_LIMIT</id> + <description>Machine Readable Workbook Thermal Memory Power Limit</description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_MRW_THERMAL_MEMORY_POWER_LIMIT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_LPASR</id> + <description> Low Power Auto Self-Refresh. This is for DDR4 MRS2. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_LPASR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_MPR_PAGE</id> + <description>MPR Page Selection This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_MPR_PAGE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_GEARDOWN_MODE</id> + <description>Gear Down Mode. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_GEARDOWN_MODE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_PER_DRAM_ACCESS</id> + <description>Per DRAM accessibility. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_PER_DRAM_ACCESS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_TEMP_READOUT</id> + <description>Temperature sensor readout. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_TEMP_READOUT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_FINE_REFRESH_MODE</id> + <description>Fine refresh mode. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_FINE_REFRESH_MODE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_CRC_WR_LATENCY</id> + <description>write latency for CRC and DM. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_CRC_WR_LATENCY</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_MPR_RD_FORMAT</id> + <description>MPR READ FORMAT. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_MPR_RD_FORMAT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_MAX_POWERDOWN_MODE</id> + <description>Max Power down mode. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_MAX_POWERDOWN_MODE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_TEMP_REF_RANGE</id> + <description>Temp ref range. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_TEMP_REF_RANGE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_TEMP_REF_MODE</id> + <description>Temp controlled ref mode. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_TEMP_REF_MODE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_INT_VREF_MON</id> + <description>Internal Vref Monitor.. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_INT_VREF_MON</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_CS_CMD_LATENCY</id> + <description>CS to CMD/ADDR Latency. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_CS_CMD_LATENCY</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_SELF_REF_ABORT</id> + <description>Self Refresh Abort. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_SELF_REF_ABORT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_RD_PREAMBLE_TRAIN</id> + <description>Read Pre amble Training Mode. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_RD_PREAMBLE_TRAIN</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_RD_PREAMBLE</id> + <description>Read Pre amble. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_RD_PREAMBLE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_WR_PREAMBLE</id> + <description>Write Pre amble. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_WR_PREAMBLE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_CA_PARITY_LATENCY</id> + <description>C/A Parity Latency Mode. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_CA_PARITY_LATENCY</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_CRC_ERROR_CLEAR</id> + <description>CRC Error Clear. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_CRC_ERROR_CLEAR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_CA_PARITY_ERROR_STATUS</id> + <description>C/A Parity Error Status. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_CA_PARITY_ERROR_STATUS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_ODT_INPUT_BUFF</id> + <description>ODT Input Buffer during power down. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_ODT_INPUT_BUFF</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_RTT_PARK</id> + <description>RTT_Park value. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_RTT_PARK</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_CA_PARITY</id> + <description>CA Parity Persistance Error. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_CA_PARITY</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DATA_MASK</id> + <description>Data Mask. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DATA_MASK</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_WRITE_DBI</id> + <description>Write DBI. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_WRITE_DBI</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_READ_DBI</id> + <description>Read DBI. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_READ_DBI</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>VREF_DQ_TRAIN_VALUE</id> + <description>vrefdq_train value. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + <array>2,2,4</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_VREF_DQ_TRAIN_VALUE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>VREF_DQ_TRAIN_RANGE</id> + <description>vrefdq_train range. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + <array>2,2,4</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_VREF_DQ_TRAIN_RANGE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>VREF_DQ_TRAIN_ENABLE</id> + <description>vrefdq_train enable. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + <array>2,2,4</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_VREF_DQ_TRAIN_ENABLE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>TCCD_L</id> + <description>tccd_l. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_TCCD_L</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_WRITE_CRC</id> + <description>Write CRC control for DDR4. Set in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_WRITE_CRC</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DRAM_2N_MODE_ENABLED</id> + <description>Describes if this MBA is in 2N address mode. The DIMM attributes associated with this MBA describes if this mode is needed for SI. The MR Keyword of the VPD gives and indication of the value needed. Set by eff_config and consumed in the mba_def.initfile.</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DRAM_2N_MODE_ENABLED</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_DIMM_POWER_TEST_REV</id> + <description>The power test revision number that is saved when data is saved on an ISDIMM. If the power test changes, then a difference indicates that the power test needs to be rerun. This attribute needs to stick around between IPLs</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_DIMM_POWER_TEST_REV</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + </attributes> diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index f19e47c1d..68f05f371 100644 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -164,9 +164,11 @@ <attribute><id>MAX_CHIPLETS_PER_PROC</id></attribute> <attribute><id>MAX_MCS_PER_SYSTEM</id></attribute> <!-- End max/min config attributes --> - <attribute><id>PROC_PBIEX_ASYNC_SEL</id></attribute> - + <attribute><id>MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA</id></attribute> + <attribute><id>MRW_SAFEMODE_MEM_THROTTLE_DENOMINATOR</id></attribute> + <attribute><id>MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP</id></attribute> + <attribute><id>MRW_THERMAL_MEMORY_POWER_LIMIT</id></attribute> </targetType> <targetType> @@ -904,6 +906,37 @@ <attribute><id>MCBIST_ADDR_SLAVE_RANK_ON</id></attribute> <attribute><id>MCBIST_ADDR_STR_MAP</id></attribute> <attribute><id>MCBIST_ADDR_RAND</id></attribute> + <attribute><id>EFF_DRAM_LPASR</id></attribute> + <attribute><id>EFF_MPR_PAGE</id></attribute> + <attribute><id>EFF_GEARDOWN_MODE</id></attribute> + <attribute><id>EFF_PER_DRAM_ACCESS</id></attribute> + <attribute><id>EFF_TEMP_READOUT</id></attribute> + <attribute><id>EFF_FINE_REFRESH_MODE</id></attribute> + <attribute><id>EFF_MPR_RD_FORMAT</id></attribute> + <attribute><id>EFF_MAX_POWERDOWN_MODE</id></attribute> + <attribute><id>EFF_TEMP_REF_RANGE</id></attribute> + <attribute><id>EFF_TEMP_REF_MODE</id></attribute> + <attribute><id>EFF_INT_VREF_MON</id></attribute> + <attribute><id>EFF_CS_CMD_LATENCY</id></attribute> + <attribute><id>EFF_SELF_REF_ABORT</id></attribute> + <attribute><id>EFF_RD_PREAMBLE_TRAIN</id></attribute> + <attribute><id>EFF_RD_PREAMBLE</id></attribute> + <attribute><id>EFF_WR_PREAMBLE</id></attribute> + <attribute><id>EFF_CA_PARITY_LATENCY</id></attribute> + <attribute><id>EFF_CRC_ERROR_CLEAR</id></attribute> + <attribute><id>EFF_CA_PARITY_ERROR_STATUS</id></attribute> + <attribute><id>EFF_ODT_INPUT_BUFF</id></attribute> + <attribute><id>EFF_RTT_PARK</id></attribute> + <attribute><id>EFF_CA_PARITY</id></attribute> + <attribute><id>EFF_DATA_MASK</id></attribute> + <attribute><id>EFF_WRITE_DBI</id></attribute> + <attribute><id>EFF_READ_DBI</id></attribute> + <attribute><id>VREF_DQ_TRAIN_VALUE</id></attribute> + <attribute><id>VREF_DQ_TRAIN_RANGE</id></attribute> + <attribute><id>VREF_DQ_TRAIN_ENABLE</id></attribute> + <attribute><id>TCCD_L</id></attribute> + <attribute><id>EFF_WRITE_CRC</id></attribute> + <attribute><id>EFF_DRAM_2N_MODE_ENABLED</id></attribute> </targetType> <targetType> @@ -1015,7 +1048,7 @@ <attribute><id>MSS_VOLT</id></attribute> <attribute><id>MSS_FREQ</id></attribute> <attribute><id>MSS_LAB_OVERRIDE_FOR_MEM_PLL</id></attribute> - <attribute><id>MSS_ECID</id></attribute> + <attribute><id>ECID</id></attribute> <attribute><id>EI_BUS_RX_MSB_LSB_SWAP</id></attribute> <attribute><id>EI_BUS_TX_MSB_LSB_SWAP</id></attribute> <attribute> |
