diff options
Diffstat (limited to 'src/usr/pore/poreve/porevesrc/bus.C')
| -rw-r--r-- | src/usr/pore/poreve/porevesrc/bus.C | 621 |
1 files changed, 335 insertions, 286 deletions
diff --git a/src/usr/pore/poreve/porevesrc/bus.C b/src/usr/pore/poreve/porevesrc/bus.C index beabe7241..ec3b49184 100644 --- a/src/usr/pore/poreve/porevesrc/bus.C +++ b/src/usr/pore/poreve/porevesrc/bus.C @@ -1,27 +1,26 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/pore/poreve/porevesrc/bus.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ -// $Id: bus.C,v 1.25 2012/03/20 22:52:49 bcbrock Exp $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/poreve/porevesrc/bus.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: bus.C,v 1.31 2012/12/06 18:03:50 bcbrock Exp $ /// \file bus.C /// \brief PoreVe bus and base device models @@ -30,14 +29,13 @@ #include <fapi.H> #include <transaction.H> - - using namespace vsbe; +using namespace fapi; //----------------------------------------------------------------------------- Bus::Bus() : - iv_primarySlaves(NULL), - iv_secondarySlaves(NULL) + iv_primarySlaves(0), + iv_secondarySlaves(0) { } @@ -53,9 +51,7 @@ Bus::attachPrimarySlave(Slave* i_slave) if( iv_primarySlaves == 0 ) { i_slave->iv_next = 0; - } - else - { + }else{ i_slave->iv_next = iv_primarySlaves; } iv_primarySlaves = i_slave; @@ -68,9 +64,7 @@ Bus::attachSecondarySlave(Slave* i_slave) if( iv_secondarySlaves == 0 ) { i_slave->iv_next = 0; - } - else - { + }else{ i_slave->iv_next = iv_secondarySlaves; } iv_secondarySlaves = i_slave; @@ -78,6 +72,53 @@ Bus::attachSecondarySlave(Slave* i_slave) //----------------------------------------------------------------------------- +ModelError +Bus::removeSlaveFromList(Slave* i_slave, Slave** i_slaves) +{ + ModelError me; + Slave** slavePtr; + Slave* thisSlave; + + slavePtr = i_slaves; + me = ME_FAILURE; + + while ((slavePtr != 0) && (*slavePtr != 0)) { + + thisSlave = *slavePtr; + + if (thisSlave == i_slave) { + + *slavePtr = thisSlave->iv_next; + thisSlave->iv_next = 0; + me = ME_SUCCESS; + break; + + } else { + + slavePtr = &(thisSlave->iv_next); + + } + } + + return me; +} + + +//----------------------------------------------------------------------------- +ModelError +Bus::detachSlave(Slave* i_slave) +{ + ModelError me; + + me = removeSlaveFromList(i_slave, &iv_primarySlaves); + if (me) { + me = removeSlaveFromList(i_slave, &iv_secondarySlaves); + } + return me; +} + + +//----------------------------------------------------------------------------- fapi::ReturnCode Bus::operation(Transaction& trans) { @@ -88,57 +129,55 @@ Bus::operation(Transaction& trans) { for( slave = iv_primarySlaves; slave; slave = slave->iv_next ) { - if( (trans.iv_address >= slave->iv_base) && - (trans.iv_address < (slave->iv_base + slave->iv_size) ) ) + if( (trans.iv_address >= slave->iv_base) && (trans.iv_address < (slave->iv_base + slave->iv_size) ) ) { - break; // found a primary slave + break; // found a primary slave } } if( slave == 0 ) - { // primary slaves did not hold the transaction address. - // Try using the secondary slaves. - for( slave = iv_secondarySlaves; slave; slave = slave->iv_next ) - { - if( (trans.iv_address >= slave->iv_base) && - (trans.iv_address < (slave->iv_base + slave->iv_size) ) ) - { - break; // found a secondary slave - } - } + { // primary slaves did not hold the transaction address. Try using the secondary slaves. + for( slave = iv_secondarySlaves; slave; slave = slave->iv_next ) + { + if( (trans.iv_address >= slave->iv_base) && (trans.iv_address < (slave->iv_base + slave->iv_size) ) ) + { + break; // found a secondary slave + } + } } break; - } while(0); + }while(1); do { - if( slave == 0 ) // neither primary nor secondary slaves held the addr + if( slave == 0 ) // neither primary nor secondary slaves held the address { - trans.busError(ME_NOT_MAPPED_ON_BUS); - FAPI_SET_HWP_ERROR(rc, RC_POREVE_BUS_ME_NOT_MAPPED_IN_BUS); - break; + trans.busError(ME_NOT_MAPPED_ON_BUS); + FAPI_ERR("No bus slave claimed address 0x%08x\n", trans.iv_address); + FAPI_SET_HWP_ERROR(rc, RC_POREVE_PORE_NOT_MAPPED_ON_BUS); + break; } - if( (trans.iv_mode & slave->iv_permissions) == 0 ) - { + if( (trans.iv_mode & slave->iv_permissions) == 0 ){ + FAPI_ERR("Access denied for address 0x%08x, " + "mode = %d, slave permissions = %d\n", + trans.iv_address, trans.iv_mode, slave->iv_permissions); trans.busError(ME_BUS_SLAVE_PERMISSION_DENIED); - FAPI_SET_HWP_ERROR(rc, RC_POREVE_BUS_ME_NOT_MAPPED_IN_BUS); + FAPI_SET_HWP_ERROR(rc, RC_POREVE_BUS_SLAVE_PERMISSION_DENIED); break; } trans.iv_offset = trans.iv_address - slave->iv_base; rc = slave->operation( trans ); break; - } while(0); + }while(1); return rc; } //----------------------------------------------------------------------------- Slave::Slave() -:iv_base(0), iv_size(0), iv_permissions(0), -iv_next(NULL), iv_target(NULL), iv_dataBuffer(NULL) { } @@ -176,28 +215,27 @@ PibSlave::operation(Transaction& io_transaction) if ( rc.ok() ) { pt->iv_pcbReturnCode = PCB_SUCCESS; } else { - fapi::ReturnCode rc1; if( rc == fapi_PCB_RESOURCE_BUSY ){ pt->iv_pcbReturnCode = PCB_RESOURCE_OCCUPIED; - rc = rc1; + rc = FAPI_RC_SUCCESS; }else if( rc == fapi_PCB_OFFLINE_ERROR ){ pt->iv_pcbReturnCode = PCB_CHIPLET_OFFLINE; - rc = rc1; + rc = FAPI_RC_SUCCESS; }else if( rc == fapi_PCB_PARTIAL_ERROR ){ pt->iv_pcbReturnCode = PCB_PARTIAL_GOOD; - rc = rc1; + rc = FAPI_RC_SUCCESS; }else if( rc == fapi_PCB_ADDRESS_ERROR ){ pt->iv_pcbReturnCode = PCB_ADDRESS_ERROR; - rc = rc1; + rc = FAPI_RC_SUCCESS; }else if( rc == fapi_PCB_CLOCK_ERROR ){ pt->iv_pcbReturnCode = PCB_CLOCK_ERROR; - rc = rc1; + rc = FAPI_RC_SUCCESS; }else if( rc == fapi_PCB_PARITY_ERROR ){ pt->iv_pcbReturnCode = PCB_PACKET_ERROR; - rc = rc1; + rc = FAPI_RC_SUCCESS; }else if( rc == fapi_PCB_TIMEOUT_ERROR ){ pt->iv_pcbReturnCode = PCB_TIMEOUT; - rc = rc1; + rc = FAPI_RC_SUCCESS; }else{ pt->iv_pcbReturnCode = PCB_TIMEOUT; } @@ -236,9 +274,9 @@ fapi::ReturnCode PibSlave::getScom(const uint32_t i_offset, uint64_t& o_data) { fapi::ReturnCode rc; - ecmdDataBufferBase l_dataBuffer; - rc = fapiGetScom( *iv_target, i_offset, l_dataBuffer ); - o_data = l_dataBuffer.getDoubleWord( 0 ); + + rc = fapiGetScom( *iv_target, i_offset, *iv_dataBuffer ); + o_data = iv_dataBuffer->getDoubleWord( 0 ); return rc; } @@ -248,10 +286,10 @@ fapi::ReturnCode PibSlave::putScom(const uint32_t i_offset, const uint64_t i_data) { fapi::ReturnCode rc; - ecmdDataBufferBase l_dataBuffer(64); - l_dataBuffer.setDoubleWord( 0, i_data ); - rc = fapiPutScom( *iv_target, i_offset, l_dataBuffer ); + iv_dataBuffer->setDoubleWordLength( 1 ); + iv_dataBuffer->setDoubleWord( 0, i_data ); + rc = fapiPutScom( *iv_target, i_offset, *iv_dataBuffer ); return rc; } @@ -259,7 +297,7 @@ PibSlave::putScom(const uint32_t i_offset, const uint64_t i_data) //----------------------------------------------------------------------------- PibMemory::PibMemory() : - iv_passThrough(false), iv_memory(NULL) + iv_passThrough(false) { } @@ -303,13 +341,9 @@ PibMemory::operation(Transaction& io_transaction) fapi::ReturnCode rc; ModelError me; - FAPI_SET_HWP_ERROR(rc, RC_POREVE_PIBMEM_OPERATION_ERROR); - if( io_transaction.iv_mode & ACCESS_MODE_READ ) { - me = iv_memory->read( - (uint32_t)(io_transaction.iv_offset * TRANSACTION_SIZE_IN_BYTES), - io_transaction.iv_data, TRANSACTION_SIZE_IN_BYTES ); + me = iv_memory->read( (uint32_t)(io_transaction.iv_offset * TRANSACTION_SIZE_IN_BYTES), io_transaction.iv_data, TRANSACTION_SIZE_IN_BYTES ); if( me == ME_NOT_MAPPED_IN_MEMORY && iv_passThrough ) { rc = getScom( io_transaction.iv_address, io_transaction.iv_data ); @@ -321,13 +355,17 @@ PibMemory::operation(Transaction& io_transaction) { me = ME_FAILURE; } + } else if (me) { + FAPI_ERR("Read of PIB memory at address 0x%08x failed", + io_transaction.iv_address); + iv_memory->dump(); + FAPI_SET_HWP_ERROR(rc, RC_POREVE_PIB_MEMORY_ACCESS_ERROR); } + } else if( io_transaction.iv_mode & ACCESS_MODE_WRITE ) { - me = iv_memory->write( - (uint32_t)(io_transaction.iv_offset * TRANSACTION_SIZE_IN_BYTES), - io_transaction.iv_data, TRANSACTION_SIZE_IN_BYTES ); + me = iv_memory->write( (uint32_t)(io_transaction.iv_offset * TRANSACTION_SIZE_IN_BYTES), io_transaction.iv_data, TRANSACTION_SIZE_IN_BYTES ); if( me == ME_NOT_MAPPED_IN_MEMORY && iv_passThrough ) { rc = putScom( io_transaction.iv_address, io_transaction.iv_data ); @@ -339,13 +377,16 @@ PibMemory::operation(Transaction& io_transaction) { me = ME_FAILURE; } + } else if (me) { + FAPI_ERR("Write to PIB memory at address 0x%08x failed", + io_transaction.iv_address); + iv_memory->dump(); + FAPI_SET_HWP_ERROR(rc, RC_POREVE_PIB_MEMORY_ACCESS_ERROR); } } else { - me = iv_memory->fetch( - (uint32_t)(io_transaction.iv_offset * TRANSACTION_SIZE_IN_BYTES), - io_transaction.iv_data, TRANSACTION_SIZE_IN_BYTES ); + me = iv_memory->fetch( (uint32_t)(io_transaction.iv_offset * TRANSACTION_SIZE_IN_BYTES), io_transaction.iv_data, TRANSACTION_SIZE_IN_BYTES ); if( me == ME_NOT_MAPPED_IN_MEMORY && iv_passThrough ) { rc = getScom( io_transaction.iv_address, io_transaction.iv_data ); @@ -357,15 +398,16 @@ PibMemory::operation(Transaction& io_transaction) { me = ME_FAILURE; } + } else if (me) { + FAPI_ERR("Fetch of PIB memory at address 0x%08x failed", + io_transaction.iv_address); + iv_memory->dump(); + FAPI_SET_HWP_ERROR(rc, RC_POREVE_PIB_MEMORY_ACCESS_ERROR); } } io_transaction.busError( me ); - // if read/write failed then rc == RC_PIBMEM_OPERATION_ERROR by default - // if read/write returned ME_NOT_MAPPED_IN_MEMORY && pass through true then - // rc == value returned from putScom or getScom - return rc; } @@ -382,17 +424,6 @@ Memory::Memory() : //----------------------------------------------------------------------------- Memory::~Memory() { - MemoryImage* m1 = iv_images; - while (m1) - { - MemoryImage* m2 = m1->iv_next; - delete m1; - m1 = m2; - if (m2 == iv_images) - { - break; - } - } } //----------------------------------------------------------------------------- @@ -402,20 +433,16 @@ Memory::checkCrc() MemoryImage* mi = iv_images; bool rc = true; - if (iv_images == 0) - { + do{ + + if( mi->checkCrc() == false ) + { rc = false; - } + break; + } + mi = mi->iv_next; - while (rc == true) - { - rc = mi->checkCrc(); - mi = mi->iv_next; - if (mi == iv_images) - { - break; - } - } + }while( mi != iv_images ); return rc; } @@ -439,74 +466,67 @@ Memory::read( o_data = 0; // Assure all bytes are cleared me = ME_SUCCESS; - do - { - if( iv_images == 0 ) + do{ + if( iv_images == 0 ) + { + me = ME_NOT_MAPPED_IN_MEMORY; + break; + } + mi = iv_images; + mi_found = 0; + do{ + + if( (i_offset >= mi->iv_base) && ((i_offset + i_size) <= (mi->iv_base + mi->iv_size) ) ) { - me = ME_NOT_MAPPED_IN_MEMORY; - break; + mi_found= 1; + iv_images = mi; // have the Memory always point to the last MemoryImage that was used + break; // we found a chunk of memory containing the transaction address } - mi = iv_images; - mi_found = 0; - do - { - if( (i_offset >= mi->iv_base) && - ((i_offset + i_size) <= (mi->iv_base + mi->iv_size) ) ) - { - mi_found= 1; - iv_images = mi; // have the Memory always point to the last - // MemoryImage that was used - break; // we found a chunk of memory containing the - // transaction address - } - mi = mi->iv_next; + mi = mi->iv_next; - } while( mi != iv_images ); + }while( mi != iv_images ); - if( ! mi_found ) - { // There was no MemoryImage that contained the transaction address - me = ME_NOT_MAPPED_IN_MEMORY; - break; - } + if( ! mi_found ) + { // There was no MemoryImage that contained the transaction address + me = ME_NOT_MAPPED_IN_MEMORY; + break; + } - if( (mi->iv_permissions & ACCESS_MODE_READ ) == 0 ) - { // The permissions over the memory block do not allow the mode - // being used by the transaction - me = ME_MEMORY_IMAGE_PERMISSION_DENIED; - break; - } + if( (mi->iv_permissions & ACCESS_MODE_READ ) == 0 ) + { // The permissions over the memory block do not allow the mode being used by the transaction + me = ME_MEMORY_IMAGE_PERMISSION_DENIED; + break; + } - // Init the character pointer into the eprom image we are using. - from_ptr = (char*)mi->iv_image + (i_offset - mi->iv_base); + // Init the character pointer into the eprom image we are using. + from_ptr = (char*)mi->iv_image + (i_offset - mi->iv_base); - // Init the character pointer into the o_data buffer. - // Take care of Endianess by moving to one or the other end of the - // buffer as appropriate. + // Init the character pointer into the o_data buffer. + // Take care of Endianess by moving to one or the other end of the buffer as appropriate. #ifdef _BIG_ENDIAN to_ptr = (char*)&o_data + (TRANSACTION_SIZE_IN_BYTES - i_size); #else to_ptr = ((char*)&o_data + i_size -1); #endif - for( cnt = 0; cnt < i_size; cnt++ ) - { - *to_ptr = *from_ptr++; + for( cnt = 0; cnt < i_size; cnt++ ) + { + *to_ptr = *from_ptr++; - // Move the to pointer either forward or backward as appropriate - // for Endianess + // Move the to pointer either forward or backward as appropriate for Endianess #ifdef _BIG_ENDIAN - to_ptr++; + to_ptr++; #else - to_ptr--; + to_ptr--; #endif - } + } - me = ME_SUCCESS; - break; - } while(0); + me = ME_SUCCESS; + break; + }while(1); #if POREVE_STATISTICS - iv_reads++; + iv_reads++; #endif return me; @@ -530,74 +550,67 @@ Memory::fetch( o_data = 0; // Assure all bytes are cleared me = ME_SUCCESS; - do - { - if( iv_images == 0 ) + do{ + if( iv_images == 0 ) + { + me = ME_NOT_MAPPED_IN_MEMORY; + break; + } + mi = iv_images; + mi_found = 0; + do{ + + if( (i_offset >= mi->iv_base) && ((i_offset + i_size) <= (mi->iv_base + mi->iv_size) ) ) { - me = ME_NOT_MAPPED_IN_MEMORY; - break; + mi_found= 1; + iv_images = mi; // have the Memory always point to the last MemoryImage that was used + break; // we found a chunk of memory containing the transaction address } - mi = iv_images; - mi_found = 0; - do - { - if( (i_offset >= mi->iv_base) && - ((i_offset + i_size) <= (mi->iv_base + mi->iv_size) ) ) - { - mi_found= 1; - iv_images = mi; // have the Memory always point to the last - // MemoryImage that was used - break; // we found a chunk of memory containing the - // transaction address - } - mi = mi->iv_next; + mi = mi->iv_next; - } while( mi != iv_images ); + }while( mi != iv_images ); - if( ! mi_found ) - { // There was no MemoryImage that contained the transaction address - me = ME_NOT_MAPPED_IN_MEMORY; - break; - } + if( ! mi_found ) + { // There was no MemoryImage that contained the transaction address + me = ME_NOT_MAPPED_IN_MEMORY; + break; + } - if( (mi->iv_permissions & ACCESS_MODE_EXECUTE ) == 0 ) - { // The permissions over the memory block do not allow the mode - // being used by the transaction - me = ME_MEMORY_IMAGE_PERMISSION_DENIED; - break; - } + if( (mi->iv_permissions & ACCESS_MODE_EXECUTE ) == 0 ) + { // The permissions over the memory block do not allow the mode being used by the transaction + me = ME_MEMORY_IMAGE_PERMISSION_DENIED; + break; + } - // Init the character pointer into the eprom image we are using. - from_ptr = (char*)mi->iv_image + i_offset; + // Init the character pointer into the eprom image we are using. + from_ptr = (char*)mi->iv_image + (i_offset - mi->iv_base); - // Init the character pointer into the o_data buffer. - // Take care of Endianess by moving to one or the other end of the - // buffer as appropriate. + // Init the character pointer into the o_data buffer. + // Take care of Endianess by moving to one or the other end of the buffer as appropriate. #ifdef _BIG_ENDIAN to_ptr = (char*)&o_data + (TRANSACTION_SIZE_IN_BYTES - i_size); #else to_ptr = ((char*)&o_data + i_size -1); #endif - for( cnt = 0; cnt < i_size; cnt++ ) - { - *to_ptr = *from_ptr++; + for( cnt = 0; cnt < i_size; cnt++ ) + { + *to_ptr = *from_ptr++; - // Move the to pointer either forward or backward as appropriate - // for Endianess + // Move the to pointer either forward or backward as appropriate for Endianess #ifdef _BIG_ENDIAN - to_ptr++; + to_ptr++; #else - to_ptr--; + to_ptr--; #endif - } + } - me = ME_SUCCESS; - break; - } while(0); + me = ME_SUCCESS; + break; + }while(1); #if POREVE_STATISTICS - iv_fetches++; + iv_fetches++; #endif return me; @@ -610,8 +623,7 @@ ModelError Memory::write( uint32_t i_offset, // the address in the eprom image uint64_t i_data, // data to write into the eprom image - size_t i_size // number of bytes to write (pretty much going to be - // TRANSACTION_SIZE_IN_BYTES) + size_t i_size // number of bytes to write (pretty much going to be TRANSACTION_SIZE_IN_BYTES) ) { char* to_ptr; @@ -622,75 +634,68 @@ Memory::write( int mi_found; me = ME_SUCCESS; - do - { - if( iv_images == 0 ) + do{ + if( iv_images == 0 ) + { + me = ME_NOT_MAPPED_IN_MEMORY; + break; + } + mi = iv_images; + mi_found = 0; + do{ + + if( (i_offset >= mi->iv_base) && ((i_offset + i_size) <= (mi->iv_base + mi->iv_size) ) ) { - me = ME_NOT_MAPPED_IN_MEMORY; - break; + mi_found= 1; + iv_images = mi; // have the Memory always point to the last MemoryImage that was used + break; // we found a chunk of memory containing the transaction address } - mi = iv_images; - mi_found = 0; - do - { - if( (i_offset >= mi->iv_base) && - ((i_offset + i_size) <= (mi->iv_base + mi->iv_size) ) ) - { - mi_found= 1; - iv_images = mi; // have the Memory always point to the last - // MemoryImage that was used - break; // we found a chunk of memory containing the - // transaction address - } - mi = mi->iv_next; + mi = mi->iv_next; - } while( mi != iv_images ); + }while( mi != iv_images ); - if( ! mi_found ) - { // There was no MemoryImage that contained the transaction address - me = ME_NOT_MAPPED_IN_MEMORY; - break; - } + if( ! mi_found ) + { // There was no MemoryImage that contained the transaction address + me = ME_NOT_MAPPED_IN_MEMORY; + break; + } - if( (mi->iv_permissions & ACCESS_MODE_WRITE ) == 0 ) - { // The permissions over the memory block do not allow the mode - // being used by the transaction - me = ME_MEMORY_IMAGE_PERMISSION_DENIED; - break; - } + if( (mi->iv_permissions & ACCESS_MODE_WRITE ) == 0 ) + { // The permissions over the memory block do not allow the mode being used by the transaction + me = ME_MEMORY_IMAGE_PERMISSION_DENIED; + break; + } - // Init the character pointer into the eprom image we are using. - to_ptr = (char*)mi->iv_image + i_offset; + // Init the character pointer into the eprom image we are using. + to_ptr = (char*)mi->iv_image + (i_offset - mi->iv_base); - // Init the character pointer into the o_data buffer. - // Take care of Endianess by moving to one or the other end of the - // buffer as appropriate. + // Init the character pointer into the o_data buffer. + // Take care of Endianess by moving to one or the other end of the buffer as appropriate. #ifdef _BIG_ENDIAN from_ptr = (char*)&i_data + (TRANSACTION_SIZE_IN_BYTES - i_size); #else from_ptr = ((char*)&i_data + i_size -1); #endif - for( cnt = 0; cnt < i_size; cnt++ ) - { - *to_ptr++ = *from_ptr; + for( cnt = 0; cnt < i_size; cnt++ ) + { + *to_ptr++ = *from_ptr; - // Move the to pointer either forward or backward as appropriate - // for Endianess + // Move the to pointer either forward or backward as appropriate for Endianess #ifdef _BIG_ENDIAN - from_ptr++; + from_ptr++; #else - from_ptr--; + from_ptr--; #endif - } + } - me = ME_SUCCESS; - break; + me = ME_SUCCESS; + break; - } while(0); + }while(1); #if POREVE_STATISTICS - iv_writes++; + iv_writes++; #endif return me; @@ -700,9 +705,8 @@ Memory::write( //----------------------------------------------------------------------------- ModelError Memory::map( - uint32_t i_base, // For direct memory this is the 0 based offset - // from the Slave iv_base - size_t i_size, // Size of this chunk of memory + uint32_t i_base, // For direct memory this is the 0 based offset from the Slave iv_base + size_t i_size, // Size of this chunk of memory int i_permissions, void* i_image, bool i_crcEnable @@ -710,23 +714,20 @@ Memory::map( { ModelError me = ME_SUCCESS; MemoryImage* n; - MemoryImage* mi = new MemoryImage( i_base, i_size, i_permissions, - i_image, i_crcEnable ); + MemoryImage* mi = new MemoryImage( i_base, i_size, i_permissions, i_image, i_crcEnable ); if( iv_images == 0 ) { - iv_images = mi; - mi->iv_next = mi; - } - else - { - n = iv_images->iv_next; - while( n->iv_next != iv_images ) - { - n = n->iv_next; - } - n->iv_next = mi; - mi->iv_next = iv_images; + iv_images = mi; + mi->iv_next = mi; + }else{ + n = iv_images->iv_next; + while( n->iv_next != iv_images ) + { + n = n->iv_next; + } + n->iv_next = mi; + mi->iv_next = iv_images; } return me; @@ -734,6 +735,28 @@ Memory::map( //----------------------------------------------------------------------------- +void +Memory::dump(void) +{ + MemoryImage* image; + + FAPI_ERR("Dump of Memory object %p", this); + if (iv_images == 0) { + + FAPI_ERR("Memory has no MemoryImage attached!"); + + } else { + + image = iv_images; + do { + image->dump(); + image = image->iv_next; + } while (image != iv_images); + } +} + + +//----------------------------------------------------------------------------- #if POREVE_STATISTICS void Memory::resetStatistics() @@ -800,6 +823,26 @@ MemoryImage::checkCrc() } //----------------------------------------------------------------------------- +void +MemoryImage::dump(void) +{ + FAPI_ERR("Dump of MemoryImage object %p\n" + "iv_base : 0x%08x\n" + "iv_size : 0x%zx\n" + "iv_permissions : %s %s %s\n" + "iv_image : %p\n" + "iv_crcEnable : %d\n" + "iv_next : %p", + this, + iv_base, iv_size, + (iv_permissions & ACCESS_MODE_READ) ? "Read" : "", + (iv_permissions & ACCESS_MODE_WRITE) ? "Write" : "", + (iv_permissions & ACCESS_MODE_EXECUTE) ? "Execute" : "", + iv_image, iv_crcEnable, iv_next); +} + + +//----------------------------------------------------------------------------- OciMemory::OciMemory() : iv_passThrough(false) { @@ -846,12 +889,9 @@ OciMemory::operation(Transaction& io_transaction) fapi::ReturnCode rc; ModelError me; - FAPI_SET_HWP_ERROR(rc, RC_POREVE_BUS_OPERATION_ERROR); - if( io_transaction.iv_mode & ACCESS_MODE_READ ) { - me = iv_memory->read( (uint32_t)io_transaction.iv_offset, - io_transaction.iv_data, TRANSACTION_SIZE_IN_BYTES ); + me = iv_memory->read( (uint32_t)io_transaction.iv_offset, io_transaction.iv_data, TRANSACTION_SIZE_IN_BYTES ); if( me == ME_NOT_MAPPED_IN_MEMORY && iv_passThrough ) { rc = read( io_transaction.iv_address, io_transaction.iv_data ); @@ -863,12 +903,16 @@ OciMemory::operation(Transaction& io_transaction) { me = ME_FAILURE; } + } else if (me) { + FAPI_ERR("Read of OCI memory at address 0x%08x failed", + io_transaction.iv_address); + iv_memory->dump(); + FAPI_SET_HWP_ERROR(rc, RC_POREVE_OCI_MEMORY_ACCESS_ERROR); } } else { - me = iv_memory->write( (uint32_t)io_transaction.iv_offset, - io_transaction.iv_data, TRANSACTION_SIZE_IN_BYTES ); + me = iv_memory->write( (uint32_t)io_transaction.iv_offset, io_transaction.iv_data, TRANSACTION_SIZE_IN_BYTES ); if( me == ME_NOT_MAPPED_IN_MEMORY && iv_passThrough ) { rc = write( io_transaction.iv_address, io_transaction.iv_data ); @@ -880,15 +924,16 @@ OciMemory::operation(Transaction& io_transaction) { me = ME_FAILURE; } + } else if (me) { + FAPI_ERR("Write to OCI memory at address 0x%08x failed", + io_transaction.iv_address); + iv_memory->dump(); + FAPI_SET_HWP_ERROR(rc, RC_POREVE_OCI_MEMORY_ACCESS_ERROR); } } io_transaction.busError( me ); - // if read/write failed then rc == RC_BUS_OPERATION_ERROR by default - // if read/write returned ME_NOT_MAPPED_IN_MEMORY && pass through true then - // rc == value returned from putScom or getScom - return rc; } @@ -932,7 +977,9 @@ fapi::ReturnCode OciSlave::read(const uint32_t i_address, uint64_t& o_data) { fapi::ReturnCode rc; - FAPI_SET_HWP_ERROR(rc, RC_POREVE_BUS_OCI_SLAVE_READ_NOT_SUPPORTED); + FAPI_ERR("The OCI slave at address 0x%08x does not " + "implement a read() method\n", i_address); + FAPI_SET_HWP_ERROR(rc, RC_POREVE_OCI_SLAVE_ERROR); return rc; } @@ -941,7 +988,9 @@ fapi::ReturnCode OciSlave::write(const uint32_t i_address, const uint64_t i_data) { fapi::ReturnCode rc; - FAPI_SET_HWP_ERROR(rc, RC_POREVE_BUS_OCI_SLAVE_WRITE_NOT_SUPPORTED); + FAPI_ERR("The OCI slave at address 0x%08x does not " + "implement a write() method\n", i_address); + FAPI_SET_HWP_ERROR(rc, RC_POREVE_OCI_SLAVE_ERROR); return rc; } |
