diff options
34 files changed, 2192 insertions, 1656 deletions
diff --git a/src/build/citest/etc/patches/centaur.act.centaur_sbe_patch b/src/build/citest/etc/patches/centaur.act.centaur_sbe_patch new file mode 100644 index 000000000..52740fa1e --- /dev/null +++ b/src/build/citest/etc/patches/centaur.act.centaur_sbe_patch @@ -0,0 +1,32 @@ +--- centaur.act_build 2013-01-18 10:21:56.829533535 -0600 ++++ centaur.act_new 2013-01-18 10:24:37.680225599 -0600 +@@ -35,6 +35,7 @@ + # SW178996 mjjones 12/13/12 Slew calibration actions + # SW176884 bradleyb 12/15/12 re-enable command complete + # SW180168 vanlee 01/02/13 Centaur Mem PLL lock action ++# SW182865 thi 01/18/13 Action file for Centaur SBE + #******************************************************************** + # + +@@ -350,3 +351,21 @@ + #*************************************** + # END - mem_pll_setup actions + #*************************************** ++ ++#*************************************** ++# BEGIN - SBE Centaur img actions ++#*************************************** ++CAUSE_EFFECT { ++ LABEL=[SBE image: VDD OK] ++ WATCH=[LOGIC(0xFF000008)] # FSI GP3 reg (0x1012) ++ CAUSE: TARGET=[LOGIC(0xFF000008)] OP=[BIT,OFF] BIT=[27] ++ CAUSE: TARGET=[LOGIC(0xFF000008)] OP=[BIT,OFF] BIT=[23] ++ EFFECT: TARGET=[LOGIC(0xFF000100)] OP=[BIT,ON] BIT=[0] ++ EFFECT: TARGET=[LOGIC(0xFF00000F)] OP=[BIT,ON] BIT=[16] ++ # Temporary use this action to turn on Nest PLL lock until Simics creates reg 0x101B ++ EFFECT: TARGET=[LOGIC(0xFF00000F)] OP=[BIT,ON] BIT=[24] ++} ++ ++#*************************************** ++# END - SBE Centaur img actions ++#*************************************** diff --git a/src/build/citest/etc/patches/patchlist.txt b/src/build/citest/etc/patches/patchlist.txt index 67c4cb454..11a1cd440 100644 --- a/src/build/citest/etc/patches/patchlist.txt +++ b/src/build/citest/etc/patches/patchlist.txt @@ -5,10 +5,9 @@ Brief description of the problem or reason for patch -Files: list of files -Coreq: list of associated changes, e.g. workarounds.presimsetup -proc_start_clock_chiplets v1.10 requires some clock bits to be set in the clock status registers -at the time when it runs. Action file need to be updated to set these bits when at the time when -instructions are started --RTC: Task 61816 will remove this patch --CMVC: 865799 --Files: s1.act_proc_start_clock_chiplets.patch +Centaur SBE image requires VDD and Nest PLL lock bits set in 0x1007 reg +Action file need to be updated to set these bits when Centaur SBE code expects them. +-RTC: Task 62644 will remove this patch +-CMVC: SW182865 +-Files: centaur.act.centaur_sbe_patch -Coreq: None
\ No newline at end of file diff --git a/src/build/citest/etc/patches/s1.act.proc_start_clock_chiplets_patch b/src/build/citest/etc/patches/s1.act.proc_start_clock_chiplets_patch deleted file mode 100644 index 1ddb9d540..000000000 --- a/src/build/citest/etc/patches/s1.act.proc_start_clock_chiplets_patch +++ /dev/null @@ -1,13 +0,0 @@ ---- s1.act_sandbox 2013-01-07 14:53:52.585244917 -0600 -+++ s1.act_updated 2013-01-07 14:54:39.095617417 -0600 -@@ -57,7 +57,9 @@ - EFFECT: TARGET=[FSIMBOX(0x1C)] OP=[OR,BUF] DATA=[LITERAL(64,000FFFFF 00000000)] - - #Also has effect of causing clocks on -- EFFECT: TARGET=[REG(0x08030008)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,000007FF FFFFFFFF)] -+ EFFECT: TARGET=[REG(0x08030008)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,007FFFFF FFFFFFFF)] -+ EFFECT: TARGET=[REG(0x04030008)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00003FFF FFFFFFFF)] -+ EFFECT: TARGET=[REG(0x09030008)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,000E07FF FFFFFFFF)] - EFFECT: TARGET=[LOGIC(0xFF000001)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,0xFDB40000 0x00000001)] - EFFECT: TARGET=[LOGIC(0xFF000001)] OP=[BIT,ON] BIT=[17] # EX5 vital - EFFECT: TARGET=[LOGIC(0xFF000001)] OP=[BIT,ON] BIT=[18] # EX5 diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup index c666adb01..66dd3cdbd 100755 --- a/src/build/citest/etc/workarounds.postsimsetup +++ b/src/build/citest/etc/workarounds.postsimsetup @@ -26,10 +26,10 @@ ## to setup the sandbox ## -echo "+++ Updating s1.act" +echo "+++ Updating centaur.act" mkdir -p $sb/simu/data/cec-chip -cp $BACKING_BUILD/src/simu/data/cec-chip/s1.act $sb/simu/data/cec-chip +cp $BACKING_BUILD/src/simu/data/cec-chip/centaur.act $sb/simu/data/cec-chip ## Added action for proc_start_clock_chiplets v1.10 and beyond -echo "+++ Update actions for proc_start_clock_chiplets v1.10" -patch -p0 $sb/simu/data/cec-chip/s1.act $HOSTBOOTROOT/src/build/citest/etc/patches/s1.act.proc_start_clock_chiplets_patch +echo "+++ Update actions for Centaur SBE image" +patch -p0 $sb/simu/data/cec-chip/centaur.act $HOSTBOOTROOT/src/build/citest/etc/patches/centaur.act.centaur_sbe_patch diff --git a/src/usr/hwpf/hwp/poreve_memory_attributes.xml b/src/usr/hwpf/hwp/poreve_memory_attributes.xml new file mode 100644 index 000000000..7e8ae8956 --- /dev/null +++ b/src/usr/hwpf/hwp/poreve_memory_attributes.xml @@ -0,0 +1,113 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/poreve_memory_attributes.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: poreve_memory_attributes.xml,v 1.3 2013/01/04 21:42:27 farrugia Exp $ --> +<!-- + Attributes related to SEEPROM and PNOR configuration required by the + PoreVe + + The PoreVe implements a system model of the PORE-SBE and attached + memory devices that must be configured accoding to the actual chip- and + system-specific configuration in order to correctly execute PORE + firmware. + + Each chip has access to 2 SEEPROM memories containing PORE + code. These memories appear on different I2C addresses and/or I2C + controller ports depending on the chip. The size of the memory + (specified as the number of address bytes) is also a required parameter + of the controller. + + The PNOR memory is managed as a pseudo-I2C device so it also requires + the memory size specification. Only "master" chips in the system have + PNOR memories attached and non-0 memory address-byte specifications. As + a side effect, the PoreVe will only be able to be configured and run + on a chip with a PNOR attached. In the case of the PNOR the I2C device + and port numbers are not required as they are ignored by the PgP + hardware. +--> +<attributes> + <!-- ********************************************************************* + --> + <attribute> + <id>ATTR_SBE_SEEPROM_I2C_ADDRESS_BYTES</id> + <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_MEMBUF_CHIP</targetType> + <description> + The number of address bytes required to address the SEEPROM memory + device that contains SBE IPL code. This will vary by device based on + the device capacity, and must be either 1, 2, 3 or 4. + + Provided by the Machine Readable Workbook + </description> + <valueType>uint8</valueType> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_SBE_SEEPROM_I2C_DEVICE_ADDRESS</id> + <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_MEMBUF_CHIP</targetType> + <description> + A 2-element array containing the I2C device address of the primary (0) + and secondary (1) SEEPROM devices containing SBE IPL code. + + Provided by the Machine Readable Workbook + </description> + <valueType>uint8</valueType> + <array>2</array> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_SBE_SEEPROM_I2C_PORT</id> + <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_MEMBUF_CHIP</targetType> + <description> + A 2-element array containing the I2C controller port number of the + primary (0) and secondary (1) SEEPROM devices containing SBE IPL code. + + Provided by the Machine Readable Workbook + </description> + <valueType>uint8</valueType> + <array>2</array> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PNOR_I2C_ADDRESS_BYTES</id> + <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_MEMBUF_CHIP</targetType> + <description> + The number of address bytes required to address the PNOR memory device + via the pseudo-I2C (LPC, ECCAX) controller. This will vary by device + based on the device capacity, and must be either 0, 1, 2, 3 or 4. + + This attribute will be set to 0 for chips with no PNOR attached + (PoreVe will never run on these chips). + + Provided by the Machine Readable Workbook + </description> + <valueType>uint8</valueType> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> +</attributes> diff --git a/src/usr/hwpf/hwp/sbe_centaur_init/sbe_centaur_init.C b/src/usr/hwpf/hwp/sbe_centaur_init/sbe_centaur_init.C index 12382cd0a..bb7c01138 100644 --- a/src/usr/hwpf/hwp/sbe_centaur_init/sbe_centaur_init.C +++ b/src/usr/hwpf/hwp/sbe_centaur_init/sbe_centaur_init.C @@ -1,26 +1,25 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/hwpf/hwp/sbe_centaur_init/sbe_centaur_init.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/sbe_centaur_init/sbe_centaur_init.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ /** * @file sbe_centaur_init.C * @@ -54,9 +53,10 @@ #include "sbe_centaur_init.H" #include <hwpisteperror.H> -// Extern function declaration extern fapi::ReturnCode fapiPoreVe(const fapi::Target i_target, - std::vector<vsbe::FapiPoreVeArg *> & io_sharedObjectArgs); + std::list<uint64_t> & io_sharedObjectArgs); + + // Constants // Memory Relocation Register for Centaur SBE image const uint64_t CENTAUR_SBE_PNOR_MRR = 0; @@ -132,7 +132,7 @@ void* call_sbe_centaur_init( void *io_pArgs ) } // Setup args - std::vector<FapiPoreVeArg *> myArgs; + std::list<uint64_t> myArgs; // Set FapiPoreVeOtherArg: run unlimited instructions FapiPoreVeOtherArg *l_otherArg = @@ -140,7 +140,7 @@ void* call_sbe_centaur_init( void *io_pArgs ) // Entry point l_otherArg->iv_entryPoint = const_cast<char*>("pnor::_sbe_pnor_start"); l_otherArg->iv_mrr = CENTAUR_SBE_PNOR_MRR; - myArgs.push_back(l_otherArg); + myArgs.push_back(reinterpret_cast<uint64_t>(l_otherArg)); // Set FapiPoreVeMemArg for pnor option, base address = 0 uint32_t base_addr = 0; @@ -148,13 +148,13 @@ void* call_sbe_centaur_init( void *io_pArgs ) FapiPoreVeMemArg* l_memArg = new FapiPoreVeMemArg(ARG_PNOR, base_addr, l_sbePnorSize, static_cast<void*>(l_dataPnor)); - myArgs.push_back(l_memArg); + myArgs.push_back(reinterpret_cast<uint64_t>(l_memArg)); // Create state argument to dump out state for debugging purpose FapiPoreVeStateArg *l_stateArg = new FapiPoreVeStateArg(NULL); l_stateArg->iv_installState = false; l_stateArg->iv_extractState = true; - myArgs.push_back(l_stateArg); + myArgs.push_back(reinterpret_cast<uint64_t>(l_stateArg)); // Loop thru all Centaurs in list for ( size_t i = 0; i < l_membufTargetList.size(); i++ ) diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile index 0cfab7f89..fb3136080 100644 --- a/src/usr/hwpf/makefile +++ b/src/usr/hwpf/makefile @@ -101,7 +101,8 @@ HWP_ATTR_XML_FILES = hwp/memory_attributes.xml \ hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml \ hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr_attributes.xml \ hwp/build_winkle_images/p8_slw_build/proc_pll_ring_attributes.xml \ - hwp/build_winkle_images/p8_slw_build/p8_xip_customize_attributes.xml + hwp/build_winkle_images/p8_slw_build/p8_xip_customize_attributes.xml \ + hwp/poreve_memory_attributes.xml #------------------------------------------------------------------------------ # Initfiles diff --git a/src/usr/pore/fapiporeve/fapiPoreVe.C b/src/usr/pore/fapiporeve/fapiPoreVe.C index e650b28a7..20294d5d3 100644 --- a/src/usr/pore/fapiporeve/fapiPoreVe.C +++ b/src/usr/pore/fapiporeve/fapiPoreVe.C @@ -1,28 +1,27 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/pore/fapiporeve/fapiPoreVe.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/fapiporeve/fapiPoreVe.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ // -*- mode: C++; c-file-style: "linux"; -*- -// $Id: fapiPoreVe.C,v 1.27 2012/04/26 21:30:31 jeshua Exp $ +// $Id: fapiPoreVe.C,v 1.29 2012/09/05 20:11:16 jeshua Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/poreve/working/fapiporeve/fapiPoreVe.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -45,6 +44,7 @@ // Install start state, if passed in // Install hooks // Install each memory image passed in +// Deconfigure missing memories // Set entry point // Set break point // Run the requested number of instructions @@ -64,44 +64,6 @@ //For hooks #ifndef __HOSTBOOT_MODULE #include <dlfcn.h> - -typedef struct { - char * name; - PoreRegisterOffset offset; -} poreReg_t; - -poreReg_t poreRegs[] = { - { "PORE_STATUS", PORE_STATUS }, - { "PORE_CONTROL", PORE_CONTROL }, - { "PORE_RESET", PORE_RESET }, - { "PORE_ERROR_MASK", PORE_ERROR_MASK }, - { "PORE_PRV_BASE_ADDR0", PORE_PRV_BASE_ADDR0 }, - { "PORE_PRV_BASE_ADDR1", PORE_PRV_BASE_ADDR1 }, - { "PORE_OCI_MEMORY_BASE_ADDR0", PORE_OCI_MEMORY_BASE_ADDR0 }, - { "PORE_OCI_MEMORY_BASE_ADDR1", PORE_OCI_MEMORY_BASE_ADDR1 }, - { "PORE_TABLE_BASE_ADDR", PORE_TABLE_BASE_ADDR }, - { "PORE_EXE_TRIGGER", PORE_EXE_TRIGGER }, - { "PORE_SCRATCH0", PORE_SCRATCH0 }, - { "PORE_SCRATCH1", PORE_SCRATCH1 }, - { "PORE_SCRATCH2", PORE_SCRATCH2 }, - { "PORE_IBUF_01", PORE_IBUF_01 }, - { "PORE_IBUF_2", PORE_IBUF_2 }, - { "PORE_DBG0", PORE_DBG0 }, - { "PORE_DBG1", PORE_DBG1 }, - { "PORE_PC_STACK0", PORE_PC_STACK0 }, - { "PORE_PC_STACK1", PORE_PC_STACK1 }, - { "PORE_ID_FLAGS", PORE_ID_FLAGS }, - { "PORE_DATA0", PORE_DATA0 }, - { "PORE_MEM_RELOC", PORE_MEM_RELOC }, - { "PORE_I2C_E0_PARAM", PORE_I2C_E0_PARAM }, - { "PORE_I2C_E1_PARAM", PORE_I2C_E1_PARAM }, - { "PORE_I2C_E2_PARAM", PORE_I2C_E2_PARAM }, - { "PORE_HIDDEN_STATE_0", PORE_HIDDEN_STATE_0 }, - { "PORE_HIDDEN_STATE_1", PORE_HIDDEN_STATE_1 }, - { "PORE_HIDDEN_STATE_2", PORE_HIDDEN_STATE_2 }, - { "PORE_HIDDEN_STATE_3", PORE_HIDDEN_STATE_3 }, - { "PORE_HIDDEN_STATE_4", PORE_HIDDEN_STATE_4 }, -}; #endif #include "hookmanager.H" @@ -119,21 +81,27 @@ const uint32_t MBOX_SBEVITAL_0x0005001C = 0x0005001C; //****************************************************************************** fapi::ReturnCode fapiPoreVe( const fapi::Target i_target, - std::vector<FapiPoreVeArg *> & io_sharedObjectArgs) + std::list<uint64_t> & io_sharedObjectArgs) { - fapi::ReturnCode rc; + fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS; PoreVe *poreve = NULL; FapiPoreVeOtherArg *pOtherArg = NULL; + bool haveOTPROM = false; + bool havePNOR = false; + bool haveSEEPROM = false; + bool haveMAINMEM = false; + bool haveSRAM = false; + bool havePIBMEM = false; //---------------------------------------------------------------------- // Find the PORE type //---------------------------------------------------------------------- - std::vector<FapiPoreVeArg *>::iterator itr; + std::list<uint64_t>::iterator itr; for( itr = io_sharedObjectArgs.begin(); (itr != io_sharedObjectArgs.end()) && (poreve == NULL); itr++ ) { - FapiPoreVeArg *arg = *itr; + FapiPoreVeArg *arg = reinterpret_cast<FapiPoreVeArg *>(*itr); //---------------------------------------------------------------------- // Use PORE type and pdbgArg to create poreve @@ -142,7 +110,7 @@ fapi::ReturnCode fapiPoreVe( { FapiPoreVeOtherArg *thisArg = (FapiPoreVeOtherArg *)arg; pOtherArg = thisArg; - fapi::Target masterTarget = i_target; + fapi::Target masterTarget = i_target; //JDS TODO - get this from an attribute poreve = PoreVe::create( thisArg->iv_poreType, masterTarget, thisArg->iv_pdbgArgs ); @@ -150,10 +118,11 @@ fapi::ReturnCode fapiPoreVe( } if( poreve == NULL ) { - FAPI_ERR( "Failed to create poreve" ); + FAPI_ERR( "Failed to create poreve\n" ); FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_FAILED_TO_CREATE_POREVE); + } else { + rc = poreve->constructorRc(); } - //---------------------------------------------------------------------- // Reset the PoreVe and set slave target @@ -169,7 +138,7 @@ fapi::ReturnCode fapiPoreVe( for( itr = io_sharedObjectArgs.begin(); (itr != io_sharedObjectArgs.end()) && rc.ok(); itr++ ) { - FapiPoreVeArg *arg = *itr; + FapiPoreVeArg *arg = reinterpret_cast<FapiPoreVeArg *>(*itr); //---------------------------------------------------------------------- // Install the start state (if passed in) @@ -192,7 +161,7 @@ fapi::ReturnCode fapiPoreVe( stateArg->iv_fd = fopen( stateArg->iv_filename, "r" ); if( stateArg->iv_fd == NULL ) { - FAPI_ERR( "Failed to open state file %s", + FAPI_ERR( "Failed to open state file %s\n", stateArg->iv_filename ); // char & FILENAME = stateArg->iv_filename; FAPI_SET_HWP_ERROR(rc, @@ -212,18 +181,75 @@ fapi::ReturnCode fapiPoreVe( char* reg = strtok( line, " =" ); PoreRegisterOffset reg_offset; - size_t i = 0; - while (i < (sizeof(poreRegs)/sizeof(poreReg_t))) - { - if( strcmp( reg, poreRegs[i].name ) == 0 ) - { - reg_offset = poreRegs[i].offset; - break; - } - i++; - } - - if (i != (sizeof(poreRegs)/sizeof(poreReg_t))) + if( strcmp( reg, "PORE_STATUS" ) == 0 ) { + reg_offset = PORE_STATUS; + } else if( strcmp( reg, "PORE_CONTROL" ) == 0 ) { + reg_offset = PORE_CONTROL; + } else if( strcmp( reg, "PORE_RESET" ) == 0 ) { + reg_offset = PORE_RESET; + } else if( strcmp( reg, "PORE_ERROR_MASK" ) == 0 ) { + reg_offset = PORE_ERROR_MASK; + } else if( strcmp( reg, "PORE_PRV_BASE_ADDR0" ) == 0 ) { + reg_offset = PORE_PRV_BASE_ADDR0; + } else if( strcmp( reg, "PORE_PRV_BASE_ADDR1" ) == 0 ) { + reg_offset = PORE_PRV_BASE_ADDR1; + } else if( strcmp( reg, "PORE_OCI_MEMORY_BASE_ADDR0" ) == 0 ) { + reg_offset = PORE_OCI_MEMORY_BASE_ADDR0; + } else if( strcmp( reg, "PORE_OCI_MEMORY_BASE_ADDR1" ) == 0 ) { + reg_offset = PORE_OCI_MEMORY_BASE_ADDR1; + } else if( strcmp( reg, "PORE_TABLE_BASE_ADDR" ) == 0 ) { + reg_offset = PORE_TABLE_BASE_ADDR; + } else if( strcmp( reg, "PORE_EXE_TRIGGER" ) == 0 ) { + reg_offset = PORE_EXE_TRIGGER; + } else if( strcmp( reg, "PORE_SCRATCH0" ) == 0 ) { + reg_offset = PORE_SCRATCH0; + } else if( strcmp( reg, "PORE_SCRATCH1" ) == 0 ) { + reg_offset = PORE_SCRATCH1; + } else if( strcmp( reg, "PORE_SCRATCH2" ) == 0 ) { + reg_offset = PORE_SCRATCH2; + } else if( strcmp( reg, "PORE_IBUF_01" ) == 0 ) { + reg_offset = PORE_IBUF_01; + } else if( strcmp( reg, "PORE_IBUF_2" ) == 0 ) { + reg_offset = PORE_IBUF_2; + } else if( strcmp( reg, "PORE_DBG0" ) == 0 ) { + reg_offset = PORE_DBG0; + } else if( strcmp( reg, "PORE_DBG1" ) == 0 ) { + reg_offset = PORE_DBG1; + } else if( strcmp( reg, "PORE_PC_STACK0" ) == 0 ) { + reg_offset = PORE_PC_STACK0; + } else if( strcmp( reg, "PORE_PC_STACK1" ) == 0 ) { + reg_offset = PORE_PC_STACK1; + } else if( strcmp( reg, "PORE_PC_STACK2" ) == 0 ) { + reg_offset = PORE_PC_STACK2; + } else if( strcmp( reg, "PORE_ID_FLAGS" ) == 0 ) { + reg_offset = PORE_ID_FLAGS; + } else if( strcmp( reg, "PORE_DATA0" ) == 0 ) { + reg_offset = PORE_DATA0; + } else if( strcmp( reg, "PORE_MEM_RELOC" ) == 0 ) { + reg_offset = PORE_MEM_RELOC; + } else if( strcmp( reg, "PORE_I2C_E0_PARAM" ) == 0 ) { + reg_offset = PORE_I2C_E0_PARAM; + } else if( strcmp( reg, "PORE_I2C_E1_PARAM" ) == 0 ) { + reg_offset = PORE_I2C_E1_PARAM; + } else if( strcmp( reg, "PORE_I2C_E2_PARAM" ) == 0 ) { + reg_offset = PORE_I2C_E2_PARAM; + } else if( strcmp( reg, "PORE_HIDDEN_STATE_0" ) == 0) { + reg_offset = PORE_HIDDEN_STATE_0; + } else if( strcmp( reg, "PORE_HIDDEN_STATE_1" ) == 0) { + reg_offset = PORE_HIDDEN_STATE_1; + } else if( strcmp( reg, "PORE_HIDDEN_STATE_2" ) == 0) { + reg_offset = PORE_HIDDEN_STATE_2; + } else if( strcmp( reg, "PORE_HIDDEN_STATE_3" ) == 0) { + reg_offset = PORE_HIDDEN_STATE_3; + } else if( strcmp( reg, "PORE_HIDDEN_STATE_4" ) == 0) { + reg_offset = PORE_HIDDEN_STATE_4; + } else { + FAPI_ERR("Unknown reg name %s on line %i\n", + reg, linenum ); + reg = NULL; + } //strcmp reg vs regname + + if( reg != NULL ) { //get the register value char* value = strtok( NULL, " =" ); @@ -247,7 +273,7 @@ fapi::ReturnCode fapiPoreVe( FAPI_ERR( "Error parsing value of %s " "on line %i\n", reg, linenum ); } - } + } //if reg != NULL } //if state_rc != NULL } while ( state_rc != NULL ); //able to read a line fclose( stateArg->iv_fd ); @@ -256,7 +282,7 @@ fapi::ReturnCode fapiPoreVe( else { FAPI_INF( "State pointer was passed in, " - "so not reading state from file" ); + "so not reading state from file\n" ); } #endif if (rc.ok()) @@ -264,7 +290,7 @@ fapi::ReturnCode fapiPoreVe( ModelError me = poreve->iv_pore.installState( *p_state ); if( me != ME_SUCCESS ) { - FAPI_ERR( "Model error installing state. Errno(%i)", + FAPI_ERR( "Model error installing state. Errno(%i)\n", (int)me); ModelError & ERROR = me; FAPI_SET_HWP_ERROR(rc, @@ -317,6 +343,7 @@ fapi::ReturnCode fapiPoreVe( (ACCESS_MODE_READ), thisArg->iv_data, thisArg->iv_crcEnable ); + haveOTPROM = true; } //PNOR @@ -327,6 +354,7 @@ fapi::ReturnCode fapiPoreVe( (ACCESS_MODE_READ|ACCESS_MODE_WRITE), thisArg->iv_data, thisArg->iv_crcEnable ); + havePNOR = true; } //SEEPROM @@ -337,6 +365,7 @@ fapi::ReturnCode fapiPoreVe( (ACCESS_MODE_READ), thisArg->iv_data, thisArg->iv_crcEnable ); + haveSEEPROM = true; } //MAINMEM @@ -347,6 +376,7 @@ fapi::ReturnCode fapiPoreVe( (ACCESS_MODE_READ|ACCESS_MODE_WRITE), thisArg->iv_data, thisArg->iv_crcEnable ); + haveMAINMEM = true; } //SRAM @@ -357,22 +387,24 @@ fapi::ReturnCode fapiPoreVe( (ACCESS_MODE_READ|ACCESS_MODE_WRITE), thisArg->iv_data, thisArg->iv_crcEnable ); + haveSRAM = true; } //PIBMEM else if( thisArg->iv_type == ARG_PIBMEM ) { poreve->iv_pibmemMemory.map( thisArg->iv_base, - thisArg->iv_size, - (ACCESS_MODE_READ|ACCESS_MODE_WRITE), - thisArg->iv_data, - thisArg->iv_crcEnable ); + thisArg->iv_size, + (ACCESS_MODE_READ|ACCESS_MODE_WRITE), + thisArg->iv_data, + thisArg->iv_crcEnable ); + havePIBMEM = true; } //Unknown type else if( thisArg->iv_type != ARG_OTHER ) { - FAPI_ERR( "Got an arg of an unknown type"); + FAPI_ERR( "Got an arg of an unknown type (type=%d)\n", thisArg->iv_type); FapiPoreVeArg_t const& TYPE = thisArg->iv_type; FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_UNKNOWN_ARG_TYPE); } @@ -380,11 +412,85 @@ fapi::ReturnCode fapiPoreVe( } //end parse options //---------------------------------------------------------------------- + // Disconnect virtual controllers for memories we don't have + // (allows access to real hardware for those memory types) + //---------------------------------------------------------------------- + if( rc.ok() ) + { + if( !haveOTPROM ) + { + ModelError me = poreve->detachSlave(&poreve->iv_otprom); + if( me != ME_SUCCESS ) + { + FAPI_ERR("Model error detaching OTPROM. Errno(%i)\n",(int)me); + ModelError & ERROR = me; + FapiPoreVeArg_t TYPE = ARG_OTPROM; + FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_ERROR_DETACHING_SLAVE); + } + } + if( !havePNOR ) + { + ModelError me = poreve->detachSlave(&poreve->iv_pnorController); + if( me != ME_SUCCESS ) + { + FAPI_ERR("Model error detaching PNOR. Errno(%i)\n",(int)me); + ModelError & ERROR = me; + FapiPoreVeArg_t TYPE = ARG_PNOR; + FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_ERROR_DETACHING_SLAVE); + } + } + if( !haveSEEPROM ) + { + ModelError me = poreve->detachSlave(&poreve->iv_seepromController); + if( me != ME_SUCCESS ) + { + FAPI_ERR("Model error detaching SEEPROM. Errno(%i)\n",(int)me); + ModelError & ERROR = me; + FapiPoreVeArg_t TYPE = ARG_SEEPROM; + FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_ERROR_DETACHING_SLAVE); + } + } + if( !haveMAINMEM ) + { + ModelError me = poreve->detachSlave(&poreve->iv_main); + if( me != ME_SUCCESS ) + { + FAPI_ERR("Model error detaching MAINMEM. Errno(%i)\n",(int)me); + ModelError & ERROR = me; + FapiPoreVeArg_t TYPE = ARG_MAINMEM; + FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_ERROR_DETACHING_SLAVE); + } + } + if( !haveSRAM ) + { + ModelError me = poreve->detachSlave(&poreve->iv_sram); + if( me != ME_SUCCESS ) + { + FAPI_ERR("Model error detaching SRAM. Errno(%i)\n",(int)me); + ModelError & ERROR = me; + FapiPoreVeArg_t TYPE = ARG_SRAM; + FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_ERROR_DETACHING_SLAVE); + } + } + if( !havePIBMEM ) + { + ModelError me = poreve->detachSlave(&poreve->iv_pibmem); + if( me != ME_SUCCESS ) + { + FAPI_ERR("Model error detaching PIBMEM. Errno(%i)\n",(int)me); + ModelError & ERROR = me; + FapiPoreVeArg_t TYPE = ARG_PIBMEM; + FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_ERROR_DETACHING_SLAVE); + } + } + } + + //---------------------------------------------------------------------- // Set entry point //---------------------------------------------------------------------- - if( pOtherArg->iv_entryPoint != NULL ) + if( (pOtherArg->iv_entryPoint != NULL) && rc.ok() ) { - FAPI_INF( "Looking up entry point %s", pOtherArg->iv_entryPoint ); + FAPI_INF( "Looking up entry point %s\n", pOtherArg->iv_entryPoint ); GlobalSymbolInfo epInfo; bool symbolFound = false; @@ -395,8 +501,8 @@ fapi::ReturnCode fapiPoreVe( if( !symbolFound || (he != HOOK_OK) ) { FAPI_ERR( "Failed to find entry point \"%s\" in hooks file. " - "HookError = %d", pOtherArg->iv_entryPoint, (int)he); - // char & POINT = pOtherArg->iv_entryPoint; + "HookError = %d\n", pOtherArg->iv_entryPoint, (int)he); +// char & POINT = pOtherArg->iv_entryPoint; HookError & ERROR = he; FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_ENTRY_POINT_NOT_FOUND); HookManager::report(); @@ -406,7 +512,7 @@ fapi::ReturnCode fapiPoreVe( //Make sure entry point is a valid type if( epInfo.iv_type != 'T' ) { - FAPI_ERR("Entry point is of ivalid type %c", epInfo.iv_type); + FAPI_ERR("Entry point is of ivalid type %c\n", epInfo.iv_type); char & TYPE = epInfo.iv_type; FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_INVALID_ENTRY_POINT_TYPE); } @@ -417,7 +523,7 @@ fapi::ReturnCode fapiPoreVe( poreve->iv_pore.setPc( epInfo.iv_address ); if( me != ME_SUCCESS ) { - FAPI_ERR( "Model error setting PC. Errno(%i)", (int)me); + FAPI_ERR( "Model error setting PC. Errno(%i)\n", (int)me); PoreAddress & ADDRESS = epInfo.iv_address; ModelError & ERROR = me; FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_ERROR_SETTING_PC); @@ -429,9 +535,9 @@ fapi::ReturnCode fapiPoreVe( //---------------------------------------------------------------------- // Set breakpoint //---------------------------------------------------------------------- - if( pOtherArg->iv_breakpoint != NULL ) + if( (pOtherArg->iv_breakpoint != NULL) && rc.ok() ) { - FAPI_INF( "Looking up breakpoint %s", pOtherArg->iv_breakpoint ); + FAPI_INF( "Looking up breakpoint %s\n", pOtherArg->iv_breakpoint ); GlobalSymbolInfo bpInfo; bool symbolFound = false; @@ -442,7 +548,7 @@ fapi::ReturnCode fapiPoreVe( if( !symbolFound || (he != HOOK_OK) ) { FAPI_ERR( "Failed to find breakpoint \"%s\" in hooks file." - "HookError = %d", pOtherArg->iv_breakpoint, (int)he); + "HookError = %d\n", pOtherArg->iv_breakpoint, (int)he); // char & POINT = pOtherArg->iv_breakpoint; HookError & ERROR = he; FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_BREAKPOINT_NOT_FOUND); @@ -453,7 +559,7 @@ fapi::ReturnCode fapiPoreVe( //Make sure break point is a valid type if( bpInfo.iv_type != 'T' ) { - FAPI_ERR("Break point is of ivalid type %c", bpInfo.iv_type); + FAPI_ERR("Break point is of ivalid type %c\n", bpInfo.iv_type); char & TYPE = bpInfo.iv_type; FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_INVALID_BREAK_POINT_TYPE); } @@ -464,7 +570,7 @@ fapi::ReturnCode fapiPoreVe( poreve->iv_pore.setBreakpoint( bpInfo.iv_address ); if( me != ME_SUCCESS ) { - FAPI_ERR( "Model error setting breakpoint. Errno(%i)", + FAPI_ERR( "Model error setting breakpoint. Errno(%i)\n", (int)me); PoreAddress & ADDRESS = bpInfo.iv_address; ModelError & ERROR = me; @@ -478,7 +584,7 @@ fapi::ReturnCode fapiPoreVe( //---------------------------------------------------------------------- // Set MRR //---------------------------------------------------------------------- - if( pOtherArg->iv_mrr != 0 ) + if( (pOtherArg->iv_mrr != 0) && rc.ok() ) { FAPI_INF( "Setting MRR to 0x%016llX", pOtherArg->iv_mrr ); @@ -486,7 +592,7 @@ fapi::ReturnCode fapiPoreVe( pOtherArg->iv_mrr & 0x00000003fffffc00ull, sizeof(uint64_t) ); if( me != ME_SUCCESS ) { - FAPI_ERR( "Model error setting MRR. Errno(%i)", (int)me); + FAPI_ERR( "Model error setting MRR. Errno(%i)\n", (int)me); uint64_t & MRR = pOtherArg->iv_mrr; ModelError & ERROR = me; FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_ERROR_SETTING_MRR); @@ -495,12 +601,13 @@ fapi::ReturnCode fapiPoreVe( //---------------------------------------------------------------------- // Run the requested number of instructions + // JDS TODO - check poreve->poreRc() to get run-time FAPI return codes //---------------------------------------------------------------------- if( rc.ok() ) { uint64_t o_actualNumInstructionsRun = 0; int runStatus = poreve->run( pOtherArg->iv_instructionCount, o_actualNumInstructionsRun ); - FAPI_INF( "PORE ran %llu instructions, and returned status 0x%X", + FAPI_INF( "PORE ran %llu instructions, and returned status 0x%X\n", o_actualNumInstructionsRun, runStatus); if( runStatus != 0 ) @@ -508,7 +615,7 @@ fapi::ReturnCode fapiPoreVe( //Parse out each status bit if( runStatus & PORE_STATUS_HALTED ) { - FAPI_INF( "PORE is stopped at a HALT instruction"); + FAPI_INF( "PORE is stopped at a HALT instruction\n"); runStatus &= ~PORE_STATUS_HALTED; //Check the SBE VITAL reg halt code for success @@ -524,20 +631,21 @@ fapi::ReturnCode fapiPoreVe( uint32_t haltcode = (data_64 >> 48) & 0x0000000F; if( haltcode != 0xF ) { - FAPI_ERR( "Halt code is 0x%x (ERROR)", haltcode ); + FAPI_ERR( "Halt code is 0x%x (ERROR)\n", haltcode ); uint32_t & ERROR = haltcode; FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_HALTED_WITH_ERROR); } else { - FAPI_INF( "Halt code is 0x%x (SUCCESS)",haltcode); + FAPI_INF( "Halt code is 0x%x (SUCCESS)\n",haltcode); + rc = fapi::FAPI_RC_SUCCESS; } } else { FAPI_ERR("PIB error getting halt code " - "(error code %i)", pib_rc ); + "(error code %i)\n", pib_rc ); int & ERROR = pib_rc; FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_PIB_ERROR_READING_SBEVITAL); @@ -545,7 +653,7 @@ fapi::ReturnCode fapiPoreVe( } else { - FAPI_ERR( "Model error getting halt code (me=0x%x)", me ); + FAPI_ERR( "Model error getting halt code (me=0x%x)\n", me ); ModelError & ERROR = me; FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_MODEL_ERROR_GETTING_HALT_CODE); @@ -553,29 +661,29 @@ fapi::ReturnCode fapiPoreVe( } if( runStatus & PORE_STATUS_ERROR_HALT ) { - FAPI_ERR( "PORE is stopped due to an architected error"); + FAPI_ERR( "PORE is stopped due to an architected error\n"); runStatus &= ~PORE_STATUS_ERROR_HALT; FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_ARCHITECTED_ERROR); - poreve->iv_pore.dump(); + poreve->iv_pore.dump(); } if( runStatus & PORE_STATUS_HARDWARE_STOP ) { - FAPI_INF( "PORE is stopped"); + FAPI_INF( "PORE is stopped\n"); runStatus &= ~PORE_STATUS_HARDWARE_STOP; } if( runStatus & PORE_STATUS_BREAKPOINT ) { - FAPI_INF( "PORE is stopped at a breakpoint"); + FAPI_INF( "PORE is stopped at a breakpoint\n"); runStatus &= ~PORE_STATUS_BREAKPOINT; } if( runStatus & PORE_STATUS_TRAP ) { - FAPI_INF( "PORE is stopped at a TRAP instruction"); + FAPI_INF( "PORE is stopped at a TRAP instruction\n"); runStatus &= ~PORE_STATUS_TRAP; } if( runStatus & PORE_STATUS_MODEL_ERROR ) { - FAPI_ERR( "PORE is stopped due to a modeling error"); + FAPI_ERR( "PORE is stopped due to a modeling error\n"); runStatus &= ~PORE_STATUS_MODEL_ERROR; FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_MODELING_ERROR); poreve->iv_pore.dump(); @@ -583,27 +691,27 @@ fapi::ReturnCode fapiPoreVe( if( runStatus & PORE_STATUS_DEBUG_STOP ) { FAPI_INF( "PORE is stopped due to a user request " - "(probably a hook)"); + "(probably a hook)\n"); runStatus &= ~PORE_STATUS_DEBUG_STOP; } //If we still have bits set, we missed something if( runStatus ) { - FAPI_ERR( "PORE is stopped with an unknown status code:0x%X", + FAPI_ERR( "PORE is stopped with an unknown status code:0x%X\n", runStatus); int & STATUS = runStatus; FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_UNKNOWN_STATUS_ERROR); } } else { //runStatus == 0 FAPI_IMP( "PORE ran the requested number of instructions " - "without hitting any stop conditions"); + "without hitting any stop conditions\n"); } if( (pOtherArg->iv_instructionCount != RUN_UNLIMITED) && (pOtherArg->iv_instructionCount != o_actualNumInstructionsRun) ) { FAPI_IMP( "PORE only ran %llu of the %llu instructions you " - "requested", o_actualNumInstructionsRun, + "requested\n", o_actualNumInstructionsRun, pOtherArg->iv_instructionCount ); } } //if( rc.ok() ) @@ -611,7 +719,7 @@ fapi::ReturnCode fapiPoreVe( //---------------------------------------------------------------------- // Extract end state //---------------------------------------------------------------------- - if( stateArg != NULL && stateArg->iv_extractState ) + if( (stateArg != NULL) && stateArg->iv_extractState && rc.ok() ) { ModelError me; PoreState * p_state = (PoreState *)stateArg->iv_data; @@ -709,7 +817,7 @@ fapi::ReturnCode fapiPoreVe( #endif if( me != ME_SUCCESS ) { - FAPI_ERR( "Model error extracting state. Errno(%i)", (int)me); + FAPI_ERR( "Model error extracting state. Errno(%i)\n", (int)me); FAPI_SET_HWP_ERROR(rc, RC_FAPIPOREVE_ERROR_EXTRACTING_STATE); } } //if extract state @@ -732,6 +840,13 @@ This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they are included here. $Log: fapiPoreVe.C,v $ +Revision 1.29 2012/09/05 20:11:16 jeshua +More robust return code handling +Cosmetic updates for things like line length + +Revision 1.28 2012/09/05 18:32:42 jeshua +Disconnect missing memories + Revision 1.27 2012/04/26 21:30:31 jeshua file renamed from ../../../fapiporeve/working/fapiPoreVe.C to fapiPoreVe.C diff --git a/src/usr/pore/fapiporeve/fapiPoreVeArg.C b/src/usr/pore/fapiporeve/fapiPoreVeArg.C index 96838432b..d5f565619 100644 --- a/src/usr/pore/fapiporeve/fapiPoreVeArg.C +++ b/src/usr/pore/fapiporeve/fapiPoreVeArg.C @@ -1,26 +1,25 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/pore/fapiporeve/fapiPoreVeArg.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/fapiporeve/fapiPoreVeArg.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ // -*- mode: C++; c-file-style: "linux"; -*- // $Id: fapiPoreVeArg.C,v 1.19 2012/04/26 21:30:40 jeshua Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/poreve/working/fapiporeve/fapiPoreVeArg.C,v $ @@ -75,23 +74,22 @@ FapiPoreVeMemArg::FapiPoreVeMemArg( const FapiPoreVeArg_t i_type, uint32_t rc = 0; if( iv_fd < 0 ) { - FAPI_ERR( "Failed to open %s file", iv_filename ); + FAPI_ERR( "Failed to open %s file\n", iv_filename ); rc = BAD_ERROR_CODE; } else { iv_size = lseek( iv_fd, 0, SEEK_END ); if( iv_size == (size_t)((off_t)-1) ) { - FAPI_ERR( "Failed to determine the size of %s file", iv_filename ); + FAPI_ERR( "Failed to determine the size of %s file\n", iv_filename ); } else { if( (iv_type == ARG_SRAM) || (iv_type == ARG_MAINMEM) || (iv_type == ARG_PNOR) || (iv_type == ARG_SEEPROM) || (iv_type == ARG_PIBMEM) ) { - iv_data = mmap( 0, iv_size, - PROT_READ | PROT_WRITE, MAP_PRIVATE, iv_fd, 0 ); + iv_data = mmap( 0, iv_size, PROT_READ | PROT_WRITE, MAP_PRIVATE, iv_fd, 0 ); } else { iv_data = mmap( 0, iv_size, PROT_READ, MAP_PRIVATE, iv_fd, 0 ); } if( iv_data == MAP_FAILED ) { - FAPI_ERR( "Failed to map %s file", iv_filename ); + FAPI_ERR( "Failed to map %s file\n", iv_filename ); rc = BAD_ERROR_CODE; } } diff --git a/src/usr/pore/fapiporeve/fapiPoreVe_errors.xml b/src/usr/pore/fapiporeve/fapiPoreVe_errors.xml index c0b0a2b83..b049c7e4d 100644 --- a/src/usr/pore/fapiporeve/fapiPoreVe_errors.xml +++ b/src/usr/pore/fapiporeve/fapiPoreVe_errors.xml @@ -1,25 +1,25 @@ -<!-- IBM_PROLOG_BEGIN_TAG - This is an automatically generated prolog. - - $Source: src/usr/pore/fapiporeve/fapiPoreVe_errors.xml $ - - IBM CONFIDENTIAL - - COPYRIGHT International Business Machines Corp. 2012 - - p1 - - Object Code Only (OCO) source materials - Licensed Internal Code Source Materials - IBM HostBoot Licensed Internal Code - - The source code for this program is not published or other- - wise divested of its trade secrets, irrespective of what has - been deposited with the U.S. Copyright Office. - - Origin: 30 - - IBM_PROLOG_END_TAG --> +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/pore/fapiporeve/fapiPoreVe_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> <!-- Error definitions for fapiPoreVe procedure --> <hwpErrors> <!-- *********************************************************************** --> @@ -49,6 +49,12 @@ <ffdc>TYPE</ffdc> </hwpError> <hwpError> + <rc>RC_FAPIPOREVE_ERROR_DETACHING_SLAVE</rc> + <description>Model error detaching a pib slave</description> + <ffdc>ERROR</ffdc> + <ffdc>TYPE</ffdc> + </hwpError> + <hwpError> <rc>RC_FAPIPOREVE_ENTRY_POINT_NOT_FOUND</rc> <description>Didn't find the entry point in the hooks file</description> <!--ffdc>POINT</ffdc--> @@ -125,52 +131,4 @@ <rc>RC_FAPIPOREVE_ERROR_EXTRACTING_STATE</rc> <description>Model error extracting state</description> </hwpError> - <hwpError> - <rc>RC_POREVE_PIB2CFAM_ME_NOT_MAPPED_IN_MEMORY</rc> - <description>pib2cfam error. Not mapped in memory</description> - </hwpError> - <hwpError> - <rc>RC_POREVE_PIB2CFAM_ME_BUS_SLAVE_PERMISSION_DENIED</rc> - <description>Bus slave permission denied</description> - </hwpError> - <hwpError> - <rc>RC_POREVE_FASTI2C_OPERATION_ERROR</rc> - <description>Fasti2c operation error</description> - </hwpError> - <hwpError> - <rc>RC_POREVE_BUS_ME_NOT_MAPPED_IN_BUS</rc> - <description>Bus error. Not mapped in bus</description> - </hwpError> - <hwpError> - <rc>RC_POREVE_ME_NO_BUS_MODEL</rc> - <description>Error. No pibmaster bus model</description> - </hwpError> - <hwpError> - <rc>RC_POREVE_LPC_OPERATION_ERROR</rc> - <description>Lpc operation error</description> - </hwpError> - <hwpError> - <rc>RC_POREVE_PIBMEM_OPERATION_ERROR</rc> - <description>pibmem operation error</description> - </hwpError> - <hwpError> - <rc>RC_POREVE_BUS_OPERATION_ERROR</rc> - <description>bus operation error</description> - </hwpError> - <hwpError> - <rc>RC_POREVE_BUS_OCI_SLAVE_READ_NOT_SUPPORTED</rc> - <description>OCI slave read not supported</description> - </hwpError> - <hwpError> - <rc>RC_POREVE_BUS_OCI_SLAVE_WRITE_NOT_SUPPORTED</rc> - <description>OCI slave read not supported</description> - </hwpError> - <hwpError> - <rc>RC_POREVE_PIBMEM_BAD_MODE</rc> - <description>Bad Mode specified in pibmem transaction</description> - </hwpError> - <hwpError> - <rc>RC_POREVE_PIBMEM_BAD_OFFSET</rc> - <description>Bad Offset specified in pibmem transaction</description> - </hwpError> </hwpErrors> diff --git a/src/usr/pore/makefile b/src/usr/pore/makefile index 4693907dd..a96b98175 100644 --- a/src/usr/pore/makefile +++ b/src/usr/pore/makefile @@ -1,27 +1,28 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. # -# $Source: src/usr/pore/makefile $ +# $Source: src/usr/pore/makefile $ # -# IBM CONFIDENTIAL +# IBM CONFIDENTIAL # -# COPYRIGHT International Business Machines Corp. 2011-2012 +# COPYRIGHT International Business Machines Corp. 2011,2013 # -# p1 +# p1 # -# Object Code Only (OCO) source materials -# Licensed Internal Code Source Materials -# IBM HostBoot Licensed Internal Code +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code # -# The source code for this program is not published or other- -# wise divested of its trade secrets, irrespective of what has -# been deposited with the U.S. Copyright Office. +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. # -# Origin: 30 +# Origin: 30 # -# IBM_PROLOG_END_TAG +# IBM_PROLOG_END_TAG ROOTPATH = ../../.. SUBDIRS = fapiporeve.d poreve.d test.d -BINARY_FILES = $(IMGDIR)/centaur.sbe_pnor.bin:00b0fbca878f6701cb4c002661c3fce3dafcde02 +# hb cacheadd --local img/centaur.sbe_pnor.bin "Centaur SBE PNOR image Sim 01-16-2013" +BINARY_FILES = $(IMGDIR)/centaur.sbe_pnor.bin:47912539ea0a25271749256b43ef4328cc3985fa include ${ROOTPATH}/config.mk diff --git a/src/usr/pore/poreve/hook/sbe_pnor.hooks.cc b/src/usr/pore/poreve/hook/sbe_pnor.hooks.cc index b0eab9d6a..953acb134 100755 --- a/src/usr/pore/poreve/hook/sbe_pnor.hooks.cc +++ b/src/usr/pore/poreve/hook/sbe_pnor.hooks.cc @@ -1,75 +1,82 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/pore/poreve/hook/sbe_pnor.hooks.cc $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/poreve/hook/sbe_pnor.hooks.cc $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ // $Id$ // // File generated by hook_indexer // Arguments : -g -b centaur.sbe_pnor.out -c bin/sbe_pnor.hooks.cc -m pnor -// Generation Date : Thu Jul 5 10:52:28 CDT 2012 +// Generation Date : Wed Jan 16 10:06:13 CST 2013 #include "hookmanager.H" using namespace vsbe; -static const char* symbols[92] = { +static const char* symbols[106] = { +"pnor::tp_pll_func_ring", "oci::cen_sbe_istep_pnor", +"pnor::return_from_cen_sbe_nest_startclocks", "oci::return_from_cen_sbe_arrayinit", "oci::cen_sbe_tp_arrayinit", "pnor::_cen_sbe_seeprom_halt", -"oci::cen_sbe_dd10_tp_bndy_pll_ring", +"oci::scan_a0", "pnor::return_from_cen_sbe_scominits", "oci::return_from_cen_sbe_tp_arrayinit", "oci::cen_sbe_tp_chiplet_init1", "oci::cen_sbe_tp_chiplet_init2", "oci::cen_sbe_scominits_control", +"pnor::scan_a0_override", "oci::return_from_cen_sbe_tp_chiplet_init1", "oci::cen_sbe_tp_chiplet_init3", -"pnor::cen_array_init_module", "pnor::callproc_prologue", "pnor::_sbe_pnor_start", "pnor::cen_sbe_do_manual_inits_control", "pnor::cen_sbe_dts_init", +"pnor::cen_sbe_nest_startclocks_control", "oci::return_from_cen_sbe_tp_chiplet_init2", +"pnor::cen_arrayinit_module", "oci::callproc_epilogue", +"pnor::tp_pll_bndy_ring", "oci::return_from_cen_sbe_tp_chiplet_init3", "pnor::return_from_cen_sbe_dts_init", +"pnor::cen_sbe_pll_setup", "pnor::cen_scan0_module", "oci::cen_sbe_tp_arrayinit_control", "oci::cen_sbe_do_manual_inits", +"oci::tp_pll_bndy_ring_alt", "oci::cen_sbe_tp_chiplet_init1_control", "oci::cen_sbe_tp_chiplet_init2_control", "oci::cen_sbe_tp_chiplet_init3_control", "oci::_cen_sbe_seeprom_halt", "pnor::cen_sbe_dts_init_control", -"pnor::return_from_cen_sbe_startclocks", "oci::return_from_cen_sbe_scominits", +"pnor::cen_sbe_pll_setup_control", "pnor::cen_sbe_pll_initf", -"oci::cen_array_init_module", +"pnor::scan_d0", "oci::callproc_prologue", "oci::_sbe_pnor_start", "oci::cen_sbe_do_manual_inits_control", "pnor::cen_sbe_initf", "pnor::cen_sbe_istep_pnor", +"oci::cen_sbe_pll_setup", "pnor::cen_sbe_tp_arrayinit", "pnor::return_from_cen_sbe_tp_arrayinit", "pnor::cen_sbe_tp_chiplet_init1", @@ -77,148 +84,168 @@ static const char* symbols[92] = { "pnor::cen_sbe_tp_chiplet_init2", "pnor::cen_sbe_pll_initf_control", "pnor::return_from_cen_sbe_tp_chiplet_init1", +"pnor::return_from_cen_sbe_pll_setup", "oci::return_from_cen_sbe_chiplet_init", "pnor::cen_sbe_tp_chiplet_init3", "pnor::cen_sbe_initf_control", "pnor::return_from_cen_sbe_tp_chiplet_init2", -"oci::return_from_cen_sbe_startclocks", +"oci::tp_pll_gptr_ring", "pnor::return_from_cen_sbe_tp_chiplet_init3", +"oci::cen_sbe_pll_setup_control", "oci::cen_sbe_pll_initf", -"pnor::cen_sbe_startclocks", +"oci::scan_d0", "pnor::cen_sbe_tp_arrayinit_control", "oci::cen_sbe_initf", -"oci::cen_sbe_tp_bndy_pll_ring_loc", +"pnor::tp_pll_bndy_ring_alt", "pnor::cen_sbe_tp_chiplet_init1_control", "oci::cen_sbe_chiplet_init_control", "pnor::cen_sbe_tp_chiplet_init2_control", "pnor::cen_sbe_tp_chiplet_init3_control", "pnor::return_from_cen_sbe_pll_initf", "pnor::cen_sbe_arrayinit", -"oci::cen_sbe_ring_table", "pnor::return_from_cen_sbe_initf", "oci::cen_sbe_pll_initf_control", -"pnor::cen_sbe_startclocks_control", +"oci::return_from_cen_sbe_pll_setup", "oci::cen_sbe_initf_control", -"oci::cen_sbe_startclocks", +"oci::cen_sbe_nest_startclocks", +"oci::tp_pll_func_ring", "pnor::cen_sbe_arrayinit_control", +"oci::return_from_cen_sbe_nest_startclocks", "pnor::cen_sbe_chiplet_init", "pnor::return_from_cen_sbe_chiplet_init", "oci::return_from_cen_sbe_pll_initf", "oci::cen_sbe_arrayinit", +"pnor::tp_pll_gptr_ring", "oci::return_from_cen_sbe_initf", "pnor::return_from_cen_sbe_do_manual_inits", "pnor::cen_sbe_scominits", -"oci::cen_sbe_startclocks_control", +"oci::scan_a0_override", "oci::cen_sbe_dts_init", -"pnor::cen_sbe_tp_bndy_pll_ring_loc", +"oci::cen_sbe_nest_startclocks_control", +"oci::cen_arrayinit_module", +"oci::tp_pll_bndy_ring", "oci::return_from_cen_sbe_dts_init", "pnor::cen_sbe_chiplet_init_control", "pnor::return_from_cen_sbe_arrayinit", "oci::cen_scan0_module", -"pnor::cen_sbe_dd10_tp_bndy_pll_ring", +"pnor::scan_a0", "oci::cen_sbe_arrayinit_control", -"pnor::cen_sbe_ring_table", "pnor::cen_sbe_scominits_control", "oci::cen_sbe_dts_init_control", "pnor::callproc_epilogue", "oci::return_from_cen_sbe_do_manual_inits", "oci::cen_sbe_scominits", "pnor::cen_sbe_do_manual_inits", +"pnor::cen_sbe_nest_startclocks", }; -static GlobalSymbolInfo info[92] = { -{PoreAddress(0x8000, 0x000002c0), 'T'}, -{PoreAddress(0x8000, 0x00000444), 'T'}, -{PoreAddress(0x8000, 0x00000aa0), 'T'}, +static GlobalSymbolInfo info[106] = { +{PoreAddress(0x800b, 0x000013c8), 'R'}, +{PoreAddress(0x8000, 0x000002e0), 'T'}, {PoreAddress(0x800b, 0x00000590), 'T'}, -{PoreAddress(0x8000, 0x000012e8), 'R'}, -{PoreAddress(0x800b, 0x00000570), 'T'}, -{PoreAddress(0x8000, 0x00000390), 'T'}, -{PoreAddress(0x8000, 0x000005bc), 'T'}, -{PoreAddress(0x8000, 0x00000788), 'T'}, -{PoreAddress(0x8000, 0x00000258), 'R'}, -{PoreAddress(0x8000, 0x000002dc), 'T'}, -{PoreAddress(0x8000, 0x00000afc), 'T'}, -{PoreAddress(0x800b, 0x00000938), 'T'}, -{PoreAddress(0x800b, 0x000010ec), 'T'}, -{PoreAddress(0x800b, 0x000002c0), 'T'}, -{PoreAddress(0x800b, 0x00000248), 'R'}, -{PoreAddress(0x800b, 0x00000fcc), 'T'}, -{PoreAddress(0x8000, 0x00000354), 'T'}, -{PoreAddress(0x8000, 0x000011dc), 'T'}, -{PoreAddress(0x8000, 0x000003cc), 'T'}, -{PoreAddress(0x800b, 0x00000480), 'T'}, -{PoreAddress(0x800b, 0x000006c4), 'T'}, -{PoreAddress(0x8000, 0x00000218), 'R'}, -{PoreAddress(0x8000, 0x00000fd4), 'T'}, -{PoreAddress(0x8000, 0x00000200), 'R'}, -{PoreAddress(0x8000, 0x00000210), 'R'}, +{PoreAddress(0x8000, 0x000004a0), 'T'}, +{PoreAddress(0x8000, 0x00000a30), 'T'}, +{PoreAddress(0x800b, 0x000005ec), 'T'}, +{PoreAddress(0x8000, 0x00001378), 'T'}, +{PoreAddress(0x800b, 0x000005cc), 'T'}, +{PoreAddress(0x8000, 0x000003ec), 'T'}, +{PoreAddress(0x8000, 0x00000618), 'T'}, +{PoreAddress(0x8000, 0x00000804), 'T'}, +{PoreAddress(0x8000, 0x00000260), 'R'}, +{PoreAddress(0x800b, 0x00001398), 'T'}, +{PoreAddress(0x8000, 0x000002fc), 'T'}, +{PoreAddress(0x8000, 0x00000a88), 'T'}, +{PoreAddress(0x800b, 0x00001194), 'T'}, +{PoreAddress(0x800b, 0x000002e0), 'T'}, +{PoreAddress(0x800b, 0x00000250), 'R'}, +{PoreAddress(0x800b, 0x000010a0), 'T'}, +{PoreAddress(0x800b, 0x00000258), 'R'}, +{PoreAddress(0x8000, 0x000003b0), 'T'}, +{PoreAddress(0x800b, 0x000008f8), 'T'}, +{PoreAddress(0x8000, 0x00001260), 'T'}, +{PoreAddress(0x800b, 0x000013d8), 'R'}, +{PoreAddress(0x8000, 0x00000428), 'T'}, +{PoreAddress(0x800b, 0x000004dc), 'T'}, +{PoreAddress(0x800b, 0x00000f9c), 'T'}, +{PoreAddress(0x800b, 0x00000748), 'T'}, {PoreAddress(0x8000, 0x00000220), 'R'}, -{PoreAddress(0x8000, 0x00000590), 'T'}, -{PoreAddress(0x800b, 0x00000238), 'R'}, -{PoreAddress(0x800b, 0x00000534), 'T'}, -{PoreAddress(0x8000, 0x00000570), 'T'}, -{PoreAddress(0x800b, 0x00000f18), 'T'}, -{PoreAddress(0x8000, 0x00000938), 'T'}, -{PoreAddress(0x8000, 0x000010ec), 'T'}, -{PoreAddress(0x8000, 0x000002c0), 'T'}, -{PoreAddress(0x8000, 0x00000248), 'R'}, -{PoreAddress(0x800b, 0x00000fd0), 'T'}, -{PoreAddress(0x800b, 0x000002c0), 'T'}, -{PoreAddress(0x800b, 0x00000aa0), 'T'}, -{PoreAddress(0x800b, 0x00000390), 'T'}, -{PoreAddress(0x800b, 0x000005bc), 'T'}, -{PoreAddress(0x8000, 0x00000be0), 'T'}, -{PoreAddress(0x800b, 0x00000788), 'T'}, -{PoreAddress(0x800b, 0x00000208), 'R'}, -{PoreAddress(0x800b, 0x000002dc), 'T'}, -{PoreAddress(0x8000, 0x00000408), 'T'}, -{PoreAddress(0x800b, 0x00000afc), 'T'}, -{PoreAddress(0x800b, 0x00000240), 'R'}, -{PoreAddress(0x800b, 0x00000354), 'T'}, -{PoreAddress(0x8000, 0x00000534), 'T'}, -{PoreAddress(0x800b, 0x000003cc), 'T'}, -{PoreAddress(0x8000, 0x00000f18), 'T'}, -{PoreAddress(0x800b, 0x00000fd8), 'T'}, -{PoreAddress(0x800b, 0x00000218), 'R'}, -{PoreAddress(0x8000, 0x00000fd0), 'T'}, -{PoreAddress(0x8000, 0x000012d8), 'R'}, -{PoreAddress(0x800b, 0x00000200), 'R'}, +{PoreAddress(0x8000, 0x000010a8), 'T'}, +{PoreAddress(0x8000, 0x00000268), 'R'}, +{PoreAddress(0x8000, 0x00000200), 'R'}, +{PoreAddress(0x8000, 0x00000218), 'R'}, {PoreAddress(0x8000, 0x00000228), 'R'}, +{PoreAddress(0x8000, 0x000005ec), 'T'}, +{PoreAddress(0x800b, 0x00000240), 'R'}, +{PoreAddress(0x8000, 0x000005cc), 'T'}, {PoreAddress(0x800b, 0x00000210), 'R'}, +{PoreAddress(0x800b, 0x00000e40), 'T'}, +{PoreAddress(0x800b, 0x0000135c), 'T'}, +{PoreAddress(0x8000, 0x00001194), 'T'}, +{PoreAddress(0x8000, 0x000002e0), 'T'}, +{PoreAddress(0x8000, 0x00000250), 'R'}, +{PoreAddress(0x800b, 0x000010a4), 'T'}, +{PoreAddress(0x800b, 0x000002e0), 'T'}, +{PoreAddress(0x8000, 0x00000f9c), 'T'}, +{PoreAddress(0x800b, 0x00000a30), 'T'}, +{PoreAddress(0x800b, 0x000003ec), 'T'}, +{PoreAddress(0x800b, 0x00000618), 'T'}, +{PoreAddress(0x8000, 0x00000b64), 'T'}, +{PoreAddress(0x800b, 0x00000804), 'T'}, +{PoreAddress(0x800b, 0x00000208), 'R'}, +{PoreAddress(0x800b, 0x000002fc), 'T'}, +{PoreAddress(0x800b, 0x00000374), 'T'}, +{PoreAddress(0x8000, 0x00000464), 'T'}, +{PoreAddress(0x800b, 0x00000a88), 'T'}, +{PoreAddress(0x800b, 0x00000248), 'R'}, +{PoreAddress(0x800b, 0x000003b0), 'T'}, +{PoreAddress(0x8000, 0x000013b8), 'R'}, +{PoreAddress(0x800b, 0x00000428), 'T'}, +{PoreAddress(0x8000, 0x00000210), 'R'}, +{PoreAddress(0x8000, 0x00000e40), 'T'}, +{PoreAddress(0x8000, 0x0000135c), 'T'}, {PoreAddress(0x800b, 0x00000220), 'R'}, -{PoreAddress(0x800b, 0x00000318), 'T'}, -{PoreAddress(0x800b, 0x00000ee0), 'T'}, -{PoreAddress(0x8000, 0x000012d8), 'R'}, -{PoreAddress(0x800b, 0x000004bc), 'T'}, +{PoreAddress(0x8000, 0x000010a4), 'T'}, +{PoreAddress(0x800b, 0x00000268), 'R'}, +{PoreAddress(0x800b, 0x00000200), 'R'}, +{PoreAddress(0x8000, 0x00000230), 'R'}, +{PoreAddress(0x800b, 0x00000218), 'R'}, +{PoreAddress(0x800b, 0x00000228), 'R'}, +{PoreAddress(0x800b, 0x00000338), 'T'}, +{PoreAddress(0x800b, 0x00000e08), 'T'}, +{PoreAddress(0x800b, 0x00000518), 'T'}, {PoreAddress(0x8000, 0x00000208), 'R'}, -{PoreAddress(0x800b, 0x00000250), 'R'}, -{PoreAddress(0x8000, 0x00000240), 'R'}, -{PoreAddress(0x8000, 0x00000fd8), 'T'}, +{PoreAddress(0x8000, 0x00000374), 'T'}, +{PoreAddress(0x8000, 0x00000248), 'R'}, +{PoreAddress(0x8000, 0x000010ac), 'T'}, +{PoreAddress(0x8000, 0x000013c8), 'R'}, +{PoreAddress(0x800b, 0x00000238), 'R'}, +{PoreAddress(0x8000, 0x00000590), 'T'}, +{PoreAddress(0x800b, 0x00000b64), 'T'}, +{PoreAddress(0x800b, 0x00000464), 'T'}, +{PoreAddress(0x8000, 0x00000338), 'T'}, +{PoreAddress(0x8000, 0x00000e08), 'T'}, +{PoreAddress(0x800b, 0x000013b8), 'R'}, +{PoreAddress(0x8000, 0x00000518), 'T'}, +{PoreAddress(0x800b, 0x00000554), 'T'}, +{PoreAddress(0x800b, 0x00001190), 'T'}, +{PoreAddress(0x8000, 0x00001398), 'T'}, +{PoreAddress(0x8000, 0x000010a0), 'T'}, +{PoreAddress(0x8000, 0x00000258), 'R'}, +{PoreAddress(0x8000, 0x000008f8), 'T'}, +{PoreAddress(0x8000, 0x000013d8), 'R'}, +{PoreAddress(0x8000, 0x000004dc), 'T'}, {PoreAddress(0x800b, 0x00000230), 'R'}, -{PoreAddress(0x800b, 0x00000be0), 'T'}, -{PoreAddress(0x800b, 0x00000408), 'T'}, -{PoreAddress(0x8000, 0x00000318), 'T'}, -{PoreAddress(0x8000, 0x00000ee0), 'T'}, -{PoreAddress(0x8000, 0x000004bc), 'T'}, -{PoreAddress(0x800b, 0x000004f8), 'T'}, -{PoreAddress(0x800b, 0x000010e8), 'T'}, -{PoreAddress(0x8000, 0x00000250), 'R'}, -{PoreAddress(0x8000, 0x00000fcc), 'T'}, -{PoreAddress(0x800b, 0x000012d8), 'R'}, -{PoreAddress(0x8000, 0x00000480), 'T'}, -{PoreAddress(0x800b, 0x00000228), 'R'}, -{PoreAddress(0x800b, 0x00000444), 'T'}, -{PoreAddress(0x8000, 0x000006c4), 'T'}, -{PoreAddress(0x800b, 0x000012e8), 'R'}, -{PoreAddress(0x8000, 0x00000230), 'R'}, -{PoreAddress(0x800b, 0x000012d8), 'R'}, -{PoreAddress(0x800b, 0x00000258), 'R'}, +{PoreAddress(0x800b, 0x000004a0), 'T'}, +{PoreAddress(0x8000, 0x00000748), 'T'}, +{PoreAddress(0x800b, 0x00001378), 'T'}, {PoreAddress(0x8000, 0x00000238), 'R'}, -{PoreAddress(0x800b, 0x000011dc), 'T'}, -{PoreAddress(0x8000, 0x000004f8), 'T'}, -{PoreAddress(0x8000, 0x000010e8), 'T'}, -{PoreAddress(0x800b, 0x00000fd4), 'T'}, +{PoreAddress(0x800b, 0x00000260), 'R'}, +{PoreAddress(0x8000, 0x00000240), 'R'}, +{PoreAddress(0x800b, 0x00001260), 'T'}, +{PoreAddress(0x8000, 0x00000554), 'T'}, +{PoreAddress(0x8000, 0x00001190), 'T'}, +{PoreAddress(0x800b, 0x000010a8), 'T'}, +{PoreAddress(0x800b, 0x000010ac), 'T'}, }; static void @@ -227,7 +254,7 @@ init() int i; FAPI_INF("HookManager : " "Indexing global symbols for centaur.sbe_pnor.out"); -for (i = 0; i < 92; i++) { +for (i = 0; i < 106; i++) { HookManager::registerGlobalSymbol(symbols[i], &(info[i])); } } diff --git a/src/usr/pore/poreve/model/poreaddress.C b/src/usr/pore/poreve/model/poreaddress.C index e31ed9535..e2e9a2d93 100644 --- a/src/usr/pore/poreve/model/poreaddress.C +++ b/src/usr/pore/poreve/model/poreaddress.C @@ -1,26 +1,25 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/pore/poreve/model/poreaddress.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/poreve/model/poreaddress.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ // $Id: poreaddress.C,v 1.1 2011/06/08 13:12:50 bcbrock Exp $ /// \file poreaddress.C @@ -35,7 +34,7 @@ using namespace vsbe; // PoreAddress //////////////////////////////////////////////////////////////////////////// -PoreAddress::PoreAddress() : iv_offset(0), iv_memorySpace(0) +PoreAddress::PoreAddress() { } diff --git a/src/usr/pore/poreve/model/poremodel.C b/src/usr/pore/poreve/model/poremodel.C index de4c020bc..eeefe779f 100644 --- a/src/usr/pore/poreve/model/poremodel.C +++ b/src/usr/pore/poreve/model/poremodel.C @@ -1,27 +1,26 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/pore/poreve/model/poremodel.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ -// $Id: poremodel.C,v 1.22 2012/06/18 13:56:57 bcbrock Exp $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/poreve/model/poremodel.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: poremodel.C,v 1.24 2012/08/06 15:11:06 jeshua Exp $ /// \file poremodel.C /// \brief The PORE hardware engine model and interface to the virtual @@ -51,7 +50,7 @@ PoreModel::restart() // Begin bug workaround - registerWriteRaw(PORE_STATUS, 0); + registerWriteRaw(PORE_STATUS, 0x0001000000000000ull); // Stack empty if (iv_ibufId == PORE_SLW) { registerWriteRaw(PORE_CONTROL,0x8005ffffffffffffull); @@ -69,7 +68,7 @@ PoreModel::restart() registerWriteRaw(PORE_OCI_MEMORY_BASE_ADDR1,0); if (iv_ibufId == PORE_SBE) { - registerWriteRaw(PORE_TABLE_BASE_ADDR, 0x0000000100040020ull); + registerWriteRaw(PORE_TABLE_BASE_ADDR, 0x0000000100040028ull); } else { registerWriteRaw(PORE_TABLE_BASE_ADDR, 0); } @@ -169,8 +168,7 @@ PoreModel::run(const uint64_t i_instructions, uint64_t& o_ran) } o_ran++; iv_instructions++; - me = getModelError(); - if (me != 0) { + if ((me = getModelError()) != 0) { break; } } diff --git a/src/usr/pore/poreve/pore_model/ibuf/pore_bus.c b/src/usr/pore/poreve/pore_model/ibuf/pore_bus.c index 7f8c2af27..c14c1738a 100644 --- a/src/usr/pore/poreve/pore_model/ibuf/pore_bus.c +++ b/src/usr/pore/poreve/pore_model/ibuf/pore_bus.c @@ -1,25 +1,25 @@ -// IBM_PROLOG_BEGIN_TAG -// This is an automatically generated prolog. -// -// $Source: src/usr/pore/poreve/pore_model/ibuf/pore_bus.c $ -// -// IBM CONFIDENTIAL -// -// COPYRIGHT International Business Machines Corp. 2012 -// -// p1 -// -// Object Code Only (OCO) source materials -// Licensed Internal Code Source Materials -// IBM HostBoot Licensed Internal Code -// -// The source code for this program is not published or other- -// wise divested of its trade secrets, irrespective of what has -// been deposited with the U.S. Copyright Office. -// -// Origin: 30 -// -// IBM_PROLOG_END +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/poreve/pore_model/ibuf/pore_bus.c $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ /****************************************************************************** * * Virtual PORe Engine @@ -49,7 +49,25 @@ #include "pore_model.h" #include "pore_ibuf.h" +/** + * When running against hardware-simulated I2C memories, the PORE model needs + * to honor the timeout specified in the I2C0 parameter register, as it may + * take a large number of polls for the transaction to complete. In no event + * however do we ever poll more than 2^29 times. + * + * ** HACK FIX ME ** + */ +#if 1 +#define I2C_COMMAND_COMPLETION ({ \ + int __pollThreshold = ((p->i2c_e_param[0].val >> 32) & 0xf); \ + if (__pollThreshold == 0) { \ + __pollThreshold = 15; \ + } \ + 1u << ((__pollThreshold * 2) - 1); \ +}) +#else #define I2C_COMMAND_COMPLETION 16 /* MAX iterations before aborting I2C */ +#endif /*** OCI Bus access **********************************************************/ @@ -90,7 +108,7 @@ static int oci_read(struct pore_bus *b, uint64_t addr, uint8_t *buf, /// the fetch buffer is empty, it does an OCI interface read and /// populates the buffer before returning the word. -static int fetchInstructionWordOci(struct pore_bus *b, PoreAddress *pc, +static int fetchInstructionWordOci(struct pore_bus *b, _PoreAddress *pc, uint32_t *word, int *err_code) { int me = 0; @@ -131,7 +149,7 @@ static int oci_fetch(struct pore_bus *b, uint64_t _pc, { int me; uint32_t i_word; - PoreAddress pc; + _PoreAddress pc; pore_model_t p = b->pore; if (!b || !ibuf_01 || !ibuf_2 || !size || !err_code) @@ -207,81 +225,35 @@ struct pore_fi2cm { }; /** - * Convert a PoreAddress + I2C register offset into a PIB address + * Convert a _PoreAddress + I2C register offset into a PIB address */ static uint32_t -i2cPibAddress(PoreAddress *address, uint16_t offset) +i2cPibAddress(_PoreAddress *address, uint16_t offset) { return ((address->memorySpace & 0x3fff) << 16) + offset; } -static int fi2cm_setAddress(struct pore_bus *b, uint64_t addr, int *err_code) -{ - int rc; - unsigned int count; - pore_model_t p = b->pore; - struct pore_fi2cm *fi2cm = (struct pore_fi2cm *)poreb_get_priv(b); - pore_i2c_en_param_reg *i2cp = fi2cm->i2c_param; - PoreAddress address; - fasti2c_control_reg control; - fasti2c_status_reg status; - uint32_t pib_addr; - - iprintf(p, "############ I2C SET ADDRESS #########################\n"); - - /* 4.7.3.1 Set Address */ - address.val = addr; - - /* 1. Write fast I2C Control Register at PRV address */ - control.val = 0; - control.with_start = 1; - control.with_address = 1; - control.with_stop = 1; - control.read_continue = 0; - control.data_length = 0; /* mark this as address write */ - control.device_address = i2cp->i2c_engine_device_id; - control.read_not_write = 0; /* address write */ - control.speed = i2cp->i2c_engine_speed; - control.port_number = i2cp->i2c_engine_port; - control.address_range = i2cp->i2c_engine_address_range; - - /* Add required address bytes to control register */ - control.val |= (address.offset << - ((4 - i2cp->i2c_engine_address_range)*8)); - - pib_addr = i2cPibAddress(&address, FASTI2C_CONTROL_OFFSET); - rc = pore_pib_write(p, pib_addr, (uint8_t *)&control.val, - sizeof(control.val), err_code); - if (rc < 0) - return rc; - - /* 2. Wait for Data fill-level is 4/8 Bytes by polling fast - * I2C status register at PRV address - */ - pib_addr = i2cPibAddress(&address, FASTI2C_STATUS_OFFSET); - for (count = 0; count < I2C_COMMAND_COMPLETION; count++) { - - rc = pore_pib_read(p, pib_addr, (uint8_t *)&status.val, - sizeof(status.val), err_code); - if (rc != sizeof(status.val)) - break; - - iprintf(p, "I2C_COMMAND_STATUS=%016llx count=%d\n" - " i2c_command_complete = %x\n" - " i2c_fifo_entry_count = %x\n", - (long long)status.val, count, - (unsigned int)status.i2c_command_complete, - (unsigned int)status.i2c_fifo_entry_count); - - if (status.i2c_command_complete) - break; - } - /* Check for timeout or error */ - if (count == I2C_COMMAND_COMPLETION || (rc < 0)) - return pore_handleErrEvent(p, 1, PORE_ERR_I2C_POLLING); - - return rc; -} +/* Modeling Notes + * + * The PORE engine optimizes read access to "fast I2C" memories by using two + * types of read transactions: The first, "Set Address", establishes an + * address in the memory, returns 4 or 8 bytes of data, and effectively + * increments the address in memory. The second, "Read Data", returns data and + * increments the stored address. When fetching instructions the PORE engine + * first establishes the fetch address (and gets the first instruction) with + * "Set Address" and then continues to fetch using "Read Data" until a branch + * is encountered. + * + * This optimization is currently _not_ modeled here. Instead all reads are + * performed using the "Set Address" type operation. There is no functional + * difference between this model and the real hardware other than the fact + * that it is not as efficient as the real hardware, but this would only be + * noticed when running the virtual PORE against a real fast I2C memory + * controller. + * + * The PORE engine does not optimize fast I2C writes. Each write operation + * always includes the address and data. + */ static int fi2cm_read(struct pore_bus *b, uint64_t addr, uint8_t *buf, unsigned int size, int *err_code) @@ -291,7 +263,7 @@ static int fi2cm_read(struct pore_bus *b, uint64_t addr, uint8_t *buf, pore_model_t p = b->pore; struct pore_fi2cm *fi2cm = (struct pore_fi2cm *)poreb_get_priv(b); pore_i2c_en_param_reg *i2cp = fi2cm->i2c_param; - PoreAddress address; + _PoreAddress address; fasti2c_control_reg control; fasti2c_status_reg status; uint32_t pib_addr; @@ -302,10 +274,6 @@ static int fi2cm_read(struct pore_bus *b, uint64_t addr, uint8_t *buf, (i2cp->i2c_engine_address_range != 4))) return PORE_ERR_INVALID_PARAM; - rc = fi2cm_setAddress(b, addr, err_code); - if (rc < 0) - return rc; - iprintf(p, "############ I2C READ (len=%d) #######################\n", size); @@ -386,22 +354,25 @@ static int fi2cm_read(struct pore_bus *b, uint64_t addr, uint8_t *buf, /** * I2C Write - * o Fill control register with required data. If i2c_engine_address_range - * allows, we need to fill the first few bytes into the control register. + * o Fill control register with the address and the required data. If + * the i2c_engine_address_range allows, we need to fill the first few bytes + * of data into the control register behind the address bytes. * o Write the data register with the remaining bytes. + * o Write the control register. * o Poll for completion of the operation. */ static int fi2cm_write(struct pore_bus *b, uint64_t addr, const uint8_t *buf, unsigned int size, int *err_code) { - int rc, count; + int rc; + unsigned int count; pore_model_t p = b->pore; struct pore_fi2cm *fi2cm = (struct pore_fi2cm *)poreb_get_priv(b); pore_i2c_en_param_reg *i2cp = fi2cm->i2c_param; fasti2c_control_reg control; fasti2c_status_reg status; - PoreAddress address; + _PoreAddress address; uint32_t pib_addr; uint64_t write_data; @@ -410,17 +381,13 @@ static int fi2cm_write(struct pore_bus *b, uint64_t addr, (i2cp->i2c_engine_address_range != 4))) return PORE_ERR_INVALID_PARAM; - rc = fi2cm_setAddress(b, addr, err_code); - if (rc < 0) - return rc; - iprintf(p, "############ I2C WRITE ###############################\n"); /* 4.7.3.3 Write Data (8 byte, SBE memory interface only) */ address.val = addr; write_data = *((uint64_t *)buf); - /* 1. Write fast I2C Control Register at PRV address */ + /* 1. Set up fast I2C Control Register */ control.val = 0; control.with_start = 1; control.with_address = 1; @@ -442,14 +409,7 @@ static int fi2cm_write(struct pore_bus *b, uint64_t addr, control.val |= (write_data >> (64 - ((4-i2cp->i2c_engine_address_range)*8))); - pib_addr = i2cPibAddress(&address, FASTI2C_CONTROL_OFFSET); - rc = pore_pib_write(p, pib_addr, (uint8_t *)&control.val, - sizeof(control.val), err_code); - if (rc < 0) - return rc; - /* 2. Write fast I2C Data Register at PRV address */ - /* Write remaining data bytes to data register (left algined)*/ write_data = write_data << ((4 - i2cp->i2c_engine_address_range) * 8); @@ -459,8 +419,15 @@ static int fi2cm_write(struct pore_bus *b, uint64_t addr, if (rc < 0) return rc; + /* 3. Write fast I2C Control Register at PRV address */ + pib_addr = i2cPibAddress(&address, FASTI2C_CONTROL_OFFSET); + rc = pore_pib_write(p, pib_addr, (uint8_t *)&control.val, + sizeof(control.val), err_code); + if (rc < 0) + return rc; + /** - * 3. Wait and poll fast I2C status register for operation to + * 4. Wait and poll fast I2C status register for operation to * complete at PRV address */ /* FIXME Check instead bit 44 (which is not right in my @@ -518,7 +485,7 @@ static int fi2c_read(struct pore_bus *b, uint64_t addr, uint8_t *buf, int i; uint32_t port; pore_model_t p = b->pore; - PoreAddress address; + _PoreAddress address; bprintf(p, " %-12s: %s(%p, 0x%llx, %p, %x)\n", b->name, __func__, b, (long long)addr, buf, len); @@ -557,7 +524,7 @@ static int fi2c_write(struct pore_bus *b, uint64_t addr, int i; uint32_t port; pore_model_t p = b->pore; - PoreAddress address; + _PoreAddress address; address.val = addr; port = address.memorySpace & 0xf; /* must match i2c_engine_id */ @@ -593,7 +560,7 @@ static int fi2c_fetch(struct pore_bus *b, uint64_t _pc, { int me = PORE_SUCCESS; uint32_t i_word; - PoreAddress pc; + _PoreAddress pc; pore_model_t p = b->pore; if (!b || !ibuf_01 || !ibuf_2 || !size || !err_code) diff --git a/src/usr/pore/poreve/pore_model/ibuf/pore_fi2c.c b/src/usr/pore/poreve/pore_model/ibuf/pore_fi2c.c index 943751d86..a5b1de5f6 100644 --- a/src/usr/pore/poreve/pore_model/ibuf/pore_fi2c.c +++ b/src/usr/pore/poreve/pore_model/ibuf/pore_fi2c.c @@ -1,25 +1,25 @@ -// IBM_PROLOG_BEGIN_TAG -// This is an automatically generated prolog. -// -// $Source: src/usr/pore/poreve/pore_model/ibuf/pore_fi2c.c $ -// -// IBM CONFIDENTIAL -// -// COPYRIGHT International Business Machines Corp. 2012 -// -// p1 -// -// Object Code Only (OCO) source materials -// Licensed Internal Code Source Materials -// IBM HostBoot Licensed Internal Code -// -// The source code for this program is not published or other- -// wise divested of its trade secrets, irrespective of what has -// been deposited with the U.S. Copyright Office. -// -// Origin: 30 -// -// IBM_PROLOG_END +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/poreve/pore_model/ibuf/pore_fi2c.c $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ /****************************************************************************** * * Virtual PORe Engine @@ -241,7 +241,6 @@ static int finalDataWrite(struct fi2c *p, const uint8_t *buf, unsigned int len) return me; } -// Modeling notes: // // o The RESET register is not modeled here // @@ -251,21 +250,30 @@ static int finalDataWrite(struct fi2c *p, const uint8_t *buf, unsigned int len) // read of the status register. This is done to simplify the PORE // engine model. // -// o Only the follwing types of control register actions are modeled: -// * Address write : with_start; with_address; !with_continue; with_stop; -// data_length == 0 -// * Data read : with_start; with_address; !with_continue; with_stop; -// data_length == [4,8] -// * Data write : with_start; with_address; !with_continue; with_stop; -// data_length == 8 +// o Only the following types of control register actions are modeled: +// +// * Set address : with_start; with_address; !with_continue; with_stop; +// RNW == 1; Data_length == [4, 8]; +// Address length != 0; Address provided +// Setting the address also fetches data and increments +// the address stored in memory +// +// * Data Read : with_start; with_address; !with_continue; with_stop; +// RNW == 1; Data_length == [4, 8]; +// Address length == 0; No address provided +// This operation fetches data and increments the address +// stored in memory. +// +// * Data write : with_start; with_address; !with_continue; with_stop; +// RNW == 0; Data_length == 8 +// Addrress length != 0; Address provided // -// o The memory models hold the last address written +// o The memory models hold the last address written and implement the +// address auto-increment after every read or write // // o Redundant reads of the STATUS register are allowed // -// o PORE only does 4/8 byte reads and 8 byte writes, so any other data -// access is considered an error (although the models could easily be -// extended to allow them). +// o PORE only allows 4/8 byte reads and 8 byte writes. static int fi2c_read(struct pore_bus *b, uint64_t addr, uint8_t *buf, unsigned int len, @@ -448,13 +456,6 @@ static int fi2c_write(struct pore_bus *b, uint64_t addr, rc = PORE_ERR_FASTI2C_CONTROL_ERROR; break; } - if (p->control.data_length == 0) { - rc = addressWrite(p); - if (rc < 0) - break; - rc = len; - break; - } if (p->control.data_length != 8) { BUG(); p->state = ERROR; @@ -465,7 +466,6 @@ static int fi2c_write(struct pore_bus *b, uint64_t addr, if (rc == PORE_SUCCESS) rc = len; break; - } else { if ((p->control.data_length != 4) && (p->control.data_length != 8)) { @@ -474,6 +474,11 @@ static int fi2c_write(struct pore_bus *b, uint64_t addr, rc = PORE_ERR_FASTI2C_CONTROL_ERROR; break; } + if (p->control.address_range != 0) { + rc = addressWrite(p); + if (rc < 0) + break; + } rc = dataRead(p); break; } diff --git a/src/usr/pore/poreve/pore_model/ibuf/pore_model.c b/src/usr/pore/poreve/pore_model/ibuf/pore_model.c index 849155169..8b0d5747c 100644 --- a/src/usr/pore/poreve/pore_model/ibuf/pore_model.c +++ b/src/usr/pore/poreve/pore_model/ibuf/pore_model.c @@ -1,26 +1,25 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/pore/poreve/pore_model/ibuf/pore_model.c $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/poreve/pore_model/ibuf/pore_model.c $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ /****************************************************************************** * * Virtual PORe Engine @@ -108,10 +107,10 @@ pore_stack0_reg_write(pore_model_t p, uint64_t val, uint64_t mask) pps0.val = val & mask; if (pps0.set_stack_pointer) { newSp = pps0.new_stack_pointer; - if ((newSp != 0) && - (newSp != 1) && + if ((newSp != 1) && (newSp != 2) && - (newSp != 4)) { + (newSp != 4) && + (newSp != 8)) { me = PORE_ERR_INVALID_STACK_POINTER; } else { p->status.stack_pointer = newSp; @@ -438,7 +437,7 @@ static void incrPc(pore_model_t p) p->status.pc += p->opcode_len; } -static void setJmpTarget(int offset, PoreAddress *next_pc) +static void setJmpTarget(int offset, _PoreAddress *next_pc) { next_pc->offset += offset * 4; } @@ -545,7 +544,7 @@ static int setAluFlags(pore_model_t p, int64_t op1, int64_t op2, /// Relocate a memory address if it's in the relocation region void pore_relocateAddress(pore_model_t p, uint64_t *addr) { - PoreAddress address; + _PoreAddress address; address.val = *addr; @@ -556,9 +555,9 @@ void pore_relocateAddress(pore_model_t p, uint64_t *addr) } /// Compute OCI effective and real addresses and handle hooks. The -/// returned address is the real (physical) PoreAddress. +/// returned address is the real (physical) _PoreAddress. static int computeOciDataAddress(pore_model_t p, uint32_t ima24, - PoreAddress *address, int read_not_write) + _PoreAddress *address, int read_not_write) { uint32_t base_select = ima24 & 0x400000; pore_oci_base_address_reg oci_base; @@ -692,14 +691,14 @@ static int push(pore_model_t p, uint64_t next_pc, int error) int rc = PORE_SUCCESS; pore_pc_stack0_reg pc_stack0; - if (p->status.stack_pointer == 0x4) { + if (p->status.stack_pointer == 0x8) { BUG(); p->dbg1.pc_stack_ovflw_undrn_err = 1; p->control.start_stop = 1; /* FIXME This is brute force */ return PORE_ERR_STACK_OVERFLOW; } - if ((p->status.stack_pointer == 0x2) && !error) { + if ((p->status.stack_pointer == 0x4) && !error) { p->dbg1.pc_stack_ovflw_undrn_err = 1; rc = pore_handleErrEvent(p, 2, PORE_ERR_STACK_OVERFLOW); if (rc < 0) { @@ -710,17 +709,15 @@ static int push(pore_model_t p, uint64_t next_pc, int error) pc_stack0.val = p->pc_stack[0].val; switch (p->status.stack_pointer) { - case 0x0: case 0x1: case 0x2: + case 0x4: p->pc_stack[2].pc_stack = p->pc_stack[1].pc_stack; p->pc_stack[1].pc_stack = p->pc_stack[0].pc_stack; pc_stack0.pc_stack = next_pc; pore_stack0_reg_write(p, pc_stack0.val, PORE_BITS_0_63); - p->status.stack_pointer = - (p->status.stack_pointer == 0) ? 1 : - (p->status.stack_pointer << 1); + p->status.stack_pointer = (p->status.stack_pointer << 1); break; default: return PORE_ERR_INVALID_STACK_POINTER; @@ -737,22 +734,22 @@ static int push(pore_model_t p, uint64_t next_pc, int error) * 0100: Stack filled up to level 2 * 1000: Stack filled up to level 3 (error handler only) */ -static int pop(pore_model_t p, PoreAddress *next_pc) +static int pop(pore_model_t p, _PoreAddress *next_pc) { int rc; pore_pc_stack0_reg pc_stack0; pc_stack0.val = p->pc_stack[0].val; switch (p->status.stack_pointer) { - case 0x0: + case 0x1: p->dbg1.pc_stack_ovflw_undrn_err = 1; rc = pore_handleErrEvent(p, 2, PORE_ERR_STACK_UNDERFLOW); if (rc < 0) return rc; - case 0x1: case 0x2: case 0x4: + case 0x8: next_pc->val = pc_stack0.pc_stack; pc_stack0.pc_stack = p->pc_stack[1].pc_stack; pore_stack0_reg_write(p, pc_stack0.val, PORE_BITS_0_63); @@ -840,7 +837,7 @@ static void signalFatalError(pore_model_t p) int pore_handleErrEvent(pore_model_t p, int error_in, int model_err) { - int me; + int me, pc_offs; int error = error_in; // Check for error on error. If yes change to err event @@ -850,6 +847,10 @@ pore_handleErrEvent(pore_model_t p, int error_in, int model_err) if (p->dbg1.debug_regs_locked == 1) error = 4; + pc_offs = p->opcode_len; + if ((pc_offs != 0) && (pc_offs != 4) && (pc_offs != 12)) + eprintf(p, "%s: err: illegal pc_offs=%d\n", __func__, pc_offs); + switch (error) { case 0: if ((p->error_mask.enable_err_output0 == 0) && @@ -869,12 +870,13 @@ pore_handleErrEvent(pore_model_t p, int error_in, int model_err) p->dbg1.debug_regs_locked = 1; /* push pc onto stack, only if there is space */ - me = push(p, p->status.pc, 1); + me = push(p, p->status.pc + pc_offs, 1); if (me < 0) { model_err = me; break; } pore_errorVector(p, 0); + model_err = PORE_ERR_HANDLED_BY_CODE; } break; case 1: @@ -895,12 +897,13 @@ pore_handleErrEvent(pore_model_t p, int error_in, int model_err) p->dbg1.debug_regs_locked = 1; /* push pc onto stack, only if there is space */ - me = push(p, p->status.pc, 1); + me = push(p, p->status.pc + pc_offs, 1); if (me < 0) { model_err = me; break; } pore_errorVector(p, 1); + model_err = PORE_ERR_HANDLED_BY_CODE; } break; case 2: @@ -921,12 +924,13 @@ pore_handleErrEvent(pore_model_t p, int error_in, int model_err) } else if (p->error_mask.enable_err_handler2) { /* push pc onto stack, only if there is space */ - me = push(p, p->status.pc, 1); + me = push(p, p->status.pc + pc_offs, 1); if (me < 0) { model_err = me; break; } pore_errorVector(p, 2); + model_err = PORE_ERR_HANDLED_BY_CODE; } break; case 3: @@ -947,12 +951,13 @@ pore_handleErrEvent(pore_model_t p, int error_in, int model_err) } else if (p->error_mask.enable_err_handler3) { /* push pc onto stack, only if there is space */ - me = push(p, p->status.pc, 1); + me = push(p, p->status.pc + pc_offs, 1); if (me < 0) { model_err = me; break; } pore_errorVector(p, 3); + model_err = PORE_ERR_HANDLED_BY_CODE; } break; case 4: @@ -970,12 +975,13 @@ pore_handleErrEvent(pore_model_t p, int error_in, int model_err) p->control.start_stop = 1; } else if (p->error_mask.enable_err_handler4) { - me = push(p, p->status.pc, 1); + me = push(p, p->status.pc + pc_offs, 1); if (me < 0) { model_err = me; break; } pore_errorVector(p, 4); + model_err = PORE_ERR_HANDLED_BY_CODE; } break; default: @@ -1193,7 +1199,7 @@ computeDirectPibDataAddress(pore_model_t p, uint32_t ima24, uint32_t *pibAddress, int read_not_write) { int me = 0; - PoreAddress address; + _PoreAddress address; uint32_t baseSelect, localAddress, chipletId, mc, port; pore_prv_base_address_reg *prv_base; @@ -1291,7 +1297,7 @@ int pore_pib_read(pore_model_t p, uint64_t addr, uint8_t *buf, /// PIB fetches. static int -fetchInstructionWordPibDirect(pore_model_t p, PoreAddress *pc, +fetchInstructionWordPibDirect(pore_model_t p, _PoreAddress *pc, uint32_t *word, int *err_code) { int rc = 0; @@ -1334,7 +1340,7 @@ static int pore_pib_fetch(pore_model_t p, uint64_t _pc, { int me; uint32_t i_word; - PoreAddress pc; + _PoreAddress pc; *ibuf_01 = *ibuf_2 = 0; pc.val = _pc; @@ -1512,7 +1518,7 @@ static int inExeInterfaceWrite(pore_model_t p, uint64_t write_data) int rc; PoreInlineDecode *dis = &p->dis; uint32_t addr_space, pib_addr; - PoreAddress address; + _PoreAddress address; uint64_t addr = dis->ima24; /* OCI/MEM Address Space *********************************************/ @@ -1534,7 +1540,7 @@ static int inExeInterfaceWrite(pore_model_t p, uint64_t write_data) if (rc == sizeof(write_data)) return PORE_SUCCESS; - rc = pore_handleErrEvent(p, 2, rc); + rc = pore_handleErrEvent(p, 1, rc); return rc; } @@ -1566,7 +1572,7 @@ static int inExeInterfaceRead(pore_model_t p, uint64_t *read_data) int rc; PoreInlineDecode *dis = &p->dis; uint32_t addr_space, pib_addr; - PoreAddress address; + _PoreAddress address; uint64_t addr = dis->ima24; *read_data = 0; @@ -1591,7 +1597,7 @@ static int inExeInterfaceRead(pore_model_t p, uint64_t *read_data) if (rc == sizeof(*read_data)) return PORE_SUCCESS; - rc = pore_handleErrEvent(p, 2, rc); + rc = pore_handleErrEvent(p, 1, rc); return rc; } @@ -1759,7 +1765,7 @@ static const uint16_t bin_2_unary[] = { 0x9000, /* 0xf 15 */ }; -static int pore_scand_read(pore_model_t p, PoreAddress *addr, uint32_t *word) +static int pore_scand_read(pore_model_t p, _PoreAddress *addr, uint32_t *word) { int rc; uint64_t data; @@ -1817,7 +1823,7 @@ static int pore_scand(pore_model_t p) pore_scratch0_reg *scr0 = &p->scratch0; uint32_t scan_data = 0, crc32_data = 0; uint64_t write_data; - PoreAddress addr; + _PoreAddress addr; PibAddress pib_addr; shift_eng_cmd_reg scan_sel; scan_type_select_reg scan_type_sel; @@ -1919,7 +1925,7 @@ static int execute(pore_model_t p) PoreInlineDecode *dis; uint64_t write_data, read_data = 0; int64_t op1, op2; - PoreAddress next_pc; + _PoreAddress next_pc; if (!p) return PORE_ERR_INVALID_PARAM; @@ -1992,7 +1998,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } p->branchTaken = 1; @@ -2006,7 +2013,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } if (__readReg(p, (pore_internal_reg_t)dis->tR) == 0) { @@ -2022,7 +2030,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } if (__readReg(p, (pore_internal_reg_t)dis->tR) != 0) { @@ -2052,7 +2061,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } me = push(p, p->status.pc + 4, 0); @@ -2111,7 +2121,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } if (dis->tR != PORE_SCRATCH1_ENC && @@ -2119,7 +2130,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } __writeReg(p, (pore_internal_reg_t)dis->tR, @@ -2133,7 +2145,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } if (dis->tR != PORE_SCRATCH1_ENC && @@ -2141,7 +2154,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } __writeReg(p, (pore_internal_reg_t)dis->tR, @@ -2155,7 +2169,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } if (dis->tR != PORE_SCRATCH1_ENC && @@ -2163,7 +2178,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } __writeReg(p, (pore_internal_reg_t)dis->tR, @@ -2177,7 +2193,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } __writeReg(p, (pore_internal_reg_t)dis->tR, @@ -2190,7 +2207,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } __writeReg(p, (pore_internal_reg_t)dis->tR, @@ -2203,7 +2221,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } __writeReg(p, (pore_internal_reg_t)dis->tR, @@ -2218,7 +2237,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } @@ -2238,7 +2258,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } @@ -2259,7 +2280,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } @@ -2279,7 +2301,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } @@ -2299,7 +2322,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } if (dis->tR != PORE_SCRATCH1_ENC && @@ -2307,7 +2331,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } @@ -2333,7 +2358,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } else if ( @@ -2342,7 +2368,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } else if (dis->tR != PORE_SCRATCH1_ENC && @@ -2350,7 +2377,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } else { @@ -2370,7 +2398,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } /** @@ -2388,7 +2417,8 @@ static int execute(pore_model_t p) BUG(); if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instruction_operand = 1; - me = pore_handleErrEvent(p,2,PORE_ERR_INVALID_OPERAND); + me = pore_handleErrEvent(p, 2, + PORE_ERR_INVALID_OPERAND); break; } @@ -2492,11 +2522,12 @@ static int execute(pore_model_t p) break; default: - eprintf(p, "err: Invalid Instruction Encoding: " + /* Disabled printout as requested in HW218122 */ + /* eprintf(p, "err: Invalid Instruction Encoding: " " %08x %08x %08x\n", (unsigned int)p->ibuf_01.ibuf0, (unsigned int)p->ibuf_01.ibuf0, - (unsigned int)p->ibuf_2.ibuf2); + (unsigned int)p->ibuf_2.ibuf2); */ if (p->dbg1.debug_regs_locked == 0) p->dbg1.invalid_instr_code = 1; @@ -2541,6 +2572,15 @@ static int execute(pore_model_t p) } } + /** + * The vPORE has been setup to handle this error via the + * exception handler code. Therefore ignore this failure and + * continue. + */ + if (me == PORE_ERR_HANDLED_BY_CODE) { + me = PORE_ERROR_IGNORED; + } + // Step mode. don't update state and don't schedule next step // Condition can occur when we are hitting an error during // instruction execution, e.g. a pib_read failed. @@ -2649,8 +2689,8 @@ int pore_step(pore_model_t p) void pore_dump(pore_model_t p) { - PoreAddress a0, a1; - PoreAddress sp0, sp1, sp2; + _PoreAddress a0, a1; + _PoreAddress sp0, sp1, sp2; int sp; uint32_t p0, p1; @@ -2766,99 +2806,6 @@ void pore_dump(pore_model_t p) /* Model Creation and Reset **************************************************/ -static int __pore_flush_reset(pore_model_t p) -{ - /* --------------- always ------------------------------------------ */ - /* STATUS */ - p->status.val = 0; - p->status.cur_state = PORE_STATE_WAIT; - p->status.pc = 0; - - p->prv_base[0].val = 0; - p->prv_base[1].val = 0; - p->oci_base[0].val = 0; - p->oci_base[1].val = 0; - - /* SCR0, SRC1, IBUF01, IBUF2 */ - p->scratch0.val = 0; - p->scratch1 = 0; - p->scratch2 = 0; - p->ibuf_01.val = 0; - p->ibuf_2.val = 0; - - /* ID_FLAGS, DBG0, DBG1, PC_STACK0/1/2, DATA0 */ - p->id_flags.val = p->id_flags.ibuf_id; /* keep ibuf_id */ - p->dbg0.val = 0; - p->dbg1.val = 0; - p->pc_stack[0].val = 0; /* clears one bits on a write */ - p->pc_stack[1].val = 0; - p->pc_stack[2].val = 0; - p->data0 = 0; - - /* Internal model state */ - p->err_code = 0; - p->branchTaken = 0; - p->broken = 0; - p->singleStep = 0; - p->forcedBranchMode = FORCED_BRANCH_DISALLOWED; - p->forcedPc = 0; - - /* Externally attached busses */ - poreb_reset(p->pib); /* reset bus models, e.g. clear buffers */ - poreb_reset(p->mem); - - return 0; -} - -int pore_flush_reset(pore_model_t p) -{ - dprintf(p, "%s: %s\n", __func__, p->name); - - /* --------------- exclude those regs for interruptible PORE case -- */ - /* EXE_TRIGGER */ - p->exe_trigger.val = 0; - - /* CONTROL */ - p->control.val = 0; - p->control.start_stop = 1; - p->control.lock_exe_trig = 0; - p->control.check_parity = 0; - p->control.prv_parity = 0; - p->control.pc_brk_pt = 0xffffffffffffull; - - /* TABLE_BASE */ - p->table_base_addr.val = 0; - - /* ERROR_MASK ... only at 1st init */ - /* page 74: IBUF Err Mask, not altered during functional PORE reset. */ - - /* MEMORY_RELOC */ - p->memory_reloc.val = 0; - - /* I2C_PARAM0/1/2 ... only at 1st init */ - - __pore_flush_reset(p); - return 0; -} - -pore_model_t pore_model_create(const char *name) -{ - pore_model_t p; - - p = (pore_model_t)malloc(sizeof(*p)); - if (!p) - return NULL; - memset(p, 0, sizeof(*p)); - - p->name = name; - pore_flush_reset(p); - p->enableHookInstruction = 0; - p->enableAddressHooks = 0; - - p->trace_flags = PORE_TRACE_ERR; - return p; -} - void pore_model_destroy(pore_model_t p) { poreb_destroy(p->pib); @@ -3081,35 +3028,190 @@ static int __fake_reset(struct pore_bus *b) return 0; } -pore_model_t -pore_sbe_create(pore_bus_t pib) +/** + * @brief Here we are setting the engine type and those registers + * which are only setup on engine creation. Also model internal states + * are reset to their start values. + */ +pore_model_t pore_model_create(const char *name) { pore_model_t p; - pore_bus_t fi2cm[3], pore2fi2cm; - p = pore_model_create("SBE"); + p = (pore_model_t)malloc(sizeof(*p)); if (!p) return NULL; - p->id_flags.ibuf_id = PORE_IBUF_ID_SBE; - p->error_mask.val = 0x00BFF00000000000ull; /* FIXME spec undefined */ + memset(p, 0, sizeof(*p)); + + + /* Some registers must only be set at model creation time */ + /* Setup depends on model type ------------------------------------- */ + p->name = name; + + /* ERROR_MASK ... only at 1st init */ + /* page 74: IBUF Err Mask, not altered during PORE reset. */ + p->error_mask.val = 0x00BFF00000000000ull; + + /* I2C_PARAM0/1/2 ... only at 1st init */ + p->i2c_e_param[0].val = 0x0; + p->i2c_e_param[1].val = 0x0; + p->i2c_e_param[2].val = 0x0; + + if (strcmp(p->name, "SBE") == 0) { + p->id_flags.ibuf_id = PORE_IBUF_ID_SBE; + + /* I2C_PARAM0/1/2 only at 1st init */ + p->i2c_e_param[0].i2c_engine_speed = 0x0f; + + } else if (strcmp(p->name, "SLW") == 0) { + p->id_flags.ibuf_id = PORE_IBUF_ID_SLW; + } else if (strcmp(p->name, "GPE0") == 0) { + p->id_flags.ibuf_id = PORE_IBUF_ID_GPE0; + } else if (strcmp(p->name, "GPE1") == 0) { + p->id_flags.ibuf_id = PORE_IBUF_ID_GPE1; + } + + /* Setup register default values */ + pore_flush_reset(p); - p->control.interrupt_sequencer_enabled = 0; - p->control.pore_interruptible = 0; + p->enableHookInstruction = 0; + p->enableAddressHooks = 0; + p->trace_flags = PORE_TRACE_ERR; + return p; +} - /* SEEPROM */ - p->i2c_e_param[0].i2c_engine_speed = 0x0f; +/** + * @brief The interruptible PORe implementation does not reset all + * registers to their default state. Therefore this function only + * resets those, which must be reset in that specific case. + */ +static int __pore_flush_reset(pore_model_t p) +{ + /* --------------- always ------------------------------------------ */ + + /* STATUS */ + p->status.val = 0; + p->status.cur_state = PORE_STATE_WAIT; + p->status.stack_pointer = 0x1; /* HW218121 */ + p->status.pc = 0; /* OCI/MEM Route */ + p->prv_base[0].val = 0; + p->prv_base[1].val = 0; p->oci_base[0].val = 0; p->oci_base[1].val = 0; - /* The 0x00040000 in the SBE address space translates to the - * 0x00008000 (>>3) on the PIB bus. - */ - /* Table base address defines where start and exception vectors are */ + /* SCR0, SRC1, IBUF01, IBUF2 */ + p->scratch0.val = 0; + p->scratch1 = 0; + p->scratch2 = 0; + p->ibuf_01.val = 0; + p->ibuf_2.val = 0; + + /* ID_FLAGS, DBG0, DBG1, PC_STACK0/1/2, DATA0 */ + p->id_flags.val = p->id_flags.ibuf_id; /* keep ibuf_id */ + p->dbg0.val = 0; + p->dbg1.val = 0; + p->pc_stack[0].val = 0; /* clears one bits on a write */ + p->pc_stack[1].val = 0; + p->pc_stack[2].val = 0; + p->data0 = 0; + + /* Internal model state */ + p->err_code = 0; + p->branchTaken = 0; + p->broken = 0; + p->singleStep = 0; + p->forcedBranchMode = FORCED_BRANCH_DISALLOWED; + p->forcedPc = 0; + + /* Externally attached busses */ + poreb_reset(p->pib); /* reset bus models, e.g. clear buffers */ + poreb_reset(p->mem); + + return 0; +} + +/** + * @brief This is the regular PORe reset case. Some registers depend + * on the type of the engine, other don't. Note that there are even + * registers which are not reset here, but only in case of engine + * instance creation. See specifiction. + */ +int pore_flush_reset(pore_model_t p) +{ + dprintf(p, "%s: %s\n", __func__, p->name); + + /* --------------- exclude those regs for interruptible PORE case -- */ + /* EXE_TRIGGER */ + p->exe_trigger.val = 0; + + /* CONTROL */ + p->control.val = 0; + p->control.start_stop = 1; + p->control.lock_exe_trig = 0; + p->control.check_parity = 0; + p->control.prv_parity = 0; + p->control.pc_brk_pt = 0xffffffffffffull; + + /* TABLE_BASE */ p->table_base_addr.val = 0; - p->table_base_addr.memory_space = 0x00001; /* for SBE */ - p->table_base_addr.table_base_address = 0x00040020; /* for SBE */ + + /* ERROR_MASK ... only at 1st init */ + /* page 74: IBUF Err Mask, not altered during functional PORE reset. */ + + /* MEMORY_RELOC */ + p->memory_reloc.val = 0; + + /* I2C_PARAM0/1/2 ... only at 1st init, see pore_model_create() */ + + /* Setup depends on model type ------------------------------------- */ + if (strcmp(p->name, "SBE") == 0) { + p->id_flags.ibuf_id = PORE_IBUF_ID_SBE; + + /* CONTROL */ + p->control.interrupt_sequencer_enabled = 0; + p->control.pore_interruptible = 0; + + /* The 0x00040000 in the SBE address space translates + * to the 0x00008000 (>>3) on the PIB bus. + */ + /* TABLE_BASE */ + p->table_base_addr.memory_space = 0x00001; /* SBE */ + p->table_base_addr.table_base_address = 0x00040028; /* SBE */ + + } else { + /* TABLE_BASE */ + p->table_base_addr.memory_space = 0x0; /* SLW/GPE */ + p->table_base_addr.table_base_address = 0x0; /* SLW/GPE */ + } + + if (strcmp(p->name, "SLW") == 0) { + p->id_flags.ibuf_id = PORE_IBUF_ID_SLW; + + /* CONTROL */ + p->control.interrupt_sequencer_enabled = 1; /* SLW */ + p->control.pore_interruptible = 1; /* SLW */ + + } else if (strcmp(p->name, "GPE0") == 0) { + p->id_flags.ibuf_id = PORE_IBUF_ID_GPE0; + + } else if (strcmp(p->name, "GPE1") == 0) { + p->id_flags.ibuf_id = PORE_IBUF_ID_GPE1; + } + + __pore_flush_reset(p); + return 0; +} + +pore_model_t +pore_sbe_create(pore_bus_t pib) +{ + pore_model_t p; + pore_bus_t fi2cm[3], pore2fi2cm; + + p = pore_model_create("SBE"); + if (!p) + return NULL; /* setup reference for the case it is not yet done. */ if (pib) @@ -3140,8 +3242,7 @@ pore_sbe_create(pore_bus_t pib) } static pore_model_t -__slw_create(const char *name, pore_bus_t pib, pore_bus_t oci, - uint32_t ibuf_id) +__slw_gpe_create(const char *name, pore_bus_t pib, pore_bus_t oci) { pore_model_t p; struct pore_bus *pore2oci_b; @@ -3149,11 +3250,6 @@ __slw_create(const char *name, pore_bus_t pib, pore_bus_t oci, p = pore_model_create(name); if (!p) return NULL; - p->id_flags.ibuf_id = ibuf_id; - p->error_mask.val = 0x00BFF00000000000ull; - - p->table_base_addr.memory_space = 0x00000; /* for SLW/GPE */ - p->table_base_addr.table_base_address = 0x00000000; /* for SLW/GPE */ /* setup reference for the case it is not yet done. */ if (pib) @@ -3186,22 +3282,17 @@ __slw_create(const char *name, pore_bus_t pib, pore_bus_t oci, pore_model_t pore_slw_create(pore_bus_t pib, pore_bus_t oci) { - pore_model_t pore; - - pore = __slw_create("SLW", pib, oci, PORE_IBUF_ID_SLW); - pore->control.interrupt_sequencer_enabled = 1; - pore->control.pore_interruptible = 1; - return pore; + return __slw_gpe_create("SLW", pib, oci); } pore_model_t pore_gpe0_create(pore_bus_t pib, pore_bus_t oci) { - return __slw_create("GPE0", pib, oci, PORE_IBUF_ID_GPE0); + return __slw_gpe_create("GPE0", pib, oci); } pore_model_t pore_gpe1_create(pore_bus_t pib, pore_bus_t oci) { - return __slw_create("GPE1", pib, oci, PORE_IBUF_ID_GPE1); + return __slw_gpe_create("GPE1", pib, oci); } diff --git a/src/usr/pore/poreve/pore_model/ibuf/pore_regs.h b/src/usr/pore/poreve/pore_model/ibuf/pore_regs.h index 8caa50c1a..0716984f1 100644 --- a/src/usr/pore/poreve/pore_model/ibuf/pore_regs.h +++ b/src/usr/pore/poreve/pore_model/ibuf/pore_regs.h @@ -1,26 +1,25 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/pore/poreve/pore_model/ibuf/pore_regs.h $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/poreve/pore_model/ibuf/pore_regs.h $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __PORE_REGS__ #define __PORE_REGS__ @@ -661,7 +660,7 @@ typedef union { #endif }; uint64_t val; -} PoreAddress; +} _PoreAddress; typedef union { struct { diff --git a/src/usr/pore/poreve/pore_model/include/pore_model.h b/src/usr/pore/poreve/pore_model/include/pore_model.h index 90ee2247c..ef3425f64 100644 --- a/src/usr/pore/poreve/pore_model/include/pore_model.h +++ b/src/usr/pore/poreve/pore_model/include/pore_model.h @@ -1,26 +1,25 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/pore/poreve/pore_model/include/pore_model.h $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/poreve/pore_model/include/pore_model.h $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __PORE_MODEL__ #define __PORE_MODEL__ @@ -51,7 +50,7 @@ extern "C" { #endif /** Version of the vPORe model */ -#define PORE_MODEL_VERSION 0x0001000E +#define PORE_MODEL_VERSION 0x00010012 /** * Different PORe incarations @@ -108,6 +107,7 @@ extern "C" { #define PORE_ERR_NOT_MAPPED_ON_FASTI2C -134 #define PORE_ERR_BUS_COLLISION -135 +#define PORE_ERR_HANDLED_BY_CODE -200 /* ... more to come */ /****************************************************************************** diff --git a/src/usr/pore/poreve/pore_model/wrapper/vsbe.C b/src/usr/pore/poreve/pore_model/wrapper/vsbe.C index ac15807e5..832f8f3f3 100644 --- a/src/usr/pore/poreve/pore_model/wrapper/vsbe.C +++ b/src/usr/pore/poreve/pore_model/wrapper/vsbe.C @@ -1,25 +1,25 @@ -// IBM_PROLOG_BEGIN_TAG -// This is an automatically generated prolog. -// -// $Source: src/usr/pore/poreve/pore_model/wrapper/vsbe.C $ -// -// IBM CONFIDENTIAL -// -// COPYRIGHT International Business Machines Corp. 2012 -// -// p1 -// -// Object Code Only (OCO) source materials -// Licensed Internal Code Source Materials -// IBM HostBoot Licensed Internal Code -// -// The source code for this program is not published or other- -// wise divested of its trade secrets, irrespective of what has -// been deposited with the U.S. Copyright Office. -// -// Origin: 30 -// -// IBM_PROLOG_END +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/poreve/pore_model/wrapper/vsbe.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ /****************************************************************************** * * \file vsbe.C @@ -342,19 +342,19 @@ ModelError Vsbe::registerRead(const vsbe::PoreRegisterOffset i_offset, ModelError Vsbe::registerWrite(const vsbe::PoreRegisterOffset i_offset, const uint64_t i_data, const size_t i_size) { + int rc; + pore_reg_t reg = PoreRegOffs_to_pore(vsbe::PoreRegisterOffset(i_offset & ~0x7)); if (((i_offset & 0x7) == 0x4) && (i_size == 4)) { // lower 32-bit - pore_writeReg(iv_engine, reg, i_data, PORE_BITS_32_63); - return ME_SUCCESS; - } - if (((i_offset & 0x7) == 0x0) && (i_size == 4)) { // upper 32-bit - pore_writeReg(iv_engine, reg, i_data << 32, PORE_BITS_0_31); - return ME_SUCCESS; - } - pore_writeReg(iv_engine, reg, i_data, PORE_BITS_0_63); - return ME_SUCCESS; + rc = pore_writeReg(iv_engine, reg, i_data, PORE_BITS_32_63); + } else if (((i_offset & 0x7) == 0x0) && (i_size == 4)) { // upper 32-bit + rc = pore_writeReg(iv_engine, reg, i_data << 32, PORE_BITS_0_31); + } else { + rc = pore_writeReg(iv_engine, reg, i_data, PORE_BITS_0_63); + } + return (rc ? ME_REGISTER_WRITE_ERROR : ME_SUCCESS); } ModelError Vsbe::registerReadRaw(const vsbe::PoreRegisterOffset i_offset, @@ -381,19 +381,19 @@ ModelError Vsbe::registerReadRaw(const vsbe::PoreRegisterOffset i_offset, ModelError Vsbe::registerWriteRaw(const vsbe::PoreRegisterOffset i_offset, const uint64_t i_data, const size_t i_size) { + int rc; + pore_reg_t reg = PoreRegOffs_to_pore(vsbe::PoreRegisterOffset(i_offset & ~0x7)); if (((i_offset & 0x7) == 0x4) && (i_size == 4)) { // lower 32-bit - pore_writeRegRaw(iv_engine, reg, i_data, PORE_BITS_32_63); - return ME_SUCCESS; - } - if (((i_offset & 0x7) == 0x0) && (i_size == 4)) { // upper 32-bit - pore_writeRegRaw(iv_engine, reg, i_data << 32, PORE_BITS_0_31); - return ME_SUCCESS; - } - pore_writeRegRaw(iv_engine, reg, i_data, PORE_BITS_0_63); - return ME_SUCCESS; + rc = pore_writeRegRaw(iv_engine, reg, i_data, PORE_BITS_32_63); + } else if (((i_offset & 0x7) == 0x0) && (i_size == 4)) { // upper 32-bit + rc = pore_writeRegRaw(iv_engine, reg, i_data << 32, PORE_BITS_0_31); + } else { + rc = pore_writeRegRaw(iv_engine, reg, i_data, PORE_BITS_0_63); + } + return (rc ? ME_REGISTER_WRITE_ERROR : ME_SUCCESS); } ModelError Vsbe::enableHookInstruction(bool i_enable) diff --git a/src/usr/pore/poreve/porevesrc/bus.C b/src/usr/pore/poreve/porevesrc/bus.C index beabe7241..ec3b49184 100644 --- a/src/usr/pore/poreve/porevesrc/bus.C +++ b/src/usr/pore/poreve/porevesrc/bus.C @@ -1,27 +1,26 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/pore/poreve/porevesrc/bus.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ -// $Id: bus.C,v 1.25 2012/03/20 22:52:49 bcbrock Exp $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/poreve/porevesrc/bus.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: bus.C,v 1.31 2012/12/06 18:03:50 bcbrock Exp $ /// \file bus.C /// \brief PoreVe bus and base device models @@ -30,14 +29,13 @@ #include <fapi.H> #include <transaction.H> - - using namespace vsbe; +using namespace fapi; //----------------------------------------------------------------------------- Bus::Bus() : - iv_primarySlaves(NULL), - iv_secondarySlaves(NULL) + iv_primarySlaves(0), + iv_secondarySlaves(0) { } @@ -53,9 +51,7 @@ Bus::attachPrimarySlave(Slave* i_slave) if( iv_primarySlaves == 0 ) { i_slave->iv_next = 0; - } - else - { + }else{ i_slave->iv_next = iv_primarySlaves; } iv_primarySlaves = i_slave; @@ -68,9 +64,7 @@ Bus::attachSecondarySlave(Slave* i_slave) if( iv_secondarySlaves == 0 ) { i_slave->iv_next = 0; - } - else - { + }else{ i_slave->iv_next = iv_secondarySlaves; } iv_secondarySlaves = i_slave; @@ -78,6 +72,53 @@ Bus::attachSecondarySlave(Slave* i_slave) //----------------------------------------------------------------------------- +ModelError +Bus::removeSlaveFromList(Slave* i_slave, Slave** i_slaves) +{ + ModelError me; + Slave** slavePtr; + Slave* thisSlave; + + slavePtr = i_slaves; + me = ME_FAILURE; + + while ((slavePtr != 0) && (*slavePtr != 0)) { + + thisSlave = *slavePtr; + + if (thisSlave == i_slave) { + + *slavePtr = thisSlave->iv_next; + thisSlave->iv_next = 0; + me = ME_SUCCESS; + break; + + } else { + + slavePtr = &(thisSlave->iv_next); + + } + } + + return me; +} + + +//----------------------------------------------------------------------------- +ModelError +Bus::detachSlave(Slave* i_slave) +{ + ModelError me; + + me = removeSlaveFromList(i_slave, &iv_primarySlaves); + if (me) { + me = removeSlaveFromList(i_slave, &iv_secondarySlaves); + } + return me; +} + + +//----------------------------------------------------------------------------- fapi::ReturnCode Bus::operation(Transaction& trans) { @@ -88,57 +129,55 @@ Bus::operation(Transaction& trans) { for( slave = iv_primarySlaves; slave; slave = slave->iv_next ) { - if( (trans.iv_address >= slave->iv_base) && - (trans.iv_address < (slave->iv_base + slave->iv_size) ) ) + if( (trans.iv_address >= slave->iv_base) && (trans.iv_address < (slave->iv_base + slave->iv_size) ) ) { - break; // found a primary slave + break; // found a primary slave } } if( slave == 0 ) - { // primary slaves did not hold the transaction address. - // Try using the secondary slaves. - for( slave = iv_secondarySlaves; slave; slave = slave->iv_next ) - { - if( (trans.iv_address >= slave->iv_base) && - (trans.iv_address < (slave->iv_base + slave->iv_size) ) ) - { - break; // found a secondary slave - } - } + { // primary slaves did not hold the transaction address. Try using the secondary slaves. + for( slave = iv_secondarySlaves; slave; slave = slave->iv_next ) + { + if( (trans.iv_address >= slave->iv_base) && (trans.iv_address < (slave->iv_base + slave->iv_size) ) ) + { + break; // found a secondary slave + } + } } break; - } while(0); + }while(1); do { - if( slave == 0 ) // neither primary nor secondary slaves held the addr + if( slave == 0 ) // neither primary nor secondary slaves held the address { - trans.busError(ME_NOT_MAPPED_ON_BUS); - FAPI_SET_HWP_ERROR(rc, RC_POREVE_BUS_ME_NOT_MAPPED_IN_BUS); - break; + trans.busError(ME_NOT_MAPPED_ON_BUS); + FAPI_ERR("No bus slave claimed address 0x%08x\n", trans.iv_address); + FAPI_SET_HWP_ERROR(rc, RC_POREVE_PORE_NOT_MAPPED_ON_BUS); + break; } - if( (trans.iv_mode & slave->iv_permissions) == 0 ) - { + if( (trans.iv_mode & slave->iv_permissions) == 0 ){ + FAPI_ERR("Access denied for address 0x%08x, " + "mode = %d, slave permissions = %d\n", + trans.iv_address, trans.iv_mode, slave->iv_permissions); trans.busError(ME_BUS_SLAVE_PERMISSION_DENIED); - FAPI_SET_HWP_ERROR(rc, RC_POREVE_BUS_ME_NOT_MAPPED_IN_BUS); + FAPI_SET_HWP_ERROR(rc, RC_POREVE_BUS_SLAVE_PERMISSION_DENIED); break; } trans.iv_offset = trans.iv_address - slave->iv_base; rc = slave->operation( trans ); break; - } while(0); + }while(1); return rc; } //----------------------------------------------------------------------------- Slave::Slave() -:iv_base(0), iv_size(0), iv_permissions(0), -iv_next(NULL), iv_target(NULL), iv_dataBuffer(NULL) { } @@ -176,28 +215,27 @@ PibSlave::operation(Transaction& io_transaction) if ( rc.ok() ) { pt->iv_pcbReturnCode = PCB_SUCCESS; } else { - fapi::ReturnCode rc1; if( rc == fapi_PCB_RESOURCE_BUSY ){ pt->iv_pcbReturnCode = PCB_RESOURCE_OCCUPIED; - rc = rc1; + rc = FAPI_RC_SUCCESS; }else if( rc == fapi_PCB_OFFLINE_ERROR ){ pt->iv_pcbReturnCode = PCB_CHIPLET_OFFLINE; - rc = rc1; + rc = FAPI_RC_SUCCESS; }else if( rc == fapi_PCB_PARTIAL_ERROR ){ pt->iv_pcbReturnCode = PCB_PARTIAL_GOOD; - rc = rc1; + rc = FAPI_RC_SUCCESS; }else if( rc == fapi_PCB_ADDRESS_ERROR ){ pt->iv_pcbReturnCode = PCB_ADDRESS_ERROR; - rc = rc1; + rc = FAPI_RC_SUCCESS; }else if( rc == fapi_PCB_CLOCK_ERROR ){ pt->iv_pcbReturnCode = PCB_CLOCK_ERROR; - rc = rc1; + rc = FAPI_RC_SUCCESS; }else if( rc == fapi_PCB_PARITY_ERROR ){ pt->iv_pcbReturnCode = PCB_PACKET_ERROR; - rc = rc1; + rc = FAPI_RC_SUCCESS; }else if( rc == fapi_PCB_TIMEOUT_ERROR ){ pt->iv_pcbReturnCode = PCB_TIMEOUT; - rc = rc1; + rc = FAPI_RC_SUCCESS; }else{ pt->iv_pcbReturnCode = PCB_TIMEOUT; } @@ -236,9 +274,9 @@ fapi::ReturnCode PibSlave::getScom(const uint32_t i_offset, uint64_t& o_data) { fapi::ReturnCode rc; - ecmdDataBufferBase l_dataBuffer; - rc = fapiGetScom( *iv_target, i_offset, l_dataBuffer ); - o_data = l_dataBuffer.getDoubleWord( 0 ); + + rc = fapiGetScom( *iv_target, i_offset, *iv_dataBuffer ); + o_data = iv_dataBuffer->getDoubleWord( 0 ); return rc; } @@ -248,10 +286,10 @@ fapi::ReturnCode PibSlave::putScom(const uint32_t i_offset, const uint64_t i_data) { fapi::ReturnCode rc; - ecmdDataBufferBase l_dataBuffer(64); - l_dataBuffer.setDoubleWord( 0, i_data ); - rc = fapiPutScom( *iv_target, i_offset, l_dataBuffer ); + iv_dataBuffer->setDoubleWordLength( 1 ); + iv_dataBuffer->setDoubleWord( 0, i_data ); + rc = fapiPutScom( *iv_target, i_offset, *iv_dataBuffer ); return rc; } @@ -259,7 +297,7 @@ PibSlave::putScom(const uint32_t i_offset, const uint64_t i_data) //----------------------------------------------------------------------------- PibMemory::PibMemory() : - iv_passThrough(false), iv_memory(NULL) + iv_passThrough(false) { } @@ -303,13 +341,9 @@ PibMemory::operation(Transaction& io_transaction) fapi::ReturnCode rc; ModelError me; - FAPI_SET_HWP_ERROR(rc, RC_POREVE_PIBMEM_OPERATION_ERROR); - if( io_transaction.iv_mode & ACCESS_MODE_READ ) { - me = iv_memory->read( - (uint32_t)(io_transaction.iv_offset * TRANSACTION_SIZE_IN_BYTES), - io_transaction.iv_data, TRANSACTION_SIZE_IN_BYTES ); + me = iv_memory->read( (uint32_t)(io_transaction.iv_offset * TRANSACTION_SIZE_IN_BYTES), io_transaction.iv_data, TRANSACTION_SIZE_IN_BYTES ); if( me == ME_NOT_MAPPED_IN_MEMORY && iv_passThrough ) { rc = getScom( io_transaction.iv_address, io_transaction.iv_data ); @@ -321,13 +355,17 @@ PibMemory::operation(Transaction& io_transaction) { me = ME_FAILURE; } + } else if (me) { + FAPI_ERR("Read of PIB memory at address 0x%08x failed", + io_transaction.iv_address); + iv_memory->dump(); + FAPI_SET_HWP_ERROR(rc, RC_POREVE_PIB_MEMORY_ACCESS_ERROR); } + } else if( io_transaction.iv_mode & ACCESS_MODE_WRITE ) { - me = iv_memory->write( - (uint32_t)(io_transaction.iv_offset * TRANSACTION_SIZE_IN_BYTES), - io_transaction.iv_data, TRANSACTION_SIZE_IN_BYTES ); + me = iv_memory->write( (uint32_t)(io_transaction.iv_offset * TRANSACTION_SIZE_IN_BYTES), io_transaction.iv_data, TRANSACTION_SIZE_IN_BYTES ); if( me == ME_NOT_MAPPED_IN_MEMORY && iv_passThrough ) { rc = putScom( io_transaction.iv_address, io_transaction.iv_data ); @@ -339,13 +377,16 @@ PibMemory::operation(Transaction& io_transaction) { me = ME_FAILURE; } + } else if (me) { + FAPI_ERR("Write to PIB memory at address 0x%08x failed", + io_transaction.iv_address); + iv_memory->dump(); + FAPI_SET_HWP_ERROR(rc, RC_POREVE_PIB_MEMORY_ACCESS_ERROR); } } else { - me = iv_memory->fetch( - (uint32_t)(io_transaction.iv_offset * TRANSACTION_SIZE_IN_BYTES), - io_transaction.iv_data, TRANSACTION_SIZE_IN_BYTES ); + me = iv_memory->fetch( (uint32_t)(io_transaction.iv_offset * TRANSACTION_SIZE_IN_BYTES), io_transaction.iv_data, TRANSACTION_SIZE_IN_BYTES ); if( me == ME_NOT_MAPPED_IN_MEMORY && iv_passThrough ) { rc = getScom( io_transaction.iv_address, io_transaction.iv_data ); @@ -357,15 +398,16 @@ PibMemory::operation(Transaction& io_transaction) { me = ME_FAILURE; } + } else if (me) { + FAPI_ERR("Fetch of PIB memory at address 0x%08x failed", + io_transaction.iv_address); + iv_memory->dump(); + FAPI_SET_HWP_ERROR(rc, RC_POREVE_PIB_MEMORY_ACCESS_ERROR); } } io_transaction.busError( me ); - // if read/write failed then rc == RC_PIBMEM_OPERATION_ERROR by default - // if read/write returned ME_NOT_MAPPED_IN_MEMORY && pass through true then - // rc == value returned from putScom or getScom - return rc; } @@ -382,17 +424,6 @@ Memory::Memory() : //----------------------------------------------------------------------------- Memory::~Memory() { - MemoryImage* m1 = iv_images; - while (m1) - { - MemoryImage* m2 = m1->iv_next; - delete m1; - m1 = m2; - if (m2 == iv_images) - { - break; - } - } } //----------------------------------------------------------------------------- @@ -402,20 +433,16 @@ Memory::checkCrc() MemoryImage* mi = iv_images; bool rc = true; - if (iv_images == 0) - { + do{ + + if( mi->checkCrc() == false ) + { rc = false; - } + break; + } + mi = mi->iv_next; - while (rc == true) - { - rc = mi->checkCrc(); - mi = mi->iv_next; - if (mi == iv_images) - { - break; - } - } + }while( mi != iv_images ); return rc; } @@ -439,74 +466,67 @@ Memory::read( o_data = 0; // Assure all bytes are cleared me = ME_SUCCESS; - do - { - if( iv_images == 0 ) + do{ + if( iv_images == 0 ) + { + me = ME_NOT_MAPPED_IN_MEMORY; + break; + } + mi = iv_images; + mi_found = 0; + do{ + + if( (i_offset >= mi->iv_base) && ((i_offset + i_size) <= (mi->iv_base + mi->iv_size) ) ) { - me = ME_NOT_MAPPED_IN_MEMORY; - break; + mi_found= 1; + iv_images = mi; // have the Memory always point to the last MemoryImage that was used + break; // we found a chunk of memory containing the transaction address } - mi = iv_images; - mi_found = 0; - do - { - if( (i_offset >= mi->iv_base) && - ((i_offset + i_size) <= (mi->iv_base + mi->iv_size) ) ) - { - mi_found= 1; - iv_images = mi; // have the Memory always point to the last - // MemoryImage that was used - break; // we found a chunk of memory containing the - // transaction address - } - mi = mi->iv_next; + mi = mi->iv_next; - } while( mi != iv_images ); + }while( mi != iv_images ); - if( ! mi_found ) - { // There was no MemoryImage that contained the transaction address - me = ME_NOT_MAPPED_IN_MEMORY; - break; - } + if( ! mi_found ) + { // There was no MemoryImage that contained the transaction address + me = ME_NOT_MAPPED_IN_MEMORY; + break; + } - if( (mi->iv_permissions & ACCESS_MODE_READ ) == 0 ) - { // The permissions over the memory block do not allow the mode - // being used by the transaction - me = ME_MEMORY_IMAGE_PERMISSION_DENIED; - break; - } + if( (mi->iv_permissions & ACCESS_MODE_READ ) == 0 ) + { // The permissions over the memory block do not allow the mode being used by the transaction + me = ME_MEMORY_IMAGE_PERMISSION_DENIED; + break; + } - // Init the character pointer into the eprom image we are using. - from_ptr = (char*)mi->iv_image + (i_offset - mi->iv_base); + // Init the character pointer into the eprom image we are using. + from_ptr = (char*)mi->iv_image + (i_offset - mi->iv_base); - // Init the character pointer into the o_data buffer. - // Take care of Endianess by moving to one or the other end of the - // buffer as appropriate. + // Init the character pointer into the o_data buffer. + // Take care of Endianess by moving to one or the other end of the buffer as appropriate. #ifdef _BIG_ENDIAN to_ptr = (char*)&o_data + (TRANSACTION_SIZE_IN_BYTES - i_size); #else to_ptr = ((char*)&o_data + i_size -1); #endif - for( cnt = 0; cnt < i_size; cnt++ ) - { - *to_ptr = *from_ptr++; + for( cnt = 0; cnt < i_size; cnt++ ) + { + *to_ptr = *from_ptr++; - // Move the to pointer either forward or backward as appropriate - // for Endianess + // Move the to pointer either forward or backward as appropriate for Endianess #ifdef _BIG_ENDIAN - to_ptr++; + to_ptr++; #else - to_ptr--; + to_ptr--; #endif - } + } - me = ME_SUCCESS; - break; - } while(0); + me = ME_SUCCESS; + break; + }while(1); #if POREVE_STATISTICS - iv_reads++; + iv_reads++; #endif return me; @@ -530,74 +550,67 @@ Memory::fetch( o_data = 0; // Assure all bytes are cleared me = ME_SUCCESS; - do - { - if( iv_images == 0 ) + do{ + if( iv_images == 0 ) + { + me = ME_NOT_MAPPED_IN_MEMORY; + break; + } + mi = iv_images; + mi_found = 0; + do{ + + if( (i_offset >= mi->iv_base) && ((i_offset + i_size) <= (mi->iv_base + mi->iv_size) ) ) { - me = ME_NOT_MAPPED_IN_MEMORY; - break; + mi_found= 1; + iv_images = mi; // have the Memory always point to the last MemoryImage that was used + break; // we found a chunk of memory containing the transaction address } - mi = iv_images; - mi_found = 0; - do - { - if( (i_offset >= mi->iv_base) && - ((i_offset + i_size) <= (mi->iv_base + mi->iv_size) ) ) - { - mi_found= 1; - iv_images = mi; // have the Memory always point to the last - // MemoryImage that was used - break; // we found a chunk of memory containing the - // transaction address - } - mi = mi->iv_next; + mi = mi->iv_next; - } while( mi != iv_images ); + }while( mi != iv_images ); - if( ! mi_found ) - { // There was no MemoryImage that contained the transaction address - me = ME_NOT_MAPPED_IN_MEMORY; - break; - } + if( ! mi_found ) + { // There was no MemoryImage that contained the transaction address + me = ME_NOT_MAPPED_IN_MEMORY; + break; + } - if( (mi->iv_permissions & ACCESS_MODE_EXECUTE ) == 0 ) - { // The permissions over the memory block do not allow the mode - // being used by the transaction - me = ME_MEMORY_IMAGE_PERMISSION_DENIED; - break; - } + if( (mi->iv_permissions & ACCESS_MODE_EXECUTE ) == 0 ) + { // The permissions over the memory block do not allow the mode being used by the transaction + me = ME_MEMORY_IMAGE_PERMISSION_DENIED; + break; + } - // Init the character pointer into the eprom image we are using. - from_ptr = (char*)mi->iv_image + i_offset; + // Init the character pointer into the eprom image we are using. + from_ptr = (char*)mi->iv_image + (i_offset - mi->iv_base); - // Init the character pointer into the o_data buffer. - // Take care of Endianess by moving to one or the other end of the - // buffer as appropriate. + // Init the character pointer into the o_data buffer. + // Take care of Endianess by moving to one or the other end of the buffer as appropriate. #ifdef _BIG_ENDIAN to_ptr = (char*)&o_data + (TRANSACTION_SIZE_IN_BYTES - i_size); #else to_ptr = ((char*)&o_data + i_size -1); #endif - for( cnt = 0; cnt < i_size; cnt++ ) - { - *to_ptr = *from_ptr++; + for( cnt = 0; cnt < i_size; cnt++ ) + { + *to_ptr = *from_ptr++; - // Move the to pointer either forward or backward as appropriate - // for Endianess + // Move the to pointer either forward or backward as appropriate for Endianess #ifdef _BIG_ENDIAN - to_ptr++; + to_ptr++; #else - to_ptr--; + to_ptr--; #endif - } + } - me = ME_SUCCESS; - break; - } while(0); + me = ME_SUCCESS; + break; + }while(1); #if POREVE_STATISTICS - iv_fetches++; + iv_fetches++; #endif return me; @@ -610,8 +623,7 @@ ModelError Memory::write( uint32_t i_offset, // the address in the eprom image uint64_t i_data, // data to write into the eprom image - size_t i_size // number of bytes to write (pretty much going to be - // TRANSACTION_SIZE_IN_BYTES) + size_t i_size // number of bytes to write (pretty much going to be TRANSACTION_SIZE_IN_BYTES) ) { char* to_ptr; @@ -622,75 +634,68 @@ Memory::write( int mi_found; me = ME_SUCCESS; - do - { - if( iv_images == 0 ) + do{ + if( iv_images == 0 ) + { + me = ME_NOT_MAPPED_IN_MEMORY; + break; + } + mi = iv_images; + mi_found = 0; + do{ + + if( (i_offset >= mi->iv_base) && ((i_offset + i_size) <= (mi->iv_base + mi->iv_size) ) ) { - me = ME_NOT_MAPPED_IN_MEMORY; - break; + mi_found= 1; + iv_images = mi; // have the Memory always point to the last MemoryImage that was used + break; // we found a chunk of memory containing the transaction address } - mi = iv_images; - mi_found = 0; - do - { - if( (i_offset >= mi->iv_base) && - ((i_offset + i_size) <= (mi->iv_base + mi->iv_size) ) ) - { - mi_found= 1; - iv_images = mi; // have the Memory always point to the last - // MemoryImage that was used - break; // we found a chunk of memory containing the - // transaction address - } - mi = mi->iv_next; + mi = mi->iv_next; - } while( mi != iv_images ); + }while( mi != iv_images ); - if( ! mi_found ) - { // There was no MemoryImage that contained the transaction address - me = ME_NOT_MAPPED_IN_MEMORY; - break; - } + if( ! mi_found ) + { // There was no MemoryImage that contained the transaction address + me = ME_NOT_MAPPED_IN_MEMORY; + break; + } - if( (mi->iv_permissions & ACCESS_MODE_WRITE ) == 0 ) - { // The permissions over the memory block do not allow the mode - // being used by the transaction - me = ME_MEMORY_IMAGE_PERMISSION_DENIED; - break; - } + if( (mi->iv_permissions & ACCESS_MODE_WRITE ) == 0 ) + { // The permissions over the memory block do not allow the mode being used by the transaction + me = ME_MEMORY_IMAGE_PERMISSION_DENIED; + break; + } - // Init the character pointer into the eprom image we are using. - to_ptr = (char*)mi->iv_image + i_offset; + // Init the character pointer into the eprom image we are using. + to_ptr = (char*)mi->iv_image + (i_offset - mi->iv_base); - // Init the character pointer into the o_data buffer. - // Take care of Endianess by moving to one or the other end of the - // buffer as appropriate. + // Init the character pointer into the o_data buffer. + // Take care of Endianess by moving to one or the other end of the buffer as appropriate. #ifdef _BIG_ENDIAN from_ptr = (char*)&i_data + (TRANSACTION_SIZE_IN_BYTES - i_size); #else from_ptr = ((char*)&i_data + i_size -1); #endif - for( cnt = 0; cnt < i_size; cnt++ ) - { - *to_ptr++ = *from_ptr; + for( cnt = 0; cnt < i_size; cnt++ ) + { + *to_ptr++ = *from_ptr; - // Move the to pointer either forward or backward as appropriate - // for Endianess + // Move the to pointer either forward or backward as appropriate for Endianess #ifdef _BIG_ENDIAN - from_ptr++; + from_ptr++; #else - from_ptr--; + from_ptr--; #endif - } + } - me = ME_SUCCESS; - break; + me = ME_SUCCESS; + break; - } while(0); + }while(1); #if POREVE_STATISTICS - iv_writes++; + iv_writes++; #endif return me; @@ -700,9 +705,8 @@ Memory::write( //----------------------------------------------------------------------------- ModelError Memory::map( - uint32_t i_base, // For direct memory this is the 0 based offset - // from the Slave iv_base - size_t i_size, // Size of this chunk of memory + uint32_t i_base, // For direct memory this is the 0 based offset from the Slave iv_base + size_t i_size, // Size of this chunk of memory int i_permissions, void* i_image, bool i_crcEnable @@ -710,23 +714,20 @@ Memory::map( { ModelError me = ME_SUCCESS; MemoryImage* n; - MemoryImage* mi = new MemoryImage( i_base, i_size, i_permissions, - i_image, i_crcEnable ); + MemoryImage* mi = new MemoryImage( i_base, i_size, i_permissions, i_image, i_crcEnable ); if( iv_images == 0 ) { - iv_images = mi; - mi->iv_next = mi; - } - else - { - n = iv_images->iv_next; - while( n->iv_next != iv_images ) - { - n = n->iv_next; - } - n->iv_next = mi; - mi->iv_next = iv_images; + iv_images = mi; + mi->iv_next = mi; + }else{ + n = iv_images->iv_next; + while( n->iv_next != iv_images ) + { + n = n->iv_next; + } + n->iv_next = mi; + mi->iv_next = iv_images; } return me; @@ -734,6 +735,28 @@ Memory::map( //----------------------------------------------------------------------------- +void +Memory::dump(void) +{ + MemoryImage* image; + + FAPI_ERR("Dump of Memory object %p", this); + if (iv_images == 0) { + + FAPI_ERR("Memory has no MemoryImage attached!"); + + } else { + + image = iv_images; + do { + image->dump(); + image = image->iv_next; + } while (image != iv_images); + } +} + + +//----------------------------------------------------------------------------- #if POREVE_STATISTICS void Memory::resetStatistics() @@ -800,6 +823,26 @@ MemoryImage::checkCrc() } //----------------------------------------------------------------------------- +void +MemoryImage::dump(void) +{ + FAPI_ERR("Dump of MemoryImage object %p\n" + "iv_base : 0x%08x\n" + "iv_size : 0x%zx\n" + "iv_permissions : %s %s %s\n" + "iv_image : %p\n" + "iv_crcEnable : %d\n" + "iv_next : %p", + this, + iv_base, iv_size, + (iv_permissions & ACCESS_MODE_READ) ? "Read" : "", + (iv_permissions & ACCESS_MODE_WRITE) ? "Write" : "", + (iv_permissions & ACCESS_MODE_EXECUTE) ? "Execute" : "", + iv_image, iv_crcEnable, iv_next); +} + + +//----------------------------------------------------------------------------- OciMemory::OciMemory() : iv_passThrough(false) { @@ -846,12 +889,9 @@ OciMemory::operation(Transaction& io_transaction) fapi::ReturnCode rc; ModelError me; - FAPI_SET_HWP_ERROR(rc, RC_POREVE_BUS_OPERATION_ERROR); - if( io_transaction.iv_mode & ACCESS_MODE_READ ) { - me = iv_memory->read( (uint32_t)io_transaction.iv_offset, - io_transaction.iv_data, TRANSACTION_SIZE_IN_BYTES ); + me = iv_memory->read( (uint32_t)io_transaction.iv_offset, io_transaction.iv_data, TRANSACTION_SIZE_IN_BYTES ); if( me == ME_NOT_MAPPED_IN_MEMORY && iv_passThrough ) { rc = read( io_transaction.iv_address, io_transaction.iv_data ); @@ -863,12 +903,16 @@ OciMemory::operation(Transaction& io_transaction) { me = ME_FAILURE; } + } else if (me) { + FAPI_ERR("Read of OCI memory at address 0x%08x failed", + io_transaction.iv_address); + iv_memory->dump(); + FAPI_SET_HWP_ERROR(rc, RC_POREVE_OCI_MEMORY_ACCESS_ERROR); } } else { - me = iv_memory->write( (uint32_t)io_transaction.iv_offset, - io_transaction.iv_data, TRANSACTION_SIZE_IN_BYTES ); + me = iv_memory->write( (uint32_t)io_transaction.iv_offset, io_transaction.iv_data, TRANSACTION_SIZE_IN_BYTES ); if( me == ME_NOT_MAPPED_IN_MEMORY && iv_passThrough ) { rc = write( io_transaction.iv_address, io_transaction.iv_data ); @@ -880,15 +924,16 @@ OciMemory::operation(Transaction& io_transaction) { me = ME_FAILURE; } + } else if (me) { + FAPI_ERR("Write to OCI memory at address 0x%08x failed", + io_transaction.iv_address); + iv_memory->dump(); + FAPI_SET_HWP_ERROR(rc, RC_POREVE_OCI_MEMORY_ACCESS_ERROR); } } io_transaction.busError( me ); - // if read/write failed then rc == RC_BUS_OPERATION_ERROR by default - // if read/write returned ME_NOT_MAPPED_IN_MEMORY && pass through true then - // rc == value returned from putScom or getScom - return rc; } @@ -932,7 +977,9 @@ fapi::ReturnCode OciSlave::read(const uint32_t i_address, uint64_t& o_data) { fapi::ReturnCode rc; - FAPI_SET_HWP_ERROR(rc, RC_POREVE_BUS_OCI_SLAVE_READ_NOT_SUPPORTED); + FAPI_ERR("The OCI slave at address 0x%08x does not " + "implement a read() method\n", i_address); + FAPI_SET_HWP_ERROR(rc, RC_POREVE_OCI_SLAVE_ERROR); return rc; } @@ -941,7 +988,9 @@ fapi::ReturnCode OciSlave::write(const uint32_t i_address, const uint64_t i_data) { fapi::ReturnCode rc; - FAPI_SET_HWP_ERROR(rc, RC_POREVE_BUS_OCI_SLAVE_WRITE_NOT_SUPPORTED); + FAPI_ERR("The OCI slave at address 0x%08x does not " + "implement a write() method\n", i_address); + FAPI_SET_HWP_ERROR(rc, RC_POREVE_OCI_SLAVE_ERROR); return rc; } diff --git a/src/usr/pore/poreve/porevesrc/bus.H b/src/usr/pore/poreve/porevesrc/bus.H index 4f4a93ef1..6373cd0a8 100644 --- a/src/usr/pore/poreve/porevesrc/bus.H +++ b/src/usr/pore/poreve/porevesrc/bus.H @@ -1,30 +1,29 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/pore/poreve/porevesrc/bus.H $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/poreve/porevesrc/bus.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __VSBE_BUS_H #define __VSBE_BUS_H -// $Id: bus.H,v 1.14 2011/12/16 21:47:59 bcbrock Exp $ +// $Id: bus.H,v 1.16 2012/12/06 18:03:51 bcbrock Exp $ /// \file bus.H /// \brief PoreVe bus and base device models @@ -72,6 +71,10 @@ public: is not mapped on the bus at all. */ /// Secondary Slaves are searched only if a Primary Slave did not support the Transaction Address void attachSecondarySlave(Slave* i_slave); + + /*! Detach the slave from the bus if it is mapped on either the primary or + secondary bus; Otherwise return the generic error ME_FAILURE */ + ModelError detachSlave(Slave* i_slave); /*! The PrimarySlaves attached to the bus are checked to find one that handles the @@ -112,6 +115,8 @@ protected: /// The Secondary list is used when the Primary list fails to contain a Transaction address Slave* iv_secondarySlaves; + /// Detach a slave from a slave list or else return ME_FAILURE. + ModelError removeSlaveFromList(Slave* i_slave, Slave** i_slaves); }; //----------------------------------------------------------------------------- @@ -190,7 +195,7 @@ public: PibSlave(); virtual ~PibSlave(); - /// Overriding Slave::operation + /// Inherits Slave::operation implementation virtual fapi::ReturnCode operation(Transaction& io_transaction); protected: @@ -441,6 +446,9 @@ public: /// true if iv_originalCrc == current crc, or if iv_crcEnable == false virtual bool checkCrc(); + /// Dump this memory image to the FAPI_ERR stream. + virtual void dump(void); + /// base address associated with iv_image in the system (not real address of iv_image) uint32_t iv_base; @@ -625,10 +633,11 @@ public: uint64_t i_data, size_t i_size); -private: + /// Dump the list of memory images to the FAPI_ERR stream. + virtual void dump(void); + /// Pointer to first MemoryImage in a circularly linked list MemoryImage* iv_images; -public: #if POREVE_STATISTICS diff --git a/src/usr/pore/poreve/porevesrc/fasti2c.C b/src/usr/pore/poreve/porevesrc/fasti2c.C index b0152e130..439b87ce7 100644 --- a/src/usr/pore/poreve/porevesrc/fasti2c.C +++ b/src/usr/pore/poreve/porevesrc/fasti2c.C @@ -1,27 +1,26 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/pore/poreve/porevesrc/fasti2c.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ -// $Id: fasti2c.C,v 1.6 2012/05/23 19:51:39 bcbrock Exp $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/poreve/porevesrc/fasti2c.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: fasti2c.C,v 1.11 2012/12/06 18:03:51 bcbrock Exp $ /// \file fasti2c.C /// \brief The "fast-mode" I2C controllers and I2C memory models used @@ -68,6 +67,9 @@ I2cMemory::addressWrite(const size_t i_bytes, const uint32_t i_address) if (i_bytes != iv_addressBytes) { BUG(); + FAPI_ERR("I2cMemory::addressWrite() failed, " + "address has %zu bytes, device supports %zu-byte addresses", + i_bytes, iv_addressBytes); me = ME_I2CMEMORY_ILLEGAL_ADDRESS; } else { me = ME_SUCCESS; @@ -133,8 +135,8 @@ FastI2cController::~FastI2cController() ModelError FastI2cController::attachMemory(I2cMemory* i_memory, - const uint8_t i_port, - const uint8_t i_deviceAddress) + const unsigned i_port, + const unsigned i_deviceAddress) { ModelError me = ME_SUCCESS; FastI2cControlRegister control; // Used to validate i_Port and i_deviceId @@ -176,7 +178,9 @@ FastI2cController::attachMemory(I2cMemory* i_memory, // Modeling notes: // -// o The RESET register is not modeled here +// o Writing the RESET register clears the STATUS register if bit 0 is set, +// however we require that writes to the RESET register only occur when the +// state machine is idle. // // o Our models ignore the I2C Speed // @@ -185,20 +189,29 @@ FastI2cController::attachMemory(I2cMemory* i_memory, // engine model. // // o Only the following types of control register actions are modeled: -// * Address write : with_start; with_address; !with_continue; with_stop; -// data_length == 0 -// * Data read : with_start; with_address; !with_continue; with_stop; -// data_length == [4,8] -// * Data write : with_start; with_address; !with_continue; with_stop; -// data_length == 8 // -// o The memory models hold the last address written +// * Set address : with_start; with_address; !with_continue; with_stop; +// RNW == 1; Data_length == [4, 8]; +// Address length != 0; Address provided +// Setting the address also fetches data and increments +// the address stored in memory +// +// * Data Read : with_start; with_address; !with_continue; with_stop; +// RNW == 1; Data_length == [4, 8]; +// Address length == 0; No address provided +// This operation fetches data and increments the address +// stored in memory. +// +// * Data write : with_start; with_address; !with_continue; with_stop; +// RNW == 0; Data_length == 8 +// Addrress length != 0; Address provided +// +// o The memory models hold the last address written and implement the +// address auto-increment after every read or write // // o Redundant reads of the STATUS register are allowed // -// o PORE only does 4/8 byte reads and 8 byte writes, so any other data -// access is considered an error (although the models could easily be -// extended to allow them). +// o PORE only allows 4/8 byte reads and 8 byte writes. fapi::ReturnCode FastI2cController::operation(Transaction& io_transaction) @@ -219,57 +232,95 @@ FastI2cController::operation(Transaction& io_transaction) switch (io_transaction.iv_offset) { + case FASTI2C_RESET_OFFSET: + + if (iv_state != IDLE) { + BUG(); + me = ME_FASTI2C_SEQUENCE_ERROR; + } else if (io_transaction.iv_data & BE64_BIT(0)) { + iv_status.value = 0; + me = ME_SUCCESS; + } else { + me = ME_SUCCESS; + } + break; + + case FASTI2C_CONTROL_OFFSET: if (io_transaction.iv_mode != ACCESS_MODE_WRITE) { BUG(); me = ME_WRITE_ONLY_REGISTER; + break; + } + + iv_control.value = io_transaction.iv_data; - } else if (iv_state != IDLE) { + if (!iv_control.fields.with_start || + !iv_control.fields.with_address || + iv_control.fields.read_continue || + !iv_control.fields.with_stop) { BUG(); - me = ME_FASTI2C_SEQUENCE_ERROR; + me = ME_FASTI2C_CONTROL_ERROR; + break; + } + + if (iv_control.fields.read_not_write == 0) { + + // A WRITE command is only allowed in the WRITE_COMMAND_EXPECTED + // state. + + if (iv_state != WRITE_COMMAND_EXPECTED) { + BUG(); + me = ME_FASTI2C_SEQUENCE_ERROR; + } + + if ((iv_control.fields.address_range == 0) || + (iv_control.fields.data_length != 8)) { + BUG(); + me = ME_FASTI2C_CONTROL_ERROR; + break; + } + + me = addressWrite(); + if (me) break; + me = initialDataWrite(); + if (me) break; + me = finalDataWrite(iv_data); + if (me) break; + + iv_state = DATA_WRITE_ONGOING; + break; } else { - iv_control.value = io_transaction.iv_data; + // A READ command is only expected in the IDLE state - if (!iv_control.fields.with_start || - !iv_control.fields.with_address || - iv_control.fields.read_continue || - !iv_control.fields.with_stop) { + if (iv_state != IDLE) { + BUG(); + me = ME_FASTI2C_SEQUENCE_ERROR; + break; + } + + if ((iv_control.fields.data_length != 4) && + (iv_control.fields.data_length != 8)) { BUG(); me = ME_FASTI2C_CONTROL_ERROR; + break; + } - } else if (iv_control.fields.read_not_write == 0) { - - if (iv_control.fields.address_range == 0) { - BUG(); - me = ME_FASTI2C_CONTROL_ERROR; - - } else { - if (iv_control.fields.data_length == 0) { - me = addressWrite(); - - } else if (iv_control.fields.data_length != 8) { - BUG(); - me = ME_FASTI2C_CONTROL_ERROR; - - } else { - me = initialDataWrite(); - } - } - } else { - if ((iv_control.fields.data_length != 4) && - (iv_control.fields.data_length != 8)) { - BUG(); - me = ME_FASTI2C_CONTROL_ERROR; - } else { - me = dataRead(); - } + if (iv_control.fields.address_range != 0) { + me = addressWrite(); + if (me) break; + iv_state = ADDRESS_WRITE_ONGOING; } - } - break; + me = dataRead(); + if (me) break; + + iv_state = DATA_READ_ONGOING; + break; + } case FASTI2C_STATUS_OFFSET: @@ -319,6 +370,8 @@ FastI2cController::operation(Transaction& io_transaction) if ((io_transaction.iv_mode == ACCESS_MODE_READ) || (io_transaction.iv_mode == ACCESS_MODE_EXECUTE)) { + // DATA reads must follow a command and status poll + switch (iv_state) { case DATA_AVAILABLE: @@ -332,18 +385,22 @@ FastI2cController::operation(Transaction& io_transaction) me = ME_FASTI2C_SEQUENCE_ERROR; break; } + } else { - switch (iv_state) { + // DATA writes must occur in the idle state, and be followed by a + // command and data poll. - case WRITE_DATA_EXPECTED: - me = finalDataWrite(io_transaction.iv_data); - iv_state = DATA_WRITE_ONGOING; + if (iv_state == IDLE) { + + iv_data = io_transaction.iv_data; + iv_state = WRITE_COMMAND_EXPECTED; + me = ME_SUCCESS; + + } else { - default: BUG(); me = ME_FASTI2C_SEQUENCE_ERROR; - break; } } break; @@ -357,7 +414,7 @@ FastI2cController::operation(Transaction& io_transaction) if (me != 0) { iv_state = ERROR; - FAPI_SET_HWP_ERROR(rc, RC_POREVE_FASTI2C_OPERATION_ERROR); + FAPI_SET_HWP_ERROR(rc, RC_POREVE_FASTI2C_ERROR); } io_transaction.busError(me); return rc; @@ -419,7 +476,6 @@ FastI2cController::addressWrite() } else { me = p->iv_memory->addressWrite(addressBytes, getI2cAddress(iv_control)); - iv_state = ADDRESS_WRITE_ONGOING; } return me; } @@ -442,7 +498,6 @@ FastI2cController::dataRead() } else { me = p->iv_memory->dataRead(dataBytes, data); iv_fifo = data << (64 - (dataBytes * 8)); - iv_state = DATA_READ_ONGOING; } return me; } @@ -465,7 +520,6 @@ FastI2cController::initialDataWrite() 63) << ((4 - addressBytes) * 8); } - iv_state = WRITE_DATA_EXPECTED; return ME_SUCCESS; } @@ -492,7 +546,6 @@ FastI2cController::finalDataWrite(const uint64_t i_data) me = ME_NOT_MAPPED_ON_FASTI2C_CONTROLLER; } else { me = p->iv_memory->dataWrite(8, iv_fifo); - iv_state = DATA_WRITE_ONGOING; } return me; } @@ -590,7 +643,7 @@ LpcController::operation(Transaction& io_transaction) } if (!handledBySuperclass) { if (me != 0) { - FAPI_SET_HWP_ERROR(rc, RC_POREVE_LPC_OPERATION_ERROR); + FAPI_SET_HWP_ERROR(rc, RC_POREVE_LPC_ERROR); } io_transaction.busError(me); } diff --git a/src/usr/pore/poreve/porevesrc/fasti2c.H b/src/usr/pore/poreve/porevesrc/fasti2c.H index 6c179c338..f2b1ac43a 100644 --- a/src/usr/pore/poreve/porevesrc/fasti2c.H +++ b/src/usr/pore/poreve/porevesrc/fasti2c.H @@ -1,30 +1,29 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/pore/poreve/porevesrc/fasti2c.H $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/poreve/porevesrc/fasti2c.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __VSBE_FASTI2C_H #define __VSBE_FASTI2C_H -// $Id: fasti2c.H,v 1.6 2012/05/23 19:51:40 bcbrock Exp $ +// $Id: fasti2c.H,v 1.7 2012/10/05 23:20:32 bcbrock Exp $ /// \file fasti2c.H /// \brief The "fast-mode" I2C controllers and memory models used @@ -391,7 +390,7 @@ public: ADDRESS_WRITE_ONGOING, DATA_READ_ONGOING, DATA_AVAILABLE, - WRITE_DATA_EXPECTED, + WRITE_COMMAND_EXPECTED, DATA_WRITE_ONGOING }; @@ -417,8 +416,8 @@ public: /// ME_AMBIGUOUS_CONFIGURATION. ModelError attachMemory(I2cMemory* i_memory, - const uint8_t i_port, - const uint8_t i_deviceAddress); + const unsigned i_port, + const unsigned i_deviceAddress); /// Handle a PIB transaction /// @@ -495,9 +494,13 @@ protected: /// The last value generated in the status register FastI2cStatusRegister iv_status; + /// The last value written to the data register + uint64_t iv_data; + /// The data FIFO. Data is left-justified in this register. uint64_t iv_fifo; + ///////////////////////////// Safety ////////////////////////////////// private: @@ -514,11 +517,12 @@ private: /// Simplified model of the LPC controller as a fast-mode I2C controller /// /// The LPC controller appears as a pseudo-FastI2cController with a couple of -/// extra specializations. The fast-mode I2C controller specification -/// is extended with two extra registers : The ECC start and stop -/// addresses. We do not model ECC in our model, therefore this model only -/// allows accesses that fall within the ECC window. The SBE will never -/// address outside of the ECC window. +/// extra specializations. +/// +/// - The fast-mode I2C controller specification is extended with two extra +/// registers : The ECC start and stop addresses. We do not model ECC in our +/// model, therefore this model only allows accesses that fall within the ECC +/// window. The SBE will never address outside of the ECC window. class vsbe::LpcController : public FastI2cController diff --git a/src/usr/pore/poreve/porevesrc/hookmanager.C b/src/usr/pore/poreve/porevesrc/hookmanager.C index e963500a7..0e4615b03 100644 --- a/src/usr/pore/poreve/porevesrc/hookmanager.C +++ b/src/usr/pore/poreve/porevesrc/hookmanager.C @@ -1,27 +1,26 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/pore/poreve/porevesrc/hookmanager.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ -// $Id: hookmanager.C,v 1.12 2012/01/06 21:25:25 bcbrock Exp $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/poreve/porevesrc/hookmanager.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: hookmanager.C,v 1.15 2012/12/06 18:03:51 bcbrock Exp $ /// \file hookmanager.C /// \brief A portable symbol table and hook execution facility @@ -32,7 +31,7 @@ #include "hookmanager.H" using namespace vsbe; - +using namespace fapi; #ifndef ULL /// The printf() checker for 64-bit GCC throws a warning if a uint64_t is @@ -103,7 +102,7 @@ HookManager::runInstructionHook(const PoreAddress& i_address, ihmi = instance()->iv_instructionHookMap.find(i_hook); if (ihmi == instance()->iv_instructionHookMap.end()) { - rc = 0; + rc = FAPI_RC_SUCCESS; } else { rc = (ihmi->second)(i_address, i_hook, i_parameter, io_pore, i_target); } @@ -493,6 +492,13 @@ HookManager::clearError() ////////////////////////// Implementation //////////////////////////// +// This routine checks to see if the i_address is mapped in the table, and if +// so, looks for a hook of the indicated type associated with that address. +// It is possible that the search may beningnly fail even though the address is +// mapped, e.g. we may be looking for a read hook but the hook mapped to the +// address is a write hook. We may want to consider a more efficient structure +// (multi-key map?) to avoid this. + fapi::ReturnCode HookManager::runHooks(const HookType i_interactiveType, const HookType i_extractedType, @@ -535,7 +541,7 @@ HookManager::runHooks(const HookType i_interactiveType, i_address.iv_offset, exHook->iv_file); instance()->iv_error = HOOK_TABLE_MISSING; - rc = 1; /// \todo Define this error + FAPI_SET_HWP_ERROR(rc, RC_POREVE_HOOKMANAGER_INCONSISTENCY); } else { @@ -553,7 +559,8 @@ HookManager::runHooks(const HookType i_interactiveType, hfmi->first, exHook->iv_index, table->iv_entries); instance()->iv_error = HOOK_INDEX_FAILURE; - rc = 1; /// \todo Define this error + FAPI_SET_HWP_ERROR(rc, + RC_POREVE_HOOKMANAGER_INCONSISTENCY); } else { @@ -562,12 +569,6 @@ HookManager::runHooks(const HookType i_interactiveType, (i_address, i_extractedType, io_pore, i_target); } } - } else { - - FAPI_ERR("%s : Bug in HookManager - Unexpected type", - __FUNCTION__); - instance()->iv_error = HOOK_BUG; - rc = 1; /// \todo Define this error } if (!rc.ok()) break; } diff --git a/src/usr/pore/poreve/porevesrc/pibmem.C b/src/usr/pore/poreve/porevesrc/pibmem.C index 2134c4d58..a286b77a7 100644 --- a/src/usr/pore/poreve/porevesrc/pibmem.C +++ b/src/usr/pore/poreve/porevesrc/pibmem.C @@ -1,27 +1,26 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/pore/poreve/porevesrc/pibmem.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ -// $Id: pibmem.C,v 1.1 2012/02/29 20:58:38 bcbrock Exp $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/poreve/porevesrc/pibmem.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: pibmem.C,v 1.3 2012/12/06 18:03:51 bcbrock Exp $ /// \file pibmem.C /// \brief A model of the P8 "PIB-attached Memory" @@ -139,7 +138,9 @@ Pibmem::operation(Transaction& io_transaction) break; default: - FAPI_SET_HWP_ERROR(rc, RC_POREVE_PIBMEM_BAD_OFFSET); // Bug + FAPI_ERR("PIBMEM: Can't read register at offset 0x%08x\n", + io_transaction.iv_offset); + FAPI_SET_HWP_ERROR(rc, RC_POREVE_PIBMEM_CONTROL_ERROR); break; } @@ -161,10 +162,6 @@ Pibmem::operation(Transaction& io_transaction) io_transaction.iv_data & PIBMEM_ADDRESS_DEFINED; break; - case PIBMEM_STATUS: - // Read-only - break; - case PIBMEM_RESET: iv_reset.value = io_transaction.iv_data & PIBMEM_RESET_DEFINED; @@ -203,14 +200,18 @@ Pibmem::operation(Transaction& io_transaction) break; default: - FAPI_SET_HWP_ERROR(rc, RC_POREVE_PIBMEM_BAD_OFFSET); // Bug + FAPI_ERR("PIBMEM: Can't write register at offset 0x%08x\n", + io_transaction.iv_offset); + FAPI_SET_HWP_ERROR(rc, RC_POREVE_PIBMEM_CONTROL_ERROR); break; } break; default: - FAPI_SET_HWP_ERROR(rc, RC_POREVE_PIBMEM_BAD_MODE); // Bug + FAPI_ERR("PIBMEM: Transaction mode is illegal - %d\n", + io_transaction.iv_mode); + FAPI_SET_HWP_ERROR(rc, RC_POREVE_PIBMEM_CONTROL_ERROR); break; } @@ -243,7 +244,7 @@ Pibmem::memoryOperation(Transaction& io_transaction, const bool i_direct) { fapi::ReturnCode rc; - uint32_t saveOffset; + uint32_t saveAddress, saveOffset; if (i_direct) { if (io_transaction.iv_offset >= iv_memorySize) { @@ -261,6 +262,10 @@ Pibmem::memoryOperation(Transaction& io_transaction, rc = PibMemory::operation(io_transaction); + if (rc) { + FAPI_ERR("The previous error was from a direct " + "PIBMEM operation to the indicated address"); + } } } else { @@ -272,11 +277,24 @@ Pibmem::memoryOperation(Transaction& io_transaction, PCB_PACKET_ERROR; } else { + saveAddress = io_transaction.iv_address; saveOffset = io_transaction.iv_offset; + + io_transaction.iv_address = iv_address.fields.address_pointer; io_transaction.iv_offset = iv_address.fields.address_pointer; + rc = PibMemory::operation(io_transaction); + + io_transaction.iv_address = saveAddress; io_transaction.iv_offset = saveOffset; + if (rc) { + FAPI_ERR("The previous error was from a PIBMEM operation " + "targeting the indicated address, issued " + "indirectly through the PIBMEM control " + "register 0x%08x", + saveAddress); + } } } diff --git a/src/usr/pore/poreve/porevesrc/pore.C b/src/usr/pore/poreve/porevesrc/pore.C index d2dd27f91..f9e0605b6 100644 --- a/src/usr/pore/poreve/porevesrc/pore.C +++ b/src/usr/pore/poreve/porevesrc/pore.C @@ -1,27 +1,26 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/pore/poreve/porevesrc/pore.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ -// $Id: pore.C,v 1.14 2012/02/29 20:58:39 bcbrock Exp $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/poreve/porevesrc/pore.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: pore.C,v 1.17 2013/01/07 16:35:18 bcbrock Exp $ /// \file pore.C /// \brief The implementation of the PoreInterface for the PoreVe environment @@ -53,8 +52,6 @@ Pore::forceBranch(const char* i_symbol) //////////////////// PoreInterface Methods ///////////////////////// -/// \bug We need a FAPI return code for an illegaly configured model - void Pore::pibMaster(PibTransaction& io_transaction) { @@ -63,7 +60,7 @@ Pore::pibMaster(PibTransaction& io_transaction) if (iv_pib == 0) { me = ME_NO_BUS_MODEL; io_transaction.busError(me); - FAPI_SET_HWP_ERROR(iv_fapiReturnCode,RC_POREVE_ME_NO_BUS_MODEL); + FAPI_SET_HWP_ERROR(iv_fapiReturnCode, RC_POREVE_NO_PIB_MODEL); } else { iv_fapiReturnCode = iv_pib->operation(io_transaction); me = io_transaction.iv_modelError; @@ -91,7 +88,7 @@ Pore::ociMaster(OciTransaction& io_transaction) if (iv_oci == 0) { me = ME_NO_BUS_MODEL; io_transaction.busError(me); - FAPI_SET_HWP_ERROR(iv_fapiReturnCode,RC_POREVE_ME_NO_BUS_MODEL); + FAPI_SET_HWP_ERROR(iv_fapiReturnCode, RC_POREVE_NO_OCI_MODEL); } else { iv_fapiReturnCode = iv_oci->operation(io_transaction); me = io_transaction.iv_modelError; @@ -119,22 +116,13 @@ Pore::wait(const uint32_t i_count) fapi::ReturnCode rc; ModelError me; -#ifndef __HOSTBOOT_MODULE nsDelay = (uint64_t)((i_count / PORE_FREQUENCY) * 1e9); simCycles = (uint64_t) (SIMULATOR_TICK_FREQUENCY * (i_count / PORE_FREQUENCY)); -#else - nsDelay = i_count; - nsDelay *= 1000000000ull; - nsDelay /= PORE_FREQUENCY; - simCycles = i_count; - simCycles *= SIMULATOR_TICK_FREQUENCY; - simCycles /= PORE_FREQUENCY; -#endif nsDelay += 1; // Always round up the real delay. iv_fapiReturnCode = fapiDelay(nsDelay, simCycles); - if (iv_fapiReturnCode.ok()) { + if (iv_fapiReturnCode == 0) { me = ME_SUCCESS; } else { me = ME_WAIT_FAILURE; @@ -249,7 +237,7 @@ Pore::operation(Transaction& io_transaction) } if (me) { - rc = 1; /// \bug Fix this + FAPI_SET_HWP_ERROR(rc, RC_POREVE_PORE_OPERATION_ERROR); } io_transaction.busError(me); return rc; @@ -303,14 +291,7 @@ Pore::dump() { PoreState state; // Need 3 regs since evaluation order is not guaranteed -#ifndef __HOSTBOOT_MODULE uint64_t reg0, reg1, reg2; -#else - uint64_t reg0 = 0, reg1 = 0, reg2 = 0; // Need to initialize - reg0 = reg0; // and use them to avoid compile error under - reg1 = reg1; // hostboot - reg2 = reg2; -#endif // NB : "Bugs" in eCMD FAPI_* implementation do not allow format strings // to be variables. @@ -318,55 +299,55 @@ Pore::dump() extractState(state); - FAPI_DBG(SEPARATOR); - FAPI_DBG("PORE dump after %llu instructions.", + FAPI_ERR(SEPARATOR); + FAPI_ERR("PORE dump after %llu instructions.", getInstructions()); - FAPI_DBG(SEPARATOR); - FAPI_DBG(" PC : %04x.%08x", + FAPI_ERR(SEPARATOR); + FAPI_ERR(" PC : %04x.%08x", (uint32_t)(pc >> 32) & 0xffff, (uint32_t)pc); - FAPI_DBG(" D0 : %016llx D1 : %016llx", + FAPI_ERR(" D0 : %016llx D1 : %016llx", (uint64_t)d0, (uint64_t)d1); - FAPI_DBG(" A0 : %04x.%08x A1 : %04x.%08x", + FAPI_ERR(" A0 : %04x.%08x A1 : %04x.%08x", (uint32_t)(a0 >> 32), (uint32_t)a0, (uint32_t)(a1 >> 32), (uint32_t)a1); - FAPI_DBG(" P0 : %02x P1 : %02x", + FAPI_ERR(" P0 : %02x P1 : %02x", (uint8_t)p0, (uint8_t)p1); - FAPI_DBG(" CTR : %06x ETR : %08x.%08x", + FAPI_ERR(" CTR : %06x ETR : %08x.%08x", (uint32_t)ctr, (uint32_t)(etr >> 32), (uint32_t)etr); - FAPI_DBG(" SPRG0 : %08x IFR : %016llx", + FAPI_ERR(" SPRG0 : %08x IFR : %016llx", (uint32_t)sprg0, (uint64_t)ifr); - FAPI_DBG(SEPARATOR); - FAPI_DBG(" IBUF : %08x %08x%08x", + FAPI_ERR(SEPARATOR); + FAPI_ERR(" IBUF : %08x %08x%08x", (uint32_t)((state.get(PORE_IBUF_01, reg0), reg0) >> 32), (uint32_t)(state.get(PORE_IBUF_01, reg1), reg1), (uint32_t)((state.get(PORE_IBUF_2, reg2), reg2) >> 32)); - FAPI_DBG(" STACK0 : %016llx", + FAPI_ERR(" STACK0 : %016llx", (state.get(PORE_PC_STACK0, reg0), reg0)); - FAPI_DBG(" STACK1 : %016llx", + FAPI_ERR(" STACK1 : %016llx", (state.get(PORE_PC_STACK1, reg0), reg0)); - FAPI_DBG(" STACK2 : %016llx", + FAPI_ERR(" STACK2 : %016llx", (state.get(PORE_PC_STACK2, reg0), reg0)); - FAPI_DBG(SEPARATOR); - FAPI_DBG(" CONTROL : %016llx STATUS : %016llx", + FAPI_ERR(SEPARATOR); + FAPI_ERR(" CONTROL : %016llx STATUS : %016llx", (state.get(PORE_CONTROL, reg0), reg0), (state.get(PORE_STATUS, reg1), reg1)); - FAPI_DBG(" DBG0 : %016llx DBG1 : %016llx", + FAPI_ERR(" DBG0 : %016llx DBG1 : %016llx", (state.get(PORE_DBG0, reg0), reg0), (state.get(PORE_DBG1, reg1), reg1)); - FAPI_DBG(SEPARATOR); - FAPI_DBG(" TBAR : %04x.%08x EMR : %016llx", + FAPI_ERR(SEPARATOR); + FAPI_ERR(" TBAR : %04x.%08x EMR : %016llx", (uint32_t)((state.get(PORE_TABLE_BASE_ADDR, reg0), reg0) >> 32), (uint32_t)(state.get(PORE_TABLE_BASE_ADDR, reg1), reg1), (uint64_t)emr); - FAPI_DBG(" MRR : %01x.%08x I2C0 : %016llx", + FAPI_ERR(" MRR : %01x.%08x I2C0 : %016llx", (uint32_t)((state.get(PORE_MEM_RELOC, reg0), reg0) >> 32), (uint32_t)(state.get(PORE_MEM_RELOC, reg1), reg1), (state.get(PORE_I2C_E0_PARAM, reg2), reg2)); - FAPI_DBG(" I2C1 : %016llx I2C2 : %016llx", + FAPI_ERR(" I2C1 : %016llx I2C2 : %016llx", (state.get(PORE_I2C_E1_PARAM, reg0), reg0), (state.get(PORE_I2C_E2_PARAM, reg1), reg1)); - FAPI_DBG(SEPARATOR); + FAPI_ERR(SEPARATOR); #undef SEPARATOR } diff --git a/src/usr/pore/poreve/porevesrc/pore.H b/src/usr/pore/poreve/porevesrc/pore.H index 3a26173e1..804974fea 100644 --- a/src/usr/pore/poreve/porevesrc/pore.H +++ b/src/usr/pore/poreve/porevesrc/pore.H @@ -1,30 +1,29 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/pore/poreve/porevesrc/pore.H $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/poreve/porevesrc/pore.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __VSBE_PORE_H #define __VSBE_PORE_H -// $Id: pore.H,v 1.15 2012/02/29 20:58:39 bcbrock Exp $ +// $Id: pore.H,v 1.16 2013/01/07 16:35:18 bcbrock Exp $ /// \file pore.H /// \brief The implementation of the PoreInterface for the PoreVe environment @@ -47,19 +46,11 @@ namespace vsbe { /// This is the putative tick frequency of the simulation environment, /// used to model the wait() method. -#ifndef __HOSTBOOT_MODULE const double SIMULATOR_TICK_FREQUENCY = 12e9; -#else - const uint64_t SIMULATOR_TICK_FREQUENCY = 12000000000ull; -#endif /// This is the expected operating frequency of the PORE hardware engine, /// used to model the wait() method. -#ifndef __HOSTBOOT_MODULE const double PORE_FREQUENCY = 600e6; -#else - const uint64_t PORE_FREQUENCY = 600000000ull; -#endif }; @@ -232,7 +223,11 @@ public: fapi::ReturnCode getFapiReturnCode(); - /// Dump the state of the engine using FAPI_DBG + /// Dump the state of the engine using FAPI_ERR + /// + /// The dump is made using FAPI_ERR() because this is currently the only + /// way to guarantee that the dump will appear regardless of the Cronus + /// debug settings. void dump(); diff --git a/src/usr/pore/poreve/porevesrc/poreve.C b/src/usr/pore/poreve/porevesrc/poreve.C index 9a3576dfd..157334625 100644 --- a/src/usr/pore/poreve/porevesrc/poreve.C +++ b/src/usr/pore/poreve/porevesrc/poreve.C @@ -1,27 +1,26 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/pore/poreve/porevesrc/poreve.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ -// $Id: poreve.C,v 1.24 2012/06/18 23:38:37 bcbrock Exp $ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/poreve/porevesrc/poreve.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: poreve.C,v 1.27 2012/12/06 18:03:52 bcbrock Exp $ /// \file poreve.C /// \brief The PORE Virtual Environment @@ -29,6 +28,7 @@ #include "poreve.H" using namespace vsbe; +using namespace fapi; //////////////////////////////////////////////////////////////////////////// @@ -74,20 +74,16 @@ PoreVeBase::PoreVeBase(const PoreIbufId i_id, // for use with Centaur targets; See the documentation for // iv_pnorI2cParam and the code for the reset() method. -#ifdef __USE_POREVE_ATTRIBUTES__ - - iv_constructorRc = FAPI_ATTR_GET_(ATTR_PNOR_I2C_ADDRESS_BYTES, + iv_constructorRc = FAPI_ATTR_GET(ATTR_PNOR_I2C_ADDRESS_BYTES, &iv_masterTarget, pnorI2cAddressBytes); if (iv_constructorRc) { FAPI_ERR("Unable to get ATTR_PNOR_I2C_ADDRESS_BYTES"); break; } -#else - - pnorI2cAddressBytes = 4; -#endif + FAPI_DBG("ATTR_PNOR_I2C_ADDRESS_BYTES attribute = %u", + pnorI2cAddressBytes); iv_pnorController.configure(&iv_masterTarget, &iv_dataBuffer, @@ -103,6 +99,14 @@ PoreVeBase::PoreVeBase(const PoreIbufId i_id, PNOR_I2C_PORT, PNOR_I2C_DEVICE_ADDRESS); + memset(iv_lpcRegisterSpace, 0, LPC_REGISTER_SPACE_SIZE); + + iv_pnorMemory.map(LPC_REGISTER_SPACE_BASE, + LPC_REGISTER_SPACE_SIZE, + ACCESS_MODE_READ | ACCESS_MODE_WRITE, + &iv_lpcRegisterSpace, + 0); + iv_pnorI2cParam.val = 0; iv_pnorI2cParam.i2c_engine_identifier = (PNOR_PIB_BASE >> 16) & 0xf; iv_pnorI2cParam.i2c_engine_address_range = 4; @@ -139,25 +143,20 @@ PoreVeBase::reset(fapi::Target i_slaveTarget) // Centaur PNOR image to execute. This is only done for Centaur since // Centaur SBE code is always run virtually. -#ifdef __USE_POREVE_ATTRIBUTES__ - /// \bug This does not work yet, but it doesn't hurt (much) to go ahead /// and initialize the register. uint8_t name; - rc = FAPI_ATTR_GET_PRIVILEGED(ATTR_NAME, i_slaveTarget, name); + rc = FAPI_ATTR_GET_PRIVILEGED(ATTR_NAME, &i_slaveTarget, name); if (!rc) { + + FAPI_DBG("ATTR_NAME attribute = %u\n", name); + if (name == ENUM_ATTR_NAME_CENTAUR) { iv_pore.registerWrite(PORE_I2C_E0_PARAM, iv_pnorI2cParam.val); } } -#else - - iv_pore.registerWrite(PORE_I2C_E0_PARAM, iv_pnorI2cParam.val); - -#endif - return rc; } @@ -303,40 +302,41 @@ PoreVe::PoreVe(const PoreIbufId i_id, seepromConfig = (i_useSecondarySeepromConfig ? 1 : 0); -#ifdef __USE_POREVE_ATTRIBUTES__ - - iv_constructorRc = FAPI_ATTR_GET(ATTR_SEEPROM_I2C_ADDRESS_BYTES, + iv_constructorRc = FAPI_ATTR_GET(ATTR_SBE_SEEPROM_I2C_ADDRESS_BYTES, &iv_masterTarget, seepromI2cAddressBytes); if (iv_constructorRc) { - FAPI_ERR("Unable to get ATTR_SEEPROM_I2C_ADDRESS_BYTES"); + FAPI_ERR("Unable to get ATTR_SBE_SEEPROM_I2C_ADDRESS_BYTES"); break; } + FAPI_DBG("ATTR_SBE_SEEPROM_I2C_ADDRESS_BYTES attribute = %u", + seepromI2cAddressBytes); - iv_constructorRc = FAPI_ATTR_GET(ATTR_SEEPROM_I2C_DEVICE_ADDRESS, + + iv_constructorRc = FAPI_ATTR_GET(ATTR_SBE_SEEPROM_I2C_DEVICE_ADDRESS, &iv_masterTarget, - seepromI2cDeviceAddtess); + seepromI2cDeviceAddress); if (iv_constructorRc) { - FAPI_ERR("Unable to get ATTR_SEEPROM_I2C_DEVICE_ADDRESS"); + FAPI_ERR("Unable to get ATTR_SBE_SEEPROM_I2C_DEVICE_ADDRESS"); break; } + FAPI_DBG("ATTR_SBE_SEEPROM_I2C_DEVICE_ADDRESS attribute = " + "{0x%02x, 0x%02x}", + seepromI2cDeviceAddress[0], + seepromI2cDeviceAddress[1]); - iv_constructorRc = FAPI_ATTR_GET(ATTR_SEEPROM_I2C_PORT, + iv_constructorRc = FAPI_ATTR_GET(ATTR_SBE_SEEPROM_I2C_PORT, &iv_masterTarget, seepromI2cPort); if (iv_constructorRc) { - FAPI_ERR("Unable to get ATTR_SEEPROM_I2C_PORT"); + FAPI_ERR("Unable to get ATTR_SBE_SEEPROM_I2C_PORT"); break; } - -#else - - seepromI2cAddressBytes = 2; // Murano primary configuration - seepromI2cDeviceAddress[0] = 0x56; - seepromI2cPort[0] = 0; - -#endif + FAPI_DBG("ATTR_SBE_SEEPROM_I2C_PORT attribute = " + "{%u, %u}", + seepromI2cPort[0], + seepromI2cPort[1]); iv_seepromController.configure(&iv_slaveTarget, &iv_dataBuffer, @@ -348,8 +348,6 @@ PoreVe::PoreVe(const PoreIbufId i_id, iv_seepromMemory.configure(seepromI2cAddressBytes); - // printf("ATTACHING MEMORY\n"); - iv_seepromController. attachMemory(&iv_seepromMemory, seepromI2cPort[seepromConfig], @@ -448,13 +446,14 @@ PoreVe::~PoreVe() } +ModelError +PoreVe::detachSlave(Slave* i_slave) +{ + ModelError me; - - - - - - - - - + me = iv_pib.detachSlave(i_slave); + if (me) { + me = iv_oci.detachSlave(i_slave); + } + return me; +} diff --git a/src/usr/pore/poreve/porevesrc/poreve.H b/src/usr/pore/poreve/porevesrc/poreve.H index 387fa6604..fc9174b40 100644 --- a/src/usr/pore/poreve/porevesrc/poreve.H +++ b/src/usr/pore/poreve/porevesrc/poreve.H @@ -1,30 +1,29 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/pore/poreve/porevesrc/poreve.H $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/poreve/porevesrc/poreve.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __VSBE_POREVE_H #define __VSBE_POREVE_H -// $Id: poreve.H,v 1.25 2012/06/18 23:38:37 bcbrock Exp $ +// $Id: poreve.H,v 1.28 2012/10/24 23:44:06 bcbrock Exp $ /// \file poreve.H /// \brief The PORE Virtual Environment @@ -169,6 +168,12 @@ namespace vsbe { /// The PNOR I2C Device Address const unsigned PNOR_I2C_DEVICE_ADDRESS = 0; + /// LPC Controller register address space + const uint32_t LPC_REGISTER_SPACE_BASE = 0xc0012000; + + /// LPC Controller register area size + const uint32_t LPC_REGISTER_SPACE_SIZE = 0x1000; + ////////////////////////////////////////////////////////////////////// // SEEPROM @@ -464,6 +469,15 @@ protected: /// scenes in the reset() method. pore_i2c_en_param_reg iv_pnorI2cParam; + + /// A memory to model the LPC controller register address space + /// + /// We do not model any behavior of the LPC controller. Instead we simply + /// provide a suitably-sized memory buffer so that reads/writes to the LPC + /// controller address space will succeed. This memory buffer is + /// statically mapped into the iv_PnorMemory. + uint8_t iv_lpcRegisterSpace[LPC_REGISTER_SPACE_SIZE]; + ///////////////////////////// Safety ////////////////////////////////// @@ -535,6 +549,41 @@ public: const fapi::Target i_masterTarget, const void* i_arg); + //////////////////// Simulation Interface ///////////////////////// + + /// Detach a slave from its bus + /// + /// \param[in] i_slave A pointer to one of the Slave subclass data members + /// of the PoreVe. If the \a i_slave is attached to any simulated bus in + /// the PoreVe it will be removed from the bus model by this call. + /// + /// The PoreVe object is always configured for full virtual simulation of + /// all bus slaves, most of which are memory models. For many lab and + /// verification cases it is desirable to configure some of the memory + /// models to use the real memory, e.g., by doing virtual simulation of + /// all memories except the PNOR. The detachSlave() method detaches a + /// virtual slave from its bus model, so that for example PIB addresses + /// normaly handled by the virtual slave would now pass through into the + /// real hardware. + /// + /// It was felt that this idea of eliminating slaves from a full + /// configuration was a more convenient abstraction than the alternatives + /// of requiring the application to explicitly specify which slaves to + /// simulate as constructor parameters or via attributes. The simple PIB + /// and OCI memories also support a 'pass-through' option that + /// automatically passes accesses to the real hardware memory for unmapped + /// addresses. However pass-through mechanisms do not exist (or make + /// complete sense) for the indirect I2C-like memories, so detachSlave() + /// was added as a general solution to meet the partial-simulation + /// requirement. + /// + /// \retval 0 Success; The slave was located and detached from its bus. + /// + /// \retval ME_FAILURE The slave was not attached to any bus in the PoreVe. + virtual ModelError + detachSlave(Slave* i_slave); + + //////////////////// Public Implementation //////////////////////////// /// The OTPROM controller model @@ -580,25 +629,7 @@ public: /// The sbeVital PIB Slave SbeVital iv_sbeVital; -#ifdef VBU_HACKS - /// The Broadside Scan components for each EX - // Bsscan iv_bsscan_ex00; - Bsscan iv_bsscan_ex01; - Bsscan iv_bsscan_ex02; - Bsscan iv_bsscan_ex03; - Bsscan iv_bsscan_ex04; - Bsscan iv_bsscan_ex05; - Bsscan iv_bsscan_ex06; - // Bsscan iv_bsscan_ex07; - // Bsscan iv_bsscan_ex08; - Bsscan iv_bsscan_ex09; - Bsscan iv_bsscan_ex10; - Bsscan iv_bsscan_ex11; - Bsscan iv_bsscan_ex12; - Bsscan iv_bsscan_ex13; - Bsscan iv_bsscan_ex14; - // Bsscan iv_bsscan_ex15; -#endif + ///////////////////////////// Safety ////////////////////////////////// private: diff --git a/src/usr/pore/poreve/porevesrc/sbevital.C b/src/usr/pore/poreve/porevesrc/sbevital.C index e5ece8ec6..1c4c6034d 100644 --- a/src/usr/pore/poreve/porevesrc/sbevital.C +++ b/src/usr/pore/poreve/porevesrc/sbevital.C @@ -1,28 +1,27 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/pore/poreve/porevesrc/sbevital.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/poreve/porevesrc/sbevital.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ // -*- mode: C++; c-file-style: "linux"; -*- -// $Id: sbevital.C,v 1.3 2012/02/27 22:51:37 jeshua Exp $ +// $Id: sbevital.C,v 1.4 2012/10/25 16:36:17 jeshua Exp $ /// \file sbevital.C /// \brief Emulate the SBE vital register in software @@ -30,6 +29,7 @@ #include "sbevital.H" using namespace vsbe; +using namespace fapi; ////////////////////////////// Creators ////////////////////////////// @@ -50,7 +50,7 @@ SbeVital::~SbeVital() fapi::ReturnCode SbeVital::operation(Transaction& io_transaction) { - fapi::ReturnCode rc; + fapi::ReturnCode rc=FAPI_RC_SUCCESS; ModelError me; //On a scom write, put the data into the register diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index 2a473d2c7..e2edcf378 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -9744,4 +9744,100 @@ Measured in GB</description> </hwpfToHbAttrMap> </attribute> +<!-- ===== Supporting poreve_memory_attributes.xml ===== --> + +<attribute> + <id>SBE_SEEPROM_I2C_ADDRESS_BYTES</id> + <description> + The number of address bytes required to address the SEEPROM memory + device that contains SBE IPL code. This will vary by device based on + the device capacity, and must be either 1, 2, 3 or 4. + </description> + <simpleType> + <uint8_t> + <default>4</default> + </uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_SBE_SEEPROM_I2C_ADDRESS_BYTES</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>SBE_SEEPROM_I2C_DEVICE_ADDRESS</id> + <description> + A 2-element array containing the I2C device address of the primary (0) + and secondary (1) SEEPROM devices containing SBE IPL code. + Provided by the Machine Readable Workbook + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_SBE_SEEPROM_I2C_DEVICE_ADDRESS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>SBE_SEEPROM_I2C_PORT</id> + <description> + A 2-element array containing the I2C controller port number of the + primary (0) and secondary (1) SEEPROM devices containing SBE IPL code. + Provided by the Machine Readable Workbook + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_SBE_SEEPROM_I2C_PORT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PNOR_I2C_ADDRESS_BYTES</id> + <description> + The number of address bytes required to address the PNOR memory device + via the pseudo-I2C (LPC, ECCAX) controller. This will vary by device + based on the device capacity, and must be either 0, 1, 2, 3 or 4. + + This attribute will be set to 0 for chips with no PNOR attached + (PoreVe will never run on these chips). + + Provided by the Machine Readable Workbook + </description> + <simpleType> + <uint8_t> + <default>4</default> + </uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PNOR_I2C_ADDRESS_BYTES</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<!-- ===== End supporting poreve_memory_attributes.xml ===== --> + + </attributes> diff --git a/src/usr/targeting/common/xmltohb/common.mk b/src/usr/targeting/common/xmltohb/common.mk index eb0aca203..45bc475a2 100644 --- a/src/usr/targeting/common/xmltohb/common.mk +++ b/src/usr/targeting/common/xmltohb/common.mk @@ -76,8 +76,8 @@ FAPI_ATTR_SOURCES = \ dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr_attributes.xml \ common_attributes.xml \ build_winkle_images/p8_slw_build/proc_pll_ring_attributes.xml \ - build_winkle_images/p8_slw_build/p8_xip_customize_attributes.xml - + build_winkle_images/p8_slw_build/p8_xip_customize_attributes.xml \ + poreve_memory_attributes.xml XMLTOHB_GENERIC_XML = generic.xml XMLTOHB_FAPI_XML = fapiattrs.xml diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index 37706903a..b2fbae3fb 100644 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -27,8 +27,6 @@ HOST BOOT TARGETS Contains the definition of the different types of targets ================================================================= --> - - <targetType> <id>base</id> <attribute><id>CLASS</id></attribute> @@ -327,6 +325,12 @@ <attribute><id>PM_PBAX_SND_RETRY_THRESHOLD</id></attribute> <attribute><id>PM_PBAX_SND_RESERV_TIMEOUT</id></attribute> <!-- End pm_attributes_all_hwp.xml --> + <!-- Begin poreve_memory_attributes.xml --> + <attribute><id>SBE_SEEPROM_I2C_ADDRESS_BYTES</id></attribute> + <attribute><id>SBE_SEEPROM_I2C_DEVICE_ADDRESS</id></attribute> + <attribute><id>SBE_SEEPROM_I2C_PORT</id></attribute> + <attribute><id>PNOR_I2C_ADDRESS_BYTES</id></attribute> + <!-- End Supporting poreve_memory_attributes.xml --> </targetType> <targetType> @@ -972,6 +976,12 @@ <attribute><id>MSS_CACHE_ENABLE</id></attribute> <attribute><id>VMEM_ID</id></attribute> <attribute><id>EI_BUS_TX_LANE_INVERT</id></attribute> + <!-- Begin poreve_memory_attributes.xml --> + <attribute><id>SBE_SEEPROM_I2C_ADDRESS_BYTES</id></attribute> + <attribute><id>SBE_SEEPROM_I2C_DEVICE_ADDRESS</id></attribute> + <attribute><id>SBE_SEEPROM_I2C_PORT</id></attribute> + <attribute><id>PNOR_I2C_ADDRESS_BYTES</id></attribute> + <!-- End poreve_memory_attributes.xml --> </targetType> <!-- Centaur MBS --> |
