diff options
Diffstat (limited to 'src/usr/isteps/istep14')
| -rw-r--r-- | src/usr/isteps/istep14/call_host_mpipl_service.C | 7 | ||||
| -rw-r--r-- | src/usr/isteps/istep14/call_mss_memdiag.C | 42 | ||||
| -rw-r--r-- | src/usr/isteps/istep14/call_mss_power_cleanup.C | 3 | ||||
| -rw-r--r-- | src/usr/isteps/istep14/call_mss_thermal_init.C | 300 | ||||
| -rw-r--r-- | src/usr/isteps/istep14/call_proc_exit_cache_contained.C | 5 | ||||
| -rw-r--r-- | src/usr/isteps/istep14/call_proc_setup_bars.C | 1 | ||||
| -rw-r--r-- | src/usr/isteps/istep14/makefile | 25 |
7 files changed, 284 insertions, 99 deletions
diff --git a/src/usr/isteps/istep14/call_host_mpipl_service.C b/src/usr/isteps/istep14/call_host_mpipl_service.C index d8bdaa5af..bab3ace62 100644 --- a/src/usr/isteps/istep14/call_host_mpipl_service.C +++ b/src/usr/isteps/istep14/call_host_mpipl_service.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -44,7 +44,6 @@ #include <vfs/vfs.H> #include <dump/dumpif.H> -#include <config.h> #ifdef CONFIG_DRTM #include <secureboot/drtm.H> @@ -158,10 +157,10 @@ void* call_host_mpipl_service (void *io_pArgs) do { - // In non-FSP based system SBE collects architected register + // In OPAL based system SBE collects architected register // data. Copy architected register data from Reserved Memory // to hypervisor memory. - if ( !INITSERVICE::spBaseServicesEnabled() ) + if( TARGETING::is_sapphire_load() ) { l_err = DUMP::copyArchitectedRegs(); if (l_err) diff --git a/src/usr/isteps/istep14/call_mss_memdiag.C b/src/usr/isteps/istep14/call_mss_memdiag.C index 38736d2c7..4c4c6b5b2 100644 --- a/src/usr/isteps/istep14/call_mss_memdiag.C +++ b/src/usr/isteps/istep14/call_mss_memdiag.C @@ -33,14 +33,21 @@ #include <util/misc.H> #include <plat_hwp_invoker.H> // for FAPI_INVOKE_HWP -#include <lib/shared/nimbus_defaults.H> // Needed before memdiags_fir.H -#include <lib/fir/memdiags_fir.H> // for mss::unmask::after_memdiags +#include <lib/shared/nimbus_defaults.H> // Needed before unmask.H +#include <lib/fir/unmask.H> // for mss::unmask::after_memdiags #include <lib/mc/port.H> // for mss::reset_reorder_queue_settings #if defined(CONFIG_IPLTIME_CHECKSTOP_ANALYSIS) && !defined(__HOSTBOOT_RUNTIME) #include <isteps/pm/occCheckstop.H> #endif +// TODO RTC:245219 +// use PRD's version of memdiags instead of this cronus verison once its working +#ifdef CONFIG_AXONE +#include <exp_mss_memdiag.H> +#include <chipids.H> // for EXPLORER ID +#endif + using namespace ISTEP; using namespace ISTEP_ERROR; using namespace ERRORLOG; @@ -161,6 +168,37 @@ void* call_mss_memdiag (void* io_pArgs) // No need to unmask or turn off FIFO. That is already contained // within the other Centaur HWPs. } +#ifdef CONFIG_AXONE + else if (MODEL_AXONE == procType ) + { + // no need to run in simics + if ( Util::isSimicsRunning() == false ) + { + // TODO RTC:245219 + // use PRD's version of memdiags instead of this cronus verison once its working + TargetHandleList trgtList; getAllChips( trgtList, TYPE_OCMB_CHIP ); + for (const auto & l_ocmb_target : trgtList) + { + uint32_t chipId = l_ocmb_target->getAttr< TARGETING::ATTR_CHIP_ID>(); + // Only call memdiags on Explorer cards, it breaks when you run on Gemini + if (chipId == POWER_CHIPID::EXPLORER_16) + { + fapi2::Target <fapi2::TARGET_TYPE_OCMB_CHIP> l_fapi_ocmb_target(l_ocmb_target); + // Start Memory Diagnostics. + FAPI_INVOKE_HWP( errl, exp_mss_memdiag, l_fapi_ocmb_target ); + if ( nullptr != errl ) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "exp_mss_memdiag (0x%08x) " + "failed", get_huid(l_ocmb_target) ); + break; + } + } + } + } + + } +#endif } while (0); diff --git a/src/usr/isteps/istep14/call_mss_power_cleanup.C b/src/usr/isteps/istep14/call_mss_power_cleanup.C index 3ca963678..524d2a536 100644 --- a/src/usr/isteps/istep14/call_mss_power_cleanup.C +++ b/src/usr/isteps/istep14/call_mss_power_cleanup.C @@ -129,9 +129,10 @@ void* call_mss_power_cleanup (void *io_pArgs) } } - // Run the nvdimm management function if the list is not empty + // Run the nvdimm management functions if the list is not empty if (!l_nvdimmTargetList.empty()){ NVDIMM::nvdimm_restore(l_nvdimmTargetList); + NVDIMM::nvdimm_encrypt_enable(l_nvdimmTargetList); } } #endif diff --git a/src/usr/isteps/istep14/call_mss_thermal_init.C b/src/usr/isteps/istep14/call_mss_thermal_init.C index 8e00df762..c11731e1d 100644 --- a/src/usr/isteps/istep14/call_mss_thermal_init.C +++ b/src/usr/isteps/istep14/call_mss_thermal_init.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,10 +37,16 @@ #include <config.h> #include <fapi2.H> #include <fapi2/plat_hwp_invoker.H> -#include <p9c_mss_thermal_init.H> -#include <p9_mss_thermal_init.H> -#include <p9_throttle_sync.H> +#ifdef CONFIG_AXONE + #include <exp_mss_thermal_init.H> + #include <chipids.H> // for EXPLORER ID + #include <p9a_throttle_sync.H> +#else + #include <p9c_mss_thermal_init.H> + #include <p9_mss_thermal_init.H> + #include <p9_throttle_sync.H> +#endif using namespace ISTEP; using namespace ISTEP_ERROR; @@ -49,43 +55,79 @@ using namespace TARGETING; namespace ISTEP_14 { +void nimbus_call_mss_thermal_init(IStepError & io_istepError); +void cumulus_call_mss_thermal_init(IStepError & io_istepError); +void axone_call_mss_thermal_init(IStepError & io_istepError); +void run_proc_throttle_sync(IStepError & io_istepError); + void* call_mss_thermal_init (void *io_pArgs) { IStepError l_StepError; + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_thermal_init entry"); + + auto l_procModel = TARGETING::targetService().getProcessorModel(); + switch (l_procModel) + { + case TARGETING::MODEL_CUMULUS: + cumulus_call_mss_thermal_init(l_StepError); + break; + case TARGETING::MODEL_AXONE: + axone_call_mss_thermal_init(l_StepError); + break; + case TARGETING::MODEL_NIMBUS: + nimbus_call_mss_thermal_init(l_StepError); + break; + default: + assert(0, "call_mss_thermal_init: Unsupported model type 0x%04X", + l_procModel); + break; + } + + // This should run whether or not mss_thermal_init worked + run_proc_throttle_sync(l_StepError); + + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_thermal_init exit"); + + // end task, returning any errorlogs to IStepDisp + return l_StepError.getErrorHandle(); +} + +#ifndef CONFIG_AXONE +void nimbus_call_mss_thermal_init(IStepError & io_istepError) +{ errlHndl_t l_errl = nullptr; - // -- Cumulus only --- - // Get all Centaur targets - TARGETING::TargetHandleList l_memBufTargetList; - getAllChips(l_memBufTargetList, TYPE_MEMBUF); + // -- Nimbus only --- + // Get all MCS targets + TARGETING::TargetHandleList l_mcsTargetList; + getAllChiplets(l_mcsTargetList, TYPE_MCS); // -------------------------------------------------------------------- - // run mss_thermal_init on all functional Centaur chips + // run mss_thermal_init on all functional MCS chiplets // -------------------------------------------------------------------- - for (auto l_pCentaur : l_memBufTargetList) + for (const auto & l_pMcs : l_mcsTargetList) { - fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP> l_fapi_pCentaur - (l_pCentaur); + fapi2::Target<fapi2::TARGET_TYPE_MCS> l_fapi_pMcs(l_pMcs); // Current run on target TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "Running call_mss_thermal_init HWP on " - "target HUID %.8X", TARGETING::get_huid(l_pCentaur)); + "Running p9_mss_thermal_init HWP on target HUID %.8X", + TARGETING::get_huid(l_pMcs) ); - FAPI_INVOKE_HWP( l_errl, p9c_mss_thermal_init, l_fapi_pCentaur ); + FAPI_INVOKE_HWP( l_errl, p9_mss_thermal_init, l_fapi_pMcs ); if ( l_errl ) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: p9c_mss_thermal_init HWP returns error", + "ERROR 0x%.8X: p9_mss_thermal_init HWP returns error", l_errl->reasonCode()); // capture the target data in the elog - ErrlUserDetailsTarget(l_pCentaur).addToLog( l_errl ); + ErrlUserDetailsTarget(l_pMcs).addToLog( l_errl ); // Create IStep error log and cross reference // to error that occurred - l_StepError.addErrorDetails( l_errl ); + io_istepError.addErrorDetails( l_errl ); // Commit Error errlCommit( l_errl, HWPF_COMP_ID ); @@ -94,43 +136,50 @@ void* call_mss_thermal_init (void *io_pArgs) } else { - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : p9c_mss_thermal_init HWP( )" ); + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : p9_mss_thermal_init HWP() on 0x%.8X MCS", + TARGETING::get_huid(l_pMcs) ); } - } + } // end MCS loop - // -- Nimbus only --- - // Get all MCS targets - TARGETING::TargetHandleList l_mcsTargetList; - getAllChiplets(l_mcsTargetList, TYPE_MCS); +} + +void cumulus_call_mss_thermal_init(IStepError & io_istepError) +{ + errlHndl_t l_errl = nullptr; + + // -- Cumulus only --- + // Get all Centaur targets + TARGETING::TargetHandleList l_memBufTargetList; + getAllChips(l_memBufTargetList, TYPE_MEMBUF); // -------------------------------------------------------------------- - // run mss_thermal_init on all functional MCS chiplets + // run mss_thermal_init on all functional Centaur chips // -------------------------------------------------------------------- - for (auto l_pMcs : l_mcsTargetList) + for (const auto & l_pCentaur : l_memBufTargetList) { - fapi2::Target<fapi2::TARGET_TYPE_MCS> l_fapi_pMcs - (l_pMcs); + fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP> l_fapi_pCentaur + (l_pCentaur); // Current run on target TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "Running call_mss_thermal_init HWP on " - "target HUID %.8X", TARGETING::get_huid(l_pMcs)); + "Running p9c_mss_thermal_init HWP on target HUID %.8X", + TARGETING::get_huid(l_pCentaur) ); - FAPI_INVOKE_HWP( l_errl, p9_mss_thermal_init, l_fapi_pMcs ); + FAPI_INVOKE_HWP( l_errl, p9c_mss_thermal_init, l_fapi_pCentaur ); if ( l_errl ) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: p9_mss_thermal_init HWP returns error", + "ERROR 0x%.8X: p9c_mss_thermal_init HWP returns error", l_errl->reasonCode()); // capture the target data in the elog - ErrlUserDetailsTarget(l_pMcs).addToLog( l_errl ); + ErrlUserDetailsTarget(l_pCentaur).addToLog( l_errl ); // Create IStep error log and cross reference // to error that occurred - l_StepError.addErrorDetails( l_errl ); + io_istepError.addErrorDetails( l_errl ); // Commit Error errlCommit( l_errl, HWPF_COMP_ID ); @@ -139,70 +188,153 @@ void* call_mss_thermal_init (void *io_pArgs) } else { - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : p9_mss_thermal_init HWP( )" ); + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : p9c_mss_thermal_init HWP( ) on 0x%.8X target", + TARGETING::get_huid(l_pCentaur) ); } - } + } // end MEMBUF loop +} +#else +void nimbus_call_mss_thermal_init(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'p9_mss_thermal_init' but Nimbus code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} - do +void cumulus_call_mss_thermal_init(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'p9c_mss_thermal_init' but Cumulus code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} +#endif + +#ifdef CONFIG_AXONE +void axone_call_mss_thermal_init(IStepError & io_istepError) +{ + errlHndl_t l_err = nullptr; + + // Get all OCMB targets + TARGETING::TargetHandleList l_ocmbTargetList; + getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP); + + for (const auto & l_ocmb_target : l_ocmbTargetList) { - // Run proc throttle sync - // Get all functional proc chip targets - //Use targeting code to get a list of all processors - TARGETING::TargetHandleList l_procChips; - getAllChips( l_procChips, TARGETING::TYPE_PROC ); + // check EXPLORER first as this is most likely the configuration + uint32_t chipId = l_ocmb_target->getAttr< TARGETING::ATTR_CHIP_ID>(); + if (chipId == POWER_CHIPID::EXPLORER_16) + { + fapi2::Target <fapi2::TARGET_TYPE_OCMB_CHIP> l_fapi_ocmb_target + (l_ocmb_target); + + // Dump current run on target + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running exp_mss_thermal_init HWP on target HUID %.8X", + TARGETING::get_huid(l_ocmb_target)); - for (const auto & l_procChip: l_procChips) + // call the HWP with each fapi2::Target + FAPI_INVOKE_HWP(l_err, exp_mss_thermal_init, l_fapi_ocmb_target); + } + else { - //Convert the TARGETING::Target into a fapi2::Target by passing - //l_procChip into the fapi2::Target constructor - fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> - l_fapi2CpuTarget((l_procChip)); + // Gemini, NOOP + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Skipping thermal_init HWP on axone target HUID 0x%.8X, chipId 0x%.4X", + TARGETING::get_huid(l_ocmb_target), chipId ); + } + + if (l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: exp_mss_thermal_init HWP returns error", + l_err->reasonCode()); + // capture the target data in the elog + ErrlUserDetailsTarget(l_ocmb_target).addToLog(l_err); + + // Create IStep error log and cross reference to error that + // occurred + io_istepError.addErrorDetails( l_err ); + + // Commit Error + errlCommit( l_err, HWPF_COMP_ID ); + + break; + } + else if (chipId == POWER_CHIPID::EXPLORER_16) + { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "Running p9_throttle_sync HWP on " - "target HUID %.8X", TARGETING::get_huid(l_procChip)); - - // Call p9_throttle_sync - FAPI_INVOKE_HWP( l_errl, p9_throttle_sync, l_fapi2CpuTarget ); - - if (l_errl) - { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: p9_throttle_sync HWP returns error", - l_errl->reasonCode()); - - // Capture the target data in the elog - ErrlUserDetailsTarget(l_procChip).addToLog(l_errl); - - // Create IStep error log and cross reference - // to error that occurred - l_StepError.addErrorDetails( l_errl ); - - // Commit Error - errlCommit( l_errl, HWPF_COMP_ID ); - - break; - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : p9_throttle_sync HWP( )" ); - } + "SUCCESS running exp_mss_thermal_init HWP on target HUID %.8X", + TARGETING::get_huid(l_ocmb_target)); } + } // end OCMB loop +} +#else +void axone_call_mss_thermal_init(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'exp_mss_thermal_init' but Axone code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} +#endif - } while (0); +void run_proc_throttle_sync(IStepError & io_istepError) +{ + errlHndl_t l_errl = nullptr; + + // Run proc throttle sync + // Get all functional proc chip targets + // Use targeting code to get a list of all processors + TARGETING::TargetHandleList l_procChips; + getAllChips( l_procChips, TARGETING::TYPE_PROC ); - if(l_StepError.isNull()) + for (const auto & l_procChip: l_procChips) { + //Convert the TARGETING::Target into a fapi2::Target by passing + //l_procChip into the fapi2::Target constructor + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> + l_fapi2CpuTarget((l_procChip)); + + // Call p9_throttle_sync +#ifndef CONFIG_AXONE TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : call_mss_thermal_init" ); - } + "Running p9_throttle_sync HWP on target HUID %.8X", + TARGETING::get_huid(l_procChip) ); + FAPI_INVOKE_HWP( l_errl, p9_throttle_sync, l_fapi2CpuTarget ); +#else + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running p9a_throttle_sync HWP on target HUID %.8X", + TARGETING::get_huid(l_procChip) ); + FAPI_INVOKE_HWP( l_errl, p9a_throttle_sync, l_fapi2CpuTarget ); +#endif + if (l_errl) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: p9_throttle_sync HWP returns error", + l_errl->reasonCode()); - // end task, returning any errorlogs to IStepDisp - return l_StepError.getErrorHandle(); + // Capture the target data in the elog + ErrlUserDetailsTarget(l_procChip).addToLog(l_errl); + + // Create IStep error log and cross reference + // to error that occurred + io_istepError.addErrorDetails( l_errl ); + + // Commit Error + errlCommit( l_errl, HWPF_COMP_ID ); + + break; + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : p9_throttle_sync HWP on 0x%.8X processor", + TARGETING::get_huid(l_procChip) ); + } + } } }; diff --git a/src/usr/isteps/istep14/call_proc_exit_cache_contained.C b/src/usr/isteps/istep14/call_proc_exit_cache_contained.C index 897bb58ac..b118401f6 100644 --- a/src/usr/isteps/istep14/call_proc_exit_cache_contained.C +++ b/src/usr/isteps/istep14/call_proc_exit_cache_contained.C @@ -47,7 +47,6 @@ #include <arch/pirformat.H> #include <isteps/hwpf_reasoncodes.H> #include <devicefw/userif.H> -#include <config.h> #include <util/misc.H> #include <hwas/common/hwas.H> #include <sys/misc.h> @@ -81,7 +80,7 @@ void* call_proc_exit_cache_contained (void *io_pArgs) "call_proc_exit_cache_contained entry" ); errlHndl_t l_errl = nullptr; -#ifdef CONFIG_SECUREBOOT +#if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE) if(SECUREBOOT::enabled()) { SECUREBOOT::CENTAUR_SECURITY::ScomCache& centaurCache = @@ -537,7 +536,7 @@ void* call_proc_exit_cache_contained (void *io_pArgs) errlCommit( l_errl, HWPF_COMP_ID ); } -#ifdef CONFIG_SECUREBOOT +#if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE) // Unload the MEMD section that was loaded at the beginning of step11 l_errl = unloadSecureSection(PNOR::MEMD); if (l_errl) diff --git a/src/usr/isteps/istep14/call_proc_setup_bars.C b/src/usr/isteps/istep14/call_proc_setup_bars.C index 25ed067d2..9cb0f402a 100644 --- a/src/usr/isteps/istep14/call_proc_setup_bars.C +++ b/src/usr/isteps/istep14/call_proc_setup_bars.C @@ -22,7 +22,6 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -#include <config.h> #include <errl/errlentry.H> #include <isteps/hwpisteperror.H> #include <initservice/isteps_trace.H> diff --git a/src/usr/isteps/istep14/makefile b/src/usr/isteps/istep14/makefile index 47c6c15e6..9aaa19c97 100644 --- a/src/usr/isteps/istep14/makefile +++ b/src/usr/isteps/istep14/makefile @@ -26,18 +26,22 @@ ROOTPATH = ../../../.. MODULE = istep14 PROCEDURE_PATH = ${ROOTPATH}/src/import/chips/p9/procedures +AXONE_PROCEDURE_PATH = ${ROOTPATH}/src/import/chips/p9a/procedures CEN_PROC_PATH = ${ROOTPATH}/src/import/chips/centaur/procedures EXP_COMMON_PATH = ${ROOTPATH}/src/import/chips/ocmb/explorer/common +EXPLORER_HWP_PATH = ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory/ #Add all the extra include paths EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/ +EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/generic/memory/lib +EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/chips/ocmb/explorer/procedures/hwp/memory/lib/ +EXTRAINCDIR += ${ROOTPATH}/src/import/ EXTRAINCDIR += ${ROOTPATH}/src/import/hwpf/fapi2/include EXTRAINCDIR += ${ROOTPATH}/src/include/usr/fapi2 EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/utils EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/utils/imageProcs EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils/imageProcs EXTRAINCDIR += ${PROCEDURE_PATH}/hwp/nest -EXTRAINCDIR += ${ROOTPATH}/src/import/ EXTRAINCDIR += ${PROCEDURE_PATH}/hwp/memory EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/common/include/ EXTRAINCDIR += ${PROCEDURE_PATH}/hwp/memory/lib/eff_config/ @@ -50,6 +54,9 @@ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/centaur/common/include/ EXTRAINCDIR += ${PROCEDURE_PATH}/hwp/memory/lib/dimm/ddr4/ EXTRAINCDIR += ${EXP_COMMON_PATH}/include/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils +EXTRAINCDIR += ${AXONE_PROCEDURE_PATH}/hwp/memory/ +EXTRAINCDIR += ${EXPLORER_HWP_PATH} OBJS += call_mss_memdiag.o OBJS += call_mss_thermal_init.o @@ -92,14 +99,24 @@ OBJS += p9_revert_sbe_mcs_setup.o # include ${PROCEDURE_PATH}/hwp/memory/p9_mss_thermal_init.mk # include ${CEN_PROC_PATH}/hwp/memory/p9c_mss_thermal_init.mk # include ${CEN_PROC_PATH}/hwp/memory/p9c_mss_unmask_errors.mk -include ${PROCEDURE_PATH}/hwp/nest/p9_throttle_sync.mk + include ${PROCEDURE_PATH}/hwp/memory/p9_mss_power_cleanup.mk -include ${ROOTPATH}/config.mk -VPATH += ${PROCEDURE_PATH}/hwp/nest/ ${PROCEDURE_PATH}/hwp/memory/ +VPATH += ${PROCEDURE_PATH}/hwp/nest/ +VPATH += ${PROCEDURE_PATH}/hwp/memory/ VPATH += ${PROCEDURE_PATH}/hwp/memory/lib/eff_config/ VPATH += ${PROCEDURE_PATH}/hwp/memory/lib/utils/ VPATH += ${PROCEDURE_PATH}/hwp/memory/lib/mcbist/ VPATH += ${PROCEDURE_PATH}/hwp/memory/lib/dimm/ VPATH += ${CEN_PROC_PATH}/hwp/memory/ VPATH += ${PROCEDURE_PATH}/hwp/memory/lib/dimm/ddr4/ + +# Axone vs non-Axone specific HWP +VPATH += $(if $(CONFIG_AXONE),${EXPLORER_HWP_PATH},) +OBJS += $(if $(CONFIG_AXONE),exp_mss_thermal_init.o,) +# TODO RTC:245219 +# use PRD's version of memdiags instead of this cronus verison once its working +OBJS += $(if $(CONFIG_AXONE),exp_mss_memdiag.o,) + +include ${ROOTPATH}/config.mk + |
