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-rw-r--r--src/usr/isteps/istep12/call_cen_dmi_scominit.C48
-rw-r--r--src/usr/isteps/istep12/call_cen_set_inband_addr.C369
-rw-r--r--src/usr/isteps/istep12/call_dmi_io_dccal.C266
-rw-r--r--src/usr/isteps/istep12/call_dmi_io_run_training.C105
-rw-r--r--src/usr/isteps/istep12/call_dmi_post_trainadv.C112
-rw-r--r--src/usr/isteps/istep12/call_dmi_pre_trainadv.C102
-rw-r--r--src/usr/isteps/istep12/call_mss_getecid.C182
-rw-r--r--src/usr/isteps/istep12/call_proc_dmi_scominit.C53
-rw-r--r--src/usr/isteps/istep12/makefile20
9 files changed, 881 insertions, 376 deletions
diff --git a/src/usr/isteps/istep12/call_cen_dmi_scominit.C b/src/usr/isteps/istep12/call_cen_dmi_scominit.C
index 8e7a9feef..868f1da2a 100644
--- a/src/usr/isteps/istep12/call_cen_dmi_scominit.C
+++ b/src/usr/isteps/istep12/call_cen_dmi_scominit.C
@@ -46,10 +46,6 @@
// HWP
#include <p9_io_cen_scominit.H>
-#ifdef CONFIG_AXONE
-#include <p9a_omi_setup_bars.H>
-#endif
-
using namespace ISTEP;
using namespace ISTEP_ERROR;
using namespace ERRORLOG;
@@ -107,50 +103,6 @@ void* call_cen_dmi_scominit (void *io_pArgs)
}
- #ifdef CONFIG_AXONE
- TARGETING::TargetHandleList l_procTargetList;
- getAllChips(l_procTargetList, TYPE_PROC);
-
- TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_dmi_scominit: %d procs found",
- l_procTargetList.size());
-
- for (const auto & l_proc_target : l_procTargetList)
- {
- TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "p9a_omi_setup_bars HWP target HUID %.8x",
- TARGETING::get_huid(l_proc_target));
-
- // call the HWP with each target
- fapi2::Target <fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_proc_target
- (l_proc_target);
-
- FAPI_INVOKE_HWP(l_err, p9a_omi_setup_bars, l_fapi_proc_target);
-
- // process return code.
- if ( l_err )
- {
- TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "ERROR 0x%.8X: p9a_omi_setup_bars HWP on target HUID %.8x",
- l_err->reasonCode(), TARGETING::get_huid(l_proc_target) );
-
- // capture the target data in the elog
- ErrlUserDetailsTarget(l_proc_target).addToLog( l_err );
-
- // Create IStep error log and cross reference to error that occurred
- l_StepError.addErrorDetails( l_err );
-
- // Commit Error
- errlCommit( l_err, ISTEP_COMP_ID );
- }
- else
- {
- TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "SUCCESS : p9a_omi_setup_bars HWP");
- }
-
- }
- #endif // CONFIG_AXONE
-
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_dmi_scominit exit" );
// end task, returning any errorlogs to IStepDisp
diff --git a/src/usr/isteps/istep12/call_cen_set_inband_addr.C b/src/usr/isteps/istep12/call_cen_set_inband_addr.C
index 196f7bed7..1b1161298 100644
--- a/src/usr/isteps/istep12/call_cen_set_inband_addr.C
+++ b/src/usr/isteps/istep12/call_cen_set_inband_addr.C
@@ -44,12 +44,15 @@
#include <util/utilmbox_scratch.H>
#include <util/misc.H>
-//HWP
-#include <p9c_set_inband_addr.H>
-
#ifdef CONFIG_AXONE
+// Axone HWPs
#include <exp_omi_init.H>
#include <p9a_omi_init.H>
+#include <p9a_disable_ocmb_i2c.H>
+#include <expupd/expupd.H>
+#else
+// Cumulus HWP
+#include <p9c_set_inband_addr.H>
#endif
//Inband SCOM
@@ -60,169 +63,313 @@ using namespace ISTEP_ERROR;
using namespace ERRORLOG;
using namespace TARGETING;
-
namespace ISTEP_12
{
+void cumulus_call_cen_set_inband_addr(IStepError & io_istepError);
+void axone_call_cen_set_inband_addr(IStepError & io_istepError);
+void enableInbandScomsOCMB( TARGETING::TargetHandleList i_ocmbTargetList );
+void disableI2cAccessToOcmbs(IStepError & io_istepError);
+
void* call_cen_set_inband_addr (void *io_pArgs)
{
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_set_inband_addr entry" );
IStepError l_StepError;
- errlHndl_t l_err = NULL;
auto l_procModel = TARGETING::targetService().getProcessorModel();
- TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_set_inband_addr entry" );
+ switch (l_procModel)
+ {
+ case TARGETING::MODEL_CUMULUS:
+ cumulus_call_cen_set_inband_addr(l_StepError);
+ // @todo RTC 187913 inband centaur scom in P9
+ // Re-enable when support available in simics
+ if ( Util::isSimicsRunning() == false )
+ {
+ //Now enable Inband SCOM for all memory mapped chips.
+ IBSCOM::enableInbandScoms();
+ }
+ break;
+ case TARGETING::MODEL_AXONE:
+ axone_call_cen_set_inband_addr(l_StepError);
+
+ // No need to disable i2c access if and error was encountered setting up the inband addr
+ if(l_StepError.isNull())
+ {
+ disableI2cAccessToOcmbs(l_StepError);
+ }
+ break;
+ case TARGETING::MODEL_NIMBUS:
+ break; // do nothing step
+ default:
+ assert(0, "call_cen_set_inband_addr: Unsupported model type 0x%04X",
+ l_procModel);
+ break;
+ }
+
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_set_inband_addr exit" );
+
+ // end task, returning any errorlogs to IStepDisp
+ return l_StepError.getErrorHandle();
+}
+
+#ifndef CONFIG_AXONE
+void cumulus_call_cen_set_inband_addr(IStepError & io_istepError)
+{
+ errlHndl_t l_err = nullptr;
+ TARGETING::TargetHandleList l_procTargetList;
+ getAllChips(l_procTargetList, TYPE_PROC);
+
+ TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_set_inband_addr: %d proc chips found",
+ l_procTargetList.size());
- if(l_procModel == TARGETING::MODEL_CUMULUS)
+ for (const auto & l_proc_target : l_procTargetList)
{
- TARGETING::TargetHandleList l_procTargetList;
- getAllChips(l_procTargetList, TYPE_PROC);
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "p9c_set_inband_addr HWP target HUID %.8x",
+ TARGETING::get_huid(l_proc_target));
- TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_set_inband_addr: %d proc chips found",
- l_procTargetList.size());
+ // call the HWP with each target
+ fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_proc_target
+ (l_proc_target);
- for (const auto & l_proc_target : l_procTargetList)
- {
+ FAPI_INVOKE_HWP(l_err, p9c_set_inband_addr, l_fapi_proc_target);
+ // process return code.
+ if ( l_err )
+ {
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "p9c_set_inband_addr HWP target HUID %.8x",
- TARGETING::get_huid(l_proc_target));
+ "ERROR 0x%.8X: p9c_set_inband_addr HWP on target HUID %.8x",
+ l_err->reasonCode(), TARGETING::get_huid(l_proc_target) );
- // call the HWP with each target
- fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_proc_target
- (l_proc_target);
+ // capture the target data in the elog
+ ErrlUserDetailsTarget(l_proc_target).addToLog( l_err );
- FAPI_INVOKE_HWP(l_err, p9c_set_inband_addr, l_fapi_proc_target);
+ // Create IStep error log and cross reference to error that occurred
+ io_istepError.addErrorDetails( l_err );
- // process return code.
- if ( l_err )
- {
- TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "ERROR 0x%.8X: p9c_set_inband_addr HWP on target HUID %.8x",
- l_err->reasonCode(), TARGETING::get_huid(l_proc_target) );
+ // Commit Error
+ errlCommit( l_err, ISTEP_COMP_ID );
- // capture the target data in the elog
- ErrlUserDetailsTarget(l_proc_target).addToLog( l_err );
+ }
+ else
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "SUCCESS : p9c_set_inband_addr HWP");
+ }
+ } // proc target loop
+}
- // Create IStep error log and cross reference to error that occurred
- l_StepError.addErrorDetails( l_err );
+void axone_call_cen_set_inband_addr(IStepError & io_istepError)
+{
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "Error: Trying to call 'exp_omi_init/p9a_omi_init' but Axone code is not compiled in");
+ assert(0, "Calling wrong Model's HWPs");
+}
- // Commit Error
- errlCommit( l_err, ISTEP_COMP_ID );
+void enableInbandScomsOCMB( TARGETING::TargetHandleList l_ocmbTargetList )
+{
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "Error: Trying to call 'enableInbandScomsOCMB' but Axone code is not compiled in");
+ assert(0, "Calling wrong Model's HWPs");
+}
+
+void disableI2cAccessToOcmbs(IStepError & io_istepError)
+{
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "Error: Trying to call 'disableI2cAccessToOcmbs' but Axone code is not compiled in");
+ assert(0, "Calling wrong Model's HWPs");
+}
- }
- else
- {
- TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "SUCCESS : p9c_set_inband_addr HWP");
- }
- }
- }
+#else
- // @todo RTC 187913 inband centaur scom in P9
- // Re-enable when support available in simics
- if ( Util::isSimicsRunning() == false )
- {
- //Now enable Inband SCOM for all membuf chips.
- IBSCOM::enableInbandScoms();
- }
+void cumulus_call_cen_set_inband_addr(IStepError & io_istepError)
+{
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "Error: Trying to call 'p9c_set_inband_addr' but Cumulus code is not compiled in");
+ assert(0, "Calling wrong Model's HWPs");
+}
-#ifdef CONFIG_AXONE
- if(l_procModel == TARGETING::MODEL_AXONE)
+void axone_call_cen_set_inband_addr(IStepError & io_istepError)
+{
+ errlHndl_t l_err = nullptr;
+ TARGETING::TargetHandleList l_ocmbTargetList;
+ getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP);
+ TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+ "axone_call_cen_set_inband_addr: %d ocmb chips found",
+ l_ocmbTargetList.size());
+
+ for (const auto & l_ocmb_target : l_ocmbTargetList)
{
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "exp_omi_init HWP target HUID %.8x",
+ TARGETING::get_huid(l_ocmb_target) );
- TARGETING::TargetHandleList l_ocmbTargetList;
- getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP);
+ // call the HWP with each target
+ fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> l_fapi_ocmb_target
+ (l_ocmb_target);
- TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_set_inband_addr: %d ocmb chips found",
- l_ocmbTargetList.size());
+ FAPI_INVOKE_HWP(l_err, exp_omi_init , l_fapi_ocmb_target);
- for (const auto & l_ocmb_target : l_ocmbTargetList)
+ // process return code.
+ if ( l_err )
{
- TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "exp_omi_init HWP target HUID %.8x",
- TARGETING::get_huid(l_ocmb_target));
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, ERR_MRK
+ "ERROR 0x%.8X: exp_omi_init HWP on target HUID 0x%.8x",
+ l_err->reasonCode(), TARGETING::get_huid(l_ocmb_target) );
- // call the HWP with each target
- fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> l_fapi_ocmb_target
- (l_ocmb_target);
+ // capture the target data in the elog
+ ErrlUserDetailsTarget(l_ocmb_target).addToLog( l_err );
- FAPI_INVOKE_HWP(l_err, exp_omi_init , l_fapi_ocmb_target);
+ // Create IStep error log and cross reference to error that occurred
+ io_istepError.addErrorDetails( l_err );
- // process return code.
- if ( l_err )
- {
- TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "ERROR 0x%.8X: exp_omi_init HWP on target HUID 0x%.8x",
- l_err->reasonCode(), TARGETING::get_huid(l_ocmb_target) );
+ // Commit Error
+ errlCommit( l_err, ISTEP_COMP_ID );
+ }
+ else
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "SUCCESS : exp_omi_init HWP on target HUID 0x%.8x",
+ TARGETING::get_huid(l_ocmb_target) );
+ }
+ } // ocmb loop
- // capture the target data in the elog
- ErrlUserDetailsTarget(l_ocmb_target).addToLog( l_err );
+ TargetHandleList l_mccTargetList;
+ getAllChiplets(l_mccTargetList, TYPE_MCC);
- // Create IStep error log and cross reference to error that occurred
- l_StepError.addErrorDetails( l_err );
+ for (const auto & l_mcc_target : l_mccTargetList)
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "p9a_omi_init HWP target HUID %.8x",
+ TARGETING::get_huid(l_mcc_target) );
- // Commit Error
- errlCommit( l_err, ISTEP_COMP_ID );
+ // call the HWP with each target
+ fapi2::Target<fapi2::TARGET_TYPE_MCC> l_fapi_mcc_target
+ (l_mcc_target);
- }
- else
- {
- TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "SUCCESS : exp_omi_init HWP on target HUID 0x%.8x",
- TARGETING::get_huid(l_ocmb_target));
- }
+ FAPI_INVOKE_HWP(l_err, p9a_omi_init, l_fapi_mcc_target);
- }
+ // process return code.
+ if ( l_err )
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, ERR_MRK
+ "ERROR 0x%.8X: p9a_omi_init HWP on target HUID %.8x",
+ l_err->reasonCode(), TARGETING::get_huid(l_mcc_target) );
- TARGETING::TargetHandleList l_mccTargetList;
- getAllChiplets(l_mccTargetList, TYPE_MCC);
+ // capture the target data in the elog
+ ErrlUserDetailsTarget(l_mcc_target).addToLog( l_err );
- for (const auto & l_mcc_target : l_mccTargetList)
+ // Create IStep error log and cross reference to error that occurred
+ io_istepError.addErrorDetails( l_err );
+
+ // Commit Error
+ errlCommit( l_err, ISTEP_COMP_ID );
+ }
+ else
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "p9a_omi_init HWP target HUID %.8x",
+ "SUCCESS : p9a_omi_init HWP on target HUID 0x%.8x ,"
+ "setting scom settings to use inband for all ocmb children",
TARGETING::get_huid(l_mcc_target));
- // call the HWP with each target
- fapi2::Target<fapi2::TARGET_TYPE_MCC> l_fapi_mcc_target
- (l_mcc_target);
+ TargetHandleList l_ocmbTargetList;
+ getChildAffinityTargets(l_ocmbTargetList , l_mcc_target,
+ CLASS_CHIP, TARGETING::TYPE_OCMB_CHIP);
+ enableInbandScomsOCMB(l_ocmbTargetList);
+ }
+ } // MCC loop
+
+ // Check if any explorer chips require a firmware update and update them
+ // (skipped on MPIPL)
+ // We should be checking for updates and perform the updates even if OMI
+ // initialization failed. It's possible that the OMI failure was due to
+ // the OCMB having an old image. The update code will automatically
+ // switch to using i2c if OMI is not enabled.
+ Target* l_pTopLevel = nullptr;
+ targetService().getTopLevelTarget( l_pTopLevel );
+ assert(l_pTopLevel, "axone_call_cen_set_inband_addr: no TopLevelTarget");
+ if (l_pTopLevel->getAttr<TARGETING::ATTR_IS_MPIPL_HB>())
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "skipping expupdUpdateAll due to MPIPL");
+ }
+ else
+ {
+ expupd::updateAll(io_istepError);
+ }
+}
- FAPI_INVOKE_HWP(l_err, p9a_omi_init, l_fapi_mcc_target);
+/**
+ * @brief Loop over all processors and disable i2c path to ocmb
+ * After this point no i2c commands will be possible until we
+ * power the chip off and on.
+ * @param io_istepError - Istep error that tracks error logs for this step
+ */
+void disableI2cAccessToOcmbs(IStepError & io_istepError)
+{
+ errlHndl_t l_err = nullptr;
+ TARGETING::TargetHandleList l_procTargetList;
+ getAllChips(l_procTargetList, TARGETING::TYPE_PROC);
+ // We only want to disable i2c if we are in secure mode
+ const bool FORCE_DISABLE = false;
- // process return code.
- if ( l_err )
- {
- TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "ERROR 0x%.8X: p9a_omi_init HWP on target HUID %.8x",
- l_err->reasonCode(), TARGETING::get_huid(l_mcc_target) );
+ for ( const auto & l_proc : l_procTargetList )
+ {
+ // call the HWP with each proc
+ fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_proc_target
+ (l_proc);
- // capture the target data in the elog
- ErrlUserDetailsTarget(l_mcc_target).addToLog( l_err );
+ FAPI_INVOKE_HWP(l_err, p9a_disable_ocmb_i2c, l_fapi_proc_target, FORCE_DISABLE);
- // Create IStep error log and cross reference to error that occurred
- l_StepError.addErrorDetails( l_err );
+ // process return code.
+ if ( l_err )
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, ERR_MRK
+ "ERROR 0x%.8X: p9a_disable_ocmb_i2c HWP on target HUID %.8x",
+ l_err->reasonCode(), TARGETING::get_huid(l_proc) );
- // Commit Error
- errlCommit( l_err, ISTEP_COMP_ID );
+ // capture the target data in the elog
+ ErrlUserDetailsTarget(l_proc).addToLog( l_err );
- }
- else
- {
- TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "SUCCESS : p9a_omi_init HWP on target HUID 0x%.8x",
- TARGETING::get_huid(l_mcc_target));
- }
+ // Create IStep error log and cross reference to error that occurred
+ io_istepError.addErrorDetails( l_err );
+ // Commit Error
+ errlCommit( l_err, ISTEP_COMP_ID );
+ }
+ else
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "SUCCESS : p9a_disable_ocmb_i2c HWP on target HUID 0x%.8x",
+ TARGETING::get_huid(l_proc));
}
}
-#endif // CONFIG_AXONE
+}
+/**
+ * @brief Enable Inband Scom for the OCMB targets
+ * @param i_ocmbTargetList - OCMB targets
+ */
+void enableInbandScomsOCMB( TARGETING::TargetHandleList i_ocmbTargetList )
+{
+ mutex_t* l_mutex = NULL;
- TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_set_inband_addr exit" );
+ for ( const auto & l_ocmb : i_ocmbTargetList )
+ {
+ //don't mess with attributes without the mutex (just to be safe)
+ l_mutex = l_ocmb->getHbMutexAttr<TARGETING::ATTR_IBSCOM_MUTEX>();
+ mutex_lock(l_mutex);
- // end task, returning any errorlogs to IStepDisp
- return l_StepError.getErrorHandle();
+ ScomSwitches l_switches = l_ocmb->getAttr<ATTR_SCOM_SWITCHES>();
+ l_switches.useI2cScom = 0;
+ l_switches.useInbandScom = 1;
+ // Modify attribute
+ l_ocmb->setAttr<ATTR_SCOM_SWITCHES>(l_switches);
+ mutex_unlock(l_mutex);
+ }
}
+#endif // CONFIG_AXONE
+
};
diff --git a/src/usr/isteps/istep12/call_dmi_io_dccal.C b/src/usr/isteps/istep12/call_dmi_io_dccal.C
index ca2d11aef..339c8be9c 100644
--- a/src/usr/isteps/istep12/call_dmi_io_dccal.C
+++ b/src/usr/isteps/istep12/call_dmi_io_dccal.C
@@ -43,113 +43,257 @@
#include <fapi2/plat_hwp_invoker.H>
#include <util/utilmbox_scratch.H>
-// HWP
+// HWP (only bring in model-specific HWP headers to save space)
+#ifdef CONFIG_AXONE
+#include <p9a_io_omi_dccal.H>
+#include <p9a_io_omi_scominit.H>
+#else
#include <p9_io_dmi_dccal.H>
#include <p9_io_cen_dccal.H>
+#endif
using namespace ISTEP;
using namespace ISTEP_ERROR;
using namespace ERRORLOG;
using namespace TARGETING;
+#define POS_0_VECTOR 0x000000FF
+#define BITS_PER_BYTE 8
namespace ISTEP_12
{
+
+// Declare local functions
+void cumulus_dccal_setup(IStepError & io_istepError);
+void axone_dccal_setup(IStepError & io_istepError);
+
void* call_dmi_io_dccal (void *io_pArgs)
{
IStepError l_StepError;
- errlHndl_t l_err = NULL;
TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_io_dccal entry" );
do
{
+ auto l_procModel = TARGETING::targetService().getProcessorModel();
- TARGETING::TargetHandleList l_procTargetList;
- getAllChips(l_procTargetList, TYPE_PROC);
+ switch (l_procModel)
+ {
+ case TARGETING::MODEL_CUMULUS:
+ cumulus_dccal_setup(l_StepError);
+ break;
+ case TARGETING::MODEL_AXONE:
+ axone_dccal_setup(l_StepError);
+ break;
+ case TARGETING::MODEL_NIMBUS:
+ default:
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "skipping p9_io_dmi_dccal because not required for current processor model 0x%x", l_procModel);
+ break;
+ }
- if(l_procTargetList[0]->getAttr<TARGETING::ATTR_MODEL>() != TARGETING::MODEL_CUMULUS)
+ }while(0);
+
+
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_io_dccal exit" );
+
+ // end task, returning any errorlogs to IStepDisp
+ return l_StepError.getErrorHandle();
+}
+
+#ifndef CONFIG_AXONE
+void cumulus_dccal_setup(IStepError & io_istepError)
+{
+ errlHndl_t l_err = nullptr;
+ TARGETING::TargetHandleList l_procTargetList;
+ getAllChips(l_procTargetList, TYPE_PROC);
+
+ for (const auto & l_proc_target : l_procTargetList)
+ {
+ // a. p9_io_dmi_dccal.C (DMI target)
+
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "p9_io_dmi_dccal HWP target HUID %.8x",
+ TARGETING::get_huid(l_proc_target));
+
+ // call the HWP with each target
+ fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_proc_target
+ (l_proc_target);
+
+ FAPI_INVOKE_HWP(l_err, p9_io_dmi_dccal, l_fapi_proc_target);
+
+ // process return code.
+ if ( l_err )
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "p9_io_dmi_dccal Proccessor model is not CUMULUS , skipping this step");
- break;
- }
+ "ERROR 0x%.8X: p9_io_dmi_dccal HWP on target HUID %.8x",
+ l_err->reasonCode(), TARGETING::get_huid(l_proc_target) );
+
+ // capture the target data in the elog
+ ErrlUserDetailsTarget(l_proc_target).addToLog( l_err );
- for (const auto & l_proc_target : l_procTargetList)
+ // Create IStep error log and cross reference to error that occurred
+ io_istepError.addErrorDetails( l_err );
+
+ // Commit Error
+ errlCommit( l_err, ISTEP_COMP_ID );
+ }
+ else
{
- // a. p9_io_dmi_dccal.C (DMI target)
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "SUCCESS : p9_io_dmi_dccal HWP on target HUID %.8x",
+ TARGETING::get_huid(l_proc_target) );
+ }
+
+ // b. p9_io_cen_dccal.C (Centaur target)
+
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "p9_io_cen_dccal HWP target HUID %.8x",
+ TARGETING::get_huid(l_proc_target));
+ FAPI_INVOKE_HWP(l_err, p9_io_cen_dccal, l_fapi_proc_target);
+
+ // process return code.
+ if ( l_err )
+ {
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "p9_io_dmi_dccal HWP target HUID %.8x",
- TARGETING::get_huid(l_proc_target));
+ "ERROR 0x%.8X: p9_io_cen_dccal HWP on target HUID %.8x",
+ l_err->reasonCode(), TARGETING::get_huid(l_proc_target) );
- // call the HWP with each target
- fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_proc_target
- (l_proc_target);
+ // capture the target data in the elog
+ ErrlUserDetailsTarget(l_proc_target).addToLog( l_err );
- FAPI_INVOKE_HWP(l_err, p9_io_dmi_dccal, l_fapi_proc_target);
+ // Create IStep error log and cross reference to error that occurred
+ io_istepError.addErrorDetails( l_err );
- // process return code.
- if ( l_err )
- {
- TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "ERROR 0x%.8X: p9_io_dmi_dccal HWP on target HUID %.8x",
- l_err->reasonCode(), TARGETING::get_huid(l_proc_target) );
+ // Commit Error
+ errlCommit( l_err, ISTEP_COMP_ID );
+ }
+ else
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "SUCCESS : p9_io_cen_dccal HWP on target HUID %.8x",
+ TARGETING::get_huid(l_proc_target) );
+ }
- // capture the target data in the elog
- ErrlUserDetailsTarget(l_proc_target).addToLog( l_err );
+ }
+}
+#else
+void cumulus_dccal_setup(IStepError & io_istepError)
+{
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "Error: Trying to call 'p9_io_dmi_dccal' and 'p9_io_cen_dccal' but Cumulus code is not compiled in");
+ assert(0, "Calling wrong Model's HWPs");
+}
+#endif
- // Create IStep error log and cross reference to error that occurred
- l_StepError.addErrorDetails( l_err );
+#ifdef CONFIG_AXONE
+void axone_dccal_setup(IStepError & io_istepError)
+{
+ errlHndl_t l_err = nullptr;
+ TargetHandleList l_omic_target_list;
+ getAllChiplets(l_omic_target_list, TYPE_OMIC);
- // Commit Error
- errlCommit( l_err, ISTEP_COMP_ID );
- }
- else
- {
- TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "SUCCESS : p9_io_dmi_dccal HWP");
- }
+ for (const auto & l_omic_target : l_omic_target_list)
+ {
+ // call the HWP with each target
+ fapi2::Target<fapi2::TARGET_TYPE_OMIC> l_fapi_omic_target
+ (l_omic_target);
- // b. p9_io_cen_dccal.C (Centaur target)
+ TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+ "p9a_io_omi_scominit HWP target HUID %.8x",
+ get_huid(l_omic_target));
- TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "p9_io_cen_dccal HWP target HUID %.8x",
- TARGETING::get_huid(l_proc_target));
+ FAPI_INVOKE_HWP(l_err, p9a_io_omi_scominit, l_fapi_omic_target);
+ // process return code.
+ if ( l_err )
+ {
+ TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+ "ERROR 0x%.8X: p9a_io_omi_scominit HWP on target HUID %.8x",
+ l_err->reasonCode(), TARGETING::get_huid(l_omic_target) );
- FAPI_INVOKE_HWP(l_err, p9_io_cen_dccal, l_fapi_proc_target);
+ // capture the target data in the elog
+ ErrlUserDetailsTarget(l_omic_target).addToLog( l_err );
- // process return code.
- if ( l_err )
- {
- TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "ERROR 0x%.8X: p9_io_cen_dccal HWP on target HUID %.8x",
- l_err->reasonCode(), TARGETING::get_huid(l_proc_target) );
+ // Create IStep error log and cross reference to error that occurred
+ io_istepError.addErrorDetails( l_err );
- // capture the target data in the elog
- ErrlUserDetailsTarget(l_proc_target).addToLog( l_err );
+ // Commit Error
+ errlCommit( l_err, ISTEP_COMP_ID );
+ }
+ else
+ {
+ TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+ "SUCCESS : p9a_io_omi_scominit HWP on target HUID %.8x",
+ TARGETING::get_huid(l_omic_target) );
+ }
- // Create IStep error log and cross reference to error that occurred
- l_StepError.addErrorDetails( l_err );
+ TargetHandleList l_omi_target_list;
- // Commit Error
- errlCommit( l_err, ISTEP_COMP_ID );
- }
- else
- {
- TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "SUCCESS : p9_io_cen_dccal HWP");
- }
+ getChildOmiTargetsByState(l_omi_target_list,
+ l_omic_target,
+ CLASS_UNIT,
+ TYPE_OMI,
+ UTIL_FILTER_FUNCTIONAL);
+
+ uint32_t l_laneVector = 0x00000000;
+
+ for(const auto & l_omi_target : l_omi_target_list)
+ {
+ // The OMI dc calibration HWP requires us to pass in the OMIC target
+ // and then a bit mask representing which positon of OMI we are calibrating.
+ // To get the position of the OMI relative to its parent OMIC, look up
+ // ATTR_OMI_DL_GROUP_POS then shift the POS_0_VECTOR = 0x000000FF by 1 byte to the left
+ // for every position away from 0 OMI_DL_GROUP_POS is.
+ // Therefore
+ // POS_0_VECTOR = 0x000000FF
+ // POS_1_VECTOR = 0x0000FF00
+ // POS_2_VECTOR = 0x00FF0000
+
+ l_laneVector |=
+ POS_0_VECTOR << (l_omi_target->getAttr<ATTR_OMI_DL_GROUP_POS>() * BITS_PER_BYTE);
}
- }while(0);
+ TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+ "p9a_io_omi_dccal HWP target HUID %.8x with lane vector 0x%x",
+ TARGETING::get_huid(l_omic_target), l_laneVector);
+ FAPI_INVOKE_HWP(l_err, p9a_io_omi_dccal, l_fapi_omic_target, l_laneVector);
- TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_io_dccal exit" );
+ // process return code.
+ if ( l_err )
+ {
+ TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+ "ERROR 0x%.8X: p9a_io_omi_dccal HWP on target HUID %.8x with lane vector 0x%x",
+ l_err->reasonCode(), TARGETING::get_huid(l_omic_target), l_laneVector);
- // end task, returning any errorlogs to IStepDisp
- return l_StepError.getErrorHandle();
+ // capture the target data in the elog
+ ErrlUserDetailsTarget(l_omic_target).addToLog( l_err );
+ l_err->collectTrace("ISTEPS_TRACE", 256);
+
+ // Create IStep error log and cross reference to error that occurred
+ io_istepError.addErrorDetails( l_err );
+
+ // Commit Error
+ errlCommit( l_err, ISTEP_COMP_ID );
+ }
+ else
+ {
+ TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+ "SUCCESS : p9a_io_omi_dccal HWP on target HUID %.8x with lane vector 0x%x",
+ TARGETING::get_huid(l_omic_target), l_laneVector );
+ }
+
+ }
+}
+#else
+void axone_dccal_setup(IStepError & io_istepError)
+{
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "Error: Trying to call 'p9a_io_omi_scominit' but Axone code is not compiled in");
+ assert(0, "Calling wrong Model's HWPs");
}
+#endif
};
diff --git a/src/usr/isteps/istep12/call_dmi_io_run_training.C b/src/usr/isteps/istep12/call_dmi_io_run_training.C
index 064a63a94..17bef45da 100644
--- a/src/usr/isteps/istep12/call_dmi_io_run_training.C
+++ b/src/usr/isteps/istep12/call_dmi_io_run_training.C
@@ -26,12 +26,12 @@
#include <trace/interface.H>
#include <initservice/taskargs.H>
+#include <initservice/isteps_trace.H>
#include <errl/errlentry.H>
-
-#include <isteps/hwpisteperror.H>
#include <errl/errludtarget.H>
-
-#include <initservice/isteps_trace.H>
+#include <util/utilmbox_scratch.H>
+#include <util/misc.H>
+#include <isteps/hwpisteperror.H>
// targeting support.
#include <targeting/common/commontargeting.H>
@@ -41,14 +41,15 @@
#include <config.h>
#include <fapi2.H>
#include <fapi2/plat_hwp_invoker.H>
-#include <util/utilmbox_scratch.H>
//HWP
#include <p9_io_dmi_linktrain.H>
#ifdef CONFIG_AXONE
#include <exp_omi_setup.H>
+#include <p9a_omi_train.H>
#include <exp_omi_train.H>
+#include <chipids.H> // for EXPLORER ID
#endif
using namespace ISTEP;
@@ -109,69 +110,91 @@ void* call_dmi_io_run_training (void *io_pArgs)
}
#ifdef CONFIG_AXONE
- TARGETING::TargetHandleList l_ocmbTargetList;
- getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP);
- for (const auto & l_ocmb_target : l_ocmbTargetList)
- {
- TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "exp_omi_setup HWP target HUID 0x%.08x",
- TARGETING::get_huid(l_ocmb_target));
-
- // call the HWP with each target
- fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> l_fapi_ocmb_target
- (l_ocmb_target);
-
- FAPI_INVOKE_HWP(l_err, exp_omi_setup, l_fapi_ocmb_target);
+ TARGETING::TargetHandleList l_ocmbTargetList;
+ getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP);
- // process return code.
- if ( l_err )
+ for (const auto & l_ocmb_target : l_ocmbTargetList)
{
- TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "ERROR 0x%.8X: exp_omi_setup HWP on target HUID 0x%.08x",
- l_err->reasonCode(), TARGETING::get_huid(l_ocmb_target) );
-
- // capture the target data in the elog
- ErrlUserDetailsTarget(l_ocmb_target).addToLog( l_err );
+ // Only run exp_omi_train on EXPLORER OCMB targets. This step
+ // cannot run on GEMINI targets.
+ uint32_t chipId = l_ocmb_target->getAttr< TARGETING::ATTR_CHIP_ID>();
+ fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> l_fapi_ocmb_target( l_ocmb_target );
+ if (chipId == POWER_CHIPID::EXPLORER_16)
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "Start omi training on target HUID 0x%.8X",
+ TARGETING::get_huid(l_ocmb_target) );
+ FAPI_INVOKE_HWP(l_err, exp_omi_train, l_fapi_ocmb_target);
+
+ // process return code.
+ if ( l_err )
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "ERROR 0x%.8X: exp_omi_train HWP on target HUID 0x%.08x",
+ l_err->reasonCode(), TARGETING::get_huid(l_ocmb_target) );
+
+ // capture the target data in the elog
+ ErrlUserDetailsTarget(l_ocmb_target).addToLog( l_err );
+
+ // Create IStep error log and cross reference to error that occurred
+ l_StepError.addErrorDetails( l_err );
+
+ // Commit Error , continue on to next OCMB
+ errlCommit( l_err, ISTEP_COMP_ID );
+ }
+ else
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "SUCCESS : exp_omi_train HWP on target 0x%.08X", TARGETING::get_huid(l_ocmb_target));
+ }
+ }
+ else
+ {
+ // Gemini, just skip exp_omi_train call
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "Skipping exp_omi_train HWP on because target HUID 0x%.8X, chipId 0x%.4X is a Gemini OCMB",
+ TARGETING::get_huid(l_ocmb_target), chipId );
+ }
+ }
- // Create IStep error log and cross reference to error that occurred
- l_StepError.addErrorDetails( l_err );
+ TARGETING::TargetHandleList l_omiTargetList;
+ getAllChiplets(l_omiTargetList, TYPE_OMI);
- // Commit Error , continue on to next OCMB
- errlCommit( l_err, ISTEP_COMP_ID );
- }
- else
+ for (const auto & l_omi_target : l_omiTargetList)
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "SUCCESS : exp_omi_setup HWP on target 0x%.08X, starting training", TARGETING::get_huid(l_ocmb_target));
+ "p9a_omi_train HWP target HUID %.8x",
+ TARGETING::get_huid(l_omi_target));
+
+ // call the HWP with each OMI target
+ fapi2::Target<fapi2::TARGET_TYPE_OMI> l_fapi_omi_target(l_omi_target);
- FAPI_INVOKE_HWP(l_err, exp_omi_train, l_fapi_ocmb_target);
+ FAPI_INVOKE_HWP(l_err, p9a_omi_train , l_fapi_omi_target );
// process return code.
if ( l_err )
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "ERROR 0x%.8X: exp_omi_train HWP on target HUID 0x%.08x",
- l_err->reasonCode(), TARGETING::get_huid(l_ocmb_target) );
+ "ERROR 0x%.8X: p9a_omi_train HWP on target HUID %.8x",
+ l_err->reasonCode(), TARGETING::get_huid(l_omi_target) );
// capture the target data in the elog
- ErrlUserDetailsTarget(l_ocmb_target).addToLog( l_err );
+ ErrlUserDetailsTarget(l_omi_target).addToLog( l_err );
// Create IStep error log and cross reference to error that occurred
l_StepError.addErrorDetails( l_err );
- // Commit Error , continue on to next OCMB
+ // Commit Error
errlCommit( l_err, ISTEP_COMP_ID );
}
else
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "SUCCESS : exp_omi_train HWP on target 0x%.08X", TARGETING::get_huid(l_ocmb_target));
+ "SUCCESS : p9a_omi_train HWP on 0x%.08X", TARGETING::get_huid(l_omi_target));
}
}
- }
-
#endif
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_io_run_training exit" );
diff --git a/src/usr/isteps/istep12/call_dmi_post_trainadv.C b/src/usr/isteps/istep12/call_dmi_post_trainadv.C
index 8f5e34106..af8ca6d0f 100644
--- a/src/usr/isteps/istep12/call_dmi_post_trainadv.C
+++ b/src/usr/isteps/istep12/call_dmi_post_trainadv.C
@@ -26,12 +26,13 @@
#include <trace/interface.H>
#include <initservice/taskargs.H>
+#include <initservice/isteps_trace.H>
#include <errl/errlentry.H>
-
-#include <isteps/hwpisteperror.H>
#include <errl/errludtarget.H>
+#include <isteps/hwpisteperror.H>
+#include <util/utilmbox_scratch.H>
+#include <util/misc.H>
-#include <initservice/isteps_trace.H>
// targeting support.
#include <targeting/common/commontargeting.H>
@@ -41,13 +42,14 @@
#include <config.h>
#include <fapi2.H>
#include <fapi2/plat_hwp_invoker.H>
-#include <util/utilmbox_scratch.H>
//HWP
#include <p9_io_dmi_post_trainadv.H>
#ifdef CONFIG_AXONE
#include <p9a_omi_train_check.H>
+#include <exp_omi_train_check.H>
+#include <chipids.H> // for EXPLORER ID
#endif
using namespace ISTEP;
@@ -129,41 +131,87 @@ void* call_dmi_post_trainadv (void *io_pArgs)
}
#ifdef CONFIG_AXONE
- // Find omi targets
- TARGETING::TargetHandleList l_omiTargetList;
- getAllChiplets(l_omiTargetList, TYPE_OMI);
-
- TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_post_trainadv: %d OMIs found",
- l_omiTargetList.size());
-
- for (const auto & l_omi_target : l_omiTargetList)
+ if( ! Util::isSimicsRunning() )
{
- // call the HWP with each OMI target
- fapi2::Target<fapi2::TARGET_TYPE_OMI> l_fapi_omi_target(l_omi_target);
+ // Find ocmb targets
+ TARGETING::TargetHandleList l_chipList;
+ TARGETING::getAllChips(l_chipList, TARGETING::TYPE_OCMB_CHIP, true);
- FAPI_INVOKE_HWP(l_err, p9a_omi_train_check, l_fapi_omi_target );
+ for (auto & l_ocmb: l_chipList)
+ {
+ // Only run exp_omi_train on EXPLORER OCMB targets. This step
+ // cannot run on GEMINI targets.
+ uint32_t chipId = l_ocmb->getAttr< TARGETING::ATTR_CHIP_ID>();
+ if (chipId == POWER_CHIPID::EXPLORER_16)
+ {
+ fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> l_ocmb_target( l_ocmb );
+ FAPI_INVOKE_HWP(l_err, exp_omi_train_check, l_ocmb_target );
+
+ // process return code.
+ if ( l_err )
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "ERROR 0x%.8X: exp_omi_train_check HWP on target HUID %.8x",
+ l_err->reasonCode(), TARGETING::get_huid(l_ocmb) );
+
+ // capture the target data in the elog
+ ErrlUserDetailsTarget(l_ocmb).addToLog( l_err );
+
+ // Create IStep error log and cross reference to error that occurred
+ l_StepError.addErrorDetails( l_err );
+
+ // Commit Error
+ errlCommit( l_err, ISTEP_COMP_ID );
+ }
+ else
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "SUCCESS : exp_omi_train_check HWP on target HUID %.08x",
+ TARGETING::get_huid(l_ocmb));
+ }
+ }
+ else
+ {
+ // Gemini, just skip exp_omi_train_check call
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "Skipping exp_omi_train_check HWP on because target HUID 0x%.8X, chipId 0x%.4X is a Gemini OCMB",
+ TARGETING::get_huid(l_ocmb), chipId );
+ }
+ }
- // process return code.
- if ( l_err )
+ // Find omi targets
+ TARGETING::TargetHandleList l_omiTargetList;
+ getAllChiplets(l_omiTargetList, TYPE_OMI);
+
+ for (const auto & l_omi_target : l_omiTargetList)
{
- TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "ERROR 0x%.8X: p9a_omi_train_check HWP on target HUID %.8x",
- l_err->reasonCode(), TARGETING::get_huid(l_omi_target) );
+ // call the HWP with each OMI target
+ fapi2::Target<fapi2::TARGET_TYPE_OMI> l_fapi_omi_target(l_omi_target);
- // capture the target data in the elog
- ErrlUserDetailsTarget(l_omi_target).addToLog( l_err );
+ FAPI_INVOKE_HWP(l_err, p9a_omi_train_check, l_fapi_omi_target );
- // Create IStep error log and cross reference to error that occurred
- l_StepError.addErrorDetails( l_err );
+ // process return code.
+ if ( l_err )
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "ERROR 0x%.8X: p9a_omi_train_check HWP on target HUID %.8x",
+ l_err->reasonCode(), TARGETING::get_huid(l_omi_target) );
- // Commit Error
- errlCommit( l_err, ISTEP_COMP_ID );
- }
- else
- {
- TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "SUCCESS : p9a_omi_train_check HWP on target HUID %.08x",
- TARGETING::get_huid(l_omi_target));
+ // capture the target data in the elog
+ ErrlUserDetailsTarget(l_omi_target).addToLog( l_err );
+
+ // Create IStep error log and cross reference to error that occurred
+ l_StepError.addErrorDetails( l_err );
+
+ // Commit Error
+ errlCommit( l_err, ISTEP_COMP_ID );
+ }
+ else
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "SUCCESS : p9a_omi_train_check HWP on target HUID %.08x",
+ TARGETING::get_huid(l_omi_target));
+ }
}
}
#endif
diff --git a/src/usr/isteps/istep12/call_dmi_pre_trainadv.C b/src/usr/isteps/istep12/call_dmi_pre_trainadv.C
index da8a9bb96..09aa8a81f 100644
--- a/src/usr/isteps/istep12/call_dmi_pre_trainadv.C
+++ b/src/usr/isteps/istep12/call_dmi_pre_trainadv.C
@@ -26,12 +26,12 @@
#include <trace/interface.H>
#include <initservice/taskargs.H>
+#include <initservice/isteps_trace.H>
#include <errl/errlentry.H>
-
-#include <isteps/hwpisteperror.H>
#include <errl/errludtarget.H>
-
-#include <initservice/isteps_trace.H>
+#include <isteps/hwpisteperror.H>
+#include <util/misc.H>
+#include <util/utilmbox_scratch.H>
// targeting support.
#include <targeting/common/commontargeting.H>
@@ -41,11 +41,13 @@
#include <config.h>
#include <fapi2.H>
#include <fapi2/plat_hwp_invoker.H>
-#include <util/utilmbox_scratch.H>
+
//HWP
#include <p9_io_dmi_pre_trainadv.H>
#ifdef CONFIG_AXONE
+#include <exp_omi_setup.H>
+#include <p9a_omi_setup.H>
#include <p9a_omi_train.H>
#endif
@@ -128,45 +130,81 @@ void* call_dmi_pre_trainadv (void *io_pArgs)
}
#ifdef CONFIG_AXONE
- TARGETING::TargetHandleList l_omiTargetList;
- getAllChiplets(l_omiTargetList, TYPE_OMI);
-
- TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_pre_trainadv: %d OMIs found",
- l_omiTargetList.size());
- for (const auto & l_omi_target : l_omiTargetList)
- {
- TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "p9a_omi_train HWP target HUID %.8x",
- TARGETING::get_huid(l_omi_target));
+ TARGETING::TargetHandleList l_ocmbTargetList;
+ getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP);
- // call the HWP with each OMI target
- fapi2::Target<fapi2::TARGET_TYPE_OMI> l_fapi_omi_target(l_omi_target);
+ for (const auto & l_ocmb_target : l_ocmbTargetList)
+ {
+ // call the HWP with each target
+ fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> l_fapi_ocmb_target
+ (l_ocmb_target);
- FAPI_INVOKE_HWP(l_err, p9a_omi_train , l_fapi_omi_target );
- // process return code.
- if ( l_err )
- {
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "ERROR 0x%.8X: p9a_omi_train HWP on target HUID %.8x",
- l_err->reasonCode(), TARGETING::get_huid(l_omi_target) );
+ "exp_omi_setup HWP target HUID 0x%.08x",
+ TARGETING::get_huid(l_ocmb_target));
+
+ FAPI_INVOKE_HWP(l_err, exp_omi_setup, l_fapi_ocmb_target);
+
+ // process return code.
+ if ( l_err )
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "ERROR 0x%.8X: exp_omi_setup HWP on target HUID 0x%.08x",
+ l_err->reasonCode(), TARGETING::get_huid(l_ocmb_target) );
- // capture the target data in the elog
- ErrlUserDetailsTarget(l_omi_target).addToLog( l_err );
+ // capture the target data in the elog
+ ErrlUserDetailsTarget(l_ocmb_target).addToLog( l_err );
- // Create IStep error log and cross reference to error that occurred
- l_StepError.addErrorDetails( l_err );
+ // Create IStep error log and cross reference to error that occurred
+ l_StepError.addErrorDetails( l_err );
- // Commit Error
- errlCommit( l_err, ISTEP_COMP_ID );
+ // Commit Error , continue on to next OCMB
+ errlCommit( l_err, ISTEP_COMP_ID );
+ }
}
- else
+
+ TARGETING::TargetHandleList l_omiTargetList;
+ getAllChiplets(l_omiTargetList, TYPE_OMI);
+
+ TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_pre_trainadv: %d OMIs found",
+ l_omiTargetList.size());
+
+ for (const auto & l_omi_target : l_omiTargetList)
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "SUCCESS : p9a_omi_train HWP on 0x%.08X", TARGETING::get_huid(l_omi_target));
+ "p9a_omi_setup HWP target HUID %.8x",
+ TARGETING::get_huid(l_omi_target));
+
+ // call the HWP with each OMI target
+ fapi2::Target<fapi2::TARGET_TYPE_OMI> l_fapi_omi_target(l_omi_target);
+
+ FAPI_INVOKE_HWP(l_err, p9a_omi_setup , l_fapi_omi_target );
+
+ // process return code.
+ if ( l_err )
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "ERROR 0x%.8X: p9a_omi_setup HWP on target HUID %.8x",
+ l_err->reasonCode(), TARGETING::get_huid(l_omi_target) );
+
+ // capture the target data in the elog
+ ErrlUserDetailsTarget(l_omi_target).addToLog( l_err );
+
+ // Create IStep error log and cross reference to error that occurred
+ l_StepError.addErrorDetails( l_err );
+
+ // Commit Error
+ errlCommit( l_err, ISTEP_COMP_ID );
+ }
+ else
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "SUCCESS : p9a_omi_setup HWP on 0x%.08X", TARGETING::get_huid(l_omi_target));
+ }
}
- }
+
#endif
diff --git a/src/usr/isteps/istep12/call_mss_getecid.C b/src/usr/isteps/istep12/call_mss_getecid.C
index 644661946..732862d32 100644
--- a/src/usr/isteps/istep12/call_mss_getecid.C
+++ b/src/usr/isteps/istep12/call_mss_getecid.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2017 */
+/* Contributors Listed Below - COPYRIGHT 2015,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -46,7 +46,14 @@
#include <util/utilmbox_scratch.H>
//HWP
-#include <p9c_mss_get_cen_ecid.H>
+#ifndef CONFIG_AXONE
+ #include <p9c_mss_get_cen_ecid.H>
+#else
+ #include <chipids.H>
+ #include <exp_getecid.H>
+ #include <gem_getecid.H>
+#endif
+
using namespace ISTEP;
using namespace ISTEP_ERROR;
@@ -56,10 +63,39 @@ using namespace TARGETING;
namespace ISTEP_12
{
+void cumulus_mss_getecid(IStepError & io_istepError);
+void axone_mss_getecid(IStepError & io_istepError);
+
void* call_mss_getecid (void *io_pArgs)
{
IStepError l_StepError;
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_getecid entry" );
+ auto l_procModel = TARGETING::targetService().getProcessorModel();
+
+ switch (l_procModel)
+ {
+ case TARGETING::MODEL_CUMULUS:
+ cumulus_mss_getecid(l_StepError);
+ break;
+ case TARGETING::MODEL_AXONE:
+ axone_mss_getecid(l_StepError);
+ break;
+ case TARGETING::MODEL_NIMBUS:
+ default:
+ break;
+ }
+
+
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_getecid exit" );
+
+ // end task, returning any errorlogs to IStepDisp
+ return l_StepError.getErrorHandle();
+}
+
+#ifndef CONFIG_AXONE
+void cumulus_mss_getecid(IStepError & io_istepError)
+{
errlHndl_t l_err = NULL;
uint8_t l_ddr_port_status = 0;
uint8_t l_cache_enable = 0;
@@ -71,28 +107,20 @@ void* call_mss_getecid (void *io_pArgs)
{ MSS_GET_CEN_ECID_DDR_STATUS_MBA0_BAD,
MSS_GET_CEN_ECID_DDR_STATUS_MBA1_BAD };
- TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_getecid entry" );
-
// Get all Centaur targets
TARGETING::TargetHandleList l_membufTargetList;
getAllChips(l_membufTargetList, TYPE_MEMBUF);
- for (TargetHandleList::const_iterator
- l_membuf_iter = l_membufTargetList.begin();
- l_membuf_iter != l_membufTargetList.end();
- ++l_membuf_iter)
+ for ( const auto & l_membuf_target : l_membufTargetList )
{
- // make a local copy of the target for ease of use
- TARGETING::Target* l_pCentaur = *l_membuf_iter;
-
// Dump current run on target
TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
"Running p9c_mss_get_cen_ecid HWP on "
- "target HUID %.8X", TARGETING::get_huid(l_pCentaur));
+ "target HUID %.8X", TARGETING::get_huid(l_membuf_target));
// call the HWP with each target
fapi2::Target <fapi2::TARGET_TYPE_MEMBUF_CHIP> l_fapi_centaur
- (l_pCentaur);
+ (l_membuf_target);
// call the HWP with each fapi2::Target
// Note: This HWP does not actually return the entire ECID data. It
@@ -108,10 +136,10 @@ void* call_mss_getecid (void *io_pArgs)
l_err->reasonCode());
// capture the target data in the elog
- ErrlUserDetailsTarget(l_pCentaur).addToLog( l_err );
+ ErrlUserDetailsTarget(l_membuf_target).addToLog( l_err );
// Create IStep error log and cross reference error that occurred
- l_StepError.addErrorDetails( l_err );
+ io_istepError.addErrorDetails( l_err );
// Commit Error
errlCommit( l_err, HWPF_COMP_ID );
@@ -131,22 +159,14 @@ void* call_mss_getecid (void *io_pArgs)
PredicateCTM l_mba_pred(CLASS_UNIT,TYPE_MBA);
TARGETING::TargetHandleList l_mbaTargetList;
getChildChiplets(l_mbaTargetList,
- l_pCentaur,
+ l_membuf_target,
TYPE_MBA);
- uint8_t l_num_func_mbas = l_mbaTargetList.size();
-
- for (TargetHandleList::const_iterator
- l_mba_iter = l_mbaTargetList.begin();
- l_mba_iter != l_mbaTargetList.end();
- ++l_mba_iter)
+ for ( const auto & l_mba_target : l_mbaTargetList )
{
- // Make a local copy of the target for ease of use
- TARGETING::Target* l_pMBA = *l_mba_iter;
-
// Get the MBA chip unit position
ATTR_CHIP_UNIT_type l_pos =
- l_pMBA->getAttr<ATTR_CHIP_UNIT>();
+ l_mba_target->getAttr<ATTR_CHIP_UNIT>();
// Check the DDR port status to see if this MBA should be
// set to nonfunctional.
@@ -154,10 +174,9 @@ void* call_mss_getecid (void *io_pArgs)
{
// call HWAS to deconfigure this target
l_err = HWAS::theDeconfigGard().deconfigureTarget(
- *l_pMBA, HWAS::DeconfigGard::
- DECONFIGURED_BY_MEMORY_CONFIG);
- l_num_func_mbas--;
-
+ *l_mba_target,
+ HWAS::DeconfigGard::
+ DECONFIGURED_BY_MEMORY_CONFIG);
if (l_err)
{
// shouldn't happen, but if it does, stop trying to
@@ -173,7 +192,7 @@ void* call_mss_getecid (void *io_pArgs)
"ERROR: error deconfiguring MBA or Centaur");
// Create IStep error log and cross ref error that occurred
- l_StepError.addErrorDetails( l_err );
+ io_istepError.addErrorDetails( l_err );
// Commit Error
errlCommit( l_err, HWPF_COMP_ID );
@@ -212,12 +231,12 @@ void* call_mss_getecid (void *io_pArgs)
// ATTR_CEN_MSS_CACHE_ENABLE is not set as writeable in src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml
// Should we remove below code?
// Set the ATTR_CEN_MSS_CACHE_ENABLE attribute
- //l_pCentaur->setAttr<TARGETING::ATTR_CEN_MSS_CACHE_ENABLE>(
+ //l_membuf_target->setAttr<TARGETING::ATTR_CEN_MSS_CACHE_ENABLE>(
// l_cache_enable);
// Read the ATTR_CEN_MSS_CACHE_ENABLE back to pick up any override
uint8_t l_cache_enable_attr =
- l_pCentaur->getAttr<TARGETING::ATTR_CEN_MSS_CACHE_ENABLE>();
+ l_membuf_target->getAttr<TARGETING::ATTR_CEN_MSS_CACHE_ENABLE>();
if (l_cache_enable != l_cache_enable_attr)
{
@@ -237,25 +256,21 @@ void* call_mss_getecid (void *io_pArgs)
{
// Deconfigure the L4 Cache Targets (there should be 1)
TargetHandleList l_list;
- getChildChiplets(l_list, l_pCentaur, TYPE_L4, false);
+ getChildChiplets(l_list, l_membuf_target, TYPE_L4, false);
TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
"call_mss_getecid: deconfiguring %d L4s (Centaur huid: 0x%.8X)",
- l_list.size(), get_huid(l_pCentaur));
+ l_list.size(), get_huid(l_membuf_target));
- for (TargetHandleList::const_iterator
- l_l4_iter = l_list.begin();
- l_l4_iter != l_list.end();
- ++l_l4_iter)
+ for ( const auto & l_l4_target : l_list )
{
TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
"call_mss_getecid: deconfiguring L4 (huid: 0x%.8X)",
- get_huid( *l_l4_iter));
+ get_huid(l_l4_target));
l_err = HWAS::theDeconfigGard().
- deconfigureTarget(**l_l4_iter ,
- HWAS::DeconfigGard::
- DECONFIGURED_BY_MEMORY_CONFIG);
+ deconfigureTarget( *l_l4_target,
+ HWAS::DeconfigGard::DECONFIGURED_BY_MEMORY_CONFIG);
if (l_err)
{
@@ -264,7 +279,7 @@ void* call_mss_getecid (void *io_pArgs)
// Create IStep error log
// and cross reference error that occurred
- l_StepError.addErrorDetails( l_err);
+ io_istepError.addErrorDetails( l_err);
// Commit Error
errlCommit(l_err, HWPF_COMP_ID);
@@ -281,11 +296,82 @@ void* call_mss_getecid (void *io_pArgs)
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"SUCCESS : mss_get_cen_ecid HWP( )" );
}
+}
+#else
+void cumulus_mss_getecid(IStepError & io_istepError)
+{
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "Error: Trying to call 'p9c_mss_get_cen_ecid' but Cumulus code is not compiled in");
+ assert(0, "Calling wrong Model's HWPs");
+}
+#endif
- TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_getecid exit" );
+#ifdef CONFIG_AXONE
+void axone_mss_getecid(IStepError & io_istepError)
+{
+ errlHndl_t l_err = NULL;
- // end task, returning any errorlogs to IStepDisp
- return l_StepError.getErrorHandle();
-}
+ // Get all OCMB targets
+ TARGETING::TargetHandleList l_ocmbTargetList;
+ getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP);
+
+ bool isGeminiChip = false;
+ for (const auto & l_ocmb_target : l_ocmbTargetList)
+ {
+ fapi2::Target <fapi2::TARGET_TYPE_OCMB_CHIP>
+ l_fapi_ocmb_target(l_ocmb_target);
+
+ // check EXPLORER first as this is most likely the configuration
+ uint32_t chipId = l_ocmb_target->getAttr< TARGETING::ATTR_CHIP_ID>();
+ if (chipId == POWER_CHIPID::EXPLORER_16)
+ {
+ isGeminiChip = false;
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "Running exp_getecid HWP on target HUID 0x%.8X",
+ TARGETING::get_huid(l_ocmb_target) );
+ FAPI_INVOKE_HWP(l_err, exp_getecid, l_fapi_ocmb_target);
+ }
+ else
+ {
+ isGeminiChip = true;
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "Running gem_getecid HWP on target HUID 0x%.8X, chipId 0x%.4X",
+ TARGETING::get_huid(l_ocmb_target), chipId );
+ FAPI_INVOKE_HWP(l_err, gem_getecid, l_fapi_ocmb_target);
+ }
+
+ // process return code.
+ if ( l_err )
+ {
+ TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+ "ERROR 0x%.8X : %s_getecid HWP returned error",
+ l_err->reasonCode(), isGeminiChip?"gem":"exp");
+
+ // capture the target data in the elog
+ ErrlUserDetailsTarget(l_ocmb_target).addToLog(l_err);
+
+ // Create IStep error log and cross reference to error that occurred
+ io_istepError.addErrorDetails( l_err );
+ // Commit Error
+ errlCommit( l_err, HWPF_COMP_ID );
+
+ break;
+ }
+ else
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "SUCCESS running %s_getecid HWP on target HUID 0x%.8X",
+ isGeminiChip?"gem":"exp", TARGETING::get_huid(l_ocmb_target) );
+ }
+ }
+}
+#else
+void axone_mss_getecid(IStepError & io_istepError)
+{
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "Error: Trying to call 'gem_getecid' or 'exp_getecid' but Axone code is not compiled in");
+ assert(0, "Calling wrong Model's HWPs");
+}
+#endif
};
diff --git a/src/usr/isteps/istep12/call_proc_dmi_scominit.C b/src/usr/isteps/istep12/call_proc_dmi_scominit.C
index b875322b4..e0c452206 100644
--- a/src/usr/isteps/istep12/call_proc_dmi_scominit.C
+++ b/src/usr/isteps/istep12/call_proc_dmi_scominit.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2018 */
+/* Contributors Listed Below - COPYRIGHT 2015,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -46,6 +46,11 @@
// HWP
#include <p9_io_dmi_scominit.H>
+#ifdef CONFIG_AXONE
+#include <p9a_omi_setup_bars.H>
+#endif
+
+
#include <mmio/mmio.H>
using namespace ISTEP;
@@ -63,6 +68,7 @@ void* call_proc_dmi_scominit (void *io_pArgs)
TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_dmi_scominit entry" );
+#ifndef CONFIG_AXONE
TARGETING::TargetHandleList l_dmiTargetList;
getAllChiplets(l_dmiTargetList, TYPE_DMI);
@@ -105,6 +111,51 @@ void* call_proc_dmi_scominit (void *io_pArgs)
}
+#else // CONFIG_AXONE
+
+ TARGETING::TargetHandleList l_procTargetList;
+ getAllChips(l_procTargetList, TYPE_PROC);
+
+ TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_dmi_scominit: %d procs found",
+ l_procTargetList.size());
+
+ for (const auto & l_proc_target : l_procTargetList)
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "p9a_omi_setup_bars HWP target HUID %.8x",
+ TARGETING::get_huid(l_proc_target));
+
+ // call the HWP with each target
+ fapi2::Target <fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_proc_target
+ (l_proc_target);
+
+ FAPI_INVOKE_HWP(l_err, p9a_omi_setup_bars, l_fapi_proc_target);
+
+ // process return code.
+ if ( l_err )
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "ERROR 0x%.8X: p9a_omi_setup_bars HWP on target HUID %.8x",
+ l_err->reasonCode(), TARGETING::get_huid(l_proc_target) );
+
+ // capture the target data in the elog
+ ErrlUserDetailsTarget(l_proc_target).addToLog( l_err );
+
+ // Create IStep error log and cross reference to error that occurred
+ l_StepError.addErrorDetails( l_err );
+
+ // Commit Error
+ errlCommit( l_err, ISTEP_COMP_ID );
+ }
+ else
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "SUCCESS : p9a_omi_setup_bars HWP");
+ }
+
+ }
+#endif // CONFIG_AXONE
+
// map OCMBs into Hostboot memory
l_err = MMIO::mmioSetup();
if ( l_err )
diff --git a/src/usr/isteps/istep12/makefile b/src/usr/isteps/istep12/makefile
index 6e565529d..62f6d5727 100644
--- a/src/usr/isteps/istep12/makefile
+++ b/src/usr/isteps/istep12/makefile
@@ -44,6 +44,9 @@ CENT_IO_HWP_PATH = $(CENT_PROC_PATH)/hwp/io
CENT_MEM_HWP_PATH = $(CENT_PROC_PATH)/hwp/memory
CENT_INITFILE_PATH = $(CENT_PROC_PATH)/hwp/initfiles
+GEM_PROCEDURES_PATH = ${ROOTPATH}/src/import/chips/ocmb/gemini/procedures
+
+
#Add all the extra include paths
EXTRAINCDIR += ${ROOTPATH}/src/include/usr/fapi2/
EXTRAINCDIR += ${ROOTPATH}/src/import/hwpf/fapi2/include/
@@ -68,6 +71,10 @@ EXTRAINCDIR += ${P9A_MSS_HWP_PATH}
EXTRAINCDIR += ${EXPLORER_HWP_PATH}
EXTRAINCDIR += ${EXPLORER_INC_PATH}
EXTRAINCDIR += ${P9A_MSS_ACCESSOR_PATH}
+EXTRAINCDIR += ${GEM_PROCEDURES_PATH}/hwp/memory
+EXTRAINCDIR += ${GEM_PROCEDURES_PATH}/hwp/memory/lib/
+EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils
+EXTRAINCDIR += ${EXPLORER_HWP_PATH}/lib
VPATH += $(P9_NEST_HWP_PATH)
VPATH += $(P9_PERV_HWP_PATH)
@@ -121,21 +128,30 @@ include $(P9_IO_HWP_PATH)/p9_io_dmi_clear_firs.mk
include $(CENT_INITFILE_PATH)/centaur_dmi_scom.mk
include $(P9_IO_HWP_PATH)/p9_io_erepairAccessorHwpFuncs.mk
-
VPATH += $(if $(CONFIG_AXONE),${P9A_MSS_HWP_PATH},)
VPATH += $(if $(CONFIG_AXONE),${EXPLORER_HWP_PATH},)
VPATH += $(if $(CONFIG_AXONE),${EXPLORER_OMI_HWP_PATH},)
VPATH += $(if $(CONFIG_AXONE),${P9_MEMORY_HWP_PATH},)
+VPATH += $(if $(CONFIG_AXONE),${GEM_PROCEDURES_PATH}/hwp/memory,)
+
OBJS += $(if $(CONFIG_AXONE),exp_omi_utils.o,)
OBJS += $(if $(CONFIG_AXONE),exp_omi_setup.o,)
OBJS += $(if $(CONFIG_AXONE),exp_omi_train.o,)
+OBJS += $(if $(CONFIG_AXONE),p9a_omi_setup.o,)
OBJS += $(if $(CONFIG_AXONE),p9a_omi_train.o,)
OBJS += $(if $(CONFIG_AXONE),p9a_omi_train_check.o,)
+OBJS += $(if $(CONFIG_AXONE),exp_omi_train_check.o,)
OBJS += $(if $(CONFIG_AXONE),p9a_omi_setup_bars.o,)
OBJS += $(if $(CONFIG_AXONE),p9a_addr_ext.o,)
OBJS += $(if $(CONFIG_AXONE),exp_omi_init.o,)
OBJS += $(if $(CONFIG_AXONE),p9a_omi_init.o,)
OBJS += $(if $(CONFIG_AXONE),p9a_omi_init_scom.o,)
-
+OBJS += $(if $(CONFIG_AXONE),p9a_omi_io_scom.o,)
+OBJS += $(if $(CONFIG_AXONE),p9a_omic_io_scom.o,)
+OBJS += $(if $(CONFIG_AXONE),p9a_io_omi_scominit.o,)
+OBJS += $(if $(CONFIG_AXONE),p9a_io_omi_dccal.o,)
+OBJS += $(if $(CONFIG_AXONE),gem_getecid.o,)
+OBJS += $(if $(CONFIG_AXONE),exp_getecid.o,)
+OBJS += $(if $(CONFIG_AXONE),p9a_disable_ocmb_i2c.o,)
include ${ROOTPATH}/config.mk
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