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-rw-r--r--src/usr/isteps/istep07/call_mss_attr_update.C33
-rw-r--r--src/usr/isteps/istep07/call_mss_eff_config.C69
-rw-r--r--src/usr/isteps/istep07/call_mss_freq.C121
-rw-r--r--src/usr/isteps/istep07/host_mss_attr_cleanup.C9
-rw-r--r--src/usr/isteps/istep07/makefile13
5 files changed, 166 insertions, 79 deletions
diff --git a/src/usr/isteps/istep07/call_mss_attr_update.C b/src/usr/isteps/istep07/call_mss_attr_update.C
index 4e015d7b8..a9e10d040 100644
--- a/src/usr/isteps/istep07/call_mss_attr_update.C
+++ b/src/usr/isteps/istep07/call_mss_attr_update.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2018 */
+/* Contributors Listed Below - COPYRIGHT 2015,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -62,7 +62,6 @@
#include <fapi2/target.H>
#include <fapi2/plat_hwp_invoker.H>
-#include <config.h>
// HWP
#include <p9_mss_attr_update.H>
@@ -72,6 +71,9 @@
#include <isteps/mem_utils.H>
+#include <secureboot/smf_utils.H>
+#include <initservice/mboxRegs.H>
+
namespace ISTEP_07
{
@@ -307,6 +309,33 @@ errlHndl_t check_proc0_memory_config(IStepError & io_istepErr)
(l_procIds[i].proc)->getAttr<ATTR_FABRIC_CHIP_ID>());
}
+ TARGETING::Target* l_sys = nullptr;
+ TARGETING::targetService().getTopLevelTarget(l_sys);
+ assert(l_sys != nullptr, "Top level target is nullptr!");
+
+ TARGETING::ATTR_MASTER_MBOX_SCRATCH_type l_scratchRegs;
+ assert(
+ l_sys->tryGetAttr<TARGETING::ATTR_MASTER_MBOX_SCRATCH>(l_scratchRegs),
+ "failed to get MASTER_MBOX_SCRATCH");
+ INITSERVICE::SPLESS::MboxScratch6_t l_scratch6 {
+ l_scratchRegs[INITSERVICE::SPLESS::SCRATCH_6]};
+
+ // If the smfConfig bit in scratch reg6 does not match the SMF_ENABLED
+ // setting on the system, then the SBE is in disagreement with the system on
+ // whether SMF mode should be enabled. We need to force SBE update here so
+ // that the XSCOM BAR on the slave proc is set correctly before
+ // we try to perform XSCOM operations in istep10.
+ if(l_scratch6.smfConfig != SECUREBOOT::SMF::isSmfEnabled())
+ {
+ TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+ "SBE and SYS disagree on the SMF setting; SBE thinks it "
+ "should be %s, but it should actually be %s;"
+ "requesting SBE update.",
+ l_scratch6.smfConfig ? "enabled" : "disabled",
+ SECUREBOOT::SMF::isSmfEnabled() ? "enabled" : "disabled");
+ l_updateNeeded = true;
+ }
+
if(l_updateNeeded)
{
do
diff --git a/src/usr/isteps/istep07/call_mss_eff_config.C b/src/usr/isteps/istep07/call_mss_eff_config.C
index 3f9b52371..e5ac21875 100644
--- a/src/usr/isteps/istep07/call_mss_eff_config.C
+++ b/src/usr/isteps/istep07/call_mss_eff_config.C
@@ -30,46 +30,59 @@
/******************************************************************************/
// Includes
/******************************************************************************/
+
+// STD
#include <stdint.h>
+#include <stdlib.h>
#include <map>
+// Generated
+#include <attributeenums.H>
+#include <config.h>
+
+// Errors and Tracing Support
#include <trace/interface.H>
#include <initservice/taskargs.H>
+#include <initservice/isteps_trace.H>
#include <errl/errlentry.H>
-
-#include <isteps/hwpisteperror.H>
#include <errl/errludtarget.H>
+#include <isteps/hwpisteperror.H>
+#include <hbotcompid.H>
-#include <initservice/isteps_trace.H>
-
+// Pnor Support
#include <pnor/pnorif.H>
-// targeting support
+// Targeting Support
#include <targeting/common/commontargeting.H>
#include <targeting/common/utilFilter.H>
-#include <config.h>
+// Fapi Support
#include <fapi2.H>
#include <fapi2/plat_hwp_invoker.H>
-// HWP
+// Nimbus Specific HWPs
#include <p9_mss_eff_config.H>
#include <p9_mss_eff_config_thermal.H>
#include <p9_mss_eff_grouping.H>
+
+// Cumulus Specific HWPs
#include <p9c_mss_eff_config.H>
#include <p9c_mss_eff_mb_interleave.H>
#include <p9c_mss_eff_config_thermal.H>
+// Axone Specific HWPs
#ifdef CONFIG_AXONE
#include <p9a_mss_eff_config.H>
-#include <p9a_mss_eff_config_thermal.H>
+#include <exp_mss_eff_config_thermal.H>
#endif
-#include <hbotcompid.H>
+// SMF Support
+#include <secureboot/smf.H>
+// NVDIMM Support
#include <nvram/nvram_interface.H>
-#include <secureboot/smf.H>
-#include <stdlib.h>
+
+
namespace ISTEP_07
{
@@ -167,13 +180,13 @@ void* call_mss_eff_config( void *io_pArgs )
{
IStepError l_StepError;
errlHndl_t l_err = nullptr;
-#ifdef CONFIG_SECUREBOOT
+#if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE)
auto memdLoaded = false;
#endif
do {
- #ifdef CONFIG_SECUREBOOT
+ #if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE)
// MEMD used by p9_mss_eff_config HWP
l_err = loadSecureSection(PNOR::MEMD);
if (l_err)
@@ -194,14 +207,11 @@ void* call_mss_eff_config( void *io_pArgs )
TARGETING::ATTR_MODEL_type l_procModel = TARGETING::targetService().getProcessorModel();
- TARGETING::Target* l_sys = nullptr;
- targetService().getTopLevelTarget(l_sys);
- assert( l_sys != nullptr );
-
TARGETING::TargetHandleList l_membufTargetList;
TARGETING::TargetHandleList l_mcsTargetList;
TARGETING::TargetHandleList l_memportTargetList;
- std::vector<fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>> l_fapi_memport_targets;
+ std::vector<fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>> l_fapi_ocmb_targets;
+
if(l_procModel == TARGETING::MODEL_CUMULUS)
{
@@ -310,11 +320,10 @@ void* call_mss_eff_config( void *io_pArgs )
const fapi2::Target <fapi2::TARGET_TYPE_MEM_PORT> l_fapi_memport_target
(l_memport_target);
- // TODO RTC: 207850 Remove workaround setting EFF_DIMM_SIZE when MSS has code that sets this
- uint32_t l_defaultMemSize[] = {0x8, 0x0};
- FAPI_ATTR_SET(fapi2::ATTR_MEM_EFF_DIMM_SIZE, l_fapi_memport_target, l_defaultMemSize);
+ const auto l_fapi2_ocmb_target =
+ l_fapi_memport_target.getParent<fapi2::TARGET_TYPE_OCMB_CHIP>();
- l_fapi_memport_targets.push_back(l_fapi_memport_target);
+ l_fapi_ocmb_targets.push_back(l_fapi2_ocmb_target);
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"call p9a_mss_eff_config HWP on MEM_PORT HUID %.8X",
@@ -475,18 +484,18 @@ void* call_mss_eff_config( void *io_pArgs )
#ifdef CONFIG_AXONE
else if(l_procModel == TARGETING::MODEL_AXONE)
{
- if(l_fapi_memport_targets.size() > 0)
+ if(l_fapi_ocmb_targets.size() > 0)
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "call p9a_mss_eff_config_thermal HWP on %d MEM_PORT targets",
- l_fapi_memport_targets.size());
+ "call exp_mss_eff_config_thermal HWP on %d OCMB_CHIP targets",
+ l_fapi_ocmb_targets.size());
- FAPI_INVOKE_HWP(l_err, p9a_mss_eff_config_thermal, l_fapi_memport_targets);
+ FAPI_INVOKE_HWP(l_err, exp_mss_eff_config_thermal, l_fapi_ocmb_targets);
if (l_err)
{
TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
- "ERROR 0x%.8X: p9a_mss_eff_config_thermal HWP",
+ "ERROR 0x%.8X: exp_mss_eff_config_thermal HWP",
l_err->reasonCode());
// Ensure istep error created and has same plid as this error
@@ -498,13 +507,13 @@ void* call_mss_eff_config( void *io_pArgs )
else
{
TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
- "SUCCESS : p9a_mss_eff_config_thermal HWP");
+ "SUCCESS : exp_mss_eff_config_thermal HWP");
}
}
else
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "No MEM_PORT targets found, skipping p9a_mss_eff_config_thermal HWP");
+ "No OCMB_CHIP targets found, skipping exp_mss_eff_config_thermal HWP");
}
}
#endif
@@ -564,7 +573,7 @@ void* call_mss_eff_config( void *io_pArgs )
} while (0);
- #ifdef CONFIG_SECUREBOOT
+ #if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE)
if(memdLoaded)
{
l_err = unloadSecureSection(PNOR::MEMD);
diff --git a/src/usr/isteps/istep07/call_mss_freq.C b/src/usr/isteps/istep07/call_mss_freq.C
index c6e6ac038..5495526ee 100644
--- a/src/usr/isteps/istep07/call_mss_freq.C
+++ b/src/usr/isteps/istep07/call_mss_freq.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2019 */
+/* Contributors Listed Below - COPYRIGHT 2015,2020 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -78,9 +78,9 @@ using namespace TARGETING;
void* call_mss_freq( void *io_pArgs )
{
IStepError l_StepError;
- errlHndl_t l_err = NULL;
+ errlHndl_t l_err = nullptr;
- #ifdef CONFIG_SECUREBOOT
+ #if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE)
bool l_isMemdLoaded = false;
#endif
@@ -88,7 +88,7 @@ void* call_mss_freq( void *io_pArgs )
do
{
- #ifdef CONFIG_SECUREBOOT
+ #if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE)
// Load MEMD so that vpd_supported_freqs can use it.
l_err = loadSecureSection(PNOR::MEMD);
if (l_err)
@@ -197,30 +197,30 @@ void* call_mss_freq( void *io_pArgs )
#ifdef CONFIG_AXONE
else if(l_procModel == TARGETING::MODEL_AXONE)
{
- TARGETING::TargetHandleList l_memportTargetList;
- getAllChiplets(l_memportTargetList, TYPE_MEM_PORT);
+ TARGETING::TargetHandleList l_procTargList;
+ getAllChips(l_procTargList, TYPE_PROC);
- for (const auto & l_memport_target : l_memportTargetList)
+ for (const auto & l_proc_target : l_procTargList)
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"p9a_mss_freq HWP target HUID %.8x",
- TARGETING::get_huid(l_memport_target));
+ TARGETING::get_huid(l_proc_target));
// call the HWP with each target ( if parallel, spin off a task )
- fapi2::Target <fapi2::TARGET_TYPE_MEM_PORT> l_fapi_memport_target
- (l_memport_target);
+ fapi2::Target <fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_proc_target
+ (l_proc_target);
- FAPI_INVOKE_HWP(l_err, p9a_mss_freq, l_fapi_memport_target);
+ FAPI_INVOKE_HWP(l_err, p9a_mss_freq, l_fapi_proc_target);
// process return code.
if ( l_err )
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"ERROR 0x%.8X: p9a_mss_freq HWP on target HUID %.8x",
- l_err->reasonCode(), TARGETING::get_huid(l_memport_target) );
+ l_err->reasonCode(), TARGETING::get_huid(l_proc_target) );
// capture the target data in the elog
- ErrlUserDetailsTarget(l_memport_target).addToLog( l_err );
+ ErrlUserDetailsTarget(l_proc_target).addToLog( l_err );
// Create IStep error log and cross reference to error that occurred
l_StepError.addErrorDetails( l_err );
@@ -248,13 +248,25 @@ void* call_mss_freq( void *io_pArgs )
// allow it to change here
TARGETING::Target * l_sys = nullptr;
TARGETING::targetService().getTopLevelTarget( l_sys );
- // TODO RTC: 207596 Get nest boot freq for OMIs
- #ifndef CONFIG_AXONE_BRING_UP
- uint32_t l_originalNest = Util::getBootNestFreq();
- #endif
+
+ TARGETING::ATTR_FREQ_PB_MHZ_type l_originalNestFreq = Util::getBootNestFreq();
+
+ // Omi Freq is only used in P9a and beyond, to limit #ifdef
+ // craziness below just leave it at 0 so it never changes
+ TARGETING::ATTR_FREQ_OMI_MHZ_type l_originalOmiFreq = 0;
+#ifdef CONFIG_AXONE
+ TARGETING::ATTR_OMI_PLL_VCO_type l_originalOmiVco = 0; // unused but needed for func call
+ l_err = fapi2::platAttrSvc::getOmiFreqAndVco(l_originalOmiFreq, l_originalOmiVco);
+ if(l_err)
+ {
+ l_StepError.addErrorDetails( l_err );
+ errlCommit( l_err, ISTEP_COMP_ID );
+ break;
+ }
+#endif
// Read MC_SYNC_MODE from SBE itself and set the attribute
- uint8_t l_bootSyncMode = 0;
+ TARGETING::ATTR_MC_SYNC_MODE_type l_bootSyncMode = 0;
l_err = SBE::getBootMcSyncMode( l_bootSyncMode );
if( l_err )
{
@@ -318,23 +330,23 @@ void* call_mss_freq( void *io_pArgs )
#ifdef CONFIG_AXONE
else if(l_procModel == TARGETING::MODEL_AXONE)
{
- TARGETING::TargetHandleList l_mcTargetList;
- getAllChiplets(l_mcTargetList, TYPE_MC);
- for (const auto & l_mc_target : l_mcTargetList)
+ TARGETING::TargetHandleList l_procTargetList;
+ getAllChips(l_procTargetList, TYPE_PROC);
+ for (const auto & l_proc_target : l_procTargetList)
{
// call the HWP with each target ( if parallel, spin off a task )
- fapi2::Target <fapi2::TARGET_TYPE_MC> l_fapi_mc_target(l_mc_target);
+ fapi2::Target <fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_proc_target(l_proc_target);
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "START : running p9a_mss_freq_system HWP on target 0x%.08X", TARGETING::get_huid(l_mc_target));;
+ "START : running p9a_mss_freq_system HWP on target 0x%.08X", TARGETING::get_huid(l_proc_target));;
- FAPI_INVOKE_HWP(l_err, p9a_mss_freq_system, l_fapi_mc_target);
+ FAPI_INVOKE_HWP(l_err, p9a_mss_freq_system, l_proc_target);
// process return code.
if ( l_err )
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "ERROR: p9a_mss_freq_system HWP while running on mc target 0x%.08X", TARGETING::get_huid(l_mc_target));;
+ "ERROR: p9a_mss_freq_system HWP while running on mc target 0x%.08X", TARGETING::get_huid(l_proc_target));;
- ERRORLOG::ErrlUserDetailsTarget(l_mc_target).addToLog(l_err);
+ ERRORLOG::ErrlUserDetailsTarget(l_proc_target).addToLog(l_err);
// Create IStep error log and cross reference to error that occurred
l_StepError.addErrorDetails( l_err );
@@ -345,7 +357,7 @@ void* call_mss_freq( void *io_pArgs )
else
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "SUCCESS : p9a_mss_freq_system HWP on target 0x%.08X", TARGETING::get_huid(l_mc_target));;
+ "SUCCESS : p9a_mss_freq_system HWP on target 0x%.08X", TARGETING::get_huid(l_proc_target));;
}
}
}
@@ -357,34 +369,55 @@ void* call_mss_freq( void *io_pArgs )
break;
}
- // TODO RTC: 207596 Get nest boot freq for OMIs
- #ifndef CONFIG_AXONE_BRING_UP
// Get latest MC_SYNC_MODE and FREQ_PB_MHZ
- uint8_t l_mcSyncMode = l_masterProc->getAttr<TARGETING::ATTR_MC_SYNC_MODE>();
- uint32_t l_newNest = l_sys->getAttr<TARGETING::ATTR_FREQ_PB_MHZ>();
+ TARGETING::ATTR_MC_SYNC_MODE_type l_mcSyncMode = l_masterProc->getAttr<TARGETING::ATTR_MC_SYNC_MODE>();
+ TARGETING::ATTR_FREQ_OMI_MHZ_type l_newOmiFreq = 0;
+ TARGETING::ATTR_FREQ_PB_MHZ_type l_newNestFreq = l_sys->getAttr<TARGETING::ATTR_FREQ_PB_MHZ>();
+#ifdef CONFIG_AXONE
+ TARGETING::ATTR_OMI_PLL_VCO_type l_newOmiVco = 0; // unused but needed for func call
+ l_err = fapi2::platAttrSvc::getOmiFreqAndVco(l_newOmiFreq, l_newOmiVco);
+ if(l_err)
+ {
+ l_StepError.addErrorDetails( l_err );
+ errlCommit( l_err, ISTEP_COMP_ID );
+ break;
+ }
+#endif
//Trigger sbe update if the nest frequency changed.
- if( (l_newNest != l_originalNest) || (l_mcSyncMode != l_bootSyncMode) )
+ if( (l_newNestFreq != l_originalNestFreq)
+ || (l_mcSyncMode != l_bootSyncMode)
+ || (l_newOmiFreq != l_originalOmiFreq)
+ )
{
TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
"The nest frequency or sync mode changed!"
" Original Nest: %d New Nest: %d"
- " Original syncMode: %d New syncMode: %d",
- l_originalNest, l_newNest, l_bootSyncMode, l_mcSyncMode );
+ " Original syncMode: %d New syncMode: %d"
+ " Original Omi : %d New Omi : %d"
+ , l_originalNestFreq, l_newNestFreq, l_bootSyncMode, l_mcSyncMode
+ , l_originalOmiFreq, l_newOmiFreq
+ );
if(l_sys->getAttr<TARGETING::ATTR_IS_MPIPL_HB>() == true)
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"Error: SBE update detected in MPIPL");
+ // It is highly unlikely nest frequency will change
+ // in Axone systems but OMI freq might. Its is impossible
+ // for OMI freq to change in Nimbus/Cumulus systems. So
+ // we will display Nest freq in error for Nimbus/Cumulus and
+ // display OMI freq for Axone.
+
/*@
* @errortype
* @moduleid MOD_SBE_PERFORM_UPDATE_CHECK
* @reasoncode RC_SBE_UPDATE_IN_MPIPL
* @userdata1[0:31] original mc sync mode
* @userdata1[32:63] new mc sync mode
- * @userdata2[0:31] original nest frequency
- * @userdata2[32:63] new nest frequency
+ * @userdata2[0:31] original (nest p9 | omi p9a+) frequency
+ * @userdata2[32:63] new (nest p9 | omi p9a+) frequency
* @devdesc SBE cannot be reset during MPIPL
* @custdesc Illegal action during boot
*/
@@ -394,8 +427,16 @@ void* call_mss_freq( void *io_pArgs )
TWO_UINT32_TO_UINT64(
TO_UINT32(l_bootSyncMode),
TO_UINT32(l_mcSyncMode)),
+#ifndef CONFIG_AXONE
+ TWO_UINT32_TO_UINT64(
+ l_originalNestFreq,
+ l_newNestFreq));
+#else
TWO_UINT32_TO_UINT64(
- l_originalNest, l_newNest));
+ l_originalOmiFreq,
+ l_newOmiFreq));
+#endif
+ l_err->collectTrace("ISTEPS_TRACE");
l_StepError.addErrorDetails( l_err );
errlCommit( l_err, ISTEP_COMP_ID );
@@ -403,8 +444,9 @@ void* call_mss_freq( void *io_pArgs )
else
{
TARGETING::setFrequencyAttributes(l_sys,
- l_newNest);
+ l_newNestFreq);
l_err = SBE::updateProcessorSbeSeeproms();
+
if( l_err )
{
TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
@@ -419,11 +461,10 @@ void* call_mss_freq( void *io_pArgs )
}
}
}
- #endif
} while(0);
- #ifdef CONFIG_SECUREBOOT
+ #if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE)
if(l_isMemdLoaded)
{
// Should not have any uncommitted errors at this point.
diff --git a/src/usr/isteps/istep07/host_mss_attr_cleanup.C b/src/usr/isteps/istep07/host_mss_attr_cleanup.C
index ed1cbc25a..4456018ae 100644
--- a/src/usr/isteps/istep07/host_mss_attr_cleanup.C
+++ b/src/usr/isteps/istep07/host_mss_attr_cleanup.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2016,2018 */
+/* Contributors Listed Below - COPYRIGHT 2016,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -56,7 +56,6 @@
#include <fapi2/target.H>
#include <fapi2/plat_hwp_invoker.H>
-#include <config.h>
// HWP
#include <p9c_mss_attr_cleanup.H>
@@ -75,7 +74,6 @@ using namespace TARGETING;
void* host_mss_attr_cleanup( void *io_pArgs )
{
IStepError l_StepError;
- errlHndl_t l_err = NULL;
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "host_mss_attr_cleanup entry");
// errlHndl_t l_err = NULL;
@@ -98,7 +96,9 @@ void* host_mss_attr_cleanup( void *io_pArgs )
l_pTopLevel->setAttr<TARGETING::ATTR_MRW_HW_MIRRORING_ENABLE>
(fapi2::ENUM_ATTR_MRW_HW_MIRRORING_ENABLE_FALSE);
}
-
+ // TODO RTC 198112 Memory Reconfig Loop for Axone
+ #ifndef CONFIG_AXONE
+ errlHndl_t l_err = nullptr;
TargetHandleList l_funcDimmList;
// Get all the functional Dimms
TARGETING::getAllLogicalCards(l_funcDimmList, TYPE_DIMM, true);
@@ -123,6 +123,7 @@ void* host_mss_attr_cleanup( void *io_pArgs )
}
}
+ #endif
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "host_mss_attr_cleanup exit" );
diff --git a/src/usr/isteps/istep07/makefile b/src/usr/isteps/istep07/makefile
index c9dfba28a..3befa6684 100644
--- a/src/usr/isteps/istep07/makefile
+++ b/src/usr/isteps/istep07/makefile
@@ -31,6 +31,7 @@ HWP_PATH_P9 += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/memory
HWP_PATH_CEN += ${ROOTPATH}/src/import/chips/centaur/procedures/hwp/memory
# Axone
HWP_PATH_P9A += ${ROOTPATH}/src/import/chips/p9a/procedures/hwp/memory
+HWP_PATH_P9A += ${ROOTPATH}/src/import/chips/ocmb/common/procedures/hwp/pmic
# Explorer
HWP_PATH_EXP += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory
@@ -71,14 +72,19 @@ EXTRAINCDIR += ${HWP_PATH_CEN}/lib/
EXTRAINCDIR += ${HWP_PATH_CEN}/lib/shared/
EXTRAINCDIR += ${HWP_PATH_CEN}/lib/utils/
EXTRAINCDIR += ${HWP_PATH_EXP}/lib/eff_config/
-EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/chips/ocmb/explorer/procedures/hwp/memory/
+EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/chips/ocmb/explorer/procedures/hwp/memory/lib/
EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/generic/memory/lib/
EXTRAINCDIR += ${EXP_COMMON_PATH}/include/
+EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/common/procedures/hwp/pmic/
+EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/common/include
+EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/chips/ocmb/common/procedures/hwp/pmic/
+EXTRAINCDIR += ${ROOTPATH}/obj/genfiles/chips/ocmb/common/procedures/hwp/pmic/lib
VPATH += ${HWP_PATH} ${HWP_PATH_P9}/lib/spd
VPATH += $(PROCEDURES_PATH)/hwp/nest ${ROOTPATH}/src/usr/fapi2
VPATH += ${PROCEDURES_PATH}/hwp/perv
VPATH += ${HWP_PATH_P9}/lib ${HWP_PATH_P9}/lib/utils ${HWP_PATH_P9}/lib/eff_config
+VPATH += ${HWP_PATH_P9A}/lib/eff_config
VPATH += ${HWP_PATH_P9}/lib/freq ${HWP_PATH_P9}/lib/dimm
VPATH += ${ROOTPATH}/src/usr/sbe
@@ -108,12 +114,13 @@ include $(HWP_PATH_CEN)/p9c_mss_bulk_pwr_throttles.mk
include $(HWP_PATH_CEN)/p9c_mss_eff_mb_interleave.mk
-# Axone only objects
+# Axone only objects
OBJS += $(if $(CONFIG_AXONE),p9a_mss_volt.o,)
OBJS += $(if $(CONFIG_AXONE),p9a_mss_freq.o,)
OBJS += $(if $(CONFIG_AXONE),p9a_mss_freq_system.o,)
OBJS += $(if $(CONFIG_AXONE),p9a_mss_eff_config.o,)
-OBJS += $(if $(CONFIG_AXONE),p9a_mss_eff_config_thermal.o,)
+OBJS += $(if $(CONFIG_AXONE),exp_mss_eff_config_thermal.o,)
+OBJS += $(if $(CONFIG_AXONE),pmic_efd_processing.o,)
#host_mss_attr_cleanup : MSS ATTR Cleanup
include $(HWP_PATH_CEN)/p9c_mss_attr_cleanup.mk
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