diff options
Diffstat (limited to 'src/usr/i2c/test')
-rw-r--r-- | src/usr/i2c/test/eecachetest.H | 121 | ||||
-rw-r--r-- | src/usr/i2c/test/makefile | 3 | ||||
-rwxr-xr-x | src/usr/i2c/test/tpmddtest.H | 36 |
3 files changed, 147 insertions, 13 deletions
diff --git a/src/usr/i2c/test/eecachetest.H b/src/usr/i2c/test/eecachetest.H new file mode 100644 index 000000000..cc5233bf6 --- /dev/null +++ b/src/usr/i2c/test/eecachetest.H @@ -0,0 +1,121 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/i2c/test/eecachetest.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2011,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef __EECACHETEST_H +#define __EECACHETEST_H + +/** + * @file eepromtest.H + * + * @brief Test cases for the eeprom cache code + */ + +#include <cxxtest/TestSuite.H> +#include "../eepromCache.H" + +extern trace_desc_t* g_trac_eeprom; + +using namespace TARGETING; +using namespace EEPROM; + +class EECACHETest: public CxxTest::TestSuite +{ + public: + + /** + * @brief Verify we can mark a cache as invalid then mark it valid again + */ + void test_invalidateCache( void ) + { + uint8_t l_numTests = 0; + uint8_t l_numFails = 0; + + TRACFCOMP( g_trac_eeprom, ENTER_MRK"test_invalidateCache" ); + + do{ + // Uncomment to verify manually + //printTableOfContents(); + + // Get a processor Target + TARGETING::TargetService& tS = TARGETING::targetService(); + TARGETING::Target* testTarget = NULL; + tS.masterProcChipTargetHandle( testTarget ); + assert(testTarget != NULL); + + // Create dummy eeprom info w/ VPD_PRIMARY set + const EEPROM_ROLE l_eepromRole = EEPROM::VPD_PRIMARY; + + eeprom_addr_t l_primaryVpdEeprom; + l_primaryVpdEeprom.eepromRole = l_eepromRole; + + eepromRecordHeader l_eepromRecordHeader_forLookup; + eepromRecordHeader * l_eepromRecordHeader_realPnor; + + buildEepromRecordHeader( testTarget, + l_primaryVpdEeprom, + l_eepromRecordHeader_forLookup); + + l_eepromRecordHeader_realPnor = reinterpret_cast<eepromRecordHeader *>(lookupEepromHeaderAddr(l_eepromRecordHeader_forLookup)); + + l_numTests++; + if(l_eepromRecordHeader_realPnor->completeRecord.cached_copy_valid != 1) + { + TS_FAIL("test_invalidateCache Master Proc VPD EECACHE is expected to be valid at start of test!"); + l_numFails++; + break; + } + + // Invalidate the cache entry + setIsValidCacheEntry(testTarget, l_eepromRole, 0); + + l_numTests++; + if(l_eepromRecordHeader_realPnor->completeRecord.cached_copy_valid != 0) + { + TS_FAIL("test_invalidateCache Master Proc VPD EECACHE is expected to be invalid after setIsValidCacheEntry(invalid) is called!"); + l_numFails++; + break; + } + + // Re-validate the cache entry + setIsValidCacheEntry(testTarget, l_eepromRole, 1); + + l_numTests++; + if(l_eepromRecordHeader_realPnor->completeRecord.cached_copy_valid != 1) + { + TS_FAIL("test_invalidateCache Master Proc VPD EECACHE is expected to be invalid after setIsValidCacheEntry(valid) is called!"); + l_numFails++; + break; + } + + // Uncomment to verify manually + // printTableOfContents(); + + }while(0); + + TRACFCOMP( g_trac_eeprom, EXIT_MRK"test_getEEPROMs numTests = %d / num fails = %d", l_numTests, l_numFails ); + } + +}; + +#endif
\ No newline at end of file diff --git a/src/usr/i2c/test/makefile b/src/usr/i2c/test/makefile index ef774e6e0..fa9cf31c0 100644 --- a/src/usr/i2c/test/makefile +++ b/src/usr/i2c/test/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2011,2015 +# Contributors Listed Below - COPYRIGHT 2011,2019 # [+] International Business Machines Corp. # # @@ -26,6 +26,7 @@ ROOTPATH = ../../../.. MODULE = testi2c TESTS = eepromddtest.H +TESTS += $(if $(CONFIG_SUPPORT_EEPROM_CACHING), eecachetest.H, ) TESTS += i2ctest.H TESTS += $(if $(CONFIG_TPMDD),tpmddtest.H,) diff --git a/src/usr/i2c/test/tpmddtest.H b/src/usr/i2c/test/tpmddtest.H index 8cd1fbc2c..0ea987949 100755 --- a/src/usr/i2c/test/tpmddtest.H +++ b/src/usr/i2c/test/tpmddtest.H @@ -111,21 +111,33 @@ class TPMDDTest: public CxxTest::TestSuite uint32_t data = 0x0; size_t dataSize = sizeof(data); + // default to most common ID + uint32_t expected_vendorID = TPMDD::TPM_VENDORID_65x; + uint8_t tpmModel = TPM_MODEL_UNDETERMINED; + TRACFCOMP( g_trac_tpmdd, "testTPMReadVendorID - Start" ); do { -#ifdef CONFIG_AXONE_BRING_UP - TRACFCOMP( g_trac_tpmdd,"Skipping test on Axone" ); - break; -#endif - // Get a TPM Target TARGETING::Target* testTarget = getTestTarget(); if (NULL == testTarget) { - continue; + break; + } + + if ( !(testTarget->tryGetAttr<ATTR_TPM_MODEL>(tpmModel)) ) + { + TS_FAIL("Unable to read ATTR_TPM_MODEL for %.8X target", + get_huid(testTarget)); + break; + } + + // This should match Axone and later systems + if (TPM_MODEL_75x == tpmModel) + { + expected_vendorID = TPMDD::TPM_VENDORID_75x; } num_ops++; @@ -144,16 +156,16 @@ class TPMDDTest: public CxxTest::TestSuite TPMDD_COMP_ID ); delete err; err = NULL; - continue; + break; } else if ((data & TPMDD::TPM_VENDORID_MASK) - // Only 65x supported in simics for now: - != TPMDD::TPM_VENDORID_65x) + != expected_vendorID) { fails++; TS_FAIL( "testTPMReadVendorID - Failed to read " - "correct vendor id ID=0x%X", data); - continue; + "correct vendor id ID=0x%X, expected 0x%X", data, + expected_vendorID); + break; } else @@ -161,7 +173,7 @@ class TPMDDTest: public CxxTest::TestSuite TRACUCOMP(g_trac_tpmdd, "testTPMReadVendorID - " "VendorID returned as expected. ID=0x%X", data); - continue; + break; } } while( 0 ); TRACFCOMP( g_trac_tpmdd, |