diff options
Diffstat (limited to 'src/usr/hwpf/hwp/memory_attributes.xml')
| -rw-r--r-- | src/usr/hwpf/hwp/memory_attributes.xml | 61 |
1 files changed, 22 insertions, 39 deletions
diff --git a/src/usr/hwpf/hwp/memory_attributes.xml b/src/usr/hwpf/hwp/memory_attributes.xml index 91851d7bf..d9d892fcd 100644 --- a/src/usr/hwpf/hwp/memory_attributes.xml +++ b/src/usr/hwpf/hwp/memory_attributes.xml @@ -21,7 +21,7 @@ <!-- --> <!-- IBM_PROLOG_END_TAG --> <attributes> -<!-- $Id: memory_attributes.xml,v 1.104 2014/01/21 16:15:37 bellows Exp $ --> +<!-- $Id: memory_attributes.xml,v 1.110 2014/02/21 16:54:50 bellows Exp $ --> <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB --> <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP --> <!-- *********************************************************************** --> @@ -1602,14 +1602,15 @@ firmware notes: none</description> <attribute> <id>ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT</id> <targetType>TARGET_TYPE_SYSTEM</targetType> - <description>This dial sets the Centaur address bits used to interleave addresses between MBA01 and MBA23. Valid values are 23 through 32. See Centaur Spec Chapter 5 for details. Used in the intifile. Will be obsolete when the MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT is set</description> + <description>This dial sets the Centaur address bits used to interleave addresses between MBA01 and MBA23. Valid values are 23 through 32. See Centaur Spec Chapter 5 for details. Used in the intifile. Will be obsolete when the MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT is set +This attribute will only be found in a Tuelta system. +</description> <valueType>uint8</valueType> <platInit/> <odmVisable/> <odmChangeable/> </attribute> -<!-- TODO: RTC 82331 - Add this attribute to the Accessor HWP <attribute> <id>ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -1619,11 +1620,13 @@ firmware notes: none</description> <odmChangeable/> <writeable/> </attribute> ---> + <attribute> <id>ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE</id> <targetType>TARGET_TYPE_SYSTEM</targetType> - <description>Value of on or off. On is 256 bit interleave. Off, the translation is on 128 bit interleave mode. See centaur workbook chapter 5. Will be obsolete when MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE is set</description> + <description>Value of on or off. On is 256 bit interleave. Off, the translation is on 128 bit interleave mode. See centaur workbook chapter 5. Will be obsolete when MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE is set. +This attribute will only be alive in the Tuelta system. +</description> <valueType>uint8</valueType> <enum>OFF = 0, ON = 1</enum> <platInit/> @@ -1631,7 +1634,6 @@ firmware notes: none</description> <odmChangeable/> </attribute> -<!-- TODO: RTC 82331 - Add this attribute to the Accessor HWP <attribute> <id>ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -1653,7 +1655,6 @@ firmware notes: none</description> <odmVisable/> <odmChangeable/> </attribute> ---> <attribute> <id>ATTR_MSS_CACHE_ENABLE</id> @@ -2518,19 +2519,6 @@ DIMM power test memory throttles for cfg_nm_m</description> <persistRuntime/> </attribute> -<!-- TODO: RTC 82331 - Add this attribute to the Accessor HWP -<attribute> - <id>ATTR_MSS_DRAM_ACTIVATE_POWER_PERCENT</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>DRAM Activation power percentage to determine the ras and cas weights for throttle controls -</description> - <valueType>uint8</valueType> - <writeable/> - <odmVisable/> - <odmChangeable/> -</attribute> ---> - <attribute> <id>ATTR_MSS_EFF_VPD_VERSION</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> @@ -2556,7 +2544,7 @@ DIMM power test memory throttles for cfg_nm_m</description> <enum>8_0G = 1, 9_6G = 2</enum> </attribute> -<!-- TODO: RTC 82331 - Add this attribute to the Accessor HWP +<!-- Not used yet <attribute> <id>ATTR_MRW_NEST_FREQUENCIES</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -2567,10 +2555,11 @@ DIMM power test memory throttles for cfg_nm_m</description> <platInit/> <enum>8_0G = 1, 9_6G = 2</enum> </attribute> +--> <attribute> <id>ATTR_MRW_STRICT_MBA_PLUG_RULE_CHECKING</id> - <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <targetType>TARGET_TYPE_SYSTEM</targetType> <description> The MRW for a system should set this to TRUE for systems that must obey plug rules. Lab environments should default this to off and allow the user to override using normal methods to test. </description> @@ -2578,22 +2567,7 @@ DIMM power test memory throttles for cfg_nm_m</description> <platInit/> <enum>FALSE = 0, TRUE = 1</enum> </attribute> ---> - -<!-- This attribute was added for defect SW244656, while the eKB version is waiting to be merged --> -<attribute> - <id>ATTR_MRW_CDIMM_MASTER_I2C_TEMP_SENSOR_ENABLE</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description>Used for Custom DIMMs to not enable the reading of the dimm temperature sensor on the master i2c bus</description> - - <valueType>uint8</valueType> - <enum>OFF = 0, ON = 1</enum> - <platInit/> - <odmVisable/> -</attribute> - -<!-- This attribute is not used in this build yet <attribute> <id>ATTR_MRW_ENHANCED_GROUPING_NO_MIRRORING</id> <targetType>TARGET_TYPE_SYSTEM</targetType> @@ -2604,8 +2578,17 @@ DIMM power test memory throttles for cfg_nm_m</description> <platInit/> <enum>FALSE = 0, TRUE = 1</enum> </attribute> - --> - + +<attribute> + <id>ATTR_MRW_CDIMM_MASTER_I2C_TEMP_SENSOR_ENABLE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Used for Custom DIMMs to not enable the reading of the dimm temperature sensor on the master i2c bus</description> + <valueType>uint8</valueType> + <enum>OFF = 0, ON = 1</enum> + <platInit/> + <odmVisable/> +</attribute> + <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB --> <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP --> </attributes> |
