diff options
16 files changed, 975 insertions, 150 deletions
diff --git a/src/include/usr/hwpf/plat/fapiPlatAttributeService.H b/src/include/usr/hwpf/plat/fapiPlatAttributeService.H index e210cfa99..4d9a8462e 100644 --- a/src/include/usr/hwpf/plat/fapiPlatAttributeService.H +++ b/src/include/usr/hwpf/plat/fapiPlatAttributeService.H @@ -794,13 +794,13 @@ fapi::ReturnCode fapiPlatGetPciOscswitchConfig fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::TFAW_MIN, &(VAL), sizeof(VAL) ) #define ATTR_SPD_SDRAM_OPTIONAL_FEATURES_GETMACRO(ID, PTARGET, VAL) \ fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \ - fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::SPD_SDRAM_OPTIONAL_FEATURES, &(VAL), sizeof(VAL) ) + fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::SDRAM_OPTIONAL_FEATURES, &(VAL), sizeof(VAL) ) #define ATTR_SPD_SDRAM_THERMAL_AND_REFRESH_OPTIONS_GETMACRO(ID, PTARGET, VAL ) \ fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \ - fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::SPD_SDRAM_THERMAL_REFRESH_OPTIONS, &(VAL), sizeof(VAL) ) + fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::SDRAM_THERMAL_REFRESH_OPTIONS, &(VAL), sizeof(VAL) ) #define ATTR_SPD_MODULE_THERMAL_SENSOR_GETMACRO(ID, PTARGET, VAL) \ fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \ - fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::SPD_MODULE_THERMAL_SENSOR, &(VAL), sizeof(VAL) ) + fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::MODULE_THERMAL_SENSOR, &(VAL), sizeof(VAL) ) #define ATTR_SPD_SDRAM_DEVICE_TYPE_GETMACRO(ID, PTARGET, VAL) \ fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \ fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::SDRAM_DEVICE_TYPE, &(VAL), sizeof(VAL) ) diff --git a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile index 9bc5aa1bb..1d6fc95c0 100644 --- a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile +++ b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile @@ -1,8 +1,14 @@ -#-- $Id: mbs_def.initfile,v 1.40 2013/11/21 19:21:50 yctschan Exp $ +#-- $Id: mbs_def.initfile,v 1.45 2014/02/24 22:12:25 yctschan Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.45 |tschang | 2/24/14| fixed MBA1 only cfg +#-- 1.44 |tschang | 2/17/14| bit 12 of MBAXCR23Q should be the same as MBAXCR01Q +#-- 1.43 |tschang | 2/07/14| HW246685 - RCE reported even if we also have chip marks or symbol marks in place +#-- 1.42 |tschang |01/30/14| Removed CDIMM TYPE and replace with custom dimm +#-- 1.41 |tschang |01/24/13| SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT changed to ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT +#-- SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE changed to ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE #-- 1.40 |tschang |11/21/13| HW271989 - updated SCOM write to do a full 64 bit write instead of a RMW #-- 1.39 |tschang |11/12/13| no functional changes - clean up unused variables #-- 1.38 |tschang |10/30/13| hash mode update for other IBM types @@ -102,11 +108,11 @@ define def_mba23_nomem = ((MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] == 0b # MBA0 (mba01) define def_mba01_1a_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); # DDR3/4 are same define def_mba01_1a_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2));# || (def_mba01_1b_cdimm)); # DDR3/4 are same -#define def_mba01_1a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as 1a_1socket RDIMM +#define def_mba01_1a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as 1a_1socket RDIMM define def_mba01_1b_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 2 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_mba01_1b_2socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 2 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_1c_cdimm)); -#define def_mba01_1b_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 2 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type1A 2 socket RDIMM cfg for DDR3/4 +#define def_mba01_1b_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 2 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type1A 2 socket RDIMM cfg for DDR3/4 ## 1C 1 and 2 sockets not supported #define def_mba01_1c_1socket = 0; @@ -115,7 +121,7 @@ define def_mba01_1b_2socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 2 ))) #define def_mba01_1c_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false define def_mba01_1c_1socket = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 3 ) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || def_mba01_1d_1socket; define def_mba01_1c_2socket = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 3 ) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || def_mba01_1d_2socket; -define def_mba01_1c_cdimm = (((MBA0.ATTR_EFF_IBM_TYPE[1][0] == 3 ) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 3 )) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type1B 2 socket RDIMM cfg for DDR3/4 +define def_mba01_1c_cdimm = (((MBA0.ATTR_EFF_IBM_TYPE[1][0] == 3 ) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 3 )) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type1B 2 socket RDIMM cfg for DDR3/4 ## Current they is no 1D IBM type in the attribute #define def_mba01_1d_1socket = 0; @@ -128,50 +134,50 @@ define def_mba01_1d_2socket = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4 ) && (MB ## note the CDIMMs 2A-2C CDIMMs are wired just like the single slot ISDIMMs define def_mba01_2a_1socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2a_cdimm)); define def_mba01_2a_2socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_2c_cdimm) || (def_mba01_3a_cdimm)); -define def_mba01_2a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 1 socket cfg +define def_mba01_2a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 1 socket cfg define def_mba01_2a_1socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2a_ddr4_cdimm)); define def_mba01_2a_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_3a_ddr4_cdimm)); -define def_mba01_2a_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 1 socket DDR4 cfg +define def_mba01_2a_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 1 socket DDR4 cfg define def_mba01_2b_1socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2b_cdimm)); define def_mba01_2b_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); -define def_mba01_2b_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 1 socket cfg +define def_mba01_2b_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 1 socket cfg define def_mba01_2b_1socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2b_ddr4_cdimm)); define def_mba01_2b_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_3b_ddr4_cdimm)); -define def_mba01_2b_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 1 socket DDR4 cfg +define def_mba01_2b_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 1 socket DDR4 cfg # centuar spec only has DDR4 for 2C cfg define def_mba01_2c_1socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2a_cdimm)); define def_mba01_2c_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); -define def_mba01_2c_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 1 socket cfg +define def_mba01_2c_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 1 socket cfg define def_mba01_2c_1socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2a_ddr4_cdimm)); define def_mba01_2c_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_3c_ddr4_cdimm)); -define def_mba01_2c_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 1 socket DDR4 cfg +define def_mba01_2c_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 1 socket DDR4 cfg define def_mba01_3a_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_mba01_3a_2socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_4a_cdimm)); -#define def_mba01_3a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 2 socket cfg -define def_mba01_3a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0) && (MBA0.ATTR_EFF_DRAM_GEN == 1)); # same as type2A 2 socket DDR4 cfg +#define def_mba01_3a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 2 socket cfg +define def_mba01_3a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1))) && (MBA0.ATTR_EFF_DRAM_GEN == 1)); # same as type2A 2 socket DDR4 cfg define def_mba01_3a_1socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_mba01_3a_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_4a_ddr4_cdimm)); -define def_mba01_3a_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0) && (MBA0.ATTR_EFF_DRAM_GEN == 2)); # same as type2A 2 socket DDR4 cfg +define def_mba01_3a_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1))) && (MBA0.ATTR_EFF_DRAM_GEN == 2)); # same as type2A 2 socket DDR4 cfg define def_mba01_3b_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_mba01_3b_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); -define def_mba01_3b_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 2 socket DDR4 cfg -define def_mba01_3b_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 2 socket DDR4 cfg ?? +define def_mba01_3b_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 2 socket DDR4 cfg +define def_mba01_3b_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 2 socket DDR4 cfg ?? define def_mba01_3c_1socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_mba01_3c_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_4c_ddr4_cdimm)); -define def_mba01_3c_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 2 socket DDR4 cfg -define def_mba01_3c_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 2 socket DDR4 cfg +define def_mba01_3c_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 2 socket DDR4 cfg +define def_mba01_3c_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 2 socket DDR4 cfg -define def_mba01_4a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 11))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type3A 2 socket cfg -define def_mba01_4a_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 11))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type3A 2 socket DDR4 cfg +define def_mba01_4a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 11))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3A 2 socket cfg +define def_mba01_4a_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 11))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3A 2 socket DDR4 cfg -define def_mba01_4b_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 12))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type3B 2 socket DDR4 cfg +define def_mba01_4b_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 12))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3B 2 socket DDR4 cfg -define def_mba01_4c_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 13))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type3C 2 socket DDR4 cfg +define def_mba01_4c_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 13))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3C 2 socket DDR4 cfg define def_mba01_5b_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 15))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); define def_mba01_5b_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 15))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); @@ -200,11 +206,11 @@ define def_mba01_7c_2socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 23))) & # MBA1 (mba23) define def_mba23_1a_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); # DDR3/4 are same define def_mba23_1a_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2));# || (def_mba23_1b_cdimm)); # DDR3/4 are same -#define def_mba23_1a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as 1a_1socket RDIMM +#define def_mba23_1a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as 1a_1socket RDIMM define def_mba23_1b_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_mba23_1b_2socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_1c_cdimm)); -#define def_mba23_1b_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type1A 2 socket RDIMM cfg for DDR3/4 +#define def_mba23_1b_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type1A 2 socket RDIMM cfg for DDR3/4 ## 1C 1 and 2 sockets not supported #define def_mba23_1c_1socket = 0; @@ -213,7 +219,7 @@ define def_mba23_1b_2socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2 ))) #define def_mba23_1c_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false define def_mba23_1c_1socket = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 3 ) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || def_mba23_1d_1socket; define def_mba23_1c_2socket = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 3 ) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || def_mba23_1d_2socket; -define def_mba23_1c_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 3 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type1B 2 socket RDIMM cfg for DDR3/4 +define def_mba23_1c_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 3 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type1B 2 socket RDIMM cfg for DDR3/4 ## Current they is no 1D IBM type in the attribute #define def_mba23_1d_1socket = 0; @@ -226,50 +232,50 @@ define def_mba23_1d_2socket = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4 ) && (MB ## note the CDIMMs 2A-2C CDIMMs are wired just like the single slot ISDIMMs define def_mba23_2a_1socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2a_cdimm)); define def_mba23_2a_2socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_2c_cdimm) || (def_mba23_3a_cdimm)); -define def_mba23_2a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 1 socket cfg +define def_mba23_2a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 1 socket cfg define def_mba23_2a_1socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2a_ddr4_cdimm)); define def_mba23_2a_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_3a_ddr4_cdimm)); -define def_mba23_2a_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 1 socket DDR4 cfg +define def_mba23_2a_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 1 socket DDR4 cfg define def_mba23_2b_1socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2b_cdimm)); define def_mba23_2b_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); -define def_mba23_2b_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 1 socket cfg +define def_mba23_2b_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 1 socket cfg define def_mba23_2b_1socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2b_ddr4_cdimm)); define def_mba23_2b_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_3b_ddr4_cdimm)); -define def_mba23_2b_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 1 socket DDR4 cfg +define def_mba23_2b_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 1 socket DDR4 cfg # centuar spec only has DDR4 for 2C cfg define def_mba23_2c_1socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2a_cdimm)); define def_mba23_2c_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); -define def_mba23_2c_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 1 socket cfg +define def_mba23_2c_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 1 socket cfg define def_mba23_2c_1socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2a_ddr4_cdimm)); define def_mba23_2c_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_3c_ddr4_cdimm)); -define def_mba23_2c_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 1 socket DDR4 cfg +define def_mba23_2c_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 1 socket DDR4 cfg define def_mba23_3a_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_mba23_3a_2socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_4a_cdimm)); -#define def_mba23_3a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 2 socket cfg -define def_mba23_3a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0) && (MBA1.ATTR_EFF_DRAM_GEN == 1)); # same as type2A 2 socket DDR4 cfg +#define def_mba23_3a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 2 socket cfg +define def_mba23_3a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1))) && (MBA1.ATTR_EFF_DRAM_GEN == 1)); # same as type2A 2 socket DDR4 cfg define def_mba23_3a_1socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_mba23_3a_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_4a_ddr4_cdimm)); -define def_mba23_3a_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0) && (MBA1.ATTR_EFF_DRAM_GEN == 2)); # same as type2A 2 socket DDR4 cfg +define def_mba23_3a_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1))) && (MBA1.ATTR_EFF_DRAM_GEN == 2)); # same as type2A 2 socket DDR4 cfg define def_mba23_3b_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_mba23_3b_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); -define def_mba23_3b_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 2 socket DDR4 cfg -define def_mba23_3b_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 2 socket DDR4 cfg ?? +define def_mba23_3b_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 2 socket DDR4 cfg +define def_mba23_3b_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 2 socket DDR4 cfg ?? define def_mba23_3c_1socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 10))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_mba23_3c_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 10))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_4c_ddr4_cdimm)); -define def_mba23_3c_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 10))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 2 socket DDR4 cfg -define def_mba23_3c_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 10))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 2 socket DDR4 cfg +define def_mba23_3c_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 10))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 2 socket DDR4 cfg +define def_mba23_3c_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 10))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 2 socket DDR4 cfg -define def_mba23_4a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 12))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type3A 2 socket cfg -define def_mba23_4a_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 12))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type3A 2 socket DDR4 cfg +define def_mba23_4a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 12))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3A 2 socket cfg +define def_mba23_4a_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 12))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3A 2 socket DDR4 cfg -define def_mba23_4b_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 12))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type3B 2 socket DDR4 cfg +define def_mba23_4b_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 12))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3B 2 socket DDR4 cfg -define def_mba23_4c_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 13))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type3C 2 socket DDR4 cfg +define def_mba23_4c_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 13))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3C 2 socket DDR4 cfg define def_mba23_5b_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 15))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); define def_mba23_5b_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 15))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); @@ -358,23 +364,23 @@ define def_mba23_mtype_7c = (def_mba23_7c_1socket ||def_mba23_7c_2socket -define def_type1_memory_populated_behind_MBA01 = (def_mba01_mtype_1a ||def_mba01_mtype_1b ||def_mba01_mtype_1c);# ||def_mba01_mtype_1d); -define def_type2_memory_populated_behind_MBA01 = (def_mba01_mtype_2a ||def_mba01_mtype_2b ||def_mba01_mtype_2c ||def_mba01_mtype_5d); -define def_type3_memory_populated_behind_MBA01 = (def_mba01_mtype_3a ||def_mba01_mtype_3b ||def_mba01_mtype_3c); -define def_type4_memory_populated_behind_MBA01 = (def_mba01_mtype_4a ||def_mba01_mtype_4b ||def_mba01_mtype_4c); -define def_type5_memory_populated_behind_MBA01 = (def_mba01_mtype_5a ||def_mba01_mtype_5b ||def_mba01_mtype_5c); -define def_type6_memory_populated_behind_MBA01 = (def_mba01_mtype_6a ||def_mba01_mtype_6b ||def_mba01_mtype_6c); -define def_type7_memory_populated_behind_MBA01 = (def_mba01_mtype_7a ||def_mba01_mtype_7b ||def_mba01_mtype_7c); -#define def_type8_memory_populated_behind_MBA01 = (def_mba01_mtype_8a ||def_mba01_mtype_8b ||def_mba01_mtype_8c); +define def_mba01_type1_memory_populated_behind_MBA01 = (def_mba01_mtype_1a ||def_mba01_mtype_1b ||def_mba01_mtype_1c);# ||def_mba01_mtype_1d); +define def_mba01_type2_memory_populated_behind_MBA01 = (def_mba01_mtype_2a ||def_mba01_mtype_2b ||def_mba01_mtype_2c ||def_mba01_mtype_5d); +define def_mba01_type3_memory_populated_behind_MBA01 = (def_mba01_mtype_3a ||def_mba01_mtype_3b ||def_mba01_mtype_3c); +define def_mba01_type4_memory_populated_behind_MBA01 = (def_mba01_mtype_4a ||def_mba01_mtype_4b ||def_mba01_mtype_4c); +define def_mba01_type5_memory_populated_behind_MBA01 = (def_mba01_mtype_5a ||def_mba01_mtype_5b ||def_mba01_mtype_5c); +define def_mba01_type6_memory_populated_behind_MBA01 = (def_mba01_mtype_6a ||def_mba01_mtype_6b ||def_mba01_mtype_6c); +define def_mba01_type7_memory_populated_behind_MBA01 = (def_mba01_mtype_7a ||def_mba01_mtype_7b ||def_mba01_mtype_7c); +#define def_mba01_type8_memory_populated_behind_MBA01 = (def_mba01_mtype_8a ||def_mba01_mtype_8b ||def_mba01_mtype_8c); -define def_type1_memory_populated_behind_MBA23 = (def_mba23_mtype_1a ||def_mba23_mtype_1b ||def_mba23_mtype_1c);# ||def_mba23_mtype_1d); -define def_type2_memory_populated_behind_MBA23 = (def_mba23_mtype_2a ||def_mba23_mtype_2b ||def_mba23_mtype_2c ||def_mba23_mtype_5d); -define def_type3_memory_populated_behind_MBA23 = (def_mba23_mtype_3a ||def_mba23_mtype_3b ||def_mba23_mtype_3c); -define def_type4_memory_populated_behind_MBA23 = (def_mba23_mtype_4a ||def_mba23_mtype_4b ||def_mba23_mtype_4c); -define def_type5_memory_populated_behind_MBA23 = (def_mba23_mtype_5a ||def_mba23_mtype_5b ||def_mba23_mtype_5c); -define def_type6_memory_populated_behind_MBA23 = (def_mba23_mtype_6a ||def_mba23_mtype_6b ||def_mba23_mtype_6c); -define def_type7_memory_populated_behind_MBA23 = (def_mba23_mtype_7a ||def_mba23_mtype_7b ||def_mba23_mtype_7c); -#define def_type8_memory_populated_behind_MBA23 = (def_mba23_mtype_8a ||def_mba23_mtype_8b ||def_mba23_mtype_8c); +define def_mba23_type1_memory_populated_behind_MBA23 = (def_mba23_mtype_1a ||def_mba23_mtype_1b ||def_mba23_mtype_1c);# ||def_mba23_mtype_1d); +define def_mba23_type2_memory_populated_behind_MBA23 = (def_mba23_mtype_2a ||def_mba23_mtype_2b ||def_mba23_mtype_2c ||def_mba23_mtype_5d); +define def_mba23_type3_memory_populated_behind_MBA23 = (def_mba23_mtype_3a ||def_mba23_mtype_3b ||def_mba23_mtype_3c); +define def_mba23_type4_memory_populated_behind_MBA23 = (def_mba23_mtype_4a ||def_mba23_mtype_4b ||def_mba23_mtype_4c); +define def_mba23_type5_memory_populated_behind_MBA23 = (def_mba23_mtype_5a ||def_mba23_mtype_5b ||def_mba23_mtype_5c); +define def_mba23_type6_memory_populated_behind_MBA23 = (def_mba23_mtype_6a ||def_mba23_mtype_6b ||def_mba23_mtype_6c); +define def_mba23_type7_memory_populated_behind_MBA23 = (def_mba23_mtype_7a ||def_mba23_mtype_7b ||def_mba23_mtype_7c); +#define def_mba23_type8_memory_populated_behind_MBA23 = (def_mba23_mtype_8a ||def_mba23_mtype_8b ||def_mba23_mtype_8c); define def_mba01_subtype_A = (def_mba01_mtype_1a || def_mba01_mtype_2a || def_mba01_mtype_3a || def_mba01_mtype_4a || def_mba01_mtype_5a || def_mba01_mtype_6a || def_mba01_mtype_7a);# || def_mba01_mtype_8a); define def_mba01_subtype_B = (def_mba01_mtype_1b || def_mba01_mtype_2b || def_mba01_mtype_3b || def_mba01_mtype_4b || def_mba01_mtype_5b || def_mba01_mtype_6b || def_mba01_mtype_7b);# || def_mba01_mtype_8b); @@ -388,7 +394,7 @@ define def_mba23_subtype_C = (def_mba23_mtype_1c define def_mba01_Centaur_or_Planar_DIMM_with_only_DIMM_slot0_populated = (def_mba01_1a_1socket ||def_mba01_1b_1socket ||def_mba01_1c_1socket ||def_mba01_2a_1socket ||def_mba01_2a_1socket_ddr4 ||def_mba01_2b_1socket ||def_mba01_2b_1socket_ddr4 ||def_mba01_2c_1socket ||def_mba01_2c_1socket_ddr4 ||def_mba01_3a_1socket ||def_mba01_3a_1socket_ddr4 ||def_mba01_3b_1socket ||def_mba01_3c_1socket_ddr4 ||def_mba01_5b_1socket ||def_mba01_5c_1socket ||def_mba01_5d_1socket ||def_mba01_7a_1socket ||def_mba01_7b_1socket ||def_mba01_7c_1socket ||def_mba01_7a_1socket_ddr4 ||def_mba01_7b_1socket_ddr4 ||def_mba01_7c_1socket_ddr4); define def_mba01_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated = (def_mba01_1a_2socket ||def_mba01_1b_2socket ||def_mba01_1c_2socket ||def_mba01_2a_2socket ||def_mba01_2a_2socket_ddr4 ||def_mba01_2b_2socket ||def_mba01_2b_2socket_ddr4 ||def_mba01_2c_2socket ||def_mba01_2c_2socket_ddr4 ||def_mba01_3a_2socket ||def_mba01_3a_2socket_ddr4 ||def_mba01_3b_2socket ||def_mba01_3c_2socket_ddr4 ||def_mba01_5b_2socket ||def_mba01_5c_2socket ||def_mba01_5d_2socket ||def_mba01_7a_2socket ||def_mba01_7b_2socket ||def_mba01_7c_2socket ||def_mba01_7a_2socket_ddr4 ||def_mba01_7b_2socket_ddr4 ||def_mba01_7c_2socket_ddr4 ||def_mba01_1c_cdimm ||def_mba01_3a_cdimm ||def_mba01_3b_cdimm ||def_mba01_3c_cdimm ||def_mba01_3a_ddr4_cdimm ||def_mba01_3b_ddr4_cdimm ||def_mba01_3c_ddr4_cdimm ||def_mba01_4a_cdimm ||def_mba01_4a_ddr4_cdimm ||def_mba01_4b_ddr4_cdimm ||def_mba01_4c_ddr4_cdimm); -#define def_mba01_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated = (def_mba01_1a_2socket ||def_mba01_1b_2socket ||def_mba01_1c_2socket ||def_mba01_2a_2socket ||def_mba01_2a_2socket_ddr4 ||def_mba01_2b_2socket ||def_mba01_2b_2socket_ddr4 ||def_mba01_2c_2socket ||def_mba01_2c_2socket_ddr4 ||def_mba01_3a_2socket ||def_mba01_3a_2socket_ddr4 ||def_mba01_3b_2socket ||def_mba01_3c_2socket_ddr4 ||def_mba01_5b_2socket ||def_mba01_5c_2socket ||def_mba01_5d_2socket ||def_mba01_7a_2socket ||def_mba01_7b_2socket ||def_mba01_7c_2socket ||def_mba01_7a_2socket_ddr4 ||def_mba01_7b_2socket_ddr4 ||def_mba01_7c_2socket_ddr4 ||def_mba01_1b_cdimm ||def_mba01_1c_cdimm ||def_mba01_3a_cdimm ||def_mba01_3b_cdimm ||def_mba01_3c_cdimm ||def_mba01_3a_ddr4_cdimm ||def_mba01_3b_ddr4_cdimm ||def_mba01_3c_ddr4_cdimm ||def_mba01_4a_cdimm ||def_mba01_4a_ddr4_cdimm ||def_mba01_4b_ddr4_cdimm ||def_mba01_4c_ddr4_cdimm); +#define def_mba01_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated = (def_mba01_1a_2socket ||def_mba01_1b_2socket ||def_mba01_1c_2socket ||def_mba01_2a_2socket ||def_mba01_2a_2socket_ddr4 ||def_mba01_2b_2socket ||def_mba01_2b_2socket_ddr4 ||def_mba01_2c_2socket ||def_mba01_2c_2socket_ddr4 ||def_mba01_3a_2socket ||def_mba01_3a_2socket_ddr4 ||def_mba01_3b_2socket ||def_mba01_3c_2socket_ddr4 ||def_mba01_5b_2socket ||def_mba01_5c_2socket ||def_mba01_5d_2socket ||def_mba01_7a_2socket ||def_mba01_7b_2socket ||def_mba01_7c_2socket ||def_mba01_7a_2socket_ddr4 ||def_mba01_7b_2socket_ddr4 ||def_mba01_7c_2socket_ddr4 ||def_mba01_1b_cdimm ||def_mba01_1c_cdimm ||def_mba01_3a_cdimm ||def_mba01_3b_cdimm ||def_mba01_3c_cdimm ||def_mba01_3a_ddr4_cdimm ||def_mba01_3b_ddr4_cdimm ||def_mba01_3c_ddr4_cdimm ||def_mba01_4a_cdimm ||def_mba01_4a_ddr4_cdimm ||def_mba01_4b_ddr4_cdimm ||def_mba01_4c_ddr4_cdimm); define def_mba23_Centaur_or_Planar_DIMM_with_only_DIMM_slot0_populated = (def_mba23_1a_1socket ||def_mba23_1b_1socket ||def_mba23_1c_1socket ||def_mba23_2a_1socket ||def_mba23_2a_1socket_ddr4 ||def_mba23_2b_1socket ||def_mba23_2b_1socket_ddr4 ||def_mba23_2c_1socket ||def_mba23_2c_1socket_ddr4 ||def_mba23_3a_1socket ||def_mba23_3a_1socket_ddr4 ||def_mba23_3b_1socket ||def_mba23_3c_1socket_ddr4 ||def_mba23_5b_1socket ||def_mba23_5c_1socket ||def_mba23_5d_1socket ||def_mba23_7a_1socket ||def_mba23_7b_1socket ||def_mba23_7c_1socket ||def_mba23_7a_1socket_ddr4 ||def_mba23_7b_1socket_ddr4 ||def_mba23_7c_1socket_ddr4); #define def_mba23_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated = (def_mba23_1a_2socket ||def_mba23_1b_2socket ||def_mba23_1c_2socket ||def_mba23_2a_2socket ||def_mba23_2a_2socket_ddr4 ||def_mba23_2b_2socket ||def_mba23_2b_2socket_ddr4 ||def_mba23_2c_2socket ||def_mba23_2c_2socket_ddr4 ||def_mba23_3a_2socket ||def_mba23_3a_2socket_ddr4 ||def_mba23_3b_2socket ||def_mba23_3c_2socket_ddr4 ||def_mba23_5b_2socket ||def_mba23_5c_2socket ||def_mba23_5d_2socket ||def_mba23_7a_2socket ||def_mba23_7b_2socket ||def_mba23_7c_2socket ||def_mba23_7a_2socket_ddr4 ||def_mba23_7b_2socket_ddr4 ||def_mba23_7c_2socket_ddr4 ||def_mba23_1b_cdimm ||def_mba23_1c_cdimm ||def_mba23_3a_cdimm ||def_mba23_3b_cdimm ||def_mba23_3c_cdimm ||def_mba23_3a_ddr4_cdimm ||def_mba23_3b_ddr4_cdimm ||def_mba23_3c_ddr4_cdimm ||def_mba23_4a_cdimm ||def_mba23_4a_ddr4_cdimm ||def_mba23_4b_ddr4_cdimm ||def_mba23_4c_ddr4_cdimm); @@ -396,6 +402,7 @@ define def_mba23_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated = (def_mb ## Temp defines until the code adds these attributes + #--****************************************************************************** #-- MBS FIR MASK Register #--****************************************************************************** @@ -405,6 +412,37 @@ define def_mba23_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated = (def_mb # # } +#--****************************************************************************** +# HW246685 : Need RCE FIR bit if NCE/SCE/MPE/MCE on 2nd try +# - Want to be able to see RCE reported even if we also have chip marks or symbol marks in place. +# - To enable maint fix: set MBSTR(60)=1 to see the RCE in conjunction with the other errors +# - To enable mainline fix: set MBSECC(16)=1 to see the RCE in conjunction with the other errors +#--****************************************************************************** + +# MBS01_MBSTRQ + scom 0x02011655 { + bits , scom_data , ATTR_FUNCTIONAL, expr; + 60 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_RCE_WITH_OTHER_ERRORS_HW246685 == 1); # cfg_maint_rce_with_ce + } + +# MBS23_MBSTRQ + scom 0x02011755 { + bits , scom_data , ATTR_FUNCTIONAL, expr; + 60 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_RCE_WITH_OTHER_ERRORS_HW246685 == 1); # cfg_maint_rce_with_ce + } + +# MBU.MBS.ECC0.MBSECCQ + scom 0x0201144A { + bits , scom_data , ATTR_FUNCTIONAL, expr; + 16 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_RCE_WITH_OTHER_ERRORS_HW246685 == 1); # Report RCE on corrections + } + +# MBU.MBS.ECC1.MBSECCQ + scom 0x0201148A { + bits , scom_data , ATTR_FUNCTIONAL, expr; + 16 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_RCE_WITH_OTHER_ERRORS_HW246685 == 1); # Report RCE on corrections + } + #--****************************************************************************** # TRACE_TRCTRL_CONFIG Trace Control Configuration Register @@ -566,18 +604,17 @@ scom 0x0201140D { # address interleave mode scom 0x0201140A { bits, scom_data , expr; -# 0:4 , 0b10001 , any; #-MW to match dials - 0:4 , 0b00000 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 0) || (MBA0.ATTR_FUNCTIONAL == 0) || (MBA1.ATTR_FUNCTIONAL == 0); # no MBA interleave - 0:4 , 0b10000 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 23) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # - 0:4 , 0b10001 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 24) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # - 0:4 , 0b10010 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 25) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # - 0:4 , 0b10011 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 26) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # - 0:4 , 0b10100 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 27) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # - 0:4 , 0b10101 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 28) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # - 0:4 , 0b10110 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 29) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # - 0:4 , 0b10111 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 30) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # - 0:4 , 0b11000 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 31) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # - 0:4 , 0b11001 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 32) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # + 0:4 , 0b00000 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 0) || (MBA0.ATTR_FUNCTIONAL == 0) || (MBA1.ATTR_FUNCTIONAL == 0); # no MBA interleave + 0:4 , 0b10000 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 23) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # + 0:4 , 0b10001 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 24) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # + 0:4 , 0b10010 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 25) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # + 0:4 , 0b10011 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 26) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # + 0:4 , 0b10100 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 27) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # + 0:4 , 0b10101 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 28) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # + 0:4 , 0b10110 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 29) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # + 0:4 , 0b10111 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 30) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # + 0:4 , 0b11000 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 31) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # + 0:4 , 0b11001 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 32) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # 5 , 0b0 , any ; # Z mode only } @@ -614,20 +651,20 @@ define def_mba23_hash0_type1a = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1) || (MBA1.AT define def_mba23_hash2_type1b_5b = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2) || (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 15)) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] != 0) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] != 0); define def_mba23_hash1_type1b_5b = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2) || (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 15)) && ((MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] == 0) || (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] == 0)); # Type 1D/5C - simplied table to hash mode 2 for all cfgs -define def_mba23_hash2_type1d_5c = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 16)); +define def_mba23_hash2_type1d_5c = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4) || (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 16)); # Type 2A - simplied table to hash mode 1 when both dimm configured and hash mode 0 when 1 dimm is configured -define def_mba23_hash1_type2a = (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] != 0) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] != 0); -define def_mba23_hash0_type2a = (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5) && ((MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] == 0) || (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] == 0)); +define def_mba23_hash1_type2a = (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] != 0) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] != 0); +define def_mba23_hash0_type2a = (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5) && ((MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] == 0) || (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] == 0)); # Type 2B - simplied table to hash mode 0 for all cfgs -define def_mba23_hash0_type2b = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6)); +define def_mba23_hash0_type2b = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6)); # Type 3A/7A - simplied table to hash mode 1 for all cfgs -define def_mba23_hash1_type3a_7a = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 21)); +define def_mba23_hash1_type3a_7a = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8) || (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 21)); # Type 3B/7B - simplied table to hash mode 0 for all cfgs -define def_mba23_hash0_type3b_7b = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 22)); +define def_mba23_hash0_type3b_7b = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9) || (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 22)); # Type 2C - simplied table to hash mode 0 for all cfgs -define def_mba23_hash0_type2c = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7)); +define def_mba23_hash0_type2c = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7)); # Type 3C/7C - simplied table to hash mode 0 for all cfgs -define def_mba23_hash0_type3c_7c = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 23)); +define def_mba23_hash0_type3c_7c = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 10) || (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 23)); define def_mba01_hash0_sel = (def_mba01_hash0_type1a) ||(def_mba01_hash0_type2a) ||(def_mba01_hash0_type2b) ||(def_mba01_hash0_type2c) ||(def_mba01_hash0_type3b_7b) ||(def_mba01_hash0_type3c_7c) ; define def_mba01_hash1_sel = (def_mba01_hash1_type1a) ||(def_mba01_hash1_type1b_5b) ||(def_mba01_hash1_type2a) ||(def_mba01_hash1_type3a_7a) ; @@ -649,14 +686,14 @@ define def_mba23_hash2_sel = (def_mba23_hash2_type1b_5b) ||(def_mba23_hash2_type scom 0x0201140B { bits , scom_data , MBA0.ATTR_FUNCTIONAL, expr; 0:3 , 0b0000 , 1 , (def_mba01_nomem == 1); # MBAXCR01Q_MBA01_config_type D - 0:3 , 0b0001 , 1 , (def_type1_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D - 0:3 , 0b0010 , 1 , (def_type2_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D - 0:3 , 0b0011 , 1 , (def_type3_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D - 0:3 , 0b0100 , 1 , (def_type4_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D - 0:3 , 0b0101 , 1 , (def_type5_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D - 0:3 , 0b0110 , 1 , (def_type6_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D - 0:3 , 0b0111 , 1 , (def_type7_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D -# 0:3 , 0b1000 , 1 , (def_type8_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D + 0:3 , 0b0001 , 1 , (def_mba01_type1_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D + 0:3 , 0b0010 , 1 , (def_mba01_type2_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D + 0:3 , 0b0011 , 1 , (def_mba01_type3_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D + 0:3 , 0b0100 , 1 , (def_mba01_type4_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D + 0:3 , 0b0101 , 1 , (def_mba01_type5_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D + 0:3 , 0b0110 , 1 , (def_mba01_type6_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D + 0:3 , 0b0111 , 1 , (def_mba01_type7_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D +# 0:3 , 0b1000 , 1 , (def_mba01_type8_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D # 4:5 , 0b01 , 1 , any ; # temp until ibm type is fully supported # MBAXCR01Q_MBA01_config_subtype D 4:5 , 0b00 , 1 , (def_mba01_subtype_A == 1); # MBAXCR01Q_MBA01_config_subtype D 4:5 , 0b01 , 1 , (def_mba01_subtype_B == 1); # MBAXCR01Q_MBA01_config_subtype D @@ -666,8 +703,8 @@ scom 0x0201140B { 6:7 , 0b10 , 1 , (MBA0.ATTR_EFF_DRAM_DENSITY == 8); # MBAXCR01Q_MBA01_DRAM_size D 8 , 0b0 , 1 , (def_mba01_Centaur_or_Planar_DIMM_with_only_DIMM_slot0_populated == 1); # MBAXCR01Q_MBA01_Configuration D 8 , 0b1 , 1 , (def_mba01_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated == 1); # MBAXCR01Q_MBA01_Configuration D -# 8 , 0b0 , 1 , (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_CHIP_UNIT_POS == 0); # MBAXCR01Q_MBA01_Configuration D -# 8 , 0b1 , 1 , ((((MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) || (ATTR_EFF_DIMM_TYPE == 0)) && (MBA0.ATTR_CHIP_UNIT_POS == 0)) == 1); # MBAXCR01Q_MBA01_Configuration D +# 8 , 0b0 , 1 , (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1); # MBAXCR01Q_MBA01_Configuration D +# 8 , 0b1 , 1 , (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2); # MBAXCR01Q_MBA01_Configuration D 9 , 0b1 , 1 , (MBA0.ATTR_EFF_DRAM_WIDTH == 4); # MBAXCR01Q_MBA01_DRAM_Width D 9 , 0b0 , 1 , (MBA0.ATTR_EFF_DRAM_WIDTH == 8); # MBAXCR01Q_MBA01_DRAM_Width D 10:11 , 0b00 , 1 , def_mba01_hash0_sel; # MBAXCR01Q_MBA01_Hash_Mode @@ -676,8 +713,8 @@ scom 0x0201140B { # 10:11 , 0b00 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 0); # MBAXCR01Q_MBA01_Hash_Mode # 10:11 , 0b01 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 1); # MBAXCR01Q_MBA01_Hash_Mode # 10:11 , 0b10 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 2); # MBAXCR01Q_MBA01_Hash_Mode - 12 , 0b0 , 1 , ((SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 0) || ((L4.ATTR_FUNCTIONAL == 0) || (ATTR_MSS_CACHE_ENABLE == 0))); # MBAXCR01Q_MBA01_Interleave_Mode - 12 , 0b1 , 1 , ((SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 1) && ((L4.ATTR_FUNCTIONAL == 1) && (ATTR_MSS_CACHE_ENABLE != 0))); # MBAXCR01Q_MBA01_Interleave_Mod + 12 , 0b0 , 1 , ((ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE == 0) || ((L4.ATTR_FUNCTIONAL == 0) || (ATTR_MSS_CACHE_ENABLE == 0))); # MBAXCR01Q_MBA01_Interleave_Mode + 12 , 0b1 , 1 , ((ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE == 1) && ((L4.ATTR_FUNCTIONAL == 1) && (ATTR_MSS_CACHE_ENABLE != 0))); # MBAXCR01Q_MBA01_Interleave_Mod } @@ -692,14 +729,14 @@ scom 0x0201140B { scom 0x0201140C { bits , scom_data , MBA1.ATTR_FUNCTIONAL, expr; 0:3 , 0b0000 , 1 , (def_mba23_nomem == 1); # MBAXCR01Q_MBA23_config_type D - 0:3 , 0b0001 , 1 , (def_type1_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D - 0:3 , 0b0010 , 1 , (def_type2_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D - 0:3 , 0b0011 , 1 , (def_type3_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D - 0:3 , 0b0100 , 1 , (def_type4_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D - 0:3 , 0b0101 , 1 , (def_type5_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D - 0:3 , 0b0110 , 1 , (def_type6_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D - 0:3 , 0b0111 , 1 , (def_type7_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D -# 0:3 , 0b1000 , 1 , (def_type8_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D + 0:3 , 0b0001 , 1 , (def_mba23_type1_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D + 0:3 , 0b0010 , 1 , (def_mba23_type2_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D + 0:3 , 0b0011 , 1 , (def_mba23_type3_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D + 0:3 , 0b0100 , 1 , (def_mba23_type4_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D + 0:3 , 0b0101 , 1 , (def_mba23_type5_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D + 0:3 , 0b0110 , 1 , (def_mba23_type6_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D + 0:3 , 0b0111 , 1 , (def_mba23_type7_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D +# 0:3 , 0b1000 , 1 , (def_mba23_type8_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D # 4:5 , 0b01 , 1 , any ;# temp until ibm type is fully supported # MBAXCR01Q_MBA23_config_subtype D 4:5 , 0b00 , 1 , (def_mba23_subtype_A == 1); # MBAXCR01Q_MBA23_config_subtype D 4:5 , 0b01 , 1 , (def_mba23_subtype_B == 1); # MBAXCR01Q_MBA23_config_subtype D @@ -709,16 +746,16 @@ scom 0x0201140C { 6:7 , 0b10 , 1 , (MBA1.ATTR_EFF_DRAM_DENSITY == 8); # MBAXCR01Q_MBA23_DRAM_size D 8 , 0b0 , 1 , (def_mba23_Centaur_or_Planar_DIMM_with_only_DIMM_slot0_populated == 1); # MBAXCR01Q_MBA23_Configuration D 8 , 0b1 , 1 , (def_mba23_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated == 1); # MBAXCR01Q_MBA23_Configuration D -# 8 , 0b0 , 1 , (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_CHIP_UNIT_POS == 0); # MBAXCR01Q_MBA23_Configuration D -# 8 , 0b1 , 1 , ((((ATTR_EFF_NUM_DROPS_PER_PORT == 2) || (ATTR_EFF_DIMM_TYPE == 0)) && (MBA0.ATTR_CHIP_UNIT_POS == 0)) == 1); # MBAXCR01Q_MBA23_Configuration D +# 8 , 0b0 , 1 , (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1); # MBAXCR01Q_MBA23_Configuration D +# 8 , 0b1 , 1 , (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2); # MBAXCR01Q_MBA23_Configuration D 9 , 0b1 , 1 , (MBA1.ATTR_EFF_DRAM_WIDTH == 4); # MBAXCR01Q_MBA23_DRAM_Width D 9 , 0b0 , 1 , (MBA1.ATTR_EFF_DRAM_WIDTH == 8); # MBAXCR01Q_MBA23_DRAM_Width D 10:11 , 0b00 , 1 , def_mba23_hash0_sel; # MBAXCR01Q_MBA23_Hash_Mode 10:11 , 0b01 , 1 , def_mba23_hash1_sel; # MBAXCR01Q_MBA23_Hash_Mode 10:11 , 0b10 , 1 , def_mba23_hash2_sel; # MBAXCR01Q_MBA23_Hash_Mode # 12 , 0b0 , 1 , any; # -MW match dials # MBAXCR01Q_MBA23_Interleave_Mode - 12 , 0b0 , 1 , (SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 0); # MBAXCR01Q_MBA23_Interleave_Mode - 12 , 0b1 , 1 , (SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 1); # MBAXCR01Q_MBA23_Interleave_Mode + 12 , 0b0 , 1 , ((ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE == 0) || ((L4.ATTR_FUNCTIONAL == 0) || (ATTR_MSS_CACHE_ENABLE == 0))); # MBAXCR01Q_MBA23_Interleave_Mode + 12 , 0b1 , 1 , ((ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE == 1) && ((L4.ATTR_FUNCTIONAL == 1) && (ATTR_MSS_CACHE_ENABLE != 0))); # MBAXCR01Q_MBA23_Interleave_Mode } diff --git a/src/usr/hwpf/hwp/mc_config/makefile b/src/usr/hwpf/hwp/mc_config/makefile index 083d7d7c3..dfdac47e2 100644 --- a/src/usr/hwpf/hwp/mc_config/makefile +++ b/src/usr/hwpf/hwp/mc_config/makefile @@ -5,7 +5,7 @@ # # IBM CONFIDENTIAL # -# COPYRIGHT International Business Machines Corp. 2012,2013 +# COPYRIGHT International Business Machines Corp. 2012,2014 # # p1 # @@ -42,6 +42,7 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_freq EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_eff_pre_config EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_attr_cleanup +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_eff_mb_interleave OBJS = mc_config.o \ mss_volt.o \ @@ -58,7 +59,8 @@ OBJS = mc_config.o \ mss_eff_config_shmoo.o \ mss_error_support.o \ mss_eff_pre_config.o \ - mss_attr_cleanup.o + mss_attr_cleanup.o \ + mss_eff_mb_interleave.o ## NOTE: add a new directory onto the vpaths when you add a new HWP ##@ VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/??? @@ -67,5 +69,6 @@ VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_volt VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_freq VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_eff_pre_config VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_attr_cleanup +VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_eff_mb_interleave include ${ROOTPATH}/config.mk diff --git a/src/usr/hwpf/hwp/mc_config/mc_config.C b/src/usr/hwpf/hwp/mc_config/mc_config.C index 7a3308136..7f4f744b3 100644 --- a/src/usr/hwpf/hwp/mc_config/mc_config.C +++ b/src/usr/hwpf/hwp/mc_config/mc_config.C @@ -65,6 +65,7 @@ #include "mss_eff_config/mss_eff_grouping.H" #include "mss_eff_config/opt_memmap.H" #include "mss_attr_cleanup/mss_attr_cleanup.H" +#include "mss_eff_mb_interleave/mss_eff_mb_interleave.H" namespace MC_CONFIG { @@ -545,6 +546,41 @@ void* call_mss_eff_config( void *io_pArgs ) } } + // Calling mss_eff_mb_interleave + if (l_StepError.isNull()) + { + TARGETING::TargetHandleList l_membufTargetList; + getAllChips(l_membufTargetList, TYPE_MEMBUF); + for (TargetHandleList::const_iterator + l_membuf_iter = l_membufTargetList.begin(); + l_membuf_iter != l_membufTargetList.end(); + ++l_membuf_iter) + { + const TARGETING::Target* l_membuf_target = *l_membuf_iter; + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "===== Running mss_eff_mb_interleave HWP on HUID %.8X", + TARGETING::get_huid(l_membuf_target)); + fapi::Target l_membuf_fapi_target(fapi::TARGET_TYPE_MEMBUF_CHIP, + (const_cast<TARGETING::Target*>(l_membuf_target)) ); + FAPI_INVOKE_HWP(l_err, mss_eff_mb_interleave, l_membuf_fapi_target); + if (l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: mss_eff_mb_interleave HWP returns error", + l_err->reasonCode()); + ErrlUserDetailsTarget(l_membuf_target).addToLog(l_err); + l_StepError.addErrorDetails(l_err); + errlCommit(l_err, HWPF_COMP_ID); + } + else + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "Successfully ran mss_eff_mb_interleave HWP on HUID %.8X", + TARGETING::get_huid(l_membuf_target)); + } + } + } + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_eff_config exit" ); return l_StepError.getErrorHandle(); diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_mb_interleave/memory_mss_eff_mb_interleave.xml b/src/usr/hwpf/hwp/mc_config/mss_eff_mb_interleave/memory_mss_eff_mb_interleave.xml new file mode 100755 index 000000000..e535e3433 --- /dev/null +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_mb_interleave/memory_mss_eff_mb_interleave.xml @@ -0,0 +1,36 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/mc_config/mss_eff_mb_interleave/memory_mss_eff_mb_interleave.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<hwpErrors> +<!-- $Id: memory_mss_eff_mb_interleave.xml,v 1.2 2014/02/18 20:20:15 bellows Exp $ --> +<!-- For file ../../ipl/fapi/mss_mss_eff_mb_interleave.C --> +<!-- // *! OWNER NAME : Mark Bellows (bellows@us.ibm.com) --> +<!-- // *! BACKUP NAME : --> + +<hwpError> + <rc>RC_MSS_EFF_MB_INTERLEAVE_PLUG_DECONFIG_DIMM</rc> + <description>This DIMM violated a plugging rules for MBA interleaving.</description> + <deconfigure><target>DIMM</target></deconfigure> + <ffdc>CASE</ffdc> +</hwpError> + +</hwpErrors> diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_mb_interleave/mss_eff_mb_interleave.C b/src/usr/hwpf/hwp/mc_config/mss_eff_mb_interleave/mss_eff_mb_interleave.C new file mode 100755 index 000000000..a068465b0 --- /dev/null +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_mb_interleave/mss_eff_mb_interleave.C @@ -0,0 +1,527 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_mb_interleave/mss_eff_mb_interleave.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2014 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: mss_eff_mb_interleave.C,v 1.7 2014/02/26 21:47:44 thi Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_mb_interleave.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2014 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *! Licensed material - Program property of IBM +// *! Refer to copyright instructions form no. G120-2083 +// *! Created on Wed Jan 8 2014 at 07:56:26 +//------------------------------------------------------------------------------ +// *! TITLE : mss_eff_mb_interleave +// *! DESCRIPTION : Set up centaur internal interleaving (between mba's) +// *| Checks and Sets ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE +// *| ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT +// *| +// *! OWNER NAME : Bellows Mark D. (Mark D),319432 Email: bellows@us.ibm.com +// *! BACKUP NAME : Email: ______@us.ibm.com + +// *! ADDITIONAL COMMENTS : +// +//------------------------------------------------------------------------------ +// Don't forget to create CVS comments when you check in your changes! +//------------------------------------------------------------------------------ +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version:| Author: | Date: | Comment: +//---------|----------|---------|----------------------------------------------- +// 1.7 | thi |26-FEB-14| Add explanation for 1.6 in this header +// 1.6 | thi |26-FEB-14| Add rc checking for attribute get +// 1.5 | bellows |21-FEB-14| Move interleave rule checkking to system level +// 1.4 | bellows |19-FEB-14| More RAS updates +// 1.3 | bellows |17-FEB-14| Additional RAS review updates +// 1.2 | bellows |14-FEB-14| Revamped Plug checking, RAS Review pass #1 comments added +// 1.1 | bellows |08-JAN-14| Created. + +#include <mss_eff_mb_interleave.H> +#include <fapi.H> + +extern "C" { + + enum DECONFIG_TYPES { DECONFIG_PORT_1_SLOT_0_IS_EMPTY_PORT_0_SLOT_0_IS_NOT=0, + DECONFIG_PORT_1_SLOT_0_IS_NOT_EQUAL_TO_PORT_0_SLOT_0_A=1, + DECONFIG_PORT_1_SLOT_0_IS_NOT_EQUAL_TO_PORT_0_SLOT_0_B=2, + DECONFIG_PORT_0_SLOT_1_DECONFIGURED_BECAUSE_PORT_0_SLOT_0_WAS_DECONFIGURED=3, + DECONFIG_PORT_1_SLOT_1_DECONFIGURED_BECAUSE_PORT_0_SLOT_0_WAS_DECONFIGURED=4, + DECONFIG_PORT_0_SLOT_1_DECONFIGURED_BECAUSE_PORT_1_SLOT_1_IS_NOT_EQUAL=5, + DECONFIG_PORT_1_SLOT_1_DECONFIGURED_BECAUSE_PORT_0_SLOT_1_IS_NOT_EQAUL=6, + DECONFIG_PORT_0_SLOT_1_DECONFIGURED_BECAUSE_PORT_0_SLOT_0_IS_NOT_EQUAL=7, + DECONFIG_PORT_1_SLOT_1_DECONFIGURED_BECAUSE_PORT_0_SLOT_0_IS_NOT_EQUAL=8, + DECONFIG_PORT_0_SLOT_1_DECONFIGURED_BECAUSE_PORT_1_SLOT_1_IS_NOT_VALID=9, + DECONFIG_PORT_1_SLOT_1_DECONFIGURED_BECAUSE_PORT_0_SLOT_1_IS_NOT_VALID=10, + DECONFIG_PORT_1_HAS_SOMETHING_BUT_PORT_0_SLOT_0_IS_EMPTY=11, + DECONFIG_PORT_0_SLOT_1_HAS_SOMETHING_BUT_PORT_0_SLOT_0_IS_EMPTY=12, + DECONFIG_SLOT_1_HAS_SOMETHING_BUT_PORT_0_SLOT_0_IS_EMPTY=13, + DECONFIG_INTERLEAVE_MODE_CONTROL_IS_REQUIRED=99 }; + + + const uint8_t MSS_MBA_ADDR_INTERLEAVE_BIT = 24; // From Eric Retter: + // the prefetch and cleaner assume that bit 24 is the interleave bit. + // We put other interleave options in for other settings that could be + // tried in performance testing + + using namespace fapi; + + class mss_eff_mb_dimm { + public: + uint8_t module_type; + uint8_t dram_gen; + uint8_t device_density; + uint8_t num_of_ranks; + uint8_t device_width; + uint8_t module_width; + uint8_t thermal_sensor; + uint8_t size; + Target mydimm_target; + bool valid; + uint8_t side; + uint8_t port; + uint8_t slot; + + mss_eff_mb_dimm(); + ReturnCode load(fapi::Target & i_dimms, uint32_t size); + bool is_valid(); + ReturnCode deconfig(uint8_t i_case); + bool operator!=(const mss_eff_mb_dimm &) const; + }; + +//---------------------------------------------- +// MSS EFF GROUPING FUNCTIONs............ +//---------------------------------------------------- + + ReturnCode mss_eff_mb_interleave(const fapi::Target & i_cen_target) { + ReturnCode rc; + + mss_eff_mb_dimm l_dimm_array[2][2][2]; // side, port, dimm + std::vector<fapi::Target> l_target_dimm_array[2]; + std::vector<fapi::Target> l_mba_chiplets; + uint8_t mba_i; + uint8_t mba; + uint8_t l_cur_mba_port; + uint8_t l_cur_mba_dimm; + uint8_t side,port,slot; + uint8_t hadadeconfig[2]; + uint8_t l_mss_derived_mba_cacheline_interleave_mode; + uint8_t l_mss_mba_addr_interleave_bit; + uint8_t mrw_mba_cacheline_interleave_mode_control; + uint32_t size[2]; + uint8_t eff_dimm_size[2][2]; + uint8_t l_attr_mrw_strict_mba_plug_rule_checking; + uint8_t l_deconfig_0_0; + + + do { +// first step, load up the dimms connected to this centaur + for(side=0;side<2;side++) { + for(port=0;port<2;port++) { + for(slot=0;slot<2;slot++) { + l_dimm_array[side][port][slot].side = side; + l_dimm_array[side][port][slot].port = port; + l_dimm_array[side][port][slot].slot = slot; + } + } + } + + rc = fapiGetChildChiplets(i_cen_target, fapi::TARGET_TYPE_MBA_CHIPLET, l_mba_chiplets); + if(rc) { + FAPI_ERR("Error retrieving fapiGetChildChiplets"); + break; + } + + rc = FAPI_ATTR_GET(ATTR_MRW_STRICT_MBA_PLUG_RULE_CHECKING, NULL, l_attr_mrw_strict_mba_plug_rule_checking); + if(rc) + { + FAPI_ERR("Error retrieving ATTR_MRW_STRICT_MBA_PLUG_RULE_CHECKING"); + break; + } + + if(l_attr_mrw_strict_mba_plug_rule_checking == ENUM_ATTR_MRW_STRICT_MBA_PLUG_RULE_CHECKING_TRUE) { + for(mba_i=0; mba_i<l_mba_chiplets.size(); mba_i++) { + + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_mba_chiplets[mba_i], mba); + if(rc) + { + FAPI_ERR("Error retrieving ATTR_CHIP_UNIT_POS"); + break; + } + + rc = fapiGetAssociatedDimms(l_mba_chiplets[mba_i], l_target_dimm_array[mba]); + if(rc) + { + FAPI_ERR("Error retrieving assodiated dimms"); + break; + } + + for (uint8_t l_dimm_index = 0; l_dimm_index < + l_target_dimm_array[mba].size(); l_dimm_index += 1) + { + rc = FAPI_ATTR_GET(ATTR_MBA_PORT, &l_target_dimm_array[mba][l_dimm_index], + l_cur_mba_port); + if(rc) + { + FAPI_ERR("Error retrieving ATTR_MBA_PORT"); + break; + } + rc = FAPI_ATTR_GET(ATTR_MBA_DIMM, &l_target_dimm_array[mba][l_dimm_index + ], l_cur_mba_dimm); + if(rc) + { + FAPI_ERR("Error retrieving ATTR_MBA_DIMM"); + break; + } + + rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_SIZE, &l_mba_chiplets[mba_i], eff_dimm_size); + if(rc) + { + FAPI_ERR("Error retrieving ATTR_EFF_DIMM_SIZE"); + break; + } + + FAPI_INF("Loading up information about dimm for mba %d port %d dimm %d", mba, l_cur_mba_port, l_cur_mba_dimm); + + FAPI_INF("DIMM size is eff_dimm_size[%d][%d] = %d", l_cur_mba_port, l_cur_mba_dimm, eff_dimm_size[l_cur_mba_port][l_cur_mba_dimm]); + + rc = l_dimm_array[mba][l_cur_mba_port][l_cur_mba_dimm].load(l_target_dimm_array[mba][l_dimm_index], eff_dimm_size[l_cur_mba_port][l_cur_mba_dimm]); + if(rc) break; + } // Each DIMM off this MBA + if(rc) break; + } // Each MBA + if(rc) break; + +// - Logical DIMMs are considered to be identical if they have the following attributes in common: Module Type (RDIMM or LRDIMM), Architecture (DDR3 vs DDR4), Device Density, Number of Ranks, Device Width, Module Width, and Thermal Sensor. + +// Plug Rule 4.1 - Logical DIMMs have to be plugged in pairs on either Port A & B or on Port C & D. Paired DIMMs must be identical. + +// Plug Rule 4.2 - If there is a Logical DIMM plugged in Slot 1 then an identical DIMM must be plugged in Slot0 + +// Plug rules 4.1 and 4.2 define valid configurations which are: +// - DIMM type X populated in slot0 only, slot1 is not populated +// - DIMM type X populated in slot0 and slot1 + for(side=0;side<2;side++) { + hadadeconfig[side]=0; + } + + for(side=0;side<2;side++) { + hadadeconfig[side]=0; + if(l_dimm_array[side][0][0].is_valid()) { // there is a dimm on port 0, slot 0, this is a must + l_deconfig_0_0=0; + + // case 0, you don't have a pair of dimms on port 0 and port 1, kill port0,0 + if(! l_dimm_array[side][1][0].is_valid()) { + FAPI_ERR("Deconfig Rule 4.1 :Plug Rule 4.1 violated, Port 1 on Side %d slot 0 is empty Port 0 slot 0 is not",side); + rc = l_dimm_array[side][0][0].deconfig(DECONFIG_PORT_1_SLOT_0_IS_EMPTY_PORT_0_SLOT_0_IS_NOT); + fapiLogError(rc); + hadadeconfig[side]=1; + l_deconfig_0_0=1; + } + + // case 1, you did not kill dimm 0,0, so now check that 0,0 == 1,0 + if( l_deconfig_0_0 == 0 && + ( l_dimm_array[side][0][0] != l_dimm_array[side][1][0])) { + FAPI_ERR("Deconfig Rule 4.1 :Plug Rule 4.1 violated, Port 1 on Side %d slot 0 is not equal to Port 0 slot 0",side); + rc = l_dimm_array[side][0][0].deconfig(DECONFIG_PORT_1_SLOT_0_IS_NOT_EQUAL_TO_PORT_0_SLOT_0_A); + fapiLogError(rc); + rc = l_dimm_array[side][1][0].deconfig(DECONFIG_PORT_1_SLOT_0_IS_NOT_EQUAL_TO_PORT_0_SLOT_0_B); + fapiLogError(rc); + hadadeconfig[side]=1; + l_deconfig_0_0=1; + } + + // if dimm 0,0 is gone, then blow away any dimm 0,1 and 1,1 + if(l_deconfig_0_0 ) { + if(l_dimm_array[side][0][1].is_valid()) { + FAPI_ERR("Deconfig Rule 4.1 :Plug Rule 4.1 violated, Port 0 on Side %d slot 1 deconfigured because Port 0 slot 0 was deconfigured",side); + rc =l_dimm_array[side][0][1].deconfig(DECONFIG_PORT_0_SLOT_1_DECONFIGURED_BECAUSE_PORT_0_SLOT_0_WAS_DECONFIGURED); + fapiLogError(rc); + hadadeconfig[side]=1; + } + if(l_dimm_array[side][1][1].is_valid()) { + FAPI_ERR("Deconfig Rule 4.1 :Plug Rule 4.1 violated, Port 1 on Side %d slot 1 deconfigured because Port 0 slot 0 was deconfigured",side); + rc = l_dimm_array[side][1][1].deconfig(DECONFIG_PORT_1_SLOT_1_DECONFIGURED_BECAUSE_PORT_0_SLOT_0_WAS_DECONFIGURED); + fapiLogError(rc); + hadadeconfig[side]=1; + } + } + else { // you have 0,0, so check if there is a 0,1 and 1,1 and they are equal + // and 0,0 must equal 0,1, otherwise, get rid of 0,1 and 1,1 + if(l_dimm_array[side][0][1].is_valid() && l_dimm_array[side][1][1].is_valid()) { + if(l_dimm_array[side][0][1] != l_dimm_array[side][1][1]) { + FAPI_ERR("Deconfig Rule 4.1 :Plug Rule 4.1 violated, Port 0 on Side %d slot 1 deconfigured because Port 1 slot 1 is not equal",side); + rc =l_dimm_array[side][0][1].deconfig(DECONFIG_PORT_0_SLOT_1_DECONFIGURED_BECAUSE_PORT_1_SLOT_1_IS_NOT_EQUAL); + fapiLogError(rc); + FAPI_ERR("Deconfig Rule 4.1 :Plug Rule 4.1 violated, Port 1 on Side %d slot 1 deconfigured because Port 0 slot 1 is not eqaul",side); + rc =l_dimm_array[side][1][1].deconfig(DECONFIG_PORT_1_SLOT_1_DECONFIGURED_BECAUSE_PORT_0_SLOT_1_IS_NOT_EQAUL); + fapiLogError(rc); + hadadeconfig[side]=1; + } + else { + if(l_dimm_array[side][0][0] != l_dimm_array[side][0][1]) { + FAPI_ERR("Deconfig Rule 4.2 :Plug Rule 4.2 violated, Port 0 on Side %d slot 1 deconfigured because Port 0 slot 0 is not equal",side); + rc =l_dimm_array[side][0][1].deconfig(DECONFIG_PORT_0_SLOT_1_DECONFIGURED_BECAUSE_PORT_0_SLOT_0_IS_NOT_EQUAL); + fapiLogError(rc); + FAPI_ERR("Deconfig Rule 4.2 :Plug Rule 4.1 violated, Port 1 on Side %d slot 1 deconfigured because Port 0 slot 0 is not equal",side); + rc =l_dimm_array[side][1][1].deconfig(DECONFIG_PORT_1_SLOT_1_DECONFIGURED_BECAUSE_PORT_0_SLOT_0_IS_NOT_EQUAL); + fapiLogError(rc); + hadadeconfig[side]=1; + } + } + } + else { + if(l_dimm_array[side][0][1].is_valid()) { + FAPI_ERR("Deconfig Rule 4.1 :Plug Rule 4.1 violated, Port 0 on Side %d slot 1 deconfigured because Port 1 slot 1 is not valid",side); + rc =l_dimm_array[side][0][1].deconfig(DECONFIG_PORT_0_SLOT_1_DECONFIGURED_BECAUSE_PORT_1_SLOT_1_IS_NOT_VALID); + fapiLogError(rc); + } + if(l_dimm_array[side][1][1].is_valid()) { + FAPI_ERR("Deconfig Rule 4.1 :Plug Rule 4.1 violated, Port 1 on Side %d slot 1 deconfigured because Port 0 slot 1 is not valid",side); + rc = l_dimm_array[side][1][1].deconfig(DECONFIG_PORT_1_SLOT_1_DECONFIGURED_BECAUSE_PORT_0_SLOT_1_IS_NOT_VALID); + fapiLogError(rc); + hadadeconfig[side]=1; + } + + } + } + } + else { // if there is no slot 0,0, then everything else is invalid + if(l_dimm_array[side][1][0].is_valid()) { + FAPI_ERR("Deconfig Rule 4.1 :Plug Rule 4.1 violated, Port 1 on Side %d has something but Port 0 slot 0 is empty",side); + rc = l_dimm_array[side][1][0].deconfig(DECONFIG_PORT_1_HAS_SOMETHING_BUT_PORT_0_SLOT_0_IS_EMPTY); + fapiLogError(rc); + hadadeconfig[side]=1; + } + if(l_dimm_array[side][0][1].is_valid()) { // there is a dimm slot 1, but slot 0 is empty + FAPI_ERR("Deconfig Rule 4.1 :Plug Rule 4.2 violated, Port 0 on Side %d slot 1 has something but Port 0 slot 0 is empty",side); + rc = l_dimm_array[side][0][1].deconfig(DECONFIG_PORT_0_SLOT_1_HAS_SOMETHING_BUT_PORT_0_SLOT_0_IS_EMPTY); + fapiLogError(rc); + hadadeconfig[side]=1; + } + if(l_dimm_array[side][1][1].is_valid()) { // there is a dimm slot 1, but slot 0 is empty + FAPI_ERR("Deconfig Rule 4.1 :Plug Rule 4.2 violated, Port 0 on Side %d slot 1 has something but Port 0 slot 0 is empty",side); + rc = l_dimm_array[side][1][1].deconfig(DECONFIG_SLOT_1_HAS_SOMETHING_BUT_PORT_0_SLOT_0_IS_EMPTY); + fapiLogError(rc); + hadadeconfig[side]=1; + } + } + if(hadadeconfig[side]) { + FAPI_INF("There was a Deconfig on side %d due to a plug rule 4.1 and/or 4.2", side); + } + else { + FAPI_INF("No Deconfig on side %d so far", side); + } + } + +// Deconfig Rule 4.1 - When Plug rules 4.1 or 4.2 are violated all Logical DIMMs behind the MBA in violation are deconfiged. This error will be redetected on the next IPL no Persistent guard required. This rule is enforced by mss_eff_cnfg HW procedure. +// +// +// Deconfig by Association Rule 4.1 - If a logical DIMM is deconfigured; all logical DIMMs on the same MBA must also be deconfigured by association. Since MBAs with no configured DIMMs are also deconfigured this will lead to the MBA also being deconfigured. This error will be redetected on the next IPL no Persistent guard required. +// +// Deconfig by Association Rule 4.2 MBAs with no configured DIMMs are deconfigured this will lead to the MBA also being deconfigured. This error will be redetected on the next IPL no Persistent guard required. + +// for(side=0;side<2;side++) { +// if(hadadeconfig[side]) { +// for(port=0;port<2;port++) { +// for(slot=0;slot<2;slot++) { +// if(l_dimm_array[side][port][slot].is_valid()) { +// FAPI_ERR("Deconfig by Association Rule 4.1 has been called on Side %d",side); +// l_dimm_array[side][port][slot].deconfig(11); +// } +// } +// } +// FAPI_ERR("Deconfig by Association Rule 4.2 has been called on Side %d",side); +// const fapi::Target & MBA = l_mba_chiplets[side]; +// FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_MB_INTERLEAVE_PLUG_DECONFIG_MBA_BY_ASSOCIATION); +// } +// } +// } + +// Note - In an IS DIMM system that is running in interleave mode: due to the interactions between Plug rules 4.1, 4.2 and 3.3 the IS DIMM will need to be plugged in quads. This means an identical pair of a total size behind one half of a Centaur Pair and another identical pair of the same total size behind the other Centaur in the Pair. Note that the 2 pairs of DIMMs need not be identical to each other just have the same total size. + } // end of strict checking + + for(side=0;side<2;side++) { + size[side]=0; + } + + for(side=0;side<2;side++) { + for(port=0;port<2;port++) { + for(slot=0;slot<2;slot++) { + size[side]+=l_dimm_array[side][port][slot].size; + } + } + } + + FAPI_INF("Sizes on each side %d %d", size[0], size[1]); + + rc=FAPI_ATTR_GET(ATTR_MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL, NULL, mrw_mba_cacheline_interleave_mode_control); + if(rc) return rc; + + switch(mrw_mba_cacheline_interleave_mode_control) { + case ENUM_ATTR_MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL_NEVER: + l_mss_derived_mba_cacheline_interleave_mode=ENUM_ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE_OFF; + l_mss_mba_addr_interleave_bit=0; + break; + case ENUM_ATTR_MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL_REQUIRED: + if(size[0] != size[1]) { + FAPI_ERR("ATTR_MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL is REQUIRED, but size on side 0 does not match size on side 1 sizes %d %d", size[0], size[1]); + l_mss_derived_mba_cacheline_interleave_mode=ENUM_ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE_OFF; + l_mss_mba_addr_interleave_bit=0; + for(side=0;side<2;side++) { + for(port=0;port<2;port++) { + for(slot=0;slot<2;slot++) { + if(l_dimm_array[side][port][slot].is_valid()) { + FAPI_ERR("Deconfig INTERLEAVE_MODE_CONTROL is REQUIRED violated Port %d on Side %d slot %d", port, side, slot); + rc = l_dimm_array[side][port][slot].deconfig(DECONFIG_INTERLEAVE_MODE_CONTROL_IS_REQUIRED); + fapiLogError(rc); + } + } + } + } + } + else { + l_mss_derived_mba_cacheline_interleave_mode=ENUM_ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE_ON; + l_mss_mba_addr_interleave_bit=MSS_MBA_ADDR_INTERLEAVE_BIT; + } + break; + case ENUM_ATTR_MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL_REQUESTED: + if(size[0] != size[1]) { + l_mss_derived_mba_cacheline_interleave_mode=ENUM_ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE_OFF; + l_mss_mba_addr_interleave_bit=0; + } + else { + l_mss_derived_mba_cacheline_interleave_mode=ENUM_ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE_ON; + l_mss_mba_addr_interleave_bit=MSS_MBA_ADDR_INTERLEAVE_BIT; + } + break; + default: + FAPI_ERR("Internal Error: ATTR_MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL is not a known value"); + l_mss_derived_mba_cacheline_interleave_mode=ENUM_ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE_OFF; + l_mss_mba_addr_interleave_bit=0; + break; + + } + + rc=FAPI_ATTR_SET(ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE, &i_cen_target, l_mss_derived_mba_cacheline_interleave_mode); + if (rc) + { + FAPI_ERR("mss_eff_mb_interleave: Error from FAPI_ATTR_SET(ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE)"); + break; + } + + rc=FAPI_ATTR_SET(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT, &i_cen_target, l_mss_mba_addr_interleave_bit); + if (rc) + { + FAPI_ERR("mss_eff_mb_interleave: Error from FAPI_ATTR_SET(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT)"); + break; + } + + } while(0); + + return rc; + } + + // default constructor + mss_eff_mb_dimm::mss_eff_mb_dimm() { + module_type=0; + dram_gen=0; + device_density=0; + num_of_ranks=0; + device_width=0; + module_width=0; + thermal_sensor=0; + size=0; + valid=0; + } + + ReturnCode mss_eff_mb_dimm::load(fapi::Target & i_dimm, uint32_t i_size) { + ReturnCode rc; + do { + rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_TYPE, &i_dimm, module_type); + if(rc) break; + + rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_DEVICE_TYPE, &i_dimm, dram_gen); + if(rc) break; + + rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_DENSITY, &i_dimm, device_density); + if(rc) break; + + rc = FAPI_ATTR_GET(ATTR_SPD_NUM_RANKS, &i_dimm, num_of_ranks); + if(rc) break; + + rc = FAPI_ATTR_GET(ATTR_SPD_DRAM_WIDTH, &i_dimm, device_width); + if(rc) break; + + rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_MEMORY_BUS_WIDTH, &i_dimm, module_width); + if(rc) break; + + rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_THERMAL_SENSOR, &i_dimm, thermal_sensor); + if(rc) break; + + mydimm_target=i_dimm; + + size=i_size; + + if(i_size != 0) { + valid=1; + } + else { + valid = 0; + } + } + while (0); + + return rc; + } + + bool mss_eff_mb_dimm::is_valid() { + return valid; + } + + ReturnCode mss_eff_mb_dimm::deconfig(uint8_t i_case){ + ReturnCode rc; + FAPI_ERR("Deconfiguring a dimm due to a plugging rule violation at centuar/mba level case num %d (%d%d%d)", i_case, side, port, slot); + const fapi::Target & DIMM = mydimm_target; + const uint8_t CASE = i_case; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_MB_INTERLEAVE_PLUG_DECONFIG_DIMM); + valid=0; + size=0; + return rc; + } + + bool mss_eff_mb_dimm::operator!=(const mss_eff_mb_dimm &a) const { + if( module_type == a.module_type && + dram_gen == a.dram_gen && + device_density == a.device_density && + num_of_ranks == a.num_of_ranks && + device_width == a.device_width && + module_width == a.module_width && + thermal_sensor == a.thermal_sensor && + size == a.size ){ + return 0; + } + else { + return 1; + } + + } +} diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_mb_interleave/mss_eff_mb_interleave.H b/src/usr/hwpf/hwp/mc_config/mss_eff_mb_interleave/mss_eff_mb_interleave.H new file mode 100755 index 000000000..cc5761a3c --- /dev/null +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_mb_interleave/mss_eff_mb_interleave.H @@ -0,0 +1,69 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_mb_interleave/mss_eff_mb_interleave.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2014 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: mss_eff_mb_interleave.H,v 1.3 2014/02/19 20:06:18 bellows Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_mb_interleave.H,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2014 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *! Licensed material - Program property of IBM +// *! Refer to copyright instructions form no. G120-2083 +// *! Created on Wed Jan 8 2014 at 07:56:37 +//------------------------------------------------------------------------------ +// *! TITLE : mss_eff_mb_interleave +// *! DESCRIPTION : see additional comments below +// *! OWNER NAME : Bellows Mark D. (Mark D),319432 Email: bellows@us.ibm.com +// *! BACKUP NAME : Email: ______@us.ibm.com + +// *! ADDITIONAL COMMENTS : +// +//------------------------------------------------------------------------------ +// Don't forget to create CVS comments when you check in your changes! +//------------------------------------------------------------------------------ +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version:| Author: | Date: | Comment: +//---------|----------|---------|----------------------------------------------- +// 1.3 | bellows |19-JAN-14| Additional RAS updates +// 1.2 | bellows |17-JAN-14| RAS +// 1.1 | bellows |08-JAN-14| Created. +#ifndef __MSS_EFF_MB_INTERLEAVE_H +#define __MSS_EFF_MB_INTERLEAVE_H + +#include <fapi.H> + +typedef fapi::ReturnCode (*mss_eff_mb_interleave_FP_t)(const fapi::Target& centaur ); + +extern "C" +{ + +// This hardware procedure checks the plugging rules for a centaur and works with interleaving within the centaur +// if various plug rules are violated at this level of the memory stack, error logs and deconfigures will happen +// Many deconfig by assoication rules are not checked here. Just 4.1 and 4.2 plus a required Interleaving check +fapi::ReturnCode mss_eff_mb_interleave(const fapi::Target & i_cen_target); + + + +} // extern "C" + +#endif diff --git a/src/usr/hwpf/hwp/memory_attributes.xml b/src/usr/hwpf/hwp/memory_attributes.xml index 91851d7bf..d9d892fcd 100644 --- a/src/usr/hwpf/hwp/memory_attributes.xml +++ b/src/usr/hwpf/hwp/memory_attributes.xml @@ -21,7 +21,7 @@ <!-- --> <!-- IBM_PROLOG_END_TAG --> <attributes> -<!-- $Id: memory_attributes.xml,v 1.104 2014/01/21 16:15:37 bellows Exp $ --> +<!-- $Id: memory_attributes.xml,v 1.110 2014/02/21 16:54:50 bellows Exp $ --> <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB --> <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP --> <!-- *********************************************************************** --> @@ -1602,14 +1602,15 @@ firmware notes: none</description> <attribute> <id>ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT</id> <targetType>TARGET_TYPE_SYSTEM</targetType> - <description>This dial sets the Centaur address bits used to interleave addresses between MBA01 and MBA23. Valid values are 23 through 32. See Centaur Spec Chapter 5 for details. Used in the intifile. Will be obsolete when the MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT is set</description> + <description>This dial sets the Centaur address bits used to interleave addresses between MBA01 and MBA23. Valid values are 23 through 32. See Centaur Spec Chapter 5 for details. Used in the intifile. Will be obsolete when the MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT is set +This attribute will only be found in a Tuelta system. +</description> <valueType>uint8</valueType> <platInit/> <odmVisable/> <odmChangeable/> </attribute> -<!-- TODO: RTC 82331 - Add this attribute to the Accessor HWP <attribute> <id>ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -1619,11 +1620,13 @@ firmware notes: none</description> <odmChangeable/> <writeable/> </attribute> ---> + <attribute> <id>ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE</id> <targetType>TARGET_TYPE_SYSTEM</targetType> - <description>Value of on or off. On is 256 bit interleave. Off, the translation is on 128 bit interleave mode. See centaur workbook chapter 5. Will be obsolete when MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE is set</description> + <description>Value of on or off. On is 256 bit interleave. Off, the translation is on 128 bit interleave mode. See centaur workbook chapter 5. Will be obsolete when MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE is set. +This attribute will only be alive in the Tuelta system. +</description> <valueType>uint8</valueType> <enum>OFF = 0, ON = 1</enum> <platInit/> @@ -1631,7 +1634,6 @@ firmware notes: none</description> <odmChangeable/> </attribute> -<!-- TODO: RTC 82331 - Add this attribute to the Accessor HWP <attribute> <id>ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -1653,7 +1655,6 @@ firmware notes: none</description> <odmVisable/> <odmChangeable/> </attribute> ---> <attribute> <id>ATTR_MSS_CACHE_ENABLE</id> @@ -2518,19 +2519,6 @@ DIMM power test memory throttles for cfg_nm_m</description> <persistRuntime/> </attribute> -<!-- TODO: RTC 82331 - Add this attribute to the Accessor HWP -<attribute> - <id>ATTR_MSS_DRAM_ACTIVATE_POWER_PERCENT</id> - <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> - <description>DRAM Activation power percentage to determine the ras and cas weights for throttle controls -</description> - <valueType>uint8</valueType> - <writeable/> - <odmVisable/> - <odmChangeable/> -</attribute> ---> - <attribute> <id>ATTR_MSS_EFF_VPD_VERSION</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> @@ -2556,7 +2544,7 @@ DIMM power test memory throttles for cfg_nm_m</description> <enum>8_0G = 1, 9_6G = 2</enum> </attribute> -<!-- TODO: RTC 82331 - Add this attribute to the Accessor HWP +<!-- Not used yet <attribute> <id>ATTR_MRW_NEST_FREQUENCIES</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -2567,10 +2555,11 @@ DIMM power test memory throttles for cfg_nm_m</description> <platInit/> <enum>8_0G = 1, 9_6G = 2</enum> </attribute> +--> <attribute> <id>ATTR_MRW_STRICT_MBA_PLUG_RULE_CHECKING</id> - <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> + <targetType>TARGET_TYPE_SYSTEM</targetType> <description> The MRW for a system should set this to TRUE for systems that must obey plug rules. Lab environments should default this to off and allow the user to override using normal methods to test. </description> @@ -2578,22 +2567,7 @@ DIMM power test memory throttles for cfg_nm_m</description> <platInit/> <enum>FALSE = 0, TRUE = 1</enum> </attribute> ---> - -<!-- This attribute was added for defect SW244656, while the eKB version is waiting to be merged --> -<attribute> - <id>ATTR_MRW_CDIMM_MASTER_I2C_TEMP_SENSOR_ENABLE</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description>Used for Custom DIMMs to not enable the reading of the dimm temperature sensor on the master i2c bus</description> - - <valueType>uint8</valueType> - <enum>OFF = 0, ON = 1</enum> - <platInit/> - <odmVisable/> -</attribute> - -<!-- This attribute is not used in this build yet <attribute> <id>ATTR_MRW_ENHANCED_GROUPING_NO_MIRRORING</id> <targetType>TARGET_TYPE_SYSTEM</targetType> @@ -2604,8 +2578,17 @@ DIMM power test memory throttles for cfg_nm_m</description> <platInit/> <enum>FALSE = 0, TRUE = 1</enum> </attribute> - --> - + +<attribute> + <id>ATTR_MRW_CDIMM_MASTER_I2C_TEMP_SENSOR_ENABLE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Used for Custom DIMMs to not enable the reading of the dimm temperature sensor on the master i2c bus</description> + <valueType>uint8</valueType> + <enum>OFF = 0, ON = 1</enum> + <platInit/> + <odmVisable/> +</attribute> + <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB --> <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP --> </attributes> diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile index 31c4eb2e3..52c735abd 100644 --- a/src/usr/hwpf/makefile +++ b/src/usr/hwpf/makefile @@ -135,7 +135,8 @@ HWP_ERROR_XML_FILES = hwp/fapiHwpErrorInfo.xml \ hwp/core_activate/proc_check_slw_done/proc_check_slw_done_errors.xml \ hwp/dram_initialization/proc_throttle_sync/proc_throttle_sync_errors.xml \ hwp/dram_initialization/mss_power_cleanup/memory_mss_power_cleanup.xml \ - hwp/runtime_errors/p8_pstate_registers.xml + hwp/runtime_errors/p8_pstate_registers.xml \ + hwp/mc_config/mss_eff_mb_interleave/memory_mss_eff_mb_interleave.xml ## these get generated into obj/genfiles/AttributeIds.H HWP_ATTR_XML_FILES = hwp/memory_attributes.xml \ diff --git a/src/usr/targeting/common/genHwsvMrwXml.pl b/src/usr/targeting/common/genHwsvMrwXml.pl index 99e8cd93c..930ee0f98 100755 --- a/src/usr/targeting/common/genHwsvMrwXml.pl +++ b/src/usr/targeting/common/genHwsvMrwXml.pl @@ -192,6 +192,9 @@ push @systemAttr, $reqPol->{'cdimm_master_i2c_temp_sensor_enable'}, "PM_SYSTEM_IVRMS_ENABLED", $reqPol->{'pm_system_ivrms_enabled'}, "PM_SYSTEM_IVRM_VPD_MIN_LEVEL", $reqPol->{'pm_system_ivrm_vpd_min_level'}, + "MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL", $reqPol->{'mba_cacheline_interleave_mode_control'}, + "MRW_ENHANCED_GROUPING_NO_MIRRORING", $reqPol->{'mcs_enhanced_grouping_no_mirroring'}, + "MRW_STRICT_MBA_PLUG_RULE_CHECKING", $reqPol->{'strict_mba_plug_rule_checking'}, ]; #------------------------------------------------------------------------------ diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index 6728aa0e8..96d21449c 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -13284,6 +13284,68 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </attribute> <attribute> + <id>MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE</id> + <description>Value of on or off. On is 256 bit interleave. Off, the translation is on 128 bit interleave mode. See centaur workbook chapter 5.</description> + <simpleType> + <uint8_t> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MRW_STRICT_MBA_PLUG_RULE_CHECKING</id> + <description> + The MRW for a system should set this to TRUE for systems that must obey plug rules. Lab environments should default this to off and allow the user to override using normal methods to test. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_MRW_STRICT_MBA_PLUG_RULE_CHECKING</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT</id> + <description>This dial sets the Centaur address bits used to interleave addresses between MBA01 and MBA23. Valid values are 23 through 32. See Centaur Spec Chapter 5 for details. Used in the intifile </description> + <simpleType> + <uint8_t> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL</id> + <description>At a system level, this attribute controls if interleaving is required, requested or never. The MRW.</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> <id>MSS_NEST_CAPABLE_FREQUENCIES</id> <description> The NEST frequencies the memory chip can run at computed by the mss_freq. The possibilities are ORed together. The platform uses these value and the MRW to determine what frequency to boot the fabric (nest) if it can. There are two values: 8G and 9.6G @@ -13301,6 +13363,22 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </hwpfToHbAttrMap> </attribute> +<attribute> + <id>MRW_ENHANCED_GROUPING_NO_MIRRORING</id> + <description> + The MRW for a system should set this to TRUE for systems that do not want to suport MCS groupings larget than 2. Mirroring also must be disabled and is unusable. IBM systems, such as Tuleta, should set this attribute to FALSE. Stradale based systems should set this to TRUE. This instructs the grouping code to group contiguous memory controllers of the same size together. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_MRW_ENHANCED_GROUPING_NO_MIRRORING</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + </attributes> diff --git a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml index 4e21a72fa..653a6859b 100644 --- a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml +++ b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml @@ -309,6 +309,18 @@ <id>MRW_CDIMM_MASTER_I2C_TEMP_SENSOR_ENABLE</id> <default>false</default> </attribute> + <attribute> + <id>MRW_STRICT_MBA_PLUG_RULE_CHECKING</id> + <default>true</default> + </attribute> + <attribute> + <id>MRW_ENHANCED_GROUPING_NO_MIRRORING</id> + <default>false</default> + </attribute> + <attribute> + <id>MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL</id> + <default>required</default> + </attribute> </targetInstance> <!-- System node 0 --> diff --git a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml index 4b6442604..ac7d78ab4 100644 --- a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml +++ b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml @@ -301,6 +301,18 @@ po<!-- IBM_PROLOG_BEGIN_TAG -- <id>MRW_CDIMM_MASTER_I2C_TEMP_SENSOR_ENABLE</id> <default>false</default> </attribute> + <attribute> + <id>MRW_STRICT_MBA_PLUG_RULE_CHECKING</id> + <default>true</default> + </attribute> + <attribute> + <id>MRW_ENHANCED_GROUPING_NO_MIRRORING</id> + <default>false</default> + </attribute> + <attribute> + <id>MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL</id> + <default>required</default> + </attribute> </targetInstance> <!-- System node 0 --> diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index b9c1cc4fa..2c5dec265 100644 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -139,12 +139,10 @@ <attribute><id>FREQ_CORE_MAX</id></attribute> <attribute><id>CPM_TURBO_BOOST_PERCENT</id></attribute> <!-- End pm_plat_attributes.xml --> - <!-- Start pm_hwp_attributes.xml --> <attribute><id>PM_SLW_CONTROL_VECTOR_OFFSET</id></attribute> <!-- End pm_hwp_attributes.xml --> - - <!-- sbe_config_update attributes --> + <!-- sbe_config_update attributes --> <attribute><id>NEST_FREQ_MHZ</id></attribute> <attribute><id>BOOT_FREQ_MHZ</id></attribute> <attribute><id>EX_GARD_BITS</id></attribute> @@ -231,6 +229,9 @@ <attribute><id>DISABLE_SCRUB_AFTER_PATTERN_TEST</id></attribute> <attribute><id>PM_PCBS_FSM_TRACE_EN</id></attribute> <attribute><id>PM_GLOBAL_FIR_TRACE_EN</id></attribute> + <attribute><id>MRW_STRICT_MBA_PLUG_RULE_CHECKING</id></attribute> + <attribute><id>MRW_ENHANCED_GROUPING_NO_MIRRORING</id></attribute> + <attribute><id>MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL</id></attribute> </targetType> <targetType> @@ -1215,6 +1216,9 @@ <attribute><id>DMI_DFE_OVERRIDE</id></attribute> <attribute><id>MSS_INIT_STATE</id></attribute> <attribute><id>MSS_NEST_CAPABLE_FREQUENCIES</id></attribute> + <attribute><id>MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT</id></attribute> + <attribute><id>MSS_NEST_CAPABLE_FREQUENCIES</id></attribute> + <attribute><id>MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE</id></attribute> </targetType> <!-- Centaur L4 --> diff --git a/src/usr/targeting/common/xmltohb/vbu_MURANO.system.xml b/src/usr/targeting/common/xmltohb/vbu_MURANO.system.xml index 867221130..6c42721ce 100644 --- a/src/usr/targeting/common/xmltohb/vbu_MURANO.system.xml +++ b/src/usr/targeting/common/xmltohb/vbu_MURANO.system.xml @@ -288,6 +288,18 @@ <id>MRW_CDIMM_MASTER_I2C_TEMP_SENSOR_ENABLE</id> <default>false</default> </attribute> + <attribute> + <id>MRW_STRICT_MBA_PLUG_RULE_CHECKING</id> + <default>true</default> + </attribute> + <attribute> + <id>MRW_ENHANCED_GROUPING_NO_MIRRORING</id> + <default>false</default> + </attribute> + <attribute> + <id>MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL</id> + <default>required</default> + </attribute> </targetInstance> <!-- System node 0 --> diff --git a/src/usr/targeting/common/xmltohb/vbu_VENICE.system.xml b/src/usr/targeting/common/xmltohb/vbu_VENICE.system.xml index 6c187f625..54cc37b83 100644 --- a/src/usr/targeting/common/xmltohb/vbu_VENICE.system.xml +++ b/src/usr/targeting/common/xmltohb/vbu_VENICE.system.xml @@ -289,6 +289,18 @@ <id>MRW_CDIMM_MASTER_I2C_TEMP_SENSOR_ENABLE</id> <default>false</default> </attribute> + <attribute> + <id>MRW_STRICT_MBA_PLUG_RULE_CHECKING</id> + <default>true</default> + </attribute> + <attribute> + <id>MRW_ENHANCED_GROUPING_NO_MIRRORING</id> + <default>false</default> + </attribute> + <attribute> + <id>MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL</id> + <default>required</default> + </attribute> </targetInstance> <!-- System node 0 --> |
