diff options
Diffstat (limited to 'src/usr/hwpf/hwp/dram_training')
-rw-r--r-- | src/usr/hwpf/hwp/dram_training/dram_training.C | 148 | ||||
-rw-r--r-- | src/usr/hwpf/hwp/dram_training/dram_training.H | 52 | ||||
-rw-r--r-- | src/usr/hwpf/hwp/dram_training/makefile | 10 | ||||
-rw-r--r-- | src/usr/hwpf/hwp/dram_training/memory_errors.xml | 241 | ||||
-rw-r--r-- | src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C | 197 | ||||
-rw-r--r-- | src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H | 79 |
6 files changed, 513 insertions, 214 deletions
diff --git a/src/usr/hwpf/hwp/dram_training/dram_training.C b/src/usr/hwpf/hwp/dram_training/dram_training.C index bf95a1b06..a9928999b 100644 --- a/src/usr/hwpf/hwp/dram_training/dram_training.C +++ b/src/usr/hwpf/hwp/dram_training/dram_training.C @@ -1,26 +1,26 @@ -// IBM_PROLOG_BEGIN_TAG -// This is an automatically generated prolog. -// -// $Source: src/usr/hwpf/hwp/dram_training/dram_training.C $ -// -// IBM CONFIDENTIAL -// -// COPYRIGHT International Business Machines Corp. 2012 -// -// p1 -// -// Object Code Only (OCO) source materials -// Licensed Internal Code Source Materials -// IBM HostBoot Licensed Internal Code -// -// The source code for this program is not published or other- -// wise divested of its trade secrets, irrespective of what has -// been deposited with the U.S. Copyright Office. -// -// Origin: 30 -// -// IBM_PROLOG_END - +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/dram_training/dram_training.C $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ /** * @file dram_training.C * @@ -71,7 +71,7 @@ const uint8_t VPO_NUM_OF_MEMBUF_TO_RUN = UNLIMITED_RUN; // #include "mc_pll_setup/mc_pll_setup.H" #include "mem_startclocks/cen_mem_startclocks.H" // #include "host_enable_vddr/host_enable_vddr.H" -// #include "mss_initf/mss_initf.H" +#include "mss_scominit/mss_scominit.H" #include "mss_ddr_phy_reset/mss_ddr_phy_reset.H" #include "mss_draminit/mss_draminit.H" // #include "mss_restore_dram_repair/mss_restore_dram_repair.H" @@ -324,60 +324,72 @@ void call_host_enable_vddr( void *io_pArgs ) // -// Wrapper function to call 13.5 : mss_initf +// Wrapper function to call 13.5 : mss_scominit // -void call_mss_initf( void *io_pArgs ) +void call_mss_scominit( void *io_pArgs ) { errlHndl_t l_err = NULL; - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_initf entry" ); - -#if 0 - // @@@@@ CUSTOM BLOCK: @@@@@ - // figure out what targets we need - // customize any other inputs - // set up loops to go through all targets (if parallel, spin off a task) - - // print call to hwp and dump physical path of the target(s) - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "===== mss_initf HWP(? ? ? )", - ? - ? - ? ); - // dump physical path to targets - EntityPath l_path; - l_path = l_@targetN_target->getAttr<ATTR_PHYS_PATH>(); - l_path.dump(); - TRACFCOMP( g_trac_mc_init, "===== " ); - - // cast OUR type of target to a FAPI type of target. - const fapi::Target l_fapi_@targetN_target( - TARGET_TYPE_MEMBUF_CHIP, - reinterpret_cast<void *> - (const_cast<TARGETING::Target*>(l_@targetN_target)) ); - - // call the HWP with each fapi::Target - l_fapirc = mss_initf( ? , ?, ? ); - - // process return code. - if ( l_fapirc== fapi::FAPI_RC_SUCCESS ) + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_scominit entry" ); + + // TODO: RTC 44947 + // This currently fails on Simics because cen_ddrphy.initfile accesses + // indirect broadcast SCOM addresses. When Simics have support for + // indirect broadcast SCOM addresses than this HWP can be executed. + // For now, just execute the HWP on VPO. + TARGETING::Target * l_pSysTarget = NULL; + TARGETING::targetService().getTopLevelTarget(l_pSysTarget); + uint8_t l_vpoMode = l_pSysTarget->getAttr<TARGETING::ATTR_IS_SIMULATION>(); + if (!l_vpoMode) { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : mss_initf HWP(? ? ? )" ); + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "INFO : not executing mss_scominit in Simics until it supports " + "indirect broadcast SCOM addresses"); } else { - /** - * @todo fapi error - just print out for now... - */ - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: mss_initf HWP(? ? ?) ", - static_cast<uint32_t>(l_fapirc) ); + // Get all Centaur targets + TARGETING::TargetHandleList l_membufTargetList; + getAllChips(l_membufTargetList, TYPE_MEMBUF); + + for ( size_t i = 0; i < l_membufTargetList.size(); i++ ) + { + // make a local copy of the target for ease of use + const TARGETING::Target* l_pCentaur = l_membufTargetList[i]; + + // Dump current run on target + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running mss_scominit HWP on..." ); + + EntityPath l_path; + l_path = l_pCentaur->getAttr<ATTR_PHYS_PATH>(); + l_path.dump(); + + // Cast to a FAPI type of target. + const fapi::Target l_fapi_centaur( + TARGET_TYPE_MEMBUF_CHIP, + reinterpret_cast<void *> + (const_cast<TARGETING::Target*>(l_pCentaur)) ); + + // call the HWP with each fapi::Target + FAPI_INVOKE_HWP(l_err, mss_scominit, l_fapi_centaur); + + if (l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: mss_scominit HWP returns error", + l_err->reasonCode()); + break; + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : mss_scominit HWP( )" ); + } + } } - // @@@@@ END CUSTOM BLOCK: @@@@@ -#endif - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_initf exit" ); + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_scominit exit" ); task_end2( l_err ); } diff --git a/src/usr/hwpf/hwp/dram_training/dram_training.H b/src/usr/hwpf/hwp/dram_training/dram_training.H index 03049eecf..e423ddfef 100644 --- a/src/usr/hwpf/hwp/dram_training/dram_training.H +++ b/src/usr/hwpf/hwp/dram_training/dram_training.H @@ -1,26 +1,26 @@ -// IBM_PROLOG_BEGIN_TAG -// This is an automatically generated prolog. -// -// $Source: src/usr/hwpf/hwp/dram_training/dram_training.H $ -// -// IBM CONFIDENTIAL -// -// COPYRIGHT International Business Machines Corp. 2012 -// -// p1 -// -// Object Code Only (OCO) source materials -// Licensed Internal Code Source Materials -// IBM HostBoot Licensed Internal Code -// -// The source code for this program is not published or other- -// wise divested of its trade secrets, irrespective of what has -// been deposited with the U.S. Copyright Office. -// -// Origin: 30 -// -// IBM_PROLOG_END - +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/dram_training/dram_training.H $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ #ifndef __DRAM_TRAINING_DRAM_TRAINING_H #define __DRAM_TRAINING_DRAM_TRAINING_H @@ -70,7 +70,7 @@ * @} * @{ * @substepnum 5 - * @substepname mss_initf + * @substepname mss_scominit * @substepdesc : Perform scom inits to MC and PHY * @target_sched serial * @} @@ -178,7 +178,7 @@ void call_host_enable_vddr( void * io_pArgs ); /** - * @brief mss_initf + * @brief mss_scominit * * 13.5 : : Perform scom inits to MC and PHY * @@ -187,7 +187,7 @@ void call_host_enable_vddr( void * io_pArgs ); * return none * */ -void call_mss_initf( void * io_pArgs ); +void call_mss_scominit( void * io_pArgs ); diff --git a/src/usr/hwpf/hwp/dram_training/makefile b/src/usr/hwpf/hwp/dram_training/makefile index b16fbdb58..8fe367558 100644 --- a/src/usr/hwpf/hwp/dram_training/makefile +++ b/src/usr/hwpf/hwp/dram_training/makefile @@ -1,4 +1,4 @@ -# IBM_PROLOG_BEGIN_TAG +# IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # # $Source: src/usr/hwpf/hwp/dram_training/makefile $ @@ -19,8 +19,7 @@ # # Origin: 30 # -# IBM_PROLOG_END - +# IBM_PROLOG_END_TAG ROOTPATH = ../../../../.. MODULE = dram_training @@ -46,6 +45,7 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit_mc EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mem_startclocks +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_scominit ## NOTE: add new object files when you add a new HWP OBJS = dram_training.o \ @@ -54,7 +54,8 @@ OBJS = dram_training.o \ mss_draminit_mc.o \ mss_draminit_training.o \ mss_ddr_phy_reset.o \ - cen_mem_startclocks.o + cen_mem_startclocks.o \ + mss_scominit.o ## NOTE: add a new directory onto the vpaths when you add a new HWP ##@ VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/??? @@ -63,5 +64,6 @@ VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit_mc VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mem_startclocks +VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_scominit include ${ROOTPATH}/config.mk diff --git a/src/usr/hwpf/hwp/dram_training/memory_errors.xml b/src/usr/hwpf/hwp/dram_training/memory_errors.xml index 741a811ca..8a3811b8d 100644 --- a/src/usr/hwpf/hwp/dram_training/memory_errors.xml +++ b/src/usr/hwpf/hwp/dram_training/memory_errors.xml @@ -21,297 +21,306 @@ IBM_PROLOG_END_TAG --> <hwpErrors> +<!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB --> +<!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP --> <!-- *********************************************************************** --> <hwpError> <rc>RC_MSS_RCD_PARITY_ERROR_PORT0</rc> - <description>An rcd parity error has been registered on port_0 </description> - </hwpError> + <description>An rcd parity error has been registered on port_0</description> +</hwpError> <hwpError> <rc>RC_MSS_RCD_PARITY_ERROR_PORT1</rc> - <description>An rcd parity error has been registered on port_1 </description> - </hwpError> + <description>An rcd parity error has been registered on port_1</description> +</hwpError> <hwpError> <rc>RC_MSS_RCD_PARITY_ERROR_LIMIT</rc> - <description>The number of rcd parity errors have exceeded the maximum allowable number </description> - </hwpError> + <description>The number of rcd parity errors have exceeded the maximum allowable number</description> +</hwpError> <hwpError> <rc>RC_MSS_CCS_HUNG</rc> - <description>The ccs failed to return from in_progress status and failed to describe an error further. </description> - </hwpError> + <description>The ccs failed to return from in_progress status and failed to describe an error further.</description> +</hwpError> <hwpError> <rc>RC_MSS_CCS_READ_MISCOMPARE</rc> - <description>The ccs errors at runtime and registers a read miscompare. </description> - </hwpError> + <description>The ccs errors at runtime and registers a read miscompare.</description> +</hwpError> <hwpError> <rc>RC_MSS_CCS_UE_SUE</rc> - <description>The ccs errors at runtime and registers a UE or SUE </description> - </hwpError> + <description>The ccs errors at runtime and registers a UE or SUE</description> +</hwpError> <hwpError> <rc>RC_MSS_CCS_CAL_TIMEOUT</rc> - <description>The ccs errors at runtime and registers a calibration operation timeout </description> - </hwpError> + <description>The ccs errors at runtime and registers a calibration operation timeout</description> +</hwpError> <hwpError> <rc>RC_MSS_PLACE_HOLDER_ERROR</rc> - <description>Not for production code. This return code is used for cases where the error code has not been approved yet. Eventually, no code should use this error code. </description> - </hwpError> + <description>Not for production code. This return code is used for cases where the error code has not been approved yet. Eventually, no code should use this error code.</description> +</hwpError> <hwpError> <rc>RC_MSS_EFF_CONFIG_RANK_GROUP_RC_ERROR_001A</rc> - <description>Plug rule violation in EFF_CONFIG_RANK_GROUP. </description> - </hwpError> + <description>Plug rule violation in EFF_CONFIG_RANK_GROUP.</description> +</hwpError> <hwpError> <rc>RC_MSS_EFF_CONFIG_RC_ERROR_001A</rc> - <description>Plug rule violation in EFF_CONFIG. </description> - </hwpError> + <description>Plug rule violation in EFF_CONFIG.</description> +</hwpError> <hwpError> <rc>RC_MSS_UNEXPECTED_MEM_CLK_STATUS</rc> - <description>A read of the memory clock status register returned an unexpected value. </description> - </hwpError> + <description>A read of the memory clock status register returned an unexpected value. </description> +</hwpError> <hwpError> <rc>RC_MSS_UNEXPECTED_NEST_CLK_STATUS</rc> - <description>A read of the nest clock status register returned an unexpected value. </description> - </hwpError> + <description>A read of the nest clock status register returned an unexpected value.</description> +</hwpError> <hwpError> <rc>RC_MSS_INIT1_OPCG_DONE_ERROR</rc> - <description>Timed out waiting for OPCG done bit(15). </description> - </hwpError> + <description>Timed out waiting for OPCG done bit(15).</description> +</hwpError> <hwpError> <rc>RC_MSS_INIT1_FSISTATUS_FAIL</rc> - <description>Failed VDD status check on FSI2PIB Status Reg bit(16). </description> - </hwpError> + <description>Failed VDD status check on FSI2PIB Status Reg bit(16).</description> +</hwpError> <hwpError> <rc>RC_MSS_PLL_LOCK_TIMEOUT</rc> - <description>Timed out waiting for PLL locks in FSI2PIB Status Reg bits(24,25). </description> - </hwpError> + <description>Timed out waiting for PLL locks in FSI2PIB Status Reg bits(24,25). </description> +</hwpError> <hwpError> <rc>RC_MSS_THOLD_ERROR</rc> - <description>THOLDS after Clock Start cmd do NOT match to the expected value. </description> - </hwpError> + <description>THOLDS after Clock Start cmd do NOT match to the expected value.</description> +</hwpError> <hwpError> <rc>RC_MSS_CCREG_MISMATCH</rc> - <description>Clock Control Register does not match the expected value. </description> - </hwpError> + <description>Clock Control Register does not match the expected value.</description> +</hwpError> <hwpError> <rc>RC_MSS_ARRAY_REPAIR_BUSY</rc> - <description>Array repair loader is busy now. 0x00050003 bit(0)=1 </description> - </hwpError> + <description>Array repair loader is busy now. 0x00050003 bit(0)=1 </description> +</hwpError> <hwpError> <rc>RC_MSS_ARRAY_REPAIR_NOT_DONE</rc> - <description>Array repair loader did NOT report repair done. </description> - </hwpError> + <description>Array repair loader did NOT report repair done. </description> +</hwpError> <hwpError> <rc>RC_MSS_ECC_TRAP_ERROR</rc> - <description>ECC trap register reported error. 0x00050004 bit(0-7) != 0x00 </description> - </hwpError> + <description>ECC trap register reported error. 0x00050004 bit(0-7) != 0x00</description> +</hwpError> <hwpError> <rc>RC_MSS_DP18_0_PLL_FAILED_TO_LOCK</rc> - <description>DP18 0x0C000 PLL failed to lock! See lock status register at address: 0x8000C0000301143F </description> - </hwpError> + <description>DP18 0x0C000 PLL failed to lock! See lock status register at address: 0x8000C0000301143F</description> +</hwpError> <hwpError> <rc>RC_MSS_DP18_1_PLL_FAILED_TO_LOCK</rc> - <description>DP18 0x1C000 PLL failed to lock! See lock status register at address: 0x8001C0000301143F </description> - </hwpError> + <description>DP18 0x1C000 PLL failed to lock! See lock status register at address: 0x8001C0000301143F</description> +</hwpError> <hwpError> <rc>RC_MSS_AD32S_0_PLL_FAILED_TO_LOCK</rc> - <description>AD32S 0x0C001 PLL failed to lock! See lock status register at address: 0x8000C0010301143F </description> - </hwpError> + <description>AD32S 0x0C001 PLL failed to lock! See lock status register at address: 0x8000C0010301143F</description> +</hwpError> <hwpError> <rc>RC_MSS_AD32S_1_PLL_FAILED_TO_LOCK</rc> - <description>AD32S 0x1C001 PLL failed to lock! See lock status register at address: 0x8001C0010301143F </description> - </hwpError> + <description>AD32S 0x1C001 PLL failed to lock! See lock status register at address: 0x8001C0010301143F</description> +</hwpError> <hwpError> <rc>RC_MSS_GENERAL_PUTSCOM_ERROR</rc> - <description>PutScom failed! See previous error message for details. </description> - </hwpError> + <description>PutScom failed! See previous error message for details.</description> +</hwpError> <hwpError> <rc>RC_MSS_GENERAL_GETSCOM_ERROR</rc> - <description>GetScom failed! See previous error message for details. </description> - </hwpError> + <description>GetScom failed! See previous error message for details.</description> +</hwpError> <hwpError> <rc>RC_MSS_UNEXPECTED_CLOCK_STATUS</rc> - <description>Unexpected clock status! See previous error message for details. </description> - </hwpError> + <description>Unexpected clock status! See previous error message for details.</description> +</hwpError> <hwpError> <rc>RC_MSS_UNEXPECTED_FIR_STATUS</rc> - <description>Unexpected FIR status! See previous error message for details. </description> - </hwpError> + <description>Unexpected FIR status! See previous error message for details.</description> +</hwpError> <hwpError> <rc>RC_MSS_INIT_CAL_FAILED</rc> - <description>Inital Calibration failed. Check init cal error register at address: 0x8001C0180301143F </description> - </hwpError> + <description>Inital Calibration failed. Check init cal error register at address: 0x8001C0180301143F </description> +</hwpError> <hwpError> <rc>RC_MSS_VOLT_UNRECOGNIZED_DRAM_DEVICE_TYPE</rc> - <description>Unsupported DIMM type found. All dimms must be DDR3 or DDR4 </description> + <description>Unsupported DIMM type found. All dimms must be DDR3 or DDR4</description> <ffdc>DEVICE_TYPE</ffdc> - </hwpError> +</hwpError> <hwpError> <rc>RC_MSS_VOLT_DDR_TYPE_MIXING_UNSUPPORTED</rc> - <description>Mixing of DDR3 and DDR4 not supported. </description> - </hwpError> + <description>Mixing of DDR3 and DDR4 not supported.</description> +</hwpError> <hwpError> <rc>RC_MSS_VOLT_DDR_TYPE_REQUIRED_VOLTAGE</rc> - <description>One or more DIMMs do not support required voltage for DDR type. </description> - </hwpError> + <description>One or more DIMMs do not support required voltage for DDR type.</description> +</hwpError> <hwpError> <rc>RC_MSS_GENERAL_SIMSTKFAC_ERROR</rc> - <description>simSTKFAC failed! See previous error message for details </description> - </hwpError> + <description>simSTKFAC failed! See previous error message for details</description> +</hwpError> <hwpError> <rc>RC_MSS_GET_FAPI_ATTRIBUTE_ERROR</rc> - <description>Failed to get FAPI attribute! See previous error message for details. </description> - </hwpError> + <description>Failed to get FAPI attribute! See previous error message for details.</description> +</hwpError> <hwpError> <rc>RC_MSS_GET_SIM_HIERARCHY_ERROR</rc> - <description>Failed to get simulation hierarchy from eCmd target. </description> - </hwpError> + <description>Failed to get simulation hierarchy from eCmd target.</description> +</hwpError> <hwpError> <rc>RC_MSS_UNSUPPORTED_FREQ_CALCULATED</rc> - <description>The frequency calculated with spd data is not supported by the jedec standards. </description> - </hwpError> + <description>The frequency calculated with spd data is not supported by the jedec standards.</description> +</hwpError> <hwpError> <rc>RC_MSS_MAINT_START_NOT_RESET</rc> - <description>MCMCCQ[0]: maint_cmd_start not reset by hw. </description> - </hwpError> + <description>MCMCCQ[0]: maint_cmd_start not reset by hw.</description> +</hwpError> <hwpError> <rc>RC_MSS_MAINT_STOP_NOT_RESET</rc> - <description>MCMCCQ[1]: maint_cmd_stop not reset by hw. </description> - </hwpError> + <description>MCMCCQ[1]: maint_cmd_stop not reset by hw.</description> +</hwpError> <hwpError> <rc>RC_MSS_MAINT_CMD_IN_PROGRESS</rc> - <description>MBMSRQ[0]: Can't start new cmd if previous cmd still in progress. </description> - </hwpError> + <description>MBMSRQ[0]: Can't start new cmd if previous cmd still in progress.</description> +</hwpError> <hwpError> <rc>RC_MSS_MAINT_NO_MEM_CNFG</rc> - <description>MBAXCRn[0:3] = 0, meaning no memory configured behind this MBA. </description> - </hwpError> + <description>MBAXCRn[0:3] = 0, meaning no memory configured behind this MBA.</description> +</hwpError> <hwpError> <rc>RC_MSS_MAINT_CCS_MUX_NOT_MAINLINE</rc> - <description>CCS_MODEQ[29] = 1, meaning mux set for CCS instead of mainline. </description> - </hwpError> + <description>CCS_MODEQ[29] = 1, meaning mux set for CCS instead of mainline.</description> +</hwpError> <hwpError> <rc>RC_MSS_MAINT_ECC_DISABLED</rc> - <description>MBSECC[0] non zero, meaning ECC check/correct disabled. </description> - </hwpError> + <description>MBSECC[0] non zero, meaning ECC check/correct disabled.</description> +</hwpError> <hwpError> <rc>RC_MSS_MAINT_INVALID_CMD</rc> - <description>MBAFIRQ[0], invalid_maint_cmd. </description> - </hwpError> + <description>MBAFIRQ[0], invalid_maint_cmd.</description> +</hwpError> <hwpError> <rc>RC_MSS_MAINT_INVALID_ADDR</rc> - <description>MBAFIRQ[1], cmd started with invalid_maint_address. </description> - </hwpError> + <description>MBAFIRQ[1], cmd started with invalid_maint_address.</description> +</hwpError> <hwpError> <rc>RC_MSS_MAINT_CMD_TIMEOUT</rc> - <description>Maint cmd timeout. </description> - </hwpError> + <description>Maint cmd timeout.</description> +</hwpError> <hwpError> <rc>RC_MSS_MAINT_INVALID_DRAM_SIZE_WIDTH</rc> - <description>Invalid dramSize or dramWidth in MBAXCRn. </description> - </hwpError> + <description>Invalid dramSize or dramWidth in MBAXCRn.</description> +</hwpError> <hwpError> <rc>RC_MSS_MAINT_INVALID_DIMM_CNFG</rc> - <description>MBAXCRn configured with invalid combination of configType, configSubType, slotConfig. </description> - </hwpError> + <description>MBAXCRn configured with invalid combination of configType, configSubType, slotConfig.</description> +</hwpError> <hwpError> <rc>RC_MSS_MAINT_NO_X4_SYMBOL</rc> - <description>Symbol mark not allowed in x4 mode. </description> - </hwpError> + <description>Symbol mark not allowed in x4 mode.</description> +</hwpError> <hwpError> <rc>RC_MSS_MAINT_INVALID_MARKSTORE</rc> - <description>Invalid galois field in markstore. </description> - </hwpError> + <description>Invalid galois field in markstore.</description> +</hwpError> <hwpError> <rc>RC_MSS_MAINT_INVALID_SYMBOL_INDEX</rc> - <description>Symbol index out of range. </description> - </hwpError> + <description>Symbol index out of range.</description> +</hwpError> <hwpError> <rc>RC_MSS_MAINT_INVALID_CHIP_INDEX</rc> - <description>Not first symbol index of a chip. </description> - </hwpError> + <description>Not first symbol index of a chip.</description> +</hwpError> <hwpError> <rc>RC_MSS_MAINT_MARKSTORE_WRITE_BLOCKED</rc> - <description>Markstore write may have been blocked due to MPE FIR set. </description> - </hwpError> + <description>Markstore write may have been blocked due to MPE FIR set.</description> +</hwpError> <hwpError> <rc>RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER</rc> - <description>Trying to steer invalid symbol. </description> - </hwpError> + <description>Trying to steer invalid symbol.</description> +</hwpError> <hwpError> <rc>RC_MSS_MAINT_NO_X8_ECC_SPARE</rc> - <description>Invalid to use ECC spare in x8 mode. </description> - </hwpError> + <description>Invalid to use ECC spare in x8 mode.</description> +</hwpError> <hwpError> <rc>RC_MSS_UNSUPPORTED_SPD_DATA</rc> - <description>Invalid SPD data returned. </description> - </hwpError> + <description>Invalid SPD data returned.</description> +</hwpError> <hwpError> <rc>RC_MSS_NO_COMMON_SUPPORTED_CL</rc> - <description>Current Configuration has no common supported CL Values. </description> - </hwpError> + <description>Current Configuration has no common supported CL Values.</description> +</hwpError> <hwpError> <rc>RC_MSS_EXCEED_TAA_MAX_NO_CL</rc> - <description> Exceeded TAA MAX with Lowest frequency. No compatable CL. </description> - </hwpError> + <description>Exceeded TAA MAX with Lowest frequency. No compatable CL.</description> +</hwpError> <hwpError> <rc>RC_MSS_MODULE_TYPE_MIX</rc> - <description> Differing DIMM types in the same configuration. </description> - </hwpError> + <description>Differing DIMM types in the same configuration.</description> +</hwpError> + <hwpError> + <rc>RC_MSS_NUM_MBA_ERROR</rc> + <description>Less than 2 MBA's returned by fapiGetChildChiplets</description> +</hwpError> + +<!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB --> +<!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C new file mode 100644 index 000000000..a79ce3cea --- /dev/null +++ b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C @@ -0,0 +1,197 @@ +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : mss_scominit +// *! DESCRIPTION : see additional comments below +// *! OWNER NAME : Menlo Wuu Email: menlowuu@us.ibm.com +// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com +// *! ADDITIONAL COMMENTS : +// +// The purpose of this procedure execute memory initfiles in proper sequence. +// +//------------------------------------------------------------------------------ +// Don't forget to create CVS comments when you check in your changes! +//------------------------------------------------------------------------------ +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version:| Author: | Date: | Comment: +//---------|----------|---------|----------------------------------------------- +// 1.7 | menlowuu |14-JUN-12| Added fixes suggested by Mike, +// replace rc_num with ReturnCode, created RC for when +// MBAs != 2, and return on all errors +// 1.6 | menlowuu |08-JUN-12| Fixed inserting centaur vector & return code. +// 1.5 | menlowuu |06-JUN-12| Added code to use +// primary centaur target, secondary mba[0/1] for mbs.if; +// primary mba[0|1] target, secondary centaur for mba.if, phy.if +// 1.4 | menlowuu |05-JUN-12| Added vector target for fapiHwpExecInitFile +// 1.3 | menlowuu |15-MAY-12| Added fapi namespace to rc_num definition +// 0.1 | menlowuu |01-DEC-11| First Draft. + + +//---------------------------------------------------------------------- +// My Includes +//---------------------------------------------------------------------- +#include <mss_scominit.H> + +//---------------------------------------------------------------------- +// Includes +//---------------------------------------------------------------------- +#include <fapiHwpExecInitFile.H> + +extern "C" { + using namespace fapi; + +//****************************************************************************** +// +//****************************************************************************** +ReturnCode mss_scominit(const Target & i_target) { + + ReturnCode rc; + std::vector<Target> vector_targets; + const char* mbs_if = "mbs_def.if"; + const char* mba_if = "mba_def.if"; + const char* phy_if = "cen_ddrphy.if"; + + FAPI_INF("Performing HWP: mss_scominit"); + + // Print the ecmd string of the chip + FAPI_INF("Input Target: %s", i_target.toEcmdString()); + + // Get a vector of the present MBA targets + rc = fapiGetChildChiplets(i_target, TARGET_TYPE_MBA_CHIPLET, + vector_targets, TARGET_STATE_PRESENT); + + if (rc) + { + FAPI_ERR("Error from fapiGetChildChiplets getting present MBA's!"); + FAPI_ERR("RC = 0x%x", static_cast<uint32_t>(rc)); + return (rc); + } + else if (vector_targets.size() != 2) + { + ReturnCode l_rc; + FAPI_ERR("fapiGetChildChiplets returned present MBAs != 2"); + FAPI_SET_HWP_ERROR(l_rc, RC_MSS_NUM_MBA_ERROR); + FAPI_ERR("Present MBAs = %i, generating RC_MSS_NUM_MBA_ERROR = 0x%x", + vector_targets.size(), static_cast<uint32_t>(l_rc)); + return (l_rc); + } + else + { + // insert centaur target at beginning of vector + vector_targets.insert(vector_targets.begin(),i_target); + + // run mbs initfile... + FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, vector_targets, mbs_if); + + if (rc) + { + FAPI_ERR(" !!! Error running MBS %s, RC = 0x%x", + mbs_if, static_cast<uint32_t>(rc)); + return (rc); + } + else + { + FAPI_INF("MBS scom initfile %s passed", mbs_if); + } + } + + // Clear vector targets + vector_targets.clear(); + + // Get a vector of the functional MBA targets + rc=fapiGetChildChiplets(i_target, TARGET_TYPE_MBA_CHIPLET, vector_targets); + + if (rc) + { + FAPI_ERR("Error from fapiGetChildChiplets getting functional MBA's!"); + return (rc); + } + else + { + uint8_t l_unitPos = 0; + + FAPI_INF("Found %i MBA chiplets", vector_targets.size()); + + // Iterate through the returned chiplets + for (uint32_t i = 0; i < vector_targets.size(); i++) + { + // Find the position of the MBA chiplet + rc=FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &vector_targets[i], l_unitPos); + + if (rc) + { + FAPI_ERR("Error getting ATTR_CHIP_UNIT_POS for MBA"); + return (rc); + } + else + { + std::vector<Target> mba_cen_targets; + + FAPI_INF("MBA%i valid", l_unitPos); + + // push current mba target then centaur target + mba_cen_targets.push_back(vector_targets[i]); + mba_cen_targets.push_back(i_target); + + // run mba and phy initfiles... + // Call Hwp to execute the mba_if file + FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, mba_cen_targets, mba_if); + + if (rc) + { + FAPI_ERR(" !!! Error running MBA%i %s, RC = 0x%x", + l_unitPos, mba_if, static_cast<uint32_t>(rc)); + return (rc); + } + else + { + FAPI_INF("MBA%i initfile %s passed", l_unitPos, mba_if); + } + + // Call Hwp to execute the phy_if file + FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, mba_cen_targets, phy_if); + + if (rc) + { + FAPI_ERR(" !!! Error running MBA%i %s, RC = 0x%x", + l_unitPos, phy_if, static_cast<uint32_t>(rc)); + return (rc); + } + else + { + FAPI_INF("MBA%i PHY initfile %s passed", l_unitPos, phy_if); + } + } // end MBA/PHY fapiHwpExecInitFile + } // valid chip unit pos + } // found functional MBAs + + return (rc); +} + +} // extern "C" diff --git a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H new file mode 100644 index 000000000..6e1865528 --- /dev/null +++ b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H @@ -0,0 +1,79 @@ +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : mss_scominit.H +// *! DESCRIPTION : see additional comments below +// *! OWNER NAME : Menlo Wuu Email: menlowuu@us.ibm.com +// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com +// *! ADDITIONAL COMMENTS : +// +// Header file for mss_scominit. +// +//------------------------------------------------------------------------------ +// Don't forget to create CVS comments when you check in your changes! +//------------------------------------------------------------------------------ +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version:| Author: | Date: | Comment: +//---------|----------|---------|----------------------------------------------- +// 1.4 | menlowuu |20-JUN-12| added type to the typedef +// 1.3 | menlowuu |13-JUN-12| added & to reference i_target in FP_t function +// added comment expecting centaur target +// 1.2 | menlowuu |06-JUN-12| Removed char* parameter for function +// 0.1 | menlowuu |01-DEC-11| First Draft. + + +#ifndef MSS_SCOMINIT_H_ +#define MSS_SCOMINIT_H_ + +//---------------------------------------------------------------------- +// My Includes +//---------------------------------------------------------------------- + + +//---------------------------------------------------------------------- +// Includes +//---------------------------------------------------------------------- +#include <fapi.H> + +typedef fapi::ReturnCode (*mss_scominit_FP_t)(const fapi::Target & i_target); + +extern "C" { + +//****************************************************************************** +// mss_scominit +//****************************************************************************** +// mss_scominit procedure [Calls the vaious memory initfiles] +// param[in] i_target [Reference to target, expecting centaur(MEMBUF) target] +// return ReturnCode + +fapi::ReturnCode mss_scominit(const fapi::Target & i_target); + +} // extern "C" + +#endif // MSS_SCOMINIT_H_ |