diff options
Diffstat (limited to 'src/import/chips/p9/common')
5 files changed, 133 insertions, 20 deletions
diff --git a/src/import/chips/p9/common/include/p9_frequency_buckets.H b/src/import/chips/p9/common/include/p9_frequency_buckets.H index ab6af1b5d..2ac8574d5 100644 --- a/src/import/chips/p9/common/include/p9_frequency_buckets.H +++ b/src/import/chips/p9/common/include/p9_frequency_buckets.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -65,6 +65,30 @@ const uint32_t MEM_PLL_FREQ_LIST[MEM_PLL_FREQ_BUCKETS] = 2666 }; +// OMI bucket descriptor +struct OmiBucketDescriptor_t +{ + uint32_t omifreq; // OMI Frequency in MHz + uint32_t vco; // VCO selector + + uint32_t mcafreq; // MCA Frequency in MHz +}; + +//MC PLL frequency in MHz for Axone +// index is bucket number +// OMI -> ATTR_FREQ_OMI_MHZ +// VCO -> ATTR_OMI_PLL_VCO +// MCA -> ATTR_FREQ_MCA_MHZ +const OmiBucketDescriptor_t OMI_PLL_FREQ_LIST[MEM_PLL_FREQ_BUCKETS] = +{ + // OMI VCO MCA Data rate + { 19200, 0, 1200 }, // ->DDR4-2400 + { 21330, 0, 1333 }, // ->DDR4-2667 + { 23460, 0, 1466 }, // ->DDR4-2933 + { 23460, 1, 1466 }, // ->DDR4-2933 + { 25600, 1, 1600 } // ->DDR4-3200 +}; + // constant definining number of OBUS PLL frequency options ('buckets') // to be built into unsigned HW image const uint8_t OBUS_PLL_FREQ_BUCKETS = 3; diff --git a/src/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h b/src/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h index b8d4c030e..0a51fbca3 100644 --- a/src/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h +++ b/src/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h @@ -41,7 +41,8 @@ extern "C" { #endif -#define HCODE_OCC_SHARED_MAGIC_NUMBER 0x4F505330 //OPS0 +#define HCODE_OCC_SHARED_MAGIC_NUMBER_OPS0 0x4F505330 //OPS0 +#define HCODE_OCC_SHARED_MAGIC_NUMBER_OPS1 0x4F505331 //OPS1 //--------------- // IPC from 405 @@ -409,17 +410,9 @@ typedef struct // ----------------------------------------------------------------------------- // Start Error Log Table -/// Maximum number of error log entries available -#define MAX_HCODE_ELOG_ENTRIES 4 - -/// Index into the array of error log entries -enum elog_entry_index -{ - ELOG_PGPE_CRITICAL = 0, - ELOG_PGPE_INFO = 1, - ELOG_SGPE_CRITICAL = 2, - ELOG_SGPE_INFO = 3, -}; +/// Maximum number of error log entries available, 1 UE per SPGE & PGPE +#define MAX_HCODE_ELOG_ENTRIES 2 +#define HCODE_ELOG_TABLE_MAGIC_WORD 0x454C5443 // "ELTC" /// Structure of an individual error log entry typedef struct @@ -461,7 +454,7 @@ typedef struct hcode_error_table } fields; } dw0; - /// Array of error log entries (index with enum elog_entry_index) + /// Array of error log entries hcode_elog_entry_t elog[MAX_HCODE_ELOG_ENTRIES]; } hcode_error_table_t; @@ -491,9 +484,6 @@ typedef struct //PGPE WOF Values pgpe_wof_values_t pgpe_wof_values; - //Reserved - uint64_t reserved1; - /// Hcode Error Log Index hcode_error_table_t errlog_idx; diff --git a/src/import/chips/p9/common/scominfo/p9_cu.H b/src/import/chips/p9/common/scominfo/p9_cu.H index 620e072a9..180828620 100644 --- a/src/import/chips/p9/common/scominfo/p9_cu.H +++ b/src/import/chips/p9/common/scominfo/p9_cu.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -68,7 +68,8 @@ extern "C" PU_PPE_CHIPUNIT, ///< PPE PU_SBE_CHIPUNIT, ///< SBE PU_CAPP_CHIPUNIT, ///< CAPP - PU_MC_CHIPUNIT, ///< mc + PU_MC_CHIPUNIT, ///< mc + PU_NPU_CHIPUNIT, ///< NPU NONE, ///< None/Invalid } p9ChipUnits_t; diff --git a/src/import/chips/p9/common/scominfo/p9_scom_addr.H b/src/import/chips/p9/common/scominfo/p9_scom_addr.H index 513cf0db6..b3d1186c0 100644 --- a/src/import/chips/p9/common/scominfo/p9_scom_addr.H +++ b/src/import/chips/p9/common/scominfo/p9_scom_addr.H @@ -452,6 +452,13 @@ extern "C" P9A_MC_OMI2_FRST_LANE = 0x10, ///< First lane of OMI % 3 = 2 } p9a_mc_lane_t; + typedef enum + { + P9A_NPU_2_RING_ID = 0x7, + P9A_NPU_2_FIR_RING_ID = 0x8, + P9A_NPU_0_FIR_RING_ID = 0xF, + } p9a_npu_ring_id_t; + // 8 7 6 5 4 3 2 1 // // |0 1 2 3| |4 5 6 7| |8 9 10 11| |12 13 14 15| |16 17 18 19| |20 21 22 23| |24 25 26 27| |28 29 30 31| diff --git a/src/import/chips/p9/common/scominfo/p9_scominfo.C b/src/import/chips/p9/common/scominfo/p9_scominfo.C index 0039625ca..ff80a3161 100644 --- a/src/import/chips/p9/common/scominfo/p9_scominfo.C +++ b/src/import/chips/p9/common/scominfo/p9_scominfo.C @@ -646,6 +646,66 @@ extern "C" break; + case PU_NPU_CHIPUNIT: + + // NPU0 and NPU1 exist on the N3 chiplet, NPU2 exists on the N1 chiplet instead + l_chiplet_id = ( 2 == i_chipUnitNum ) ? N1_CHIPLET_ID : N3_CHIPLET_ID ; + l_scom.set_chiplet_id( l_chiplet_id ); + + // Covers the following addresses: + // NPU0: 05011000 to 050113FF + // NPU1: 05011400 to 050117FF + // NPU2: 03011C00 to 03011FFF + if ( N3_NPU_0_RING_ID == l_ring || + N3_NPU_1_RING_ID == l_ring || + P9A_NPU_2_RING_ID == l_ring ) + { + // NPU0/NPU1 + if ( N3_CHIPLET_ID == l_chiplet_id ) + { + l_scom.set_ring( N3_NPU_0_RING_ID + i_chipUnitNum ); + } + // NPU2 + else if ( N1_CHIPLET_ID == l_chiplet_id ) + { + l_scom.set_ring( P9A_NPU_2_RING_ID ); + } + else + { + l_scom.set_addr( FAILED_TRANSLATION ); + } + } + // Covers the following addresses: + // NPU0: 05013C00 to 05013C8F + // NPU1: 05013CC0 to 05013D4F + // NPU2: 03012000 to 0301208F + else if ( P9A_NPU_0_FIR_RING_ID == l_ring || + P9A_NPU_2_FIR_RING_ID == l_ring ) + { + // NPU0/NPU1 + if ( N3_CHIPLET_ID == l_chiplet_id ) + { + l_scom.set_ring( P9A_NPU_0_FIR_RING_ID ); + l_scom.set_sat_id( (l_sat_id % 3) + (3 * i_chipUnitNum) ); + } + // NPU2 + else if ( N1_CHIPLET_ID == l_chiplet_id ) + { + l_scom.set_ring( P9A_NPU_2_FIR_RING_ID ); + l_scom.set_sat_id( l_sat_id % 3 ); + } + else + { + l_scom.set_addr( FAILED_TRANSLATION ); + } + } + else + { + l_scom.set_addr( FAILED_TRANSLATION ); + } + + break; + default: l_scom.set_addr(FAILED_TRANSLATION); break; @@ -1179,7 +1239,7 @@ extern "C" } } - if (P9A_MC_OMIC0_PPE_RING_ID <= l_ring && l_ring < P9A_MC_OMIC2_PPE_RING_ID && l_port == UNIT_PORT_ID) + if (P9A_MC_OMIC0_PPE_RING_ID <= l_ring && l_ring <= P9A_MC_OMIC2_PPE_RING_ID && l_port == UNIT_PORT_ID) { o_chipUnitRelated = true; o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_OMIC_CHIPUNIT, @@ -1498,6 +1558,37 @@ extern "C" o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_PPE_CHIPUNIT, (l_chiplet_id - OB0_CHIPLET_ID) + PPE_IO_OB0_CHIPUNIT_NUM)); } + + // PU_NPU_CHIPUNIT + // npu: 0..1 + if ( (l_port == UNIT_PORT_ID) && + (l_chiplet_id == N3_CHIPLET_ID) && + (N3_NPU_0_RING_ID <= l_ring && l_ring <= N3_NPU_1_RING_ID) ) + { + o_chipUnitRelated = true; + o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_NPU_CHIPUNIT, + (l_ring - N3_NPU_0_RING_ID))); + } + + if ( (l_port == UNIT_PORT_ID) && + (l_chiplet_id == N3_CHIPLET_ID) && + (l_ring == P9A_NPU_0_FIR_RING_ID) ) + { + o_chipUnitRelated = true; + o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_NPU_CHIPUNIT, + (l_sat_id / 3))); + } + + // PU_NPU_CHIPUNIT + // npu: 2 + if ( (l_port == UNIT_PORT_ID) && + (l_chiplet_id == N1_CHIPLET_ID) && + (l_ring == P9A_NPU_2_RING_ID || l_ring == P9A_NPU_2_FIR_RING_ID) ) + { + o_chipUnitRelated = true; + o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_NPU_CHIPUNIT, 2)); + } + } return (!l_scom.is_valid()); |
