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| author | Greg Still <stillgs@us.ibm.com> | 2016-10-18 13:05:21 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-06-22 22:42:14 -0400 |
| commit | fa9c9af4022ae80421c377867dabf6fb1dd1e22b (patch) | |
| tree | f060b8445fb89503c79155cf02ff4b932e0ccc3c /src | |
| parent | fbfac0cc3be29fc556128a95859ef3a3318e915f (diff) | |
| download | talos-hostboot-fa9c9af4022ae80421c377867dabf6fb1dd1e22b.tar.gz talos-hostboot-fa9c9af4022ae80421c377867dabf6fb1dd1e22b.zip | |
p9_ppe_commands: add -step_trap support
Change-Id: I734f2cafae2d6cb67b909459b80266052a988542
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31451
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42287
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/lib/p9_ppe_utils.H | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_ppe_utils.H b/src/import/chips/p9/procedures/hwp/lib/p9_ppe_utils.H index 03c3cfacf..656e2da9d 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_ppe_utils.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_ppe_utils.H @@ -64,12 +64,12 @@ typedef struct /** * @brief Offsets from base address for XIRs. */ -const static uint64_t PPE_XIXCR = 0x0; -const static uint64_t PPE_XIRAMRA = 0x1; -const static uint64_t PPE_XIRAMGA = 0x2; -const static uint64_t PPE_XIRAMDBG = 0x3; -const static uint64_t PPE_XIRAMEDR = 0x4; -const static uint64_t PPE_XIDBGPRO = 0x5; +const static uint64_t PPE_XIXCR = 0x0; //XCR_NONE +const static uint64_t PPE_XIRAMRA = 0x1; //XCR_SPRG0 +const static uint64_t PPE_XIRAMGA = 0x2; //IR_SPRG0 +const static uint64_t PPE_XIRAMDBG = 0x3; //XSR_SPRG0 +const static uint64_t PPE_XIRAMEDR = 0x4; //IR_EDR +const static uint64_t PPE_XIDBGPRO = 0x5; //XSR_IAR enum PPE_DUMP_MODE { |
