diff options
author | Thi Tran <thi@us.ibm.com> | 2012-12-07 13:50:38 -0600 |
---|---|---|
committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2012-12-19 08:53:04 -0600 |
commit | f94a72b34c65ee2ab3e4d736f1c334159af99d58 (patch) | |
tree | 461a77e4e2b9b8d9de1e8bb950dcba4c67fe9272 /src | |
parent | d00706a9f8869af321b4ddb3dea0106d19cea312 (diff) | |
download | talos-hostboot-f94a72b34c65ee2ab3e4d736f1c334159af99d58.tar.gz talos-hostboot-f94a72b34c65ee2ab3e4d736f1c334159af99d58.zip |
Implementing io_dccal HWP to HostBoot
RTC: 41360
Change-Id: I04982bfdc11e7500106c95b7731927fe3e500cd7
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2598
Tested-by: Jenkins Server
Reviewed-by: Brian H. Horton <brianh@linux.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/include/usr/hwpf/istepreasoncodes.H | 6 | ||||
-rw-r--r-- | src/usr/hwpf/hwp/bus_training/io_dccal.C | 503 | ||||
-rw-r--r-- | src/usr/hwpf/hwp/bus_training/io_dccal.H | 54 | ||||
-rw-r--r-- | src/usr/hwpf/hwp/bus_training/makefile | 3 | ||||
-rw-r--r-- | src/usr/hwpf/hwp/dmi_training/dmi_io_dccal/dmi_io_dccal.C | 32 | ||||
-rw-r--r-- | src/usr/hwpf/hwp/dmi_training/dmi_io_dccal/dmi_io_dccal.H | 35 | ||||
-rw-r--r-- | src/usr/hwpf/hwp/dmi_training/dmi_training.C | 351 | ||||
-rw-r--r-- | src/usr/hwpf/hwp/dmi_training/makefile | 5 | ||||
-rw-r--r-- | src/usr/hwpf/hwp/edi_ei_initialization/edi_ei_initialization.C | 138 | ||||
-rwxr-xr-x | src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_dccal/fabric_io_dccal.C | 32 | ||||
-rwxr-xr-x | src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_dccal/fabric_io_dccal.H | 35 | ||||
-rw-r--r-- | src/usr/hwpf/hwp/edi_ei_initialization/makefile | 6 |
12 files changed, 1044 insertions, 156 deletions
diff --git a/src/include/usr/hwpf/istepreasoncodes.H b/src/include/usr/hwpf/istepreasoncodes.H index f0db7365c..f79326448 100644 --- a/src/include/usr/hwpf/istepreasoncodes.H +++ b/src/include/usr/hwpf/istepreasoncodes.H @@ -111,6 +111,8 @@ enum istepModuleId ISTEP_FABRIC_IO_RESTORE_EREPAIR = 0x3E, ISTEP_VDDR_ENABLE = 0x3F, ISTEP_VDDR_DISABLE = 0x40, + ISTEP_DMI_IO_DCCAL = 0x41, + ISTEP_FABRIC_IO_DCCAL = 0x42, }; /** @@ -155,6 +157,10 @@ enum istepReasonCode ISTEP_DMI_GET_RESTORE_LANES_FAILED = ISTEP_COMP_ID | 0x1F, ISTEP_FABRIC_GET_RESTORE_LANES_FAILED = ISTEP_COMP_ID | 0x20, ISTEP_GET_PBUS_CONNECTIONS_FAILED = ISTEP_COMP_ID | 0x21, + ISTEP_DMI_IO_DCCAL_MCS_FAILED = ISTEP_COMP_ID | 0x22, + ISTEP_DMI_IO_DCCAL_MEMBUF_FAILED = ISTEP_COMP_ID | 0x23, + ISTEP_FABRIC_IO_DCCAL_ENDPOINT1_FAILED = ISTEP_COMP_ID | 0x24, + ISTEP_FABRIC_IO_DCCAL_ENDPOINT2_FAILED = ISTEP_COMP_ID | 0x25, }; // end ISTEP } diff --git a/src/usr/hwpf/hwp/bus_training/io_dccal.C b/src/usr/hwpf/hwp/bus_training/io_dccal.C new file mode 100644 index 000000000..1c9386710 --- /dev/null +++ b/src/usr/hwpf/hwp/bus_training/io_dccal.C @@ -0,0 +1,503 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/bus_training/io_dccal.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: io_dccal.C,v 1.14 2012/12/07 13:43:57 varkeykv Exp $
+// *!***************************************************************************
+// *! (C) Copyright International Business Machines Corp. 1997, 1998
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *!***************************************************************************
+// *! FILENAME : io_dccal.C
+// *! TITLE :
+// *! DESCRIPTION : Impedance & offset calibration
+// *! CONTEXT :
+// *!
+// *! OWNER NAME : Varghese, Varkey Email: varkey.kv@in.ibm.com
+// *! BACKUP NAME : Swaminathan, Janani Email: jaswamin@in.ibm.com
+// *!
+// *!***************************************************************************
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|Author: | Date: | Comment:
+// --------|--------|--------|--------------------------------------------------
+// 1.0 |varkeykv|09/27/11|Initial check in . Have to modify targets once bus target is defined and available.Not tested in any way other than in unit SIM IOTK
+// 1.1 |varkeykv |17/11/11|Code cleanup . Fixed header files. Changed fAPI API
+//------------------------------------------------------------------------------
+
+#include <fapi.H>
+#include "io_dccal.H"
+#include "gcr_funcs.H"
+
+extern "C" {
+
+
+using namespace fapi;
+
+int binStrToInt(char *str,uint32_t length) {
+ int i = 0;
+ for ( uint32_t j = 0; j <length; j++ ) {
+ char c = str[j];
+ if ( c == '0' ) {
+ i = (i << 1);
+ } else {
+ i = (i << 1) | 0x1;
+ }
+ }
+ return i;
+}
+
+uint32_t BinaryRound(uint32_t val, uint32_t numTruncBits, uint32_t center) {
+ // Round val by removing numTruncBits
+ // If the truncated fraction is exactly 0.5, round
+ // toward center
+ uint32_t newVal = 0x0;
+
+ uint32_t mask = 0x0;
+ for (uint32_t i = 0; i < numTruncBits; i++) {
+ mask = (mask << 1) + 0x1;
+ }
+
+ uint32_t half = 0x1 << (numTruncBits-1);
+
+ if ( (val & mask) > half ) {
+ newVal = (val >> numTruncBits) + 1; // round up
+ } else if ( (val & mask) < half ) {
+ newVal = (val >> numTruncBits); // round down
+ } else {
+ // On the boundary! Round towards the nominal value
+ if ( val < (center << numTruncBits) ) {
+ newVal = (val >> numTruncBits) + 1; // round up
+ } else {
+ newVal = (val >> numTruncBits); // round down
+ }
+ }
+
+ return newVal;
+}
+
+
+// Offset cal doesnt do anything in VBU/sim ...
+ReturnCode run_offset_cal(const Target &target,io_interface_t master_interface,uint32_t master_group){
+// Assuming I will receive a target and slave_target from the Invoker.
+ ReturnCode rc;
+ uint32_t rc_ecmd=0;
+ uint16_t bits = 0;
+ ecmdDataBufferBase data_buffer;
+
+ ecmdDataBufferBase set_bits(16);
+ ecmdDataBufferBase clear_bits(16);
+ io_interface_t chip_interface=master_interface;//first we run on master chip
+ uint32_t group=master_group;
+ const Target *target_ptr=⌖ // Assuming I am allowed to do this .
+
+ for(int i=0;i<2;++i){ // master and slave side looper
+ FAPI_DBG("IO_DCCAL : Starting Offset Calibration on interface %d group %d",chip_interface,group);
+ bits=rx_start_offset_cal;
+ rc_ecmd|=set_bits.insert(bits,0,16);
+ bits=rx_start_offset_cal_clear;
+ rc_ecmd|=clear_bits.insert(bits,0,16);
+ if(rc_ecmd)
+ {
+ rc.setEcmdError(rc_ecmd);
+ return(rc);
+ }
+ rc=GCR_write(*target_ptr,chip_interface,rx_training_start_pg,group,0,set_bits ,clear_bits);if (rc) {return(rc);}
+
+ // Poll for the done bit
+ rc=GCR_read(*target_ptr,master_interface,rx_training_status_pg ,group,0,data_buffer);if (rc) {return(rc);} // have to add support for field parsing
+
+ int done_bit=rx_offset_cal_done;
+ int fail_bit=rx_offset_cal_failed;
+ bool fail= data_buffer.getHalfWord(0) & fail_bit;
+ bool done = data_buffer.getHalfWord(0)& done_bit;
+ int timeoutCnt = 0;
+ while ( ( !done ) && ( timeoutCnt < 150 ) && !fail )
+ {
+ // wait for 80000 time units
+ // Time units may be something for simulation, and something else (or nothing) for hardware
+ // At any rate, this is intended to be approximately 100 us.
+ rc=GCR_read(*target_ptr,chip_interface,rx_training_status_pg,group,0,data_buffer); if (rc) {return(rc);}// have to add support for field parsing
+ fail= data_buffer.getHalfWord(0) & fail_bit;
+ done = data_buffer.getHalfWord(0)& done_bit;
+ fapiDelay(1000000,1000000);
+ timeoutCnt++;
+ }
+
+ if ( fail)
+ {
+ FAPI_ERR("IO Offset cal error on interface %d",chip_interface);
+ //Set HWP error
+ FAPI_SET_HWP_ERROR(rc,IO_DCCAL_OFFCAL_ERROR_RC);
+ return rc;
+ }
+ // Check for errors
+ else if ( timeoutCnt >= 100 && !done && !fail )
+ {
+ FAPI_ERR("Timed out waiting for Done bit to be set");
+ //Set HWP error
+ FAPI_SET_HWP_ERROR(rc,IO_DCCAL_OFFCAL_TIMEOUT_RC);
+ return rc;
+ }
+ else
+ {
+ FAPI_DBG("IO Offset cal Completed on interface %d",chip_interface);
+ }
+ }
+ return(rc);
+}
+
+ReturnCode run_zcal_debug(const Target& target,io_interface_t interface,uint32_t group)
+{
+ ReturnCode rc;
+ ecmdDataBufferBase data_buffer(16);
+ rc=GCR_read(target,interface,tx_impcal_nval_pb,group,0,data_buffer);if (rc) {return(rc);} // have to add support for field parsing
+ rc=GCR_read(target,interface,tx_impcal_pval_pb,group,0,data_buffer);if (rc) {return(rc);} // have to add support for field parsing
+ rc=GCR_read(target,interface,tx_impcal_p_4x_pb,group,0,data_buffer);if (rc) {return(rc);} // have to add support for field parsing
+ return rc;
+}
+
+ReturnCode run_zcal(const Target& target,io_interface_t master_interface,uint32_t master_group){
+ ReturnCode rc;
+ const Target *target_ptr=⌖ // Assuming I am allowed to do this .
+ uint32_t m=128; // MARGIN RATIO
+ uint32_t k2=0; // POST CURSOR DRIVE RATIO
+ bool swOverride=false;// IS SW_OVERRIDE requested
+ uint16_t bits = 0;
+ uint32_t rc_ecmd=0;
+ ecmdDataBufferBase set_bits(16);
+ ecmdDataBufferBase clear_bits(16);
+ ecmdDataBufferBase data_buffer(16);
+ rc_ecmd|=set_bits.flushTo0();
+ rc_ecmd|=clear_bits.flushTo1(); // I dont want to clear anything by default
+ if(rc_ecmd)
+ {
+ rc.setEcmdError(rc_ecmd);
+ return(rc);
+ }
+ io_interface_t chip_interface=master_interface;//first we run on master chip
+ uint32_t group=master_group;
+ // Get all the input attributes from PLAT
+ /*
+ Need to check if these attributes are required or not
+ rc = FAPI_ATTR_GET(ATTR_IOD_MARGIN_RATIO, &target, m); // Fetch the attribute for the chip we are working on
+ rc = FAPI_ATTR_GET(ATTR_IOD_POST_CURSOR_DRIVER_RATIO, &target, k2);
+ // Find if we are in SW_OVERRIDE mode
+ rc = FAPI_ATTR_GET(ATTR_IOD_ZCAL_SW_OVERRIDE, &target, swOverride);
+ */
+
+ const uint32_t min = (10<<3); // impcntl min - - p8 - 10<<3
+ const uint32_t max = (40<<3); // impcntl max - - p8 - 40<<3
+
+ uint32_t zcal_p = 0;
+ uint32_t zcal_n = 0;
+
+ uint32_t zcal_override = 0;
+
+ if ((zcal_n>0) && (zcal_p>0) )
+ {
+ zcal_override = 1;
+ }
+
+ if ( k2 > 0x20 ) {
+ FAPI_DBG("POST CURSOR DRIVER RATIO k2 has exceeded 0.25");
+ FAPI_SET_HWP_ERROR(rc,IO_DCCAL_ZCAL_K2_EXCEEDED_RC);
+ return rc;
+ }
+
+ if ( m > 0x80 ) {
+ FAPI_DBG("MARGIN RATIO m has exceeded 100 percent");
+ FAPI_SET_HWP_ERROR(rc,IO_DCCAL_ZCAL_M_EXCEEDED_RC);
+ return rc;
+ }
+
+ //if ( m < 0x40 ) {
+ // FAPI_DBG("MARGIN RATIO m is less than 50 percent");
+ // FAPI_SET_HWP_ERROR(rc,IO_DCCAL_ZCAL_M_LOW_RC);
+ // return rc;
+ //}
+ if ( ( ! zcal_override ) && ( ! swOverride ) )
+ {
+
+ FAPI_DBG("IO_DCCAL : Starting Impedance Calibration ");
+ //Get initial settings for debug purpose
+ run_zcal_debug(*target_ptr,chip_interface,group);
+ // Need to first set start bit to 0 to enable rise to 1 transition , also skip readback since this is WO field
+ rc=GCR_write(*target_ptr,chip_interface,tx_impcal_pb,group,0,set_bits,clear_bits,true);if (rc) {return(rc);}
+ bits=tx_zcal_req;
+ rc_ecmd|=set_bits.insert(bits,0,16);
+ bits=tx_zcal_req_clear;
+ rc_ecmd|=clear_bits.insert(bits,0,16);
+ if(rc_ecmd)
+ {
+ rc.setEcmdError(rc_ecmd);
+ return(rc);
+ }
+ // Skip a readback and verify
+ rc=GCR_write(*target_ptr,chip_interface,tx_impcal_pb,group,0,set_bits,clear_bits,true);if (rc) {return(rc);}
+ // Poll for the done bit
+ rc=GCR_read(*target_ptr,chip_interface,tx_impcal_pb,group,0,data_buffer);if (rc) {return(rc);} // have to add support for field parsing
+ int done_bit=tx_zcal_done;
+ int fail_bit=tx_zcal_error;
+ bool fail= data_buffer.getHalfWord(0) & fail_bit;
+ bool done = data_buffer.getHalfWord(0)& done_bit;
+ int timeoutCnt = 0;
+ while ( ( !done ) && ( timeoutCnt <150 ) ) {
+ // wait for 80000 time units
+ // Time units may be something for simulation, and something else (or nothing) for hardware
+ // At any rate, this is intended to be approximately 100 us.
+ rc=GCR_read(*target_ptr,chip_interface,tx_impcal_pb,group,0,data_buffer); if (rc) {return(rc);}// have to add support for field parsing
+ done = data_buffer.getHalfWord(0)& done_bit;
+ fail= data_buffer.getHalfWord(0) & fail_bit;
+ fapiDelay(10000,10000000); //Wait around for HW
+ timeoutCnt++;
+ }
+ if(fail)
+ {
+ FAPI_DBG("IO Impedance cal error on interface %d ",chip_interface);
+ run_zcal_debug(*target_ptr,chip_interface,group);
+ //set HWP error
+ FAPI_SET_HWP_ERROR(rc,IO_DCCAL_ZCAL_ERROR_RC);
+ return(rc);
+
+ }
+ // Check for errors
+ else if ( timeoutCnt >= 100 &&!done && !fail )
+ {
+ FAPI_DBG("Timed out waiting for Done bit to be set");
+ //set HWP error
+ FAPI_SET_HWP_ERROR(rc,IO_DCCAL_ZCAL_TIMEOUT_RC);
+ return rc;
+ }
+ else
+ {
+ FAPI_DBG("IO Impedance cal DONE successfully on interface %d",chip_interface);
+ }
+
+
+ // Read the calculated values
+ // (Values are: xxxxxx yy zz, where yy are 2R and 4R values, and zz is a binary fraction)
+ rc=GCR_read(*target_ptr,chip_interface,tx_impcal_nval_pb,group,0,data_buffer);if (rc) {return(rc);} // have to add support for field parsing
+ data_buffer.extractToRight(&zcal_n,0,9);
+ rc=GCR_read(*target_ptr,chip_interface,tx_impcal_pval_pb,group,0,data_buffer);if (rc) {return(rc);} // have to add support for field parsing
+ data_buffer.extractToRight(&zcal_p,0,9);
+
+ }
+ else if ( swOverride )
+ {
+ /*
+ Software override might be required in case of workarounds to HW
+ */
+ }
+
+ if ( ( (uint32_t)zcal_n < min )|| ( (uint32_t)zcal_n > max ) )
+ {
+ FAPI_ERR("zcal_n value is out of impcntl range");
+ FAPI_SET_HWP_ERROR(rc, IO_DCCAL_ZCALN_VALUE_OUT_OF_RANGE_RC);
+ return rc;
+ }
+ if ( ( (uint32_t)zcal_p < min )|| ( (uint32_t)zcal_p > max ) )
+ {
+ FAPI_ERR("zcal_p value is out of impcntl range");
+ FAPI_SET_HWP_ERROR(rc, IO_DCCAL_ZCALP_VALUE_OUT_OF_RANGE_RC);
+ return rc;
+ }
+
+ // margin = (1 -m)*zcal/2
+ // bits: 7 10
+ uint32_t margin_p = (0x80 - m) * zcal_p / 2; // 7+2 = 9 binary decimal places // when it is 1 - something should it not be 0x01 - m?
+ uint32_t margin_n = (0x80 - m) * zcal_n / 2; // 7+2 = 9 binary decimal places
+
+ // postcursor = (zcal - 2*margin)*k2
+ // bits: 7 7 10
+ uint32_t post_p = (zcal_p - (margin_p<<1))*k2; // 7+7+2 = 16 binary decimal places
+ uint32_t post_n = (zcal_n - (margin_n<<1))*k2; // 7+7+2 = 16 binary decimal places
+
+ uint32_t main_p = (zcal_p - (margin_p<<1))- post_p; // 2 binary decimal places
+ uint32_t main_n = (zcal_n - (margin_n<<1))- post_n; // 2 binary decimal places
+
+
+ // Rounding
+ post_p = BinaryRound(post_p, 16, 999); // round up
+ post_n = BinaryRound(post_n, 16, 999); // round up
+ margin_p = BinaryRound(margin_p, 9, 999); // round up
+ margin_n = BinaryRound(margin_n, 9, 999); // round up
+ main_p = BinaryRound(main_p, 2, 999); // round up
+ main_n = BinaryRound(main_n, 2, 999); // round up
+
+ FAPI_DBG("main_p value %d",main_p);
+ FAPI_DBG("post_p value %d",post_p);
+ FAPI_DBG("margin_p value %d",margin_p);
+ FAPI_DBG("main_n value %d",main_n);
+ FAPI_DBG("post_n value %d",post_n);
+ FAPI_DBG("margin_n value %d",margin_n);
+
+ //p segments
+ rc_ecmd|=set_bits.insert(main_p,0,7,25);
+ bits=tx_ffe_main_p_enc_clear;
+ rc_ecmd|=clear_bits.insert(bits,0,16);
+ if(rc_ecmd)
+ {
+ rc.setEcmdError(rc_ecmd);
+ return(rc);
+ }
+ rc=GCR_write(*target_ptr,chip_interface,tx_ffe_main_pg ,group,0,set_bits,clear_bits);if (rc) {return(rc);}
+ rc_ecmd|=set_bits.insert(post_p,0,5,27);
+ bits=tx_ffe_post_p_enc_clear;
+ rc_ecmd|=clear_bits.insert(bits,0,16);
+ if(rc_ecmd)
+ {
+ rc.setEcmdError(rc_ecmd);
+ return(rc);
+ }
+ rc=GCR_write(*target_ptr,chip_interface,tx_ffe_post_pg ,group,0,set_bits,clear_bits);if (rc) {return(rc);}
+ rc_ecmd|=set_bits.insert(margin_p,0,5,27);
+ bits=tx_ffe_margin_p_enc_clear;
+ rc_ecmd|=clear_bits.insert(bits,0,16);
+ if(rc_ecmd)
+ {
+ rc.setEcmdError(rc_ecmd);
+ return(rc);
+ }
+ rc=GCR_write(*target_ptr,chip_interface,tx_ffe_margin_pg ,group,0,set_bits,clear_bits);if (rc) {return(rc);}
+
+ //N segments
+ rc_ecmd|=set_bits.insert(main_n,0,7,25);
+ bits=tx_ffe_main_n_enc_clear;
+ rc_ecmd|=clear_bits.insert(bits,0,16);
+ if(rc_ecmd)
+ {
+ rc.setEcmdError(rc_ecmd);
+ return(rc);
+ }
+ rc=GCR_write(*target_ptr,chip_interface,tx_ffe_main_pg ,group,0,set_bits,clear_bits);if (rc) {return(rc);}
+ rc_ecmd|=set_bits.insert(post_n,0,5,27);
+ bits=tx_ffe_post_n_enc_clear;
+ rc_ecmd|=clear_bits.insert(bits,0,16);
+ if(rc_ecmd)
+ {
+ rc.setEcmdError(rc_ecmd);
+ return(rc);
+ }
+ rc=GCR_write(*target_ptr,chip_interface,tx_ffe_post_pg ,group,0,set_bits,clear_bits);if (rc) {return(rc);}
+ rc_ecmd|=set_bits.insert(margin_n,0,5,27);
+ bits=tx_ffe_margin_n_enc_clear;
+ rc_ecmd|=clear_bits.insert(bits,0,16);
+ if(rc_ecmd)
+ {
+ rc.setEcmdError(rc_ecmd);
+ return(rc);
+ }
+ rc=GCR_write(*target_ptr,chip_interface,tx_ffe_margin_pg ,group,0,set_bits,clear_bits);if (rc) {return(rc);}
+
+
+ return rc;
+}
+
+// Determines if target is a master ..I had assumed that PLAT wrapper code will know which side is master and which is slave
+ReturnCode isChipMaster(const Target& chip_target, io_interface_t chip_interface,uint32_t current_group, bool & masterchip_found ) {
+ ReturnCode rc;
+ ecmdDataBufferBase mode_data(16);
+ masterchip_found=false;
+
+ // Check if rx_master_mode bit is set for chip
+ // Read rx_master_mode for chip
+ if(chip_interface==CP_FABRIC_X0)
+ {
+ rc=GCR_read(chip_target , chip_interface, ei4_rx_mode_pg, current_group,0, mode_data);
+ }
+ else
+ {
+ rc=GCR_read(chip_target , chip_interface, rx_mode_pg, current_group,0, mode_data);
+ }
+ if (rc) {
+ FAPI_DBG("io_run_training: Error reading master mode bit\n");
+ }
+ // Check if chip is master
+ if (mode_data.isBitSet(0)) {
+ FAPI_DBG("This chip is a master\n");
+ masterchip_found =true;
+ }
+ return(rc);
+}
+
+// These functions work on a pair of targets. One is the master side of the bus interface, the other the slave side. For eg; in EDI(DMI2)PU is the master and Centaur is the slave
+// In EI4 both sides have pu targets
+ReturnCode io_dccal(const Target& target){
+ ReturnCode rc;
+ io_interface_t master_interface=CP_IOMC0_P0;
+ uint32_t master_group=0;
+ FAPI_DBG("Running IO DCCAL PROCEDURE");
+ // This is a DMI/MC bus
+ if( (target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET )){
+ FAPI_DBG("This is a Processor DMI bus using base DMI scom address");
+ master_interface=CP_IOMC0_P0; // base scom for MC bus
+ master_group=3; // Design requires us to do this as per scom map and layout
+ // EDI/DMI needs both impedance cal and offset cal
+ // Z cal doesnt require group since its a per bus feature , but to satisfy PLAT swapped translation requirements we pass group=3 on master
+ rc=run_zcal(target,master_interface,master_group);if (rc) {return(rc);};
+ // Offset cal requires group address
+ rc=run_offset_cal(target,master_interface,master_group);if (rc) {return(rc);};
+ }
+ else if( (target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP)){
+ FAPI_DBG("This is a Centaur DMI bus using base DMI scom address");
+ master_interface=CEN_DMI; // base scom for CEN
+ master_group=0;
+ // EDI/DMI needs both impedance cal and offset cal
+ // Z cal doesnt require group since its a per bus feature , but to satisfy PLAT swapped translation requirements we pass group=3 on master
+ rc=run_zcal(target,master_interface,master_group);if (rc) {return(rc);};
+ // Offset cal requires group address
+ rc=run_offset_cal(target,master_interface,master_group);if (rc) {return(rc);};
+ }
+ //This is an X Bus
+ else if( (target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT )){
+ FAPI_DBG("This is a X Bus training invocation");
+ master_interface=CP_FABRIC_X0; // base scom for X bus
+ master_group=0; // Design requires us to do this as per scom map and layout
+ if(rc.ok()){
+ // No Z cal in EI4/X bus design
+ for(int i=0;i<5;++i){
+ master_group=i;
+ rc=run_offset_cal(target,master_interface,master_group);if (rc) {return(rc);};
+ }
+ }
+ }
+ //This is an A Bus
+ else if( (target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT )){
+ FAPI_DBG("This is an A Bus training invocation");
+ master_interface=CP_FABRIC_A0; // base scom for A bus , assume translation to A1 by PLAT
+ master_group=0; // Design requires us to do this as per scom map and layout
+ // EDI-A bus needs both impedance cal and offset cal
+ rc=run_zcal(target,master_interface,master_group);if (rc) {return(rc);};
+ rc=run_offset_cal(target,master_interface,master_group);if (rc) {return(rc);};
+ }
+ else{
+ FAPI_ERR("Invalid io_dccal HWP invocation . Target doesnt belong to DMI/X/A instances");
+ FAPI_SET_HWP_ERROR(rc, IO_DCCAL_INVALID_INVOCATION_RC);
+ }
+ return rc;
+}
+
+
+
+
+
+} //end extern C
diff --git a/src/usr/hwpf/hwp/bus_training/io_dccal.H b/src/usr/hwpf/hwp/bus_training/io_dccal.H new file mode 100644 index 000000000..d632f4a01 --- /dev/null +++ b/src/usr/hwpf/hwp/bus_training/io_dccal.H @@ -0,0 +1,54 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/bus_training/io_dccal.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: io_dccal.H,v 1.7 2012/11/27 08:43:45 varkeykv Exp $
+#ifndef IO_DCCAL_H_
+#define IO_DCCAL_H_
+
+#include <fapi.H>
+
+using namespace fapi;
+
+/**
+ * io_dccal HWP func pointer typedef
+ *
+ */
+typedef fapi::ReturnCode (*io_dccal_FP_t)(const fapi::Target &target);
+
+extern "C"
+{
+
+/**
+ * io_dccal HWP
+ *
+ * master_target is any IO target P8 MCS,XBUS,Abus or centaur
+ *
+ *
+ *
+ *
+ */
+
+fapi::ReturnCode io_dccal(const fapi::Target &target);
+
+} // extern "C"
+#endif // IO_DCCAL_H_
+
diff --git a/src/usr/hwpf/hwp/bus_training/makefile b/src/usr/hwpf/hwp/bus_training/makefile index 3fa717649..82c279c88 100644 --- a/src/usr/hwpf/hwp/bus_training/makefile +++ b/src/usr/hwpf/hwp/bus_training/makefile @@ -34,7 +34,8 @@ EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp ## pointer to common HWP files EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include -OBJS = gcr_funcs.o io_funcs.o io_run_training.o pbusLinkSvc.o proc_fab_smp.o +OBJS = gcr_funcs.o io_funcs.o io_run_training.o pbusLinkSvc.o proc_fab_smp.o \ + io_dccal.o ## NOTE: add a new directory onto the vpaths when you add a new HWP ## vpath %.C proc_cen_framelock:io_run_training diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_io_dccal/dmi_io_dccal.C b/src/usr/hwpf/hwp/dmi_training/dmi_io_dccal/dmi_io_dccal.C new file mode 100644 index 000000000..a79ac0e91 --- /dev/null +++ b/src/usr/hwpf/hwp/dmi_training/dmi_io_dccal/dmi_io_dccal.C @@ -0,0 +1,32 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/dmi_training/dmi_io_dccal/dmi_io_dccal.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +#include <fapi.H> +#include "io_dccal.H" + +extern "C" { + +ReturnCode dmi_io_dccal(const Target &master_target){ + return io_dccal(master_target); +} + +} // extern diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_io_dccal/dmi_io_dccal.H b/src/usr/hwpf/hwp/dmi_training/dmi_io_dccal/dmi_io_dccal.H new file mode 100644 index 000000000..c690e323d --- /dev/null +++ b/src/usr/hwpf/hwp/dmi_training/dmi_io_dccal/dmi_io_dccal.H @@ -0,0 +1,35 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/dmi_training/dmi_io_dccal/dmi_io_dccal.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef DMI_IO_DCCAL_H_ +#define DMI_IO_DCCAL_H_ + +using namespace fapi; + +extern "C" +{ + +fapi::ReturnCode dmi_io_dccal(const fapi::Target &master_target); + +} // extern "C" + +#endif // DMI_IO_DCCAL_H diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_training.C b/src/usr/hwpf/hwp/dmi_training/dmi_training.C index 92da34526..719c5eca3 100644 --- a/src/usr/hwpf/hwp/dmi_training/dmi_training.C +++ b/src/usr/hwpf/hwp/dmi_training/dmi_training.C @@ -69,9 +69,9 @@ #include "proc_cen_set_inband_addr.H" #include "mss_get_cen_ecid.H" #include "io_restore_erepair.H" - -// eRepair Restore #include <erepairAccessorHwpFuncs.H> +#include "dmi_io_dccal/dmi_io_dccal.H" +#include <pbusLinkSvc.H> namespace DMI_TRAINING { @@ -81,6 +81,12 @@ using namespace ISTEP_ERROR; using namespace ERRORLOG; using namespace TARGETING; using namespace fapi; +using namespace EDI_EI_INITIALIZATION; + +//***************************************************************** +// Function prototypes +//***************************************************************** +void get_dmi_io_targets(TargetPairs_t& o_dmi_io_targets); // @@ -582,14 +588,132 @@ void* call_dmi_erepair( void *io_pArgs ) // void* call_dmi_io_dccal( void *io_pArgs ) { - errlHndl_t l_err = NULL; + errlHndl_t l_errl = NULL; + ISTEP_ERROR::IStepError l_StepError; - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_io_dccal entry" ); + // We are not running this analog procedure in VPO + if (TARGETING::is_vpo()) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Skip dmi_io_dccal in VPO!"); + return l_StepError.getErrorHandle(); + } + // TODO: RTC 60627 + // Reinstate this to enable dmi_io_dccal + return l_StepError.getErrorHandle(); - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_io_dccal exit" ); + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_dmi_io_dccal entry" ); - return l_err; + TargetPairs_t l_dmi_io_dccal_targets; + get_dmi_io_targets(l_dmi_io_dccal_targets); + + + // Note: + // Due to lab tester board environment, HW procedure writer (Varkey) has + // requested to send in one target of a time (we used to send in + // the MCS and MEMBUF pair in one call). Even though they don't have to be + // in order, we should keep the pair concept here in case we need to send + // in a pair in the future again. + for (TargetPairs_t::iterator l_itr = l_dmi_io_dccal_targets.begin(); + l_itr != l_dmi_io_dccal_targets.end(); ++l_itr) + { + const fapi::Target l_fapi_mcs_target( + TARGET_TYPE_MCS_CHIPLET, + reinterpret_cast<void *> + (const_cast<TARGETING::Target*>(l_itr->first))); + + const fapi::Target l_fapi_membuf_target( + TARGET_TYPE_MEMBUF_CHIP, + reinterpret_cast<void *> + (const_cast<TARGETING::Target*>(l_itr->second))); + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "===== Call dmi_io_dccal HWP( mcs 0x%.8X, mem 0x%.8X) : ", + TARGETING::get_huid(l_itr->first), + TARGETING::get_huid(l_itr->second)); + + EntityPath l_path; + l_path = l_itr->first->getAttr<ATTR_PHYS_PATH>(); + l_path.dump(); + l_path = l_itr->second->getAttr<ATTR_PHYS_PATH>(); + l_path.dump(); + + // Call on the MCS + FAPI_INVOKE_HWP(l_errl, dmi_io_dccal, l_fapi_mcs_target); + + if (l_errl) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X : dmi_io_dccal HWP Target MCS 0x%.8X", + l_errl->reasonCode(), TARGETING::get_huid(l_itr->first)); + /*@ + * @errortype + * @reasoncode ISTEP_DMI_IO_DCCAL_MCS_FAILED + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid ISTEP_DMI_IO_DCCAL + * @userdata1 bytes 0-1: plid identifying first error + * bytes 2-3: reason code of first error + * @userdata2 bytes 0-1: total number of elogs included + * bytes 2-3: N/A + * @devdesc call to dmi_io_dccal on MCS has failed + */ + l_StepError.addErrorDetails(ISTEP_DMI_IO_DCCAL_MCS_FAILED, + ISTEP_DMI_IO_DCCAL, + l_errl); + + errlCommit( l_errl, HWPF_COMP_ID ); + // We want to continue the training despite the error, so + // no break + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : call_dmi_io_dccal HWP - Target 0x%.8X", + TARGETING::get_huid(l_itr->first)); + } + + // Call on the MEMBUF + FAPI_INVOKE_HWP(l_errl, dmi_io_dccal, l_fapi_membuf_target); + if (l_errl) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X : dmi_io_dccal HWP Target Membuf 0x%.8X", + l_errl->reasonCode(), TARGETING::get_huid(l_itr->second)); + /*@ + * @errortype + * @reasoncode ISTEP_DMI_IO_DCCAL_MEMBUF_FAILED + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid ISTEP_DMI_IO_DCCAL + * @userdata1 bytes 0-1: plid identifying first error + * bytes 2-3: reason code of first error + * @userdata2 bytes 0-1: total number of elogs included + * bytes 2-3: N/A + * @devdesc call to dmi_io_dccal on MEMBUF has failed + */ + l_StepError.addErrorDetails(ISTEP_DMI_IO_DCCAL_MEMBUF_FAILED, + ISTEP_DMI_IO_DCCAL, + l_errl); + + errlCommit( l_errl, HWPF_COMP_ID ); + // We want to continue the training despite the error, so + // no break + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : call_dmi_io_dccal HWP - Target 0x%.8X", + TARGETING::get_huid(l_itr->second)); + } + + } + + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_dmi_io_dccal exit" ); + + // end task, returning any errorlogs to IStepDisp + return l_StepError.getErrorHandle(); } @@ -620,132 +744,69 @@ void* call_dmi_io_run_training( void *io_pArgs ) TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_io_run_training entry" ); + TargetPairs_t l_dmi_io_dccal_targets; + get_dmi_io_targets(l_dmi_io_dccal_targets); + TARGETING::TargetHandleList l_cpuTargetList; getAllChips(l_cpuTargetList, TYPE_PROC); - for (TargetHandleList::iterator l_cpu_iter = l_cpuTargetList.begin(); - l_cpu_iter != l_cpuTargetList.end(); - ++l_cpu_iter) + TargetPairs_t::iterator l_itr; + for (l_itr = l_dmi_io_dccal_targets.begin(); + (!l_err) && (l_itr != l_dmi_io_dccal_targets.end()); ++l_itr) { - // make a local copy of the CPU target - const TARGETING::Target* l_cpu_target = *l_cpu_iter; - - uint8_t l_cpuNum = l_cpu_target->getAttr<ATTR_POSITION>(); - - // find all MCS chiplets of the proc - TARGETING::TargetHandleList l_mcsTargetList; - getChildChiplets( l_mcsTargetList, l_cpu_target, TYPE_MCS ); - - for (TargetHandleList::iterator l_mcs_iter = l_mcsTargetList.begin(); - l_mcs_iter != l_mcsTargetList.end(); - ++l_mcs_iter) - { - // make a local copy of the MCS target - const TARGETING::Target* l_mcs_target = *l_mcs_iter; - - uint8_t l_mcsNum = l_mcs_target->getAttr<ATTR_CHIP_UNIT>(); - - // find all the Centaurs that are associated with this MCS - TARGETING::TargetHandleList l_memTargetList; - getAffinityChips(l_memTargetList, l_mcs_target, TYPE_MEMBUF); - - for (TargetHandleList::iterator l_mem_iter = l_memTargetList.begin(); - l_mem_iter != l_memTargetList.end(); - ++l_mem_iter) - { - // make a local copy of the MEMBUF target - const TARGETING::Target* l_mem_target = *l_mem_iter; - - uint8_t l_memNum = l_mem_target->getAttr<ATTR_POSITION>(); - - // struct containing custom parameters that is fed to HWP - // call the HWP with each target ( if parallel, spin off a task ) - const fapi::Target l_fapi_master_target( - TARGET_TYPE_MCS_CHIPLET, - reinterpret_cast<void *> - ( const_cast<TARGETING::Target*>(l_mcs_target) ) - ); - const fapi::Target l_fapi_slave_target( - TARGET_TYPE_MEMBUF_CHIP, - reinterpret_cast<void *> - (const_cast<TARGETING::Target*>(l_mem_target)) - ); - - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "===== Call dmi_io_run_training HWP( cpu 0x%x, mcs 0x%x, mem 0x%x ) : ", - l_cpuNum, - l_mcsNum, - l_memNum ); + const fapi::Target l_fapi_master_target( + TARGET_TYPE_MCS_CHIPLET, + reinterpret_cast<void *> + (const_cast<TARGETING::Target*>(l_itr->first))); - EntityPath l_path; - l_path = l_cpu_target->getAttr<ATTR_PHYS_PATH>(); - l_path.dump(); - l_path = l_mcs_target->getAttr<ATTR_PHYS_PATH>(); - l_path.dump(); - l_path = l_mem_target->getAttr<ATTR_PHYS_PATH>(); - l_path.dump(); - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "===== " ); - FAPI_INVOKE_HWP(l_err, dmi_io_run_training, - l_fapi_master_target, l_fapi_slave_target); - - if (l_err) - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X : dmi_io_run_training HWP" - "( cpu 0x%x, mcs 0x%x, mem 0x%x ) ", - l_err->reasonCode(), - l_cpuNum, - l_mcsNum, - l_memNum ); - - // capture the target data in the elog - ErrlUserDetailsTarget(l_mem_target).addToLog( l_err ); - - /*@ - * @errortype - * @reasoncode ISTEP_DMI_TRAINING_FAILED - * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE - * @moduleid ISTEP_DMI_IO_RUN_TRAINING - * @userdata1 bytes 0-1: plid identifying first error - * bytes 2-3: reason code of first error - * @userdata2 bytes 0-1: total number of elogs included - * bytes 2-3: N/A - * @devdesc call to dmi_io_run_training has failed - */ - l_StepError.addErrorDetails(ISTEP_DMI_TRAINING_FAILED, - ISTEP_DMI_IO_RUN_TRAINING, - l_err); - - errlCommit( l_err, HWPF_COMP_ID ); - - break; // Break out mem target loop - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : dmi_io_run_training HWP" - "( cpu 0x%x, mcs 0x%x, mem 0x%x ) ", - l_cpuNum, - l_mcsNum, - l_memNum ); - } + const fapi::Target l_fapi_slave_target( + TARGET_TYPE_MEMBUF_CHIP, + reinterpret_cast<void *> + (const_cast<TARGETING::Target*>(l_itr->second))); - } //end for l_mem_target + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "===== Call dmi_io_run_training HWP(mcs 0x%x, mem 0x%x ) : ", + TARGETING::get_huid(l_itr->first), + TARGETING::get_huid(l_itr->second)); - // if there is an error bail out - if ( !l_StepError.isNull() ) - { - break; // Break out l_mcs_target - } + EntityPath l_path; + l_path = l_itr->first->getAttr<ATTR_PHYS_PATH>(); + l_path.dump(); + l_path = l_itr->second->getAttr<ATTR_PHYS_PATH>(); + l_path.dump(); - } // end for l_mcs_target + FAPI_INVOKE_HWP(l_err, dmi_io_run_training, + l_fapi_master_target, l_fapi_slave_target); - if ( !l_StepError.isNull() ) + if (l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X : dmi_io_run_training HWP", + l_err->reasonCode()); + /*@ + * @errortype + * @reasoncode ISTEP_DMI_TRAINING_FAILED + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid ISTEP_DMI_IO_RUN_TRAINING + * @userdata1 bytes 0-1: plid identifying first error + * bytes 2-3: reason code of first error + * @userdata2 bytes 0-1: total number of elogs included + * bytes 2-3: N/A + * @devdesc call to dmi_io_run_training has failed + */ + l_StepError.addErrorDetails(ISTEP_DMI_TRAINING_FAILED, + ISTEP_DMI_IO_RUN_TRAINING, + l_err); + errlCommit( l_err, HWPF_COMP_ID ); + break; // Break out target list loop + } + else { - break; // Break out l_cpu_target + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : dmi_io_run_training HWP"); } - } // end for l_cpu_target + } // end target pair list TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_io_run_training exit" ); @@ -983,6 +1044,56 @@ void* call_cen_set_inband_addr( void *io_pArgs ) return l_StepError.getErrorHandle(); } +// +// Utility function to get DMI IO target list +// First is MCS target, Second is MEMBUF target +// +void get_dmi_io_targets(TargetPairs_t& o_dmi_io_targets) +{ + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "get_dmi_io_targets" ); + + o_dmi_io_targets.clear(); + TARGETING::TargetHandleList l_cpuTargetList; + getAllChips(l_cpuTargetList, TYPE_PROC); + + for ( TargetHandleList::iterator l_iter = l_cpuTargetList.begin(); + l_iter != l_cpuTargetList.end(); ++l_iter ) + { + // make a local copy of the CPU target + const TARGETING::Target* l_cpu_target = *l_iter; + + // find all MCS chiplets of the proc + TARGETING::TargetHandleList l_mcsTargetList; + getChildChiplets( l_mcsTargetList, l_cpu_target, TYPE_MCS ); + + for ( TargetHandleList::iterator l_iterMCS = l_mcsTargetList.begin(); + l_iterMCS != l_mcsTargetList.end(); ++l_iterMCS ) + { + // make a local copy of the MCS target + const TARGETING::Target* l_mcs_target = *l_iterMCS; + + // find all the Centaurs that are associated with this MCS + TARGETING::TargetHandleList l_memTargetList; + getAffinityChips(l_memTargetList, l_mcs_target, TYPE_MEMBUF); + + for ( TargetHandleList::iterator l_iterMemBuf = l_memTargetList.begin(); + l_iterMemBuf != l_memTargetList.end(); ++l_iterMemBuf ) + { + // make a local copy of the MEMBUF target + const TARGETING::Target* l_mem_target = *l_iterMemBuf; + o_dmi_io_targets.insert(std::pair<const TARGETING::Target*, + const TARGETING::Target*>(l_mcs_target, l_mem_target)); + + } //end for l_mem_target + + } // end for l_mcs_target + + } // end for l_cpu_target + + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "get_dmi_io_targets exit" ); + + return; +} }; // end namespace diff --git a/src/usr/hwpf/hwp/dmi_training/makefile b/src/usr/hwpf/hwp/dmi_training/makefile index a97273d7f..8ad952631 100644 --- a/src/usr/hwpf/hwp/dmi_training/makefile +++ b/src/usr/hwpf/hwp/dmi_training/makefile @@ -43,13 +43,15 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/dmi_scominit EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/mss_getecid EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/io_restore_erepair +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/dmi_io_dccal OBJS = dmi_training.o \ proc_cen_framelock.o \ dmi_io_run_training.o \ dmi_scominit.o \ proc_cen_set_inband_addr.o \ - mss_get_cen_ecid.o + mss_get_cen_ecid.o \ + dmi_io_dccal.o ## NOTE: add a new directory onto the vpaths when you add a new HWP VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock @@ -57,5 +59,6 @@ VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/dmi_scominit VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/mss_getecid +VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/dmi_io_dccal include ${ROOTPATH}/config.mk diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/edi_ei_initialization.C b/src/usr/hwpf/hwp/edi_ei_initialization/edi_ei_initialization.C index 82b354290..a2bb5e300 100644 --- a/src/usr/hwpf/hwp/edi_ei_initialization/edi_ei_initialization.C +++ b/src/usr/hwpf/hwp/edi_ei_initialization/edi_ei_initialization.C @@ -67,6 +67,7 @@ // Uncomment these files as they become available: #include "io_restore_erepair.H" // #include "fabric_io_dccal/fabric_io_dccal.H" +// #include "fabric_erepair/fabric_erepair.H" // #include "fabric_pre_trainadv/fabric_pre_trainadv.H" #include "fabric_io_run_training/fabric_io_run_training.H" // #include "fabric_post_trainadv/fabric_post_trainadv.H" @@ -74,6 +75,7 @@ // #include "host_attnlisten_proc/host_attnlisten_proc.H" #include "proc_fab_iovalid/proc_fab_iovalid.H" #include <diag/prdf/common/prdfMain.H> +#include "fabric_io_dccal/fabric_io_dccal.H" // eRepair Restore #include <erepairAccessorHwpFuncs.H> @@ -286,48 +288,122 @@ void* call_fabric_erepair( void *io_pArgs ) void* call_fabric_io_dccal( void *io_pArgs ) { errlHndl_t l_errl = NULL; + IStepError l_StepError; - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + // We are not running this analog procedure in VPO + if (TARGETING::is_vpo()) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Skip call_fabric_io_dccal in VPO!"); + return l_StepError.getErrorHandle(); + } + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_fabric_io_dccal entry" ); -#if 0 - // @@@@@ CUSTOM BLOCK: @@@@@ - // figure out what targets we need - // customize any other inputs - // set up loops to go through all targets (if parallel, spin off a task) + TargetPairs_t l_PbusConnections; + TargetPairs_t::iterator l_itr; + const uint32_t MaxBusSet = 2; + TYPE busSet[MaxBusSet] = { TYPE_ABUS, TYPE_XBUS }; - // dump physical path to targets - EntityPath l_path; - l_path = l_@targetN_target->getAttr<ATTR_PHYS_PATH>(); - l_path.dump(); + // Note: + // Due to lab tester board environment, HW procedure writer (Varkey) has + // requested to send in one target of a time (we used to send in + // both ends in one call). Even though they don't have to be + // in order, we should keep the pair concept here in case we need to send + // in a pair in the future again. + for (uint32_t ii = 0; (!l_errl) && (ii < MaxBusSet); ii++) + { + l_errl = PbusLinkSvc::getTheInstance().getPbusConnections( + l_PbusConnections, busSet[ii] ); - // cast OUR type of target to a FAPI type of target. - const fapi::Target l_fapi_@targetN_target( - TARGET_TYPE_MEMBUF_CHIP, - reinterpret_cast<void *> - (const_cast<TARGETING::Target*>(l_@targetN_target)) ); + for (l_itr = l_PbusConnections.begin(); + l_itr != l_PbusConnections.end(); ++l_itr) + { + const fapi::Target l_fapi_endp1_target( + (ii ? TARGET_TYPE_XBUS_ENDPOINT : TARGET_TYPE_ABUS_ENDPOINT), + reinterpret_cast<void *> + (const_cast<TARGETING::Target*>(l_itr->first))); + const fapi::Target l_fapi_endp2_target( + (ii ? TARGET_TYPE_XBUS_ENDPOINT : TARGET_TYPE_ABUS_ENDPOINT), + reinterpret_cast<void *> + (const_cast<TARGETING::Target*>(l_itr->second))); - // call the HWP with each fapi::Target - FAPI_INVOKE_HWP( l_errl, fabric_io_dccal, _args_...); - if ( l_errl ) - { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR : .........." ); - errlCommit( l_errl, HWPF_COMP_ID ); - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : .........." ); + EntityPath l_path; + l_path = l_itr->first->getAttr<ATTR_PHYS_PATH>(); + l_path.dump(); + l_path = l_itr->second->getAttr<ATTR_PHYS_PATH>(); + l_path.dump(); + + // call the HWP with each bus connection + FAPI_INVOKE_HWP( l_errl, fabric_io_dccal, l_fapi_endp1_target ); + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "%s : %cbus connection fabric_io_dccal. Target 0x%.8X", + (l_errl ? "ERROR" : "SUCCESS"), (ii ? 'X' : 'A'), + TARGETING::get_huid(l_itr->first) ); + if ( l_errl ) + { + /*@ + * @errortype + * @reasoncode ISTEP_FABRIC_IO_DCCAL_ENDPOINT1_FAILED + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid ISTEP_FABRIC_IO_DCCAL + * @userdata1 bytes 0-1: plid identifying first error + * bytes 2-3: reason code of first error + * @userdata2 bytes 0-1: total number of elogs included + * bytes 2-3: N/A + * @devdesc call to fabric_io_run_training has failed + * see error log in the user details section for + * additional details. + */ + l_StepError.addErrorDetails(ISTEP_FABRIC_IO_DCCAL_ENDPOINT1_FAILED, + ISTEP_FABRIC_IO_DCCAL, + l_errl ); + + errlCommit( l_errl, HWPF_COMP_ID ); + // We want to continue the training despite the error, so + // no break + } + + // call the HWP with each bus connection + FAPI_INVOKE_HWP( l_errl, fabric_io_dccal, l_fapi_endp2_target ); + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "%s : %cbus connection fabric_io_dccal. Target 0x%.8X", + (l_errl ? "ERROR" : "SUCCESS"), (ii ? 'X' : 'A'), + TARGETING::get_huid(l_itr->second) ); + if ( l_errl ) + { + /*@ + * @errortype + * @reasoncode ISTEP_FABRIC_IO_DCCAL_ENDPOINT2_FAILED + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid ISTEP_FABRIC_IO_DCCAL + * @userdata1 bytes 0-1: plid identifying first error + * bytes 2-3: reason code of first error + * @userdata2 bytes 0-1: total number of elogs included + * bytes 2-3: N/A + * @devdesc call to fabric_io_run_training has failed + * see error log in the user details section for + * additional details. + */ + l_StepError.addErrorDetails(ISTEP_FABRIC_IO_DCCAL_ENDPOINT2_FAILED, + ISTEP_FABRIC_IO_DCCAL, + l_errl ); + + errlCommit( l_errl, HWPF_COMP_ID ); + // We want to continue the training despite the error, so + // no break + } + } } - // @@@@@ END CUSTOM BLOCK: @@@@@ -#endif - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_fabric_io_dccal exit" ); // end task, returning any errorlogs to IStepDisp - return l_errl; + return l_StepError.getErrorHandle(); } diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_dccal/fabric_io_dccal.C b/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_dccal/fabric_io_dccal.C new file mode 100755 index 000000000..66eca1b0c --- /dev/null +++ b/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_dccal/fabric_io_dccal.C @@ -0,0 +1,32 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_dccal/fabric_io_dccal.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +#include <fapi.H> +#include "io_dccal.H" + +extern "C" { + +ReturnCode fabric_io_dccal(const Target &target){ + return io_dccal(target); +} + +} // extern diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_dccal/fabric_io_dccal.H b/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_dccal/fabric_io_dccal.H new file mode 100755 index 000000000..5bf88fbd5 --- /dev/null +++ b/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_dccal/fabric_io_dccal.H @@ -0,0 +1,35 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_dccal/fabric_io_dccal.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef FABRIC_IO_DCCAL_H_ +#define FABRIC_IO_DCCAL_H_ + +using namespace fapi; + +extern "C" +{ + +fapi::ReturnCode fabric_io_dccal(const fapi::Target &target); + +} // extern "C" + +#endif // FABRIC_IO_DCCAL_H diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/makefile b/src/usr/hwpf/hwp/edi_ei_initialization/makefile index d238956b8..e3ec7c175 100644 --- a/src/usr/hwpf/hwp/edi_ei_initialization/makefile +++ b/src/usr/hwpf/hwp/edi_ei_initialization/makefile @@ -45,11 +45,11 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/io_restore_erepair ## EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization/<HWP_dir> EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_run_training - +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_dccal ## NOTE: add new object files when you add a new HWP OBJS = edi_ei_initialization.o \ - proc_fab_iovalid.o fabric_io_run_training.o + proc_fab_iovalid.o fabric_io_run_training.o fabric_io_dccal.o ## NOTE: add a new directory onto the vpaths when you add a new HWP @@ -57,7 +57,7 @@ OBJS = edi_ei_initialization.o \ # VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization/<HWP_dir> VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_run_training - +VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_dccal include ${ROOTPATH}/config.mk |