Added register reset functionality for DD2

DD2 updates register reset functionality to require writes to clear registers.
This updates to do writes for both DD1 and DD2.
This commit also fixes a UT fail caused by wat_debug_attention w/a not on DD2.

Change-Id: Ib30e72e8773d16513ddf1c958fa76612a662cbb6
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40763
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40863
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

10 files changed, 453 insertions, 65 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.H
index a6b5a1e25..2e03d9924 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.H
@@ -262,8 +262,10 @@ inline fapi2::ReturnCode reset_err( const fapi2::Target<T>& i_target )
     l_data.clearBit<TT::RESET_ERR_RPT>();
     FAPI_TRY( write_config0(i_target, l_data) );
 
-    // We have to read ERR_STATUS0. It resets when read.
-    FAPI_TRY( read_error_status0(i_target, l_data) );
+    // Now we need to reset the ERROR_STATUS0 register
+    l_data = 0;
+    FAPI_TRY( write_error_status0(i_target, l_data), "%s failed to clear APB error register via write",
+              mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
index 9277b78fc..f4591f18c 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
@@ -71,6 +71,55 @@ namespace mss
 {
 
 ///
+/// @brief Clears all training related errors - specialization for MCA
+/// @param[in] i_target the port in question
+/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS iff no error
+///
+template< >
+fapi2::ReturnCode clear_initial_cal_errors( const fapi2::Target<TARGET_TYPE_MCA>& i_target )
+{
+    FAPI_INF("%s resetting errors", mss::c_str(i_target));
+
+    // Reset DPs first
+    FAPI_TRY(mss::dp16::reset_rd_vref_errors(i_target), "%s error resetting RD VREF errors", mss::c_str(i_target));
+    FAPI_TRY(mss::dp16::reset_wr_error0(i_target), "%s error resetting DP16 WR error0", mss::c_str(i_target));
+    FAPI_TRY(mss::dp16::reset_rd_status0(i_target), "%s error resetting DP16 RD LVL errors", mss::c_str(i_target));
+    FAPI_TRY(mss::dp16::reset_rd_lvl_status2(i_target), "%s error resetting DP16 RD LVL status2", mss::c_str(i_target));
+    FAPI_TRY(mss::dp16::reset_rd_lvl_status0(i_target), "%s error resetting DP16 RD LVL status0", mss::c_str(i_target));
+    FAPI_TRY(mss::dp16::reset_wr_vref_error(i_target), "%s error resetting DP16 WR VREF errors", mss::c_str(i_target));
+
+    // Now APB/RC/WC/SEQ
+    FAPI_TRY(mss::apb::reset_err(i_target), "%s error resetting APB errors", mss::c_str(i_target));
+    FAPI_TRY(mss::rc::reset_error_status0(i_target), "%s error resetting RC errors status0", mss::c_str(i_target));
+    FAPI_TRY(mss::seq::reset_error_status0(i_target), "%s error resetting SEQ error status0", mss::c_str(i_target));
+    FAPI_TRY(mss::wc::reset_error_status0(i_target), "%s error resetting WC error status0", mss::c_str(i_target));
+
+    // Now the control
+    FAPI_TRY(mss::pc::reset_error_status0(i_target), "%s error resetting PC error status0", mss::c_str(i_target));
+    FAPI_TRY(mss::pc::reset_init_cal_error(i_target), "%s error resetting PC init cal errors", mss::c_str(i_target));
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Clears all training related errors - specialization for MCBIST
+/// @param[in] i_target the port in question
+/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS iff no error
+///
+template< >
+fapi2::ReturnCode clear_initial_cal_errors( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target )
+{
+    for (const auto& p : mss::find_targets_with_magic<TARGET_TYPE_MCA>(i_target))
+    {
+        FAPI_TRY(clear_initial_cal_errors(p), "%s Error processing init cal errors", mss::c_str(p));
+    }
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
 /// @brief change resetn to the given state
 /// @param[in] i_target the mcbist
 /// @param[in] i_state the desired state
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H
index 195c540ce..69c776666 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H
@@ -127,6 +127,15 @@ template< fapi2::TargetType T >
 fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target<T>& i_target );
 
 ///
+/// @brief Clears all training related errors
+/// @tparam T the type of the target in question
+/// @param[in] i_target the port in question
+/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS iff no error
+///
+template< fapi2::TargetType T >
+fapi2::ReturnCode clear_initial_cal_errors( const fapi2::Target<T>& i_target );
+
+///
 /// @brief Setup all the cal config register
 /// @tparam T, the target type of the MCA/MBA
 /// @param[in] i_target the target associated with this cal setup
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
index 4652ecde4..0f6102caa 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
@@ -569,6 +569,42 @@ const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::RD_DIA_CONFIG5_REG =
     MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4,
 };
 
+const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::RD_LVL_STATUS0_REG =
+{
+    MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_0,
+    MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_1,
+    MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_2,
+    MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_3,
+    MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_4,
+};
+
+const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::RD_LVL_STATUS2_REG =
+{
+    MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_0,
+    MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_1,
+    MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_2,
+    MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_3,
+    MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_4,
+};
+
+const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::RD_STATUS0_REG =
+{
+    MCA_DDRPHY_DP16_RD_STATUS0_P0_0,
+    MCA_DDRPHY_DP16_RD_STATUS0_P0_1,
+    MCA_DDRPHY_DP16_RD_STATUS0_P0_2,
+    MCA_DDRPHY_DP16_RD_STATUS0_P0_3,
+    MCA_DDRPHY_DP16_RD_STATUS0_P0_4,
+};
+
+const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::WR_ERROR0_REG =
+{
+    MCA_DDRPHY_DP16_WR_ERROR0_P0_0,
+    MCA_DDRPHY_DP16_WR_ERROR0_P0_1,
+    MCA_DDRPHY_DP16_WR_ERROR0_P0_2,
+    MCA_DDRPHY_DP16_WR_ERROR0_P0_3,
+    MCA_DDRPHY_DP16_WR_ERROR0_P0_4,
+};
+
 ///
 /// @brief Given a RD_VREF value, create a PHY 'standard' bit field for that percentage.
 /// @tparam T fapi2 Target Type - derived
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
index 9f1c2f177..2ba070e67 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
@@ -199,6 +199,12 @@ class dp16Traits<fapi2::TARGET_TYPE_MCA>
         static const std::vector< uint64_t > DATA_BIT_ENABLE0_REG;
         static const std::vector< uint64_t > DATA_BIT_ENABLE1_REG;
 
+        // Reset on read in DD1 registers
+        static const std::vector< uint64_t > RD_LVL_STATUS0_REG;
+        static const std::vector< uint64_t > RD_LVL_STATUS2_REG;
+        static const std::vector< uint64_t > RD_STATUS0_REG;
+        static const std::vector< uint64_t > WR_ERROR0_REG;
+
         // Definitions of the gate delay and waterfall bits' locations
         constexpr static const uint64_t GATE_DELAY_BIT_POS[NUM_QUAD_PER_DP16] =
         {
@@ -2098,6 +2104,87 @@ inline void set_blue_waterfall_range( const fapi2::Target<T>& i_target,
     FAPI_INF("set_blue_waterfall_range: 0x%01lx", i_value);
 }
 
+///
+/// @brief Reset rd_lvl_status0 registers
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = dp16Traits<T> >
+inline fapi2::ReturnCode reset_rd_lvl_status0( const fapi2::Target<T>& i_target )
+{
+    FAPI_TRY(mss::scom_blastah(i_target, TT::RD_LVL_STATUS0_REG, 0));
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Reset rd_lvl_status2 registers
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = dp16Traits<T> >
+inline fapi2::ReturnCode reset_rd_lvl_status2( const fapi2::Target<T>& i_target )
+{
+    FAPI_TRY(mss::scom_blastah(i_target, TT::RD_LVL_STATUS2_REG, 0));
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Reset rd_status0 registers
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = dp16Traits<T> >
+inline fapi2::ReturnCode reset_rd_status0( const fapi2::Target<T>& i_target )
+{
+    FAPI_TRY(mss::scom_blastah(i_target, TT::RD_STATUS0_REG, 0));
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Reset wr_error0 registers
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = dp16Traits<T> >
+inline fapi2::ReturnCode reset_wr_error0( const fapi2::Target<T>& i_target )
+{
+    FAPI_TRY(mss::scom_blastah(i_target, TT::WR_ERROR0_REG, 0));
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Resets the RD VREF error registers
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = dp16Traits<T> >
+inline fapi2::ReturnCode reset_rd_vref_errors( const fapi2::Target<T>& i_target )
+{
+    // Indiscrementantly blast all errors to 0's
+    FAPI_TRY(mss::scom_blastah(i_target, TT::RD_VREF_CAL_ERROR_REG, 0));
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
 } // close namespace dp16
 } // close namespace mss
 
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H
index 0fcc81dbb..ba2a14345 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H
@@ -174,7 +174,8 @@ namespace pc
 template< fapi2::TargetType T, typename TT = pcTraits<T> >
 inline fapi2::ReturnCode read_config1( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
 {
-    FAPI_TRY( mss::getScom(i_target, TT::PC_CONFIG1_REG, o_data) );
+    FAPI_TRY( mss::getScom(i_target, TT::PC_CONFIG1_REG, o_data), "%s failed to read pc_config1 register",
+              mss::c_str(i_target) );
     FAPI_INF("pc_config1: 0x%016llx", o_data);
 
 fapi_try_exit:
@@ -194,7 +195,8 @@ inline fapi2::ReturnCode write_config1( const fapi2::Target<T>& i_target,
                                         const fapi2::buffer<uint64_t>& i_data )
 {
     FAPI_INF("pc_config1: 0x%016llx", i_data);
-    FAPI_TRY( mss::putScom(i_target, TT::PC_CONFIG1_REG, i_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::PC_CONFIG1_REG, i_data), "%s failed to write pc_config1 register",
+              mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -221,7 +223,8 @@ fapi2::ReturnCode reset_config1( const fapi2::Target<T>& i_target );
 template< fapi2::TargetType T, typename TT = pcTraits<T> >
 inline fapi2::ReturnCode read_config0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
 {
-    FAPI_TRY( mss::getScom(i_target, TT::PC_CONFIG0_REG, o_data) );
+    FAPI_TRY( mss::getScom(i_target, TT::PC_CONFIG0_REG, o_data), "%s failed to read pc_config0 register",
+              mss::c_str(i_target) );
     FAPI_INF("pc_config0: 0x%016llx", o_data);
 
 fapi_try_exit:
@@ -241,7 +244,8 @@ inline fapi2::ReturnCode write_config0( const fapi2::Target<T>& i_target,
                                         const fapi2::buffer<uint64_t>& i_data )
 {
     FAPI_INF("pc_config0: 0x%016llx", i_data);
-    FAPI_TRY( mss::putScom(i_target, TT::PC_CONFIG0_REG, i_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::PC_CONFIG0_REG, i_data), "%s failed to write pc_config0 register",
+              mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -268,7 +272,8 @@ fapi2::ReturnCode reset_config0( const fapi2::Target<T>& i_target );
 template< fapi2::TargetType T, typename TT = pcTraits<T> >
 inline fapi2::ReturnCode read_init_cal_config1( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
 {
-    FAPI_TRY( mss::getScom(i_target, TT::PC_INIT_CAL_CONFIG1_REG, o_data) );
+    FAPI_TRY( mss::getScom(i_target, TT::PC_INIT_CAL_CONFIG1_REG, o_data), "%s failed to read pc_init_cal_config1 register",
+              mss::c_str(i_target) );
     FAPI_INF("Read pc_init_cal_config1: 0x%016llx", o_data);
 
 fapi_try_exit:
@@ -288,7 +293,8 @@ inline fapi2::ReturnCode write_init_cal_config1( const fapi2::Target<T>& i_targe
         const fapi2::buffer<uint64_t>& i_data )
 {
     FAPI_INF("Writing to pc_init_cal_config1: 0x%016llx", i_data);
-    FAPI_TRY( mss::putScom(i_target, TT::PC_INIT_CAL_CONFIG1_REG, i_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::PC_INIT_CAL_CONFIG1_REG, i_data),
+              "%s failed to write pc_init_cal_config1 register", mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -382,7 +388,8 @@ inline void set_refresh_interval( fapi2::buffer<uint64_t>& o_data, const uint64_
 template< fapi2::TargetType T, typename TT = pcTraits<T> >
 inline fapi2::ReturnCode read_dll_zcal_status( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
 {
-    FAPI_TRY( mss::getScom(i_target, TT::PC_DLL_ZCAL_CAL_STATUS_REG, o_data) );
+    FAPI_TRY( mss::getScom(i_target, TT::PC_DLL_ZCAL_CAL_STATUS_REG, o_data),
+              "%s failed to read pc_dll_zcal_status register", mss::c_str(i_target) );
     FAPI_INF("pc_dll_zcal_status: 0x%016llx", o_data);
 
 fapi_try_exit:
@@ -504,7 +511,8 @@ inline mss::states get_zcal_status( const fapi2::buffer<uint64_t>& i_data )
 template< fapi2::TargetType T, typename TT = pcTraits<T> >
 inline fapi2::ReturnCode read_error_status0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
 {
-    FAPI_TRY( mss::getScom(i_target, TT::PC_ERROR_STATUS0_REG, o_data) );
+    FAPI_TRY( mss::getScom(i_target, TT::PC_ERROR_STATUS0_REG, o_data), "%s failed to read pc_error_status0 register",
+              mss::c_str(i_target) );
     FAPI_INF("pc_error_status0: 0x%016llx", o_data);
 
 fapi_try_exit:
@@ -524,7 +532,8 @@ inline fapi2::ReturnCode write_error_status0( const fapi2::Target<T>& i_target,
         const fapi2::buffer<uint64_t>& i_data )
 {
     FAPI_INF("pc_error_status0: 0x%016llx", i_data);
-    FAPI_TRY( mss::putScom(i_target, TT::PC_ERROR_STATUS0_REG, i_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::PC_ERROR_STATUS0_REG, i_data), "%s failed to write pc_error_status0 register",
+              mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -540,7 +549,8 @@ fapi_try_exit:
 template< fapi2::TargetType T, typename TT = pcTraits<T> >
 inline fapi2::ReturnCode reset_error_status0( const fapi2::Target<T>& i_target )
 {
-    FAPI_TRY( write_error_status0(i_target, 0) );
+    FAPI_TRY( write_error_status0(i_target, 0), "%s failed to clear pc_error_status0 register via write",
+              mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -557,7 +567,8 @@ fapi_try_exit:
 template< fapi2::TargetType T, typename TT = pcTraits<T> >
 inline fapi2::ReturnCode read_init_cal_error( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
 {
-    FAPI_TRY( mss::getScom(i_target, TT::PC_INIT_CAL_ERROR_REG, o_data) );
+    FAPI_TRY( mss::getScom(i_target, TT::PC_INIT_CAL_ERROR_REG, o_data), "%s failed to read pc_init_cal_error register",
+              mss::c_str(i_target) );
     FAPI_INF("pc_init_cal_error: 0x%016llx", o_data);
 
 fapi_try_exit:
@@ -575,7 +586,8 @@ inline fapi2::ReturnCode write_init_cal_error( const fapi2::Target<T>& i_target,
         const fapi2::buffer<uint64_t>& i_data )
 {
     FAPI_INF("pc_init_cal_error: 0x%016llx", i_data);
-    FAPI_TRY( mss::putScom(i_target, TT::PC_INIT_CAL_ERROR_REG, i_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::PC_INIT_CAL_ERROR_REG, i_data), "%s failed to write pc_init_cal_error register",
+              mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -591,7 +603,8 @@ fapi_try_exit:
 template< fapi2::TargetType T, typename TT = pcTraits<T> >
 inline fapi2::ReturnCode reset_init_cal_error( const fapi2::Target<T>& i_target )
 {
-    FAPI_TRY( write_init_cal_error(i_target, 0) );
+    FAPI_TRY( write_init_cal_error(i_target, 0), "%s failed to clear pc_init_cal_error register via write",
+              mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -627,7 +640,8 @@ fapi_try_exit:
 template< fapi2::TargetType T, typename TT = pcTraits<T> >
 inline fapi2::ReturnCode read_resets( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
 {
-    FAPI_TRY( mss::getScom(i_target, TT::PC_RESETS_REG, o_data) );
+    FAPI_TRY( mss::getScom(i_target, TT::PC_RESETS_REG, o_data), "%s failed to read pc_resets register",
+              mss::c_str(i_target) );
     FAPI_INF("pc_resets: 0x%016llx", o_data);
 
 fapi_try_exit:
@@ -644,7 +658,8 @@ template< fapi2::TargetType T, typename TT = pcTraits<T> >
 inline fapi2::ReturnCode write_resets( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
 {
     FAPI_INF("pc_resets: 0x%016llx", i_data);
-    FAPI_TRY( mss::putScom(i_target, TT::PC_RESETS_REG, i_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::PC_RESETS_REG, i_data), "%s failed to write pc_resets register",
+              mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
index e46cb9b70..fa50d25ee 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
@@ -132,7 +132,8 @@ namespace rc
 template< fapi2::TargetType T, typename TT = rcTraits<T> >
 inline fapi2::ReturnCode read_vref_config0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
 {
-    FAPI_TRY( mss::getScom(i_target, TT::RC_VREF_CONFIG0_REG, o_data) );
+    FAPI_TRY( mss::getScom(i_target, TT::RC_VREF_CONFIG0_REG, o_data), "%s failed to read rc_vref_config0 register",
+              mss::c_str(i_target) );
     FAPI_DBG("rc_vref_config0: 0x%016llx", o_data);
 fapi_try_exit:
     return fapi2::current_err;
@@ -149,7 +150,8 @@ inline fapi2::ReturnCode write_vref_config0( const fapi2::Target<T>& i_target,
         const fapi2::buffer<uint64_t>& i_data )
 {
     FAPI_DBG("rc_vref_config0: 0x%016llx", i_data);
-    FAPI_TRY( mss::putScom(i_target, TT::RC_VREF_CONFIG0_REG, i_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::RC_VREF_CONFIG0_REG, i_data), "%s failed to write rc_vref_config0 register",
+              mss::c_str(i_target) );
 fapi_try_exit:
     return fapi2::current_err;
 }
@@ -163,7 +165,8 @@ fapi_try_exit:
 template< fapi2::TargetType T, typename TT = rcTraits<T> >
 inline fapi2::ReturnCode read_vref_config1( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
 {
-    FAPI_TRY( mss::getScom(i_target, TT::RC_VREF_CONFIG1_REG, o_data) );
+    FAPI_TRY( mss::getScom(i_target, TT::RC_VREF_CONFIG1_REG, o_data), "%s failed to read rc_vref_config1 register",
+              mss::c_str(i_target) );
     FAPI_DBG("rc_vref_config1: 0x%016llx", o_data);
 fapi_try_exit:
     return fapi2::current_err;
@@ -180,7 +183,8 @@ inline fapi2::ReturnCode write_vref_config1( const fapi2::Target<T>& i_target,
         const fapi2::buffer<uint64_t>& i_data )
 {
     FAPI_DBG("rc_vref_config1: 0x%016llx", i_data);
-    FAPI_TRY( mss::putScom(i_target, TT::RC_VREF_CONFIG1_REG, i_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::RC_VREF_CONFIG1_REG, i_data), "%s failed to write rc_vref_config1 register",
+              mss::c_str(i_target) );
 fapi_try_exit:
     return fapi2::current_err;
 }
@@ -195,7 +199,8 @@ fapi_try_exit:
 template< fapi2::TargetType T, typename TT = rcTraits<T> >
 inline fapi2::ReturnCode read_config0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
 {
-    FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG0_REG, o_data) );
+    FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG0_REG, o_data), "%s failed to read rc_config0 register",
+              mss::c_str(i_target) );
     FAPI_DBG("rc_config0: 0x%016llx", o_data);
 fapi_try_exit:
     return fapi2::current_err;
@@ -211,7 +216,8 @@ template< fapi2::TargetType T, typename TT = rcTraits<T> >
 inline fapi2::ReturnCode write_config0( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
 {
     FAPI_DBG("rc_config0: 0x%016llx", i_data);
-    FAPI_TRY( mss::putScom(i_target, TT::RC_CONFIG0_REG, i_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::RC_CONFIG0_REG, i_data), "%s failed to write rc_config0 register",
+              mss::c_str(i_target) );
 fapi_try_exit:
     return fapi2::current_err;
 }
@@ -226,7 +232,8 @@ fapi_try_exit:
 template< fapi2::TargetType T, typename TT = rcTraits<T> >
 inline fapi2::ReturnCode read_config1( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
 {
-    FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG1_REG, o_data) );
+    FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG1_REG, o_data), "%s failed to read rc_config1 register",
+              mss::c_str(i_target) );
     FAPI_DBG("rc_config1: 0x%016llx", o_data);
 fapi_try_exit:
     return fapi2::current_err;
@@ -242,7 +249,8 @@ template< fapi2::TargetType T, typename TT = rcTraits<T> >
 inline fapi2::ReturnCode write_config1( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
 {
     FAPI_DBG("rc_config1: 0x%016llx", i_data);
-    FAPI_TRY( mss::putScom(i_target, TT::RC_CONFIG1_REG, i_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::RC_CONFIG1_REG, i_data), "%s failed to write rc_config1 register",
+              mss::c_str(i_target) );
 fapi_try_exit:
     return fapi2::current_err;
 }
@@ -256,7 +264,8 @@ fapi_try_exit:
 template< fapi2::TargetType T, typename TT = rcTraits<T> >
 inline fapi2::ReturnCode read_config2( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
 {
-    FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG2_REG, o_data) );
+    FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG2_REG, o_data), "%s failed to read rc_config2 register",
+              mss::c_str(i_target) );
     FAPI_DBG("rc_config2: 0x%016llx", o_data);
 fapi_try_exit:
     return fapi2::current_err;
@@ -272,7 +281,8 @@ template< fapi2::TargetType T, typename TT = rcTraits<T> >
 inline fapi2::ReturnCode write_config2( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
 {
     FAPI_DBG("rc_config2: 0x%016llx", i_data);
-    FAPI_TRY( mss::putScom(i_target, TT::RC_CONFIG2_REG, i_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::RC_CONFIG2_REG, i_data), "%s failed to write rc_config2 register",
+              mss::c_str(i_target) );
 fapi_try_exit:
     return fapi2::current_err;
 }
@@ -286,7 +296,8 @@ fapi_try_exit:
 template< fapi2::TargetType T, typename TT = rcTraits<T> >
 inline fapi2::ReturnCode read_config3( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
 {
-    FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG3_REG, o_data) );
+    FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG3_REG, o_data), "%s failed to read rc_config3 register",
+              mss::c_str(i_target) );
     FAPI_DBG("rc_config3: 0x%016llx", o_data);
 fapi_try_exit:
     return fapi2::current_err;
@@ -302,7 +313,8 @@ template< fapi2::TargetType T, typename TT = rcTraits<T> >
 inline fapi2::ReturnCode write_config3( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
 {
     FAPI_DBG("rc_config3: 0x%016llx", i_data);
-    FAPI_TRY( mss::putScom(i_target, TT::RC_CONFIG3_REG, i_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::RC_CONFIG3_REG, i_data), "%s failed to write rc_config3 register",
+              mss::c_str(i_target) );
 fapi_try_exit:
     return fapi2::current_err;
 }
@@ -323,7 +335,7 @@ inline fapi2::ReturnCode reset_config0( const fapi2::Target<T>& i_target )
     l_data.insertFromRight<TT::GLOBAL_PHY_OFFSET, TT::GLOBAL_PHY_OFFSET_LEN>(l_gpo);
     l_data.setBit<TT::PERFORM_RDCLK_ALIGN>();
 
-    FAPI_TRY( write_config0(i_target, l_data) );
+    FAPI_TRY( write_config0(i_target, l_data), "%s failed to reset rc_config0 register via write", mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -340,7 +352,7 @@ inline fapi2::ReturnCode reset_config1( const fapi2::Target<T>& i_target )
     fapi2::buffer<uint64_t> l_data;
 
     // Centaur was all 0's ...
-    FAPI_TRY( write_config1(i_target, l_data) );
+    FAPI_TRY( write_config1(i_target, l_data), "%s failed to reset rc_config1 register via write", mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -367,7 +379,7 @@ inline fapi2::ReturnCode reset_config2( const fapi2::Target<T>& i_target )
     // 57:58, 0b11, any;  # BURST_WINDOW, compare all 8 beats (AS recommended)
     l_data.insertFromRight<TT::BURST_WINDOW, TT::BURST_WINDOW_LEN>(0b11);
 
-    FAPI_TRY( write_config2(i_target, l_data) );
+    FAPI_TRY( write_config2(i_target, l_data), "%s failed to reset rc_config2 register via write", mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -387,7 +399,7 @@ inline fapi2::ReturnCode reset_config3( const fapi2::Target<T>& i_target )
     // Change to COARSE_CAL_STEP_SIZE='0100'
     l_data.insertFromRight<TT::COARSE_CAL_STEP_SIZE, TT::COARSE_CAL_STEP_SIZE_LEN>(0b0100);
 
-    FAPI_TRY( write_config3(i_target, l_data) );
+    FAPI_TRY( write_config3(i_target, l_data), "%s failed to reset rc_config3 register via write", mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -445,7 +457,8 @@ inline fapi2::ReturnCode reset_vref_config0( const fapi2::Target<T>& i_target )
     l_data.insertFromRight<TT::GUESS_WAIT_TIME, TT::GUESS_WAIT_TIME_LEN>(SLOW_AS_YOU_CAN_GO);
 #endif
 
-    FAPI_TRY( write_vref_config0(i_target, l_data) );
+    FAPI_TRY( write_vref_config0(i_target, l_data), "%s failed to reset rc_vref_config0 register via write",
+              mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -473,7 +486,61 @@ inline fapi2::ReturnCode reset_vref_config1( const fapi2::Target<T>& i_target )
 
     // Note: when initial cal is setup, this register will change to accomodate the
     // initial cal read centering and read vref centering cal steps.
-    FAPI_TRY( write_vref_config1(i_target, l_data) );
+    FAPI_TRY( write_vref_config1(i_target, l_data), "%s failed to reset rc_vref_config1 register via write",
+              mss::c_str(i_target) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Write RC_ERROR_STATUS0
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to rcTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = rcTraits<T> >
+inline fapi2::ReturnCode write_error_status0( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
+{
+    FAPI_DBG("rc_error_status0: 0x%016llx", i_data);
+    FAPI_TRY( mss::putScom(i_target, TT::RC_ERROR_STATUS0_REG, i_data), "%s failed to write rc_error_status0 register",
+              mss::c_str(i_target) );
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Read RC_ERROR_STATUS0
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to rcTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[out] o_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = rcTraits<T> >
+inline fapi2::ReturnCode read_error_status0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
+{
+    FAPI_TRY( mss::getScom(i_target, TT::RC_ERROR_STATUS0_REG, o_data), "%s failed to read rc_error_status0 register",
+              mss::c_str(i_target) );
+    FAPI_DBG("rc_error_status0: 0x%016llx", o_data);
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief reset RC_ERROR_STATUS0
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to rcTraits<T>
+/// @param[in] i_target fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = rcTraits<T> >
+inline fapi2::ReturnCode reset_error_status0( const fapi2::Target<T>& i_target )
+{
+    FAPI_TRY( write_error_status0(i_target, 0), "%s failed to clear RC error_status0 register via write",
+              mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H
index a2f1c7d5b..20c275f62 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H
@@ -138,7 +138,8 @@ uint64_t exp_helper( const uint64_t i_value );
 template< fapi2::TargetType T, typename TT = seqTraits<T> >
 inline fapi2::ReturnCode read_config0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
 {
-    FAPI_TRY( mss::getScom(i_target, TT::SEQ_CONFIG0_REG, o_data) );
+    FAPI_TRY( mss::getScom(i_target, TT::SEQ_CONFIG0_REG, o_data), "%s failed to read seq_config0 register",
+              mss::c_str(i_target) );
     FAPI_DBG("seq_config0: 0x%016lx", o_data);
 fapi_try_exit:
     return fapi2::current_err;
@@ -156,7 +157,8 @@ template< fapi2::TargetType T, typename TT = seqTraits<T> >
 inline fapi2::ReturnCode write_config0( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
 {
     FAPI_DBG("seq_config0: 0x%016lx", i_data);
-    FAPI_TRY( mss::putScom(i_target, TT::SEQ_CONFIG0_REG, i_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::SEQ_CONFIG0_REG, i_data), "%s failed to write seq_config0 register",
+              mss::c_str(i_target) );
 fapi_try_exit:
     return fapi2::current_err;
 }
@@ -172,13 +174,57 @@ fapi_try_exit:
 template< fapi2::TargetType T, typename TT = seqTraits<T> >
 inline fapi2::ReturnCode read_error_status0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
 {
-    FAPI_TRY( mss::getScom(i_target, TT::SEQ_ERROR0_REG, o_data) );
+    FAPI_TRY( mss::getScom(i_target, TT::SEQ_ERROR0_REG, o_data), "%s failed to read seq_error_status0 register",
+              mss::c_str(i_target) );
     FAPI_DBG("seq_error_status0: 0x%016lx", o_data);
 fapi_try_exit:
     return fapi2::current_err;
 }
 
-// SEQ_ERROR_STATUS0 is read-only
+///
+/// @brief Write SEQ_ERROR_STATUS0
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to seqTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+/// @note SEQ_ERROR_STATUS0 is read-only in DD1 only, so we'll ignore this in DD2
+///
+template< fapi2::TargetType T, typename TT = seqTraits<T> >
+inline fapi2::ReturnCode write_error_status0( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
+{
+    // Skips if we're a DD1 part, as this means we can't write to this register
+    if(mss::chip_ec_nimbus_lt_2_0(i_target))
+    {
+        FAPI_INF("%s is a DD1 part, so wc_error_status 0 is a read only register - skipping the write", mss::c_str(i_target));
+        return fapi2::FAPI2_RC_SUCCESS;
+    }
+
+    // Does the write
+    FAPI_DBG("error_status0: 0x%016lx", i_data);
+    FAPI_TRY( mss::putScom(i_target, TT::SEQ_ERROR0_REG, i_data), "%s failed to write seq_error_status0 register",
+              mss::c_str(i_target) );
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief reset SEQ_ERROR_STATUS0
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to seqTraits<T>
+/// @param[in] i_target fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = seqTraits<T> >
+inline fapi2::ReturnCode reset_error_status0( const fapi2::Target<T>& i_target )
+{
+    fapi2::buffer<uint64_t> l_data;
+    FAPI_TRY( write_error_status0(i_target, l_data), "%s failed to clear SEQ error_status0 register via write",
+              mss::c_str(i_target) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
 
 ///
 /// @brief Read SEQ_MEM_TIMING_PARAM0
@@ -191,7 +237,8 @@ fapi_try_exit:
 template< fapi2::TargetType T, typename TT = seqTraits<T> >
 inline fapi2::ReturnCode read_timing0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
 {
-    FAPI_TRY( mss::getScom(i_target, TT::SEQ_TIMING0_REG, o_data) );
+    FAPI_TRY( mss::getScom(i_target, TT::SEQ_TIMING0_REG, o_data), "%s failed to read seq_timing0 register",
+              mss::c_str(i_target) );
     FAPI_DBG("seq_timing0: 0x%016lx", o_data);
 fapi_try_exit:
     return fapi2::current_err;
@@ -209,7 +256,8 @@ template< fapi2::TargetType T, typename TT = seqTraits<T> >
 inline fapi2::ReturnCode write_timing0( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
 {
     FAPI_DBG("seq_timing0: 0x%016lx", i_data);
-    FAPI_TRY( mss::putScom(i_target, TT::SEQ_TIMING0_REG, i_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::SEQ_TIMING0_REG, i_data), "%s failed to write seq_timing0 register",
+              mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -241,7 +289,8 @@ inline void set_trfc_cycles( fapi2::buffer<uint64_t>& io_data, const uint64_t i_
 template< fapi2::TargetType T, typename TT = seqTraits<T> >
 inline fapi2::ReturnCode read_timing1( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
 {
-    FAPI_TRY( mss::getScom(i_target, TT::SEQ_TIMING1_REG, o_data) );
+    FAPI_TRY( mss::getScom(i_target, TT::SEQ_TIMING1_REG, o_data), "%s failed to read seq_timing1 register",
+              mss::c_str(i_target) );
     FAPI_DBG("seq_timing1: 0x%016lx", o_data);
 fapi_try_exit:
     return fapi2::current_err;
@@ -259,7 +308,8 @@ template< fapi2::TargetType T, typename TT = seqTraits<T> >
 inline fapi2::ReturnCode write_timing1( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
 {
     FAPI_DBG("seq_timing1: 0x%016lx", i_data);
-    FAPI_TRY( mss::putScom(i_target, TT::SEQ_TIMING1_REG, i_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::SEQ_TIMING1_REG, i_data), "%s failed to write seq_timing1 register",
+              mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -276,7 +326,8 @@ fapi_try_exit:
 template< fapi2::TargetType T, typename TT = seqTraits<T> >
 inline fapi2::ReturnCode read_timing2( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
 {
-    FAPI_TRY( mss::getScom(i_target, TT::SEQ_TIMING2_REG, o_data) );
+    FAPI_TRY( mss::getScom(i_target, TT::SEQ_TIMING2_REG, o_data), "%s failed to read seq_timing2 register",
+              mss::c_str(i_target) );
     FAPI_DBG("seq_timing2: 0x%016lx", o_data);
 fapi_try_exit:
     return fapi2::current_err;
@@ -294,7 +345,8 @@ template< fapi2::TargetType T, typename TT = seqTraits<T> >
 inline fapi2::ReturnCode write_timing2( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
 {
     FAPI_DBG("seq_timing2: 0x%016lx", i_data);
-    FAPI_TRY( mss::putScom(i_target, TT::SEQ_TIMING2_REG, i_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::SEQ_TIMING2_REG, i_data), "%s failed to write seq_timing2 register",
+              mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -328,11 +380,13 @@ fapi2::ReturnCode reset_rd_wr_data( const fapi2::Target<T>& i_target )
 
     l_data.insertFromRight<TT::MPR_PATTERN, TT::MPR_PATTERN_LEN>(MPR01_PATTERN);
     FAPI_INF("seq_rd_wr0 0x%llx", l_data);
-    FAPI_TRY( mss::putScom(i_target, TT::SEQ_RDWR_DATA0, l_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::SEQ_RDWR_DATA0, l_data), "%s failed to reset seq_rd_wr0 register via write",
+              mss::c_str(i_target) );
 
     l_data.insertFromRight<TT::MPR_PATTERN, TT::MPR_PATTERN_LEN>(MPR23_PATTERN);
     FAPI_INF("seq_rd_wr1 0x%llx", l_data);
-    FAPI_TRY( mss::putScom(i_target, TT::SEQ_RDWR_DATA1, l_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::SEQ_RDWR_DATA1, l_data), "%s failed to reset seq_rd_wr1 register via write",
+              mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -354,7 +408,7 @@ inline fapi2::ReturnCode reset_config0( const fapi2::Target<T>& i_target )
 
     // DDR4 needs delayed partiy TK for DDR5/DDR3 ...
     l_data.setBit<TT::DELAYED_PARITY>();
-    FAPI_TRY( write_config0(i_target, l_data) );
+    FAPI_TRY( write_config0(i_target, l_data), "%s failed to reset seq_config0 register via write", mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H
index 09348a7ff..60016b59b 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H
@@ -140,7 +140,8 @@ template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T
 inline fapi2::ReturnCode read_config0( const fapi2::Target<T>& i_target,
                                        fapi2::buffer<uint64_t>& o_data )
 {
-    FAPI_TRY( mss::getScom(i_target, TT::WC_CONFIG0_REG, o_data) );
+    FAPI_TRY( mss::getScom(i_target, TT::WC_CONFIG0_REG, o_data), "%s failed to read wc_config0 register",
+              mss::c_str(i_target) );
     FAPI_DBG("wc_config0: 0x%016llx", o_data);
 fapi_try_exit:
     return fapi2::current_err;
@@ -159,7 +160,8 @@ inline fapi2::ReturnCode write_config0( const fapi2::Target<T>& i_target,
                                         const fapi2::buffer<uint64_t>& i_data )
 {
     FAPI_DBG("wc_config0: 0x%016llx", i_data);
-    FAPI_TRY( mss::putScom(i_target, TT::WC_CONFIG0_REG, i_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::WC_CONFIG0_REG, i_data), "%s failed to write wc_config0 register",
+              mss::c_str(i_target) );
 fapi_try_exit:
     return fapi2::current_err;
 }
@@ -176,7 +178,8 @@ template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T
 inline fapi2::ReturnCode read_config1( const fapi2::Target<T>& i_target,
                                        fapi2::buffer<uint64_t>& o_data )
 {
-    FAPI_TRY( mss::getScom(i_target, TT::WC_CONFIG1_REG, o_data) );
+    FAPI_TRY( mss::getScom(i_target, TT::WC_CONFIG1_REG, o_data), "%s failed to read wc_config1 register",
+              mss::c_str(i_target) );
     FAPI_DBG("wc_config1: 0x%016llx", o_data);
 fapi_try_exit:
     return fapi2::current_err;
@@ -195,7 +198,8 @@ inline fapi2::ReturnCode write_config1( const fapi2::Target<T>& i_target,
                                         const fapi2::buffer<uint64_t>& i_data )
 {
     FAPI_DBG("wc_config1: 0x%016llx", i_data);
-    FAPI_TRY( mss::putScom(i_target, TT::WC_CONFIG1_REG, i_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::WC_CONFIG1_REG, i_data), "%s failed to write wc_config1 register",
+              mss::c_str(i_target) );
 fapi_try_exit:
     return fapi2::current_err;
 }
@@ -212,7 +216,8 @@ template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T
 inline fapi2::ReturnCode read_config2( const fapi2::Target<T>& i_target,
                                        fapi2::buffer<uint64_t>& o_data )
 {
-    FAPI_TRY( mss::getScom(i_target, TT::WC_CONFIG2_REG, o_data) );
+    FAPI_TRY( mss::getScom(i_target, TT::WC_CONFIG2_REG, o_data), "%s failed to read wc_config2 register",
+              mss::c_str(i_target) );
     FAPI_DBG("wc_config2: 0x%016llx", o_data);
 fapi_try_exit:
     return fapi2::current_err;
@@ -231,7 +236,8 @@ inline fapi2::ReturnCode write_config2( const fapi2::Target<T>& i_target,
                                         const fapi2::buffer<uint64_t>& i_data )
 {
     FAPI_DBG("wc_config2: 0x%016llx", i_data);
-    FAPI_TRY( mss::putScom(i_target, TT::WC_CONFIG2_REG, i_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::WC_CONFIG2_REG, i_data), "%s failed to write wc_config2 register",
+              mss::c_str(i_target) );
 fapi_try_exit:
     return fapi2::current_err;
 }
@@ -249,7 +255,8 @@ template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T
 inline fapi2::ReturnCode read_config3( const fapi2::Target<T>& i_target,
                                        fapi2::buffer<uint64_t>& o_data )
 {
-    FAPI_TRY( mss::getScom(i_target, TT::WC_CONFIG3_REG, o_data) );
+    FAPI_TRY( mss::getScom(i_target, TT::WC_CONFIG3_REG, o_data), "%s failed to read wc_config3 register",
+              mss::c_str(i_target) );
     FAPI_DBG("wc_config3: 0x%016llx", o_data);
 fapi_try_exit:
     return fapi2::current_err;
@@ -268,7 +275,8 @@ inline fapi2::ReturnCode write_config3( const fapi2::Target<T>& i_target,
                                         const fapi2::buffer<uint64_t>& i_data )
 {
     FAPI_DBG("wc_config3: 0x%016llx", i_data);
-    FAPI_TRY( mss::putScom(i_target, TT::WC_CONFIG3_REG, i_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::WC_CONFIG3_REG, i_data), "%s failed to write wc_config3 register",
+              mss::c_str(i_target) );
 fapi_try_exit:
     return fapi2::current_err;
 }
@@ -286,7 +294,8 @@ template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T
 inline fapi2::ReturnCode read_rtt_wr_swap_enable( const fapi2::Target<T>& i_target,
         fapi2::buffer<uint64_t>& o_data )
 {
-    FAPI_TRY( mss::getScom(i_target, TT::WC_RTT_WR_SWAP_ENABLE_REG, o_data) );
+    FAPI_TRY( mss::getScom(i_target, TT::WC_RTT_WR_SWAP_ENABLE_REG, o_data),
+              "%s failed to read wc_rtt_wr_swap_enable register", mss::c_str(i_target) );
     FAPI_DBG("wc_rtt_wr_swap_enable: 0x%016llx", o_data);
 fapi_try_exit:
     return fapi2::current_err;
@@ -305,7 +314,8 @@ inline fapi2::ReturnCode write_rtt_wr_swap_enable( const fapi2::Target<T>& i_tar
         const fapi2::buffer<uint64_t>& i_data )
 {
     FAPI_DBG("wc_rtt_wr_swap_enable: 0x%016llx", i_data);
-    FAPI_TRY( mss::putScom(i_target, TT::WC_RTT_WR_SWAP_ENABLE_REG, i_data) );
+    FAPI_TRY( mss::putScom(i_target, TT::WC_RTT_WR_SWAP_ENABLE_REG, i_data),
+              "%s failed to write wc_rtt_wr_swap_enable register", mss::c_str(i_target) );
 fapi_try_exit:
     return fapi2::current_err;
 }
@@ -342,7 +352,7 @@ inline fapi2::ReturnCode reset_config0( const fapi2::Target<T>& i_target )
     l_data.setBit<TT::CUSTOM_INIT_WRITE>();
 
     FAPI_DBG("wc_config0 reset 0x%llx (tWLO_tWLOE: %d)", l_data, mss::twlo_twloe(i_target));
-    FAPI_TRY( write_config0(i_target, l_data) );
+    FAPI_TRY( write_config0(i_target, l_data), "%s failed to reset wc_config0 register via write", mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -368,7 +378,7 @@ inline fapi2::ReturnCode reset_config1( const fapi2::Target<T>& i_target )
 
     FAPI_DBG("wc_config1 reset 0x%llx (big 0x%x small 0x%x wr_pre_dly 0x%x)",
              l_data, WR_LVL_BIG_STEP, WR_LVL_SMALL_STEP, WR_LVL_PRE_DLY);
-    FAPI_TRY( write_config1(i_target, l_data) );
+    FAPI_TRY( write_config1(i_target, l_data), "%s failed to reset wc_config1 register via write", mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -393,7 +403,7 @@ inline fapi2::ReturnCode reset_config2( const fapi2::Target<T>& i_target )
     l_data.insertFromRight<TT::FW_RD_WR, TT::FW_RD_WR_LEN>(l_fw_rd_wr);
 
     FAPI_DBG("wc_config2 reset 0x%llx", l_data);
-    FAPI_TRY( write_config2(i_target, l_data) );
+    FAPI_TRY( write_config2(i_target, l_data), "%s failed to reset wc_config2 register via write", mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -423,7 +433,7 @@ inline fapi2::ReturnCode reset_config3( const fapi2::Target<T>& i_target )
     }
 
     FAPI_DBG("wc_config3 reset 0x%llx", l_data);
-    FAPI_TRY( write_config3(i_target, l_data) );
+    FAPI_TRY( write_config3(i_target, l_data), "%s failed to reset wc_config3 register via write", mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -477,7 +487,8 @@ inline fapi2::ReturnCode reset_rtt_wr_swap_enable( const fapi2::Target<T>& i_tar
     }
 
     FAPI_DBG("wc_rtt_wr_swap_enable reset 0x%llx", l_data);
-    FAPI_TRY( write_rtt_wr_swap_enable(i_target, l_data) );
+    FAPI_TRY( write_rtt_wr_swap_enable(i_target, l_data), "%s failed to reset wc_rtt_wr_swap_enable register via write",
+              mss::c_str(i_target) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -505,6 +516,59 @@ fapi_try_exit:
     return fapi2::current_err;
 }
 
+///
+/// @brief Write WC_ERROR_STATUS0
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to wcTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_WC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = wcTraits<T> >
+inline fapi2::ReturnCode write_error_status0( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
+{
+    FAPI_DBG("wc_error_status0: 0x%016llx", i_data);
+    FAPI_TRY( mss::putScom(i_target, TT::WC_ERROR_STATUS0_REG, i_data), "%s failed to write wc_error_status0 register",
+              mss::c_str(i_target) );
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Read WC_ERROR_STATUS0
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to wcTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[out] o_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_WC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = wcTraits<T> >
+inline fapi2::ReturnCode read_error_status0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
+{
+    FAPI_TRY( mss::getScom(i_target, TT::WC_ERROR_STATUS0_REG, o_data), "%s failed to read wc_error_status0 register",
+              mss::c_str(i_target) );
+    FAPI_DBG("wc_error_status0: 0x%016llx", o_data);
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief reset wc_error_status0
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to wcTraits<T>
+/// @param[in] i_target fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_WC_SUCCESS if ok
+///
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits<T> >
+inline fapi2::ReturnCode reset_error_status0( const fapi2::Target<T>& i_target )
+{
+    FAPI_TRY( write_error_status0(i_target, 0), "%s failed to clear WC error_status0 register via write",
+              mss::c_str(i_target) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
 
 }
 
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C
index f213261c1..61f551320 100644
--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C
@@ -120,7 +120,6 @@ extern "C"
             // so we don't add it in the PHY calibration setup and do it separately here.
             FAPI_TRY( mss::setup_and_execute_zqcal(p, l_cal_steps_enabled) );
 
-            FAPI_TRY( mss::putScom(p, MCA_DDRPHY_PC_INIT_CAL_ERROR_P0, 0) );
             FAPI_TRY( mss::putScom(p, MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0, 0) );
 
             // Disable port fails as it doesn't appear the MC handles initial cal timeouts
@@ -138,8 +137,14 @@ extern "C"
             // Get our rank pairs.
             FAPI_TRY( mss::rank::get_rank_pairs(p, l_pairs) );
 
-            // Setup the config register
+            // Hits the resets iff zqcal is set so we don't unnecessarily reset errors
+            if  ((l_cal_steps_enabled.getBit<mss::cal_steps::DRAM_ZQCAL>()) ||
+                 (l_cal_steps_enabled.getBit<mss::cal_steps::DB_ZQCAL>()))
+            {
+                FAPI_TRY(mss::clear_initial_cal_errors(p), "%s error resetting errors prior to init cal", mss::c_str(p));
+            }
 
+            // Check to see if we're supposed to reset the delay values before starting training
             // don't reset if we're running special training - assumes there's a checkpoint which has valid state.
             if ((l_reset_disable == fapi2::ENUM_ATTR_MSS_MRW_RESET_DELAY_BEFORE_CAL_YES) && (i_special_training == 0))
             {