future proof EC feature attributes, add missing P9N DD2 inits

  redefine EC feature attributes, using inverse logic where required, to qualify
  inits specific to P9N DD1 where possible, to eliminate need for updates for
  future chips in plan

  attempt to remove usage of generic P9N_DD1_SPY_NAMES and P9N_DD2_SPY_NAMES
  attributes added to support initial P9NDD2 engineering data -- several spies
  were not being set as a result

  -----------------
  initfile updates:
  -----------------

  p9.cme.scan.initfile
    add HW391162, SCAN_SICR_TLBIE_QUIESCE feature attributes

  p9.core.common.scan.initfile
    remove fused core init, it was applying scan default for P9N DD1 and is
    not needed for P9N DD2+ given fuse controls

  p9.core.scan.initfile
    add CORE_P9NDD1 to qualify P9N DD1 specific register hierarchy and
    dial programming

    replace usage of P9N_DD1_SPY_NAMES, P9N_DD2_SPY_NAMES using CORE_P9NDD1
    and inverse, to pick up initial pass at P9C DD1 inits

  p9.cxa.scom.initfile
    add CXA_P9NDD1_SPY_NAMES to qualify P9N DD1 specific register hierarchy

  p9.ddrphy.scom.initfile
    add DDRPHY_P9NDD1_SPY_NAMES to qualify P9N DD1 specific register hierarchy

  p9.dpll.scan.initfile
    remove POSTDD1N_DPLL_SETTINGS feature attribute, use DD1_DPLL_SETTINGS
    attribute and inverse to drive inits

  p9.l2.scan.initfile
    invert definition of OPTIMAL_LARX_STCX_PERF, HW409069 feature attributes

  p9.l3.scan.initfile
  p9.l3.scom.initifle
    remove OPTIMAL_LCO_SCOM, HW396230_SCOM feature attributes
    use HW386657, HW396230 attributes to drive inits

  p9.mca.scom.initfile
    add MCA_P9NDD1_ASYNC to differentiate asynchronous boundary crossing
    programming and dial name differences between P9N DD1, P9N DD2

  p9.mmu.scan.initfile
  p9.mmu.scom.initfile
    invert definition of NMMU_DMT_DD2, NMMU_ISS734_DD2_1 feature attributes

  p9.ncu.scan.initfile
  p9.ncu.scom.initifle
    remove HW396230_SCOM, use HW396230 attribute to drive inits

  p9.npu.scom.initfile
    remove usage of P9N_DD1_SPY_NAMES, refactor CONFIG_ENABLE_PBUS specification
    to work for both P9NDD1, P9NDD2 ENGD

  p9.obus.scan.initfile
    remove EC qualification of OBUS FIR mask for simulation

  sample.ec.scan.initfile
    remove testcase requiring use of P9N_DD1_SPY_NAMES, properties of
    testcase are covered by other tests

  -----------------
  HWP updates:
  -----------------

  p9_xip_customize
    add customization of epsilon attributes for NMMU application

  p9_chiplet_scominit
    invert definition of P9_NDL_IOVALID feature attribute
    remove usage of P9N_DD1_SPY_NAMES

  p9_npu_scominit
    replace usage of P9N_DD1_SPY_NAMES with SETUP_BARS_NPU_DD1_ADDR

  p9_sbe_tracearray
    invert definition of CORE_TRACE_SCOMABLE feature attribute

  p9_sim_get_nia
    remove usage of P9N_DD1_SPY_NAMES, directly process CT/EC attributes
    (ok as this HWP is used for VBU sim only and not consumed by FW)

Change-Id: I63bfe8a4bfb8824b94e35a3688a6c69eecc1cf01
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40911
Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com>
Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40916
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>

10 files changed, 255 insertions, 242 deletions

diff --git a/src/import/chips/p9/initfiles/p9n.mca.scom.initfile b/src/import/chips/p9/initfiles/p9n.mca.scom.initfile
index 4ff487428..f7b797ed6 100644
--- a/src/import/chips/p9/initfiles/p9n.mca.scom.initfile
+++ b/src/import/chips/p9/initfiles/p9n.mca.scom.initfile
@@ -767,7 +767,7 @@ define def_perf_tune_case = (MCBIST.ATTR_MSS_FREQ==2400) && (SYS.ATTR_FREQ_PB_MH
 # DD1
 
 # "L" field
-ispy MCP.PORT0.ECC64.SCOM.MBSECCQ_VAL_TO_DATA_DELAY [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD1_SPY_NAMES] {
+ispy MCP.PORT0.ECC64.SCOM.MBSECCQ_VAL_TO_DATA_DELAY [when=S && ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC] {
   spyv, expr;
   # OLD - keeping here because this Boston 2400/1600 fix is likely temporary (HW411339)
   #3,      (def_perf_tune_case==0); # untuned
@@ -778,7 +778,7 @@ ispy MCP.PORT0.ECC64.SCOM.MBSECCQ_VAL_TO_DATA_DELAY [when=S && ATTR_CHIP_EC_FEAT
 }
 
 # "D" field
-ispy MCP.PORT0.ECC64.SCOM.MBSECCQ_NEST_VAL_TO_DATA_DELAY [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD1_SPY_NAMES] {
+ispy MCP.PORT0.ECC64.SCOM.MBSECCQ_NEST_VAL_TO_DATA_DELAY [when=S && ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC] {
   spyv, expr;
   # OLD - keeping here because this Boston 2400/1600 fix is likely temporary (HW411339)
   #0,      (def_perf_tune_case==0); # untuned
@@ -789,7 +789,7 @@ ispy MCP.PORT0.ECC64.SCOM.MBSECCQ_NEST_VAL_TO_DATA_DELAY [when=S && ATTR_CHIP_EC
 }
 
 # "dn" field
-espy MCP.PORT0.ECC64.SCOM.MBSECCQ_DELAY_NONBYPASS [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD1_SPY_NAMES] {
+espy MCP.PORT0.ECC64.SCOM.MBSECCQ_DELAY_NONBYPASS [when=S && ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC] {
   # OLD - keeping here because this Boston 2400/1600 fix is likely temporary (HW411339)
   #spyv;
   #OFF; # untuned and tuned same value
@@ -799,7 +799,7 @@ espy MCP.PORT0.ECC64.SCOM.MBSECCQ_DELAY_NONBYPASS [when=S && ATTR_CHIP_EC_FEATUR
 }
 
 # "h" field
-espy MCP.PORT0.ECC64.SCOM.MBSECCQ_DELAY_VALID_1X [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD1_SPY_NAMES] {
+espy MCP.PORT0.ECC64.SCOM.MBSECCQ_DELAY_VALID_1X [when=S && ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC] {
   spyv;
   OFF; # untuned and tuned same value
 }
@@ -809,7 +809,7 @@ espy MCP.PORT0.ECC64.SCOM.MBSECCQ_DELAY_VALID_1X [when=S && ATTR_CHIP_EC_FEATURE
 # (note hierarchies for ECC scoms are slightly different in dd2)
 
 # "L" field
-ispy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_VAL_TO_DATA_DELAY [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD2_SPY_NAMES] {
+ispy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_VAL_TO_DATA_DELAY [when=S && !ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC] {
   spyv, expr;
   5,      (PROC.ATTR_MC_SYNC_MODE==1);                                                              # sync
   5,      (PROC.ATTR_MC_SYNC_MODE==0) &&                                (def_mn_freq_ratio < 1250); # async 2400m/2000n and below
@@ -817,7 +817,7 @@ ispy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_VAL_TO_DATA_DELAY [when=S && ATTR_CHIP_EC_
 }
 
 # "T" field (new for DD2)
-espy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_BYPASS_TENURE_3 [when=S && ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS] {
+espy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_BYPASS_TENURE_3 [when=S && !ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC] {
   spyv, expr;
   OFF,    (PROC.ATTR_MC_SYNC_MODE==1);                                                              # sync
   OFF,    (PROC.ATTR_MC_SYNC_MODE==0)                                && (def_mn_freq_ratio <  963); # async 1866m/2000n
@@ -829,7 +829,7 @@ espy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_BYPASS_TENURE_3 [when=S && ATTR_CHIP_EC_FE
 }
 
 # "D" field
-ispy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_NEST_VAL_TO_DATA_DELAY [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD2_SPY_NAMES] {
+ispy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_NEST_VAL_TO_DATA_DELAY [when=S && !ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC] {
   spyv, expr;
   0,      (PROC.ATTR_MC_SYNC_MODE==1);                                                              # sync
   2,      (PROC.ATTR_MC_SYNC_MODE==0) &&                                (def_mn_freq_ratio <  963); # async 1866m/2000n
@@ -841,13 +841,13 @@ ispy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_NEST_VAL_TO_DATA_DELAY [when=S && ATTR_CHI
 }
 
 # "dn" field
-espy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_DELAY_NONBYPASS [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD2_SPY_NAMES] {
+espy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_DELAY_NONBYPASS [when=S && !ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC] {
   spyv;
   ON; # same across all frequency settings
 }
 
 # "h" field
-espy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_DELAY_VALID_1X [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD2_SPY_NAMES] {
+espy MCP.PORT0.ECC64.ECC.SCOM.MBSECCQ_DELAY_VALID_1X [when=S && !ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC] {
   spyv, expr;
   OFF,    (PROC.ATTR_MC_SYNC_MODE==1);                                                              # sync
   OFF,    (PROC.ATTR_MC_SYNC_MODE==0) &&                                (def_mn_freq_ratio <  963); # async 1866m/2000n
diff --git a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C
index f8c9c2554..e5bea690a 100644
--- a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C
+++ b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C
@@ -150,6 +150,11 @@ fapi2::ReturnCode writeMboxRegs (
     MBOX_ATTR_WRITE (ATTR_DD1_SLOW_PCI_REF_CLOCK,   FAPI_SYSTEM,    i_image);
     MBOX_ATTR_CLEAR (ATTR_PROC_EFF_FABRIC_GROUP_ID, i_procTarget,   i_image);
     MBOX_ATTR_CLEAR (ATTR_PROC_EFF_FABRIC_CHIP_ID,  i_procTarget,   i_image);
+    MBOX_ATTR_WRITE (ATTR_PROC_EPS_READ_CYCLES_T0,  FAPI_SYSTEM,    i_image);
+    MBOX_ATTR_WRITE (ATTR_PROC_EPS_READ_CYCLES_T1,  FAPI_SYSTEM,    i_image);
+    MBOX_ATTR_WRITE (ATTR_PROC_EPS_READ_CYCLES_T2,  FAPI_SYSTEM,    i_image);
+    MBOX_ATTR_WRITE (ATTR_PROC_EPS_WRITE_CYCLES_T1, FAPI_SYSTEM,    i_image);
+    MBOX_ATTR_WRITE (ATTR_PROC_EPS_WRITE_CYCLES_T2, FAPI_SYSTEM,    i_image);
 
 fapi_try_exit:
     FAPI_DBG("writeMboxRegs Exiting...");
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_cxa_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_cxa_scom.C
index aaac66374..7072d5413 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_cxa_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_cxa_scom.C
@@ -108,14 +108,29 @@ fapi2::ReturnCode p9_cxa_scom(const fapi2::Target<fapi2::TARGET_TYPE_CAPP>& TGT0
             FAPI_TRY(fapi2::putScom(TGT0, 0x2010819ull, l_scom_buffer));
         }
         {
+            FAPI_TRY(fapi2::getScom( TGT0, 0x201081bull, l_scom_buffer ));
+
             if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
             {
-                FAPI_TRY(fapi2::getScom( TGT0, 0x201081bull, l_scom_buffer ));
+                l_scom_buffer.insert<45, 3, 61, uint64_t>(literal_0b111 );
+            }
 
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
                 l_scom_buffer.insert<45, 3, 61, uint64_t>(literal_0b111 );
+            }
+
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
+            {
+                l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b0010 );
+            }
+
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
                 l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b0010 );
-                FAPI_TRY(fapi2::putScom(TGT0, 0x201081bull, l_scom_buffer));
             }
+
+            FAPI_TRY(fapi2::putScom(TGT0, 0x201081bull, l_scom_buffer));
         }
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x201081cull, l_scom_buffer ));
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C
index 27b4df4b7..94aa1adeb 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C
@@ -55,8 +55,8 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
         fapi2::ATTR_NAME_Type l_chip_id;
         FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, TGT0, l_chip_id));
         FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT0, l_chip_ec));
-        fapi2::ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2_Type l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2;
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2, TGT0, l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2));
+        fapi2::ATTR_CHIP_EC_FEATURE_NMMU_NDD1_Type l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_NMMU_NDD1, TGT0, l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1));
         fapi2::ATTR_PROC_FABRIC_PUMP_MODE_Type l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE, TGT1, l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE));
         fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T1_Type l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1;
@@ -67,11 +67,11 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x5012c03ull, l_scom_buffer ));
 
-            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0))
+            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0))
             {
                 l_scom_buffer.insert<0, 22, 0, uint64_t>(literal_0x04047C0000000000 );
             }
-            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0))
+            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0))
             {
                 l_scom_buffer.insert<0, 22, 0, uint64_t>(literal_0x04247C0000000000 );
             }
@@ -87,11 +87,11 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x5012c07ull, l_scom_buffer ));
 
-            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0))
+            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0))
             {
                 l_scom_buffer.insert<0, 22, 0, uint64_t>(literal_0x409B000000000000 );
             }
-            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0))
+            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0))
             {
                 l_scom_buffer.insert<0, 22, 0, uint64_t>(literal_0x40FB000000000000 );
             }
@@ -134,11 +134,11 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x5012c43ull, l_scom_buffer ));
 
-            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0))
+            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0))
             {
                 l_scom_buffer.insert<0, 48, 16, uint64_t>(literal_0x0000FAF800FF );
             }
-            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0))
+            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0))
             {
                 l_scom_buffer.insert<0, 48, 16, uint64_t>(literal_0x0000FAFC00FB );
             }
@@ -154,11 +154,11 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x5012c47ull, l_scom_buffer ));
 
-            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0))
+            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0))
             {
                 l_scom_buffer.insert<0, 48, 16, uint64_t>(literal_0x910000040F00 );
             }
-            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0))
+            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0))
             {
                 l_scom_buffer.insert<0, 48, 16, uint64_t>(literal_0x9D1100000F04 );
             }
@@ -171,11 +171,11 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
             l_scom_buffer.insert<30, 1, 59, uint64_t>(literal_0b11111 );
             l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b11111 );
 
-            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0))
+            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0))
             {
                 l_scom_buffer.insert<0, 12, 52, uint64_t>(literal_0x00E );
             }
-            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0))
+            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0))
             {
                 l_scom_buffer.insert<0, 12, 52, uint64_t>(literal_0x000 );
             }
@@ -227,12 +227,12 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
                 l_scom_buffer.insert<44, 8, 56, uint64_t>(l_NMMU_MM_MPSS_MODE_MPSS_ENA_PREF_PGSZ_ENA_G_64KB_H_64KB );
             }
 
-            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0))
+            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0))
             {
                 constexpr auto l_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_PID_DIS_ON = 0x1;
                 l_scom_buffer.insert<21, 1, 63, uint64_t>(l_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_PID_DIS_ON );
             }
-            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0))
+            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0))
             {
                 constexpr auto l_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_PID_DIS_OFF = 0x0;
                 l_scom_buffer.insert<21, 1, 63, uint64_t>(l_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_PID_DIS_OFF );
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_npu_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_npu_scom.C
index 833b84e25..c7da8cd69 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_npu_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_npu_scom.C
@@ -91,20 +91,9 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
 
             l_scom_buffer.insert<4, 1, 63, uint64_t>(literal_0b0 );
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
-            {
-                if ((l_def_NVLINK_ACTIVE == literal_1))
-                {
-                    l_scom_buffer.insert<38, 1, 63, uint64_t>(literal_0x1 );
-                }
-            }
-
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            if ((l_def_NVLINK_ACTIVE == literal_1))
             {
-                if ((l_def_NVLINK_ACTIVE == literal_1))
-                {
-                    l_scom_buffer.insert<38, 1, 63, uint64_t>(literal_0x1 );
-                }
+                l_scom_buffer.insert<38, 1, 63, uint64_t>(literal_0x1 );
             }
 
             if ((l_def_NVLINK_ACTIVE == literal_1))
@@ -424,20 +413,9 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
 
             l_scom_buffer.insert<4, 1, 63, uint64_t>(literal_0b0 );
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
-            {
-                if ((l_def_NVLINK_ACTIVE == literal_1))
-                {
-                    l_scom_buffer.insert<38, 1, 63, uint64_t>(literal_0x1 );
-                }
-            }
-
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            if ((l_def_NVLINK_ACTIVE == literal_1))
             {
-                if ((l_def_NVLINK_ACTIVE == literal_1))
-                {
-                    l_scom_buffer.insert<38, 1, 63, uint64_t>(literal_0x1 );
-                }
+                l_scom_buffer.insert<38, 1, 63, uint64_t>(literal_0x1 );
             }
 
             if ((l_def_NVLINK_ACTIVE == literal_1))
@@ -1147,7 +1125,7 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
 
             l_scom_buffer.insert<4, 1, 63, uint64_t>(literal_0b0 );
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
             {
                 if ((l_def_NVLINK_ACTIVE == literal_1))
                 {
@@ -1155,7 +1133,7 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
                 }
             }
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
             {
                 if ((l_def_NVLINK_ACTIVE == literal_1))
                 {
@@ -1564,7 +1542,7 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
 
             l_scom_buffer.insert<4, 1, 63, uint64_t>(literal_0b0 );
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
             {
                 if ((l_def_NVLINK_ACTIVE == literal_1))
                 {
@@ -1572,7 +1550,7 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
                 }
             }
 
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
             {
                 if ((l_def_NVLINK_ACTIVE == literal_1))
                 {
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9n_ddrphy_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9n_ddrphy_scom.C
index d9759dd7e..f4a4ea3c5 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9n_ddrphy_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9n_ddrphy_scom.C
@@ -56,17 +56,25 @@ fapi2::ReturnCode p9n_ddrphy_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& T
         FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT1, l_chip_ec));
         fapi2::buffer<uint64_t> l_scom_buffer;
         {
+            FAPI_TRY(fapi2::getScom( TGT0, 0x800000030701103full, l_scom_buffer ));
+
             if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
             {
-                FAPI_TRY(fapi2::getScom( TGT0, 0x800000030701103full, l_scom_buffer ));
-
                 if (( true ))
                 {
                     l_scom_buffer.insert<48, 16, 48, uint64_t>(literal_0x0120 );
                 }
+            }
 
-                FAPI_TRY(fapi2::putScom(TGT0, 0x800000030701103full, l_scom_buffer));
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                if (( true ))
+                {
+                    l_scom_buffer.insert<48, 16, 48, uint64_t>(literal_0x0120 );
+                }
             }
+
+            FAPI_TRY(fapi2::putScom(TGT0, 0x800000030701103full, l_scom_buffer));
         }
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x800000240701103full, l_scom_buffer ));
@@ -309,17 +317,25 @@ fapi2::ReturnCode p9n_ddrphy_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& T
             FAPI_TRY(fapi2::putScom(TGT0, 0x800000ad0701103full, l_scom_buffer));
         }
         {
+            FAPI_TRY(fapi2::getScom( TGT0, 0x800004030701103full, l_scom_buffer ));
+
             if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
             {
-                FAPI_TRY(fapi2::getScom( TGT0, 0x800004030701103full, l_scom_buffer ));
-
                 if (( true ))
                 {
                     l_scom_buffer.insert<48, 16, 48, uint64_t>(literal_0x0120 );
                 }
+            }
 
-                FAPI_TRY(fapi2::putScom(TGT0, 0x800004030701103full, l_scom_buffer));
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                if (( true ))
+                {
+                    l_scom_buffer.insert<48, 16, 48, uint64_t>(literal_0x0120 );
+                }
             }
+
+            FAPI_TRY(fapi2::putScom(TGT0, 0x800004030701103full, l_scom_buffer));
         }
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x800004240701103full, l_scom_buffer ));
@@ -562,17 +578,25 @@ fapi2::ReturnCode p9n_ddrphy_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& T
             FAPI_TRY(fapi2::putScom(TGT0, 0x800004ad0701103full, l_scom_buffer));
         }
         {
+            FAPI_TRY(fapi2::getScom( TGT0, 0x800008030701103full, l_scom_buffer ));
+
             if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
             {
-                FAPI_TRY(fapi2::getScom( TGT0, 0x800008030701103full, l_scom_buffer ));
-
                 if (( true ))
                 {
                     l_scom_buffer.insert<48, 16, 48, uint64_t>(literal_0x0120 );
                 }
+            }
 
-                FAPI_TRY(fapi2::putScom(TGT0, 0x800008030701103full, l_scom_buffer));
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                if (( true ))
+                {
+                    l_scom_buffer.insert<48, 16, 48, uint64_t>(literal_0x0120 );
+                }
             }
+
+            FAPI_TRY(fapi2::putScom(TGT0, 0x800008030701103full, l_scom_buffer));
         }
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x800008240701103full, l_scom_buffer ));
@@ -815,17 +839,25 @@ fapi2::ReturnCode p9n_ddrphy_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& T
             FAPI_TRY(fapi2::putScom(TGT0, 0x800008ad0701103full, l_scom_buffer));
         }
         {
+            FAPI_TRY(fapi2::getScom( TGT0, 0x80000c030701103full, l_scom_buffer ));
+
             if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
             {
-                FAPI_TRY(fapi2::getScom( TGT0, 0x80000c030701103full, l_scom_buffer ));
-
                 if (( true ))
                 {
                     l_scom_buffer.insert<48, 16, 48, uint64_t>(literal_0x0120 );
                 }
+            }
 
-                FAPI_TRY(fapi2::putScom(TGT0, 0x80000c030701103full, l_scom_buffer));
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                if (( true ))
+                {
+                    l_scom_buffer.insert<48, 16, 48, uint64_t>(literal_0x0120 );
+                }
             }
+
+            FAPI_TRY(fapi2::putScom(TGT0, 0x80000c030701103full, l_scom_buffer));
         }
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x80000c240701103full, l_scom_buffer ));
@@ -1068,17 +1100,25 @@ fapi2::ReturnCode p9n_ddrphy_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& T
             FAPI_TRY(fapi2::putScom(TGT0, 0x80000cad0701103full, l_scom_buffer));
         }
         {
+            FAPI_TRY(fapi2::getScom( TGT0, 0x800010030701103full, l_scom_buffer ));
+
             if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
             {
-                FAPI_TRY(fapi2::getScom( TGT0, 0x800010030701103full, l_scom_buffer ));
-
                 if (( true ))
                 {
                     l_scom_buffer.insert<48, 16, 48, uint64_t>(literal_0x0120 );
                 }
+            }
 
-                FAPI_TRY(fapi2::putScom(TGT0, 0x800010030701103full, l_scom_buffer));
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) )
+            {
+                if (( true ))
+                {
+                    l_scom_buffer.insert<48, 16, 48, uint64_t>(literal_0x0120 );
+                }
             }
+
+            FAPI_TRY(fapi2::putScom(TGT0, 0x800010030701103full, l_scom_buffer));
         }
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x800010240701103full, l_scom_buffer ));
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C
index 651398548..8124012a8 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C
@@ -67,8 +67,7 @@ const uint64_t FBC_IOO_DL_FIR_ACTION1 = 0x0303C0000300FFFCULL;
 const uint64_t FBC_IOO_DL_FIR_MASK    = 0xFCFC3FFFFCFF000CULL;
 
 // link 0,1 internal errors are a simulation artifact in dd1 so they need to be masked
-const uint64_t FBC_IOO_DL_FIR_MASK_SIM_DD1 = 0xFCFC3FFFFCFF000FULL;
-const uint64_t OBUS_3_LL3_FIR_MASK_SIM_DD1 = 0x300000000000000FULL;
+const uint64_t FBC_IOO_DL_FIR_MASK_SIM = 0xFCFC3FFFFCFF000FULL;
 
 static const uint8_t OBRICK0_POS  = 0x0;
 static const uint8_t OBRICK1_POS  = 0x1;
@@ -97,15 +96,13 @@ fapi2::ReturnCode p9_chiplet_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PRO
     std::vector<fapi2::Target<fapi2::TARGET_TYPE_OBUS_BRICK>> l_obrick_targets;
     fapi2::buffer<uint64_t> l_ob0data(0x0);
     fapi2::buffer<uint64_t> l_ob3data(0x0);
-    uint8_t l_dd1 = 0;
-    uint8_t l_ndl_iovalid = 0;
+    uint8_t l_no_ndl_iovalid = 0;
     uint8_t l_is_simulation = 0;
 
     FAPI_DBG("Start");
-    // Get attribute to check if it is dd1 or dd2
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_P9N_DD1_SPY_NAMES, i_target, l_dd1));
-    // Get attribute to check if NDL IOValids need set (dd2+)
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_P9_NDL_IOVALID, i_target, l_ndl_iovalid));
+
+    // Get attribute to check if NDL IOValids need to be set (dd2+)
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_P9_NO_NDL_IOVALID, i_target, l_no_ndl_iovalid));
     // Get simulation indicator attribute
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, FAPI_SYSTEM, l_is_simulation));
 
@@ -113,7 +110,7 @@ fapi2::ReturnCode p9_chiplet_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PRO
     fapi2::toString(i_target, l_procTargetStr, sizeof(l_procTargetStr));
 
 
-    if (l_ndl_iovalid)
+    if (!l_no_ndl_iovalid)
     {
 
         l_obrick_targets = i_target.getChildren<fapi2::TARGET_TYPE_OBUS_BRICK>();
@@ -234,9 +231,9 @@ fapi2::ReturnCode p9_chiplet_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PRO
         FAPI_TRY(fapi2::putScom(*l_iter, OBUS_LL0_PB_IOOL_FIR_ACTION1_REG, FBC_IOO_DL_FIR_ACTION1),
                  "Error from putScom (OBUS_LL0_PB_IOOL_FIR_ACTION1_REG)");
 
-        if ((l_dd1 != 0) && (l_is_simulation == 1))
+        if (l_is_simulation == 1)
         {
-            FAPI_TRY(fapi2::putScom(*l_iter, OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG, FBC_IOO_DL_FIR_MASK_SIM_DD1),
+            FAPI_TRY(fapi2::putScom(*l_iter, OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG, FBC_IOO_DL_FIR_MASK_SIM),
                      "Error from putScom (OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_SIM_DD1)");
         }
         else
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_npu_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_npu_scominit.C
index c2f47164b..eb74516c4 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_npu_scominit.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_npu_scominit.C
@@ -65,8 +65,9 @@ fapi2::ReturnCode p9_npu_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CH
     auto l_perv_tgt = i_target.getChildren<fapi2::TARGET_TYPE_PERV>
                       (fapi2::TARGET_FILTER_NEST_WEST, fapi2::TARGET_STATE_FUNCTIONAL);
 
-    // Get attribute to check if it is dd1 or dd2
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_P9N_DD1_SPY_NAMES, i_target, l_dd1));
+    // read attribute to determine if NDD1 addresses need to be used
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_DD1_ADDR, i_target, l_dd1),
+             "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_DD1_ADDR");
 
     //Check to see if NPU is valid in PG (N3 chiplet)
     for (auto l_tgt : l_perv_tgt)
@@ -104,7 +105,7 @@ fapi2::ReturnCode p9_npu_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CH
         else
         {
             FAPI_TRY(fapi2::putScomUnderMask(i_target, NOTP9NDD1_NPU_SM2_XTS_ATRMISS, l_atrmiss, l_atrmiss),
-                     "Error from putScomUnderMask (PU_NPU_SM2_XTS_ATRMISS)");
+                     "Error from putScomUnderMask (NOTP9NDD1_NPU_SM2_XTS_ATRMISS)");
         }
 
 
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.C
index f6cb436e6..637116c8c 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.C
@@ -249,16 +249,16 @@ fapi2::ReturnCode p9_sbe_tracearray(
      * Check an EC feature to see if that's fixed. */
     if (ta_type == fapi2::TARGET_TYPE_CORE)
     {
-        uint8_t l_core_trace_scomable = 0;
+        uint8_t l_core_trace_not_scomable = 0;
 
         fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> proc_target =
             i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE,
-                               proc_target, l_core_trace_scomable),
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_CORE_TRACE_NOT_SCOMABLE,
+                               proc_target, l_core_trace_not_scomable),
                  "Failed to query chip EC feature "
-                 "ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE");
+                 "ATTR_CHIP_EC_FEATURE_CORE_TRACE_NOT_SCOMABLE");
 
-        if (!l_core_trace_scomable)
+        if (l_core_trace_not_scomable)
         {
             FAPI_ERR("Core arrays cannot be dumped in this chip EC; "
                      "please use fastarray instead.");
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index 19156f1e2..98fcf5ffd 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -31,11 +31,10 @@
 <attributes>
   <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_P9N_DD1_SPY_NAMES</id>
+    <id>ATTR_CHIP_EC_FEATURE_P9_NO_NDL_IOVALID</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Returns true if spy name has changed from dd1 to dd2.
-      Less than Nimbus ec 0x20
+      Returns true if the chip has no NDL IOValid bits
     </description>
     <chipEcFeature>
       <chip>
@@ -49,42 +48,6 @@
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_P9N_DD2_SPY_NAMES</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>
-      Returns true if spy name has changed from dd1 to dd2.
-      Greater than or equal to 0x20
-    </description>
-    <chipEcFeature>
-      <chip>
-        <name>ENUM_ATTR_NAME_NIMBUS</name>
-        <ec>
-          <value>0x20</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
-        </ec>
-      </chip>
-    </chipEcFeature>
-  </attribute>
-  <!-- ********************************************************************* -->
-  <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_P9_NDL_IOVALID</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>
-      Returns true if the chip has NDL IOValid bits
-      P9N dd2
-    </description>
-    <chipEcFeature>
-      <chip>
-        <name>ENUM_ATTR_NAME_NIMBUS</name>
-        <ec>
-          <value>0x20</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
-        </ec>
-      </chip>
-    </chipEcFeature>
-  </attribute>
-  <!-- ********************************************************************* -->
-  <attribute>
     <id>ATTR_CHIP_EC_FEATURE_EARLYMODE_FIX</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
@@ -102,18 +65,18 @@
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE</id>
+    <id>ATTR_CHIP_EC_FEATURE_CORE_TRACE_NOT_SCOMABLE</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Returns true if the core trace arrays are dumpable via SCOM.
-      Nimbus EC 0x20 or greater
+      Returns true if the core trace arrays are not dumpable via SCOM.
+      Nimbus EC 0x10
     </description>
     <chipEcFeature>
       <chip>
         <name>ENUM_ATTR_NAME_NIMBUS</name>
         <ec>
           <value>0x20</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
+          <test>LESS_THAN</test>
         </ec>
       </chip>
     </chipEcFeature>
@@ -1691,24 +1654,17 @@
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2</id>
+    <id>ATTR_CHIP_EC_FEATURE_NMMU_NDD1</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Sets inits for DD2, also DMT mode
+      Configure NMMU for Nimbus DD1
     </description>
     <chipEcFeature>
       <chip>
         <name>ENUM_ATTR_NAME_NIMBUS</name>
         <ec>
           <value>0x20</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
-        </ec>
-      </chip>
-      <chip>
-        <name>ENUM_ATTR_NAME_CUMULUS</name>
-        <ec>
-          <value>0x10</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
+          <test>LESS_THAN</test>
         </ec>
       </chip>
     </chipEcFeature>
@@ -1749,24 +1705,18 @@
   </attribute>
   <!-- ******************************************************************** -->
     <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_NMMU_ISS734_DD2_1</id>
+    <id>ATTR_CHIP_EC_FEATURE_NMMU_NOT_ISS734</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      issue734 dial, exists dd2.1+
+      NMMU does not require application of issue734 fixes
+      Issue734 exists on Nimbus dd2.1+
     </description>
     <chipEcFeature>
       <chip>
         <name>ENUM_ATTR_NAME_NIMBUS</name>
         <ec>
           <value>0x21</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
-        </ec>
-      </chip>
-      <chip>
-        <name>ENUM_ATTR_NAME_CUMULUS</name>
-        <ec>
-          <value>0x10</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
+          <test>LESS_THAN</test>
         </ec>
       </chip>
     </chipEcFeature>
@@ -2002,7 +1952,7 @@
   </attribute>
   <!-- ******************************************************************** -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_HW396230_SCAN_ONLY</id>
+    <id>ATTR_CHIP_EC_FEATURE_HW396230</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
       Nimbus DD1 only: set L3/NCU skip group scope via scan only
@@ -2019,30 +1969,6 @@
   </attribute>
   <!-- ******************************************************************** -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_HW396230_SCOM</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>
-      Nimbus DD2+: able to set L3/NCU skip group scope via SCOM
-    </description>
-    <chipEcFeature>
-      <chip>
-        <name>ENUM_ATTR_NAME_NIMBUS</name>
-        <ec>
-          <value>0x20</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
-        </ec>
-      </chip>
-      <chip>
-        <name>ENUM_ATTR_NAME_CUMULUS</name>
-        <ec>
-          <value>0x10</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
-        </ec>
-      </chip>
-    </chipEcFeature>
-  </attribute>
-  <!-- ******************************************************************** -->
-  <attribute>
     <id>ATTR_CHIP_EC_FEATURE_HW405880_LCO_IN_RETENTION</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
@@ -2061,10 +1987,10 @@
   </attribute>
   <!-- ******************************************************************** -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_OPTIMAL_LCO_SCAN_ONLY</id>
+    <id>ATTR_CHIP_EC_FEATURE_HW386657</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Nimbus DD1 only: set the optimal dial setups for LCO's
+      Nimbus DD1 only: set the optimal dial setups for LCO's via scan
     </description>
     <chipEcFeature>
       <chip>
@@ -2078,30 +2004,6 @@
   </attribute>
   <!-- ******************************************************************** -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_OPTIMAL_LCO_SCOM</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>
-      Nimbus DD2+: set the optimal dial setups for LCO's
-    </description>
-    <chipEcFeature>
-      <chip>
-        <name>ENUM_ATTR_NAME_NIMBUS</name>
-        <ec>
-          <value>0x20</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
-        </ec>
-      </chip>
-      <chip>
-        <name>ENUM_ATTR_NAME_CUMULUS</name>
-        <ec>
-          <value>0x10</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
-        </ec>
-      </chip>
-    </chipEcFeature>
-  </attribute>
-  <!-- ******************************************************************** -->
-  <attribute>
     <id>ATTR_CHIP_EC_FEATURE_DISABLE_CP_ME</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
@@ -2119,31 +2021,24 @@
   </attribute>
   <!-- ******************************************************************** -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_OPTIMAL_LARX_STCX_PERF</id>
+    <id>ATTR_CHIP_EC_FEATURE_UNTUNED_LARX_STCX_PERF</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Nimbus DD2+: set the optimal dial setups for larx/stcx
+      Nimbus DD1: Larx/stcx dials are non performance tuned
     </description>
     <chipEcFeature>
       <chip>
         <name>ENUM_ATTR_NAME_NIMBUS</name>
         <ec>
           <value>0x20</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
-        </ec>
-      </chip>
-      <chip>
-        <name>ENUM_ATTR_NAME_CUMULUS</name>
-        <ec>
-          <value>0x10</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
+          <test>LESS_THAN</test>
         </ec>
       </chip>
     </chipEcFeature>
   </attribute>
   <!-- ******************************************************************** -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_HW409069</id>
+    <id>ATTR_CHIP_EC_FEATURE_NOT_HW409069</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
       Nimbus DD2+: HW409069 load_larx protection not activated because of dtag_data_resp
@@ -2154,14 +2049,7 @@
         <name>ENUM_ATTR_NAME_NIMBUS</name>
         <ec>
           <value>0x20</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
-        </ec>
-      </chip>
-      <chip>
-        <name>ENUM_ATTR_NAME_CUMULUS</name>
-        <ec>
-          <value>0x10</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
+          <test>LESS_THAN</test>
         </ec>
       </chip>
     </chipEcFeature>
@@ -3148,6 +3036,113 @@
     </chipEcFeature>
   </attribute>
 
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_HW391162</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Nimbus DD1 only: spoof pb_init in cache contained mode
+      Enables L2 checkers to monitor for transactions arbitrating
+      to broadcast onto the fabric
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_SCAN_SICR_TLBIE_QUIESCE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Nimbus DD1 only: scan ON NCU_TLBIE_QUISCE fence
+      for non-cache contained modes.  Flush state corrected in HW
+      for future revisions
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_CXA_P9NDD1_SPY_NAMES</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Use Nimbus DD1 CXA spy register definition names
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_DDRPHY_P9NDD1_SPY_NAMES</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Use Nimbus DD1 DDR PHY spy register definition names
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Program MCA ECC logic to support Nimbus DD1
+      asynchronus boundary crossing requirements
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_CORE_P9NDD1</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Nimbus DD1 core spy behavior qualifier
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
   <!-- ******************************************************************** -->
   <!-- Memory Section                                                       -->
   <!-- ******************************************************************** -->
@@ -3524,7 +3519,7 @@
     <id>ATTR_CHIP_EC_FEATURE_HW404176_ASSERT_SCAN_CLK</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Only MC in Cumulus need to generate scan clock in even cycle instead of odd
+      Cumulus only: MC chiplet requires scan clock in even cycle instead of odd
     </description>
     <chipEcFeature>
       <chip>
@@ -3541,7 +3536,7 @@
     <id>ATTR_CHIP_EC_FEATURE_HW406337</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Cumulus only dropping MC chiplet fence during arrayinit
+      Cumulus only: dropping MC chiplet fence during arrayinit
     </description>
     <chipEcFeature>
       <chip>
@@ -3646,24 +3641,6 @@
   </attribute>
   <!-- ******************************************************************** -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_POSTDD1N_DPLL_SETTINGS</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>
-      Post DD1 update : Used for new DD2 settings such as ..._EXTERNAL_JUMP_VALUES latch is new for DD2. True if:
-      Nimbus EC greater than or equal to 20
-    </description>
-    <chipEcFeature>
-      <chip>
-        <name>ENUM_ATTR_NAME_NIMBUS</name>
-        <ec>
-          <value>0x20</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
-        </ec>
-      </chip>
-    </chipEcFeature>
-  </attribute>
-  <!-- ******************************************************************** -->
-  <attribute>
     <id>ATTR_CHIP_EC_FEATURE_INT_DD1</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>