diff options
| author | Thi Tran <thi@us.ibm.com> | 2014-04-04 15:30:36 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2014-04-06 17:59:45 -0500 |
| commit | 446e97faa867094d1628a5c83b7b1d094c0f5064 (patch) | |
| tree | bcdb3e8e5f3b90262c61cc100f8c232f4d15c3eb /src/usr | |
| parent | 6d0eaa6dab973a952a38ec2f859d1e8df59e972a (diff) | |
| download | talos-hostboot-446e97faa867094d1628a5c83b7b1d094c0f5064.tar.gz talos-hostboot-446e97faa867094d1628a5c83b7b1d094c0f5064.zip | |
SW253122: 810 HWP: Memory Fast Powerdown mode debug needed for performance
Change-Id: Iaa6bb5540e1c4d511add8861d01d347f97c981a6
CQ:SW253122
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/10152
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/10155
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr')
6 files changed, 1304 insertions, 165 deletions
diff --git a/src/usr/hwpf/hwp/initfiles/mba_def.initfile b/src/usr/hwpf/hwp/initfiles/mba_def.initfile index 4eaf3be5f..4a66dca3a 100644 --- a/src/usr/hwpf/hwp/initfiles/mba_def.initfile +++ b/src/usr/hwpf/hwp/initfiles/mba_def.initfile @@ -1,9 +1,16 @@ -#-- $Id: mba_def.initfile,v 1.62 2014/02/18 17:25:16 yctschan Exp $ +#-- $Id: mba_def.initfile,v 1.68 2014/04/04 16:46:15 jdsloat Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.68|jdsloat | 4/04/14| Turned off Power controls for GA1 concerns - Turn back on at a later date +#-- 1.67|tschang | 4/01/14| Adjusted the PUP Avail and SEPD/FEPD time. +#-- 1.66|tschang | 3/28/14| Removed Performance enhancement for rdtag with DMI freq +#-- |baysah | 3/31/14| Added def_margin_pup_fast=12 and def_margin_pup_slow=0 for Yuen with values from Randy/Anuwat +#-- 1.65|tschang | 3/18/14| Fixed typos in the dly7 settings from 0001 to 01111 +#-- 1.64|baysah | 3/05/14| Added MBA Power Ctrol Settings and backed out the refresh avoidance settings until spec benchmark results +#-- 1.63|tschang | 3/03/14| Performance enhancement for rdtag with DMI freq, refresh avoidance and CFG_PUP_AVAIL #-- 1.62|tschang | 2/14/14| Set Safe mode throttle when ATTR_CENTAUR_EC_ENABLE_SAFE_MODE_THROTTLE is 1 #-- 1.61|tschang | 2/14/14| Safe mode throttle using sys attributes ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP, ATTR_MRW_MEM_THROTTLE_DENOMINATOR #-- 1.60|tschang | 2/03/14| Removed CDIMM TYPE and replace with custom dimm @@ -222,6 +229,8 @@ define def_equal_test = (SYS.ATTR_SCRATCH_UINT32_1 == SYS.ATTR_SCRATCH_UINT # mba tmr0 register timings are added to the value below define def_margin1 = (1); define def_margin2 = (0); +define def_margin_pup_fast = (7); +define def_margin_pup_slow = (0); define def_margin_rdtag = (4); @@ -1471,6 +1480,16 @@ define def_mcb_addr_total22_max24 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATT define def_mcb_addr_total22_max25 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 8) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 22 )); ####################################### +# MBA01_MBA_MBAREFAQ Base Address: 0x03010436 +# MBA23_MBA_MBAREFAQ Base Address: 0x03010c36 +####################################### + +scom 0x03010436 { + bits , scom_data , ATTR_FUNCTIONAL, expr; +# 0:63 , 0xE1FFFFC421020C00 , 1 , any; #Enable Dynamic Refresh Avoidance with coef2 + 0:63 , 0x6591B48421021400 , 1 , any; #Old Default settings to turn off Dynamic refresh avoidance +} +####################################### # MBA01_MBA_RRQ0Q Base Address: 0x0301040E # MBA23_MBA_RRQ0Q Base Address: 0x03010C0E ####################################### @@ -1781,7 +1800,7 @@ scom 0x0301040B { 8:11 , 0b1000 + def_margin2 , 1 , (CENTAUR.ATTR_MSS_FREQ == 1866) || (CENTAUR.ATTR_MSS_FREQ == 2133); # RRDM_dly 3 D 8:11 , 0b1001 + def_margin2 , 1 , (CENTAUR.ATTR_MSS_FREQ == 2400); # RRDM_dly 3 D # fails will 0 margin 12:15 - 12:15 , 0b0001 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys7 == 1); # RWSMSR_dly 4 + 12:15 , 0b0111 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys7 == 1); # RWSMSR_dly 4 12:15 , 0b1000 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys8 == 1); # RWSMSR_dly 4 12:15 , 0b1001 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys9 == 1); # RWSMSR_dly 4 12:15 , 0b1010 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys10 == 1); # RWSMSR_dly 4 @@ -1790,7 +1809,7 @@ scom 0x0301040B { 12:15 , 0b1101 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys13 == 1); # RWSMSR_dly 4 12:15 , 0b1110 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys14 == 1); # RWSMSR_dly 4 12:15 , 0b1111 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys15 == 1); # RWSMSR_dly 4 - 16:19 , 0b0001 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys7 == 1); # RWSMDR_dly 5 + 16:19 , 0b0111 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys7 == 1); # RWSMDR_dly 5 16:19 , 0b1000 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys8 == 1); # RWSMDR_dly 5 16:19 , 0b1001 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys9 == 1); # RWSMDR_dly 5 16:19 , 0b1010 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys10 == 1); # RWSMDR_dly 5 @@ -1799,7 +1818,7 @@ scom 0x0301040B { 16:19 , 0b1101 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys13 == 1); # RWSMDR_dly 5 16:19 , 0b1110 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys14 == 1); # RWSMDR_dly 5 16:19 , 0b1111 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys15 == 1); # RWSMDR_dly 5 - 20:23 , 0b0001 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys7 == 1); # RWDM_dly 6 + 20:23 , 0b0111 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys7 == 1); # RWDM_dly 6 20:23 , 0b1000 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys8 == 1); # RWDM_dly 6 20:23 , 0b1001 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys9 == 1); # RWDM_dly 6 20:23 , 0b1010 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys10 == 1); # RWDM_dly 6 @@ -1990,17 +2009,28 @@ scom 0x03010432 { scom 0x03010434 { bits , scom_data , ATTR_FUNCTIONAL, expr; # 3:5 , 0b010 , 1 , any; # cfg_min_max_domains 36 - 6:10 , 0b00100 , 1 , (def_MBARPC0Q_cfg_pup_avail_dly4 == 1); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b00101 , 1 , (def_MBARPC0Q_cfg_pup_avail_dly5 == 1); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b00110 , 1 , (def_MBARPC0Q_cfg_pup_avail_dly6 == 1); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b00111 , 1 , (def_MBARPC0Q_cfg_pup_avail_dly7 == 1); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b01000 , 1 , (def_MBARPC0Q_cfg_pup_avail_dly8 == 1); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b01101 , 1 , (def_MBARPC0Q_cfg_pup_avail_dly13 == 1); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b10000 , 1 , (def_MBARPC0Q_cfg_pup_avail_dly16 == 1); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b10100 , 1 , (def_MBARPC0Q_cfg_pup_avail_dly20 == 1); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b10111 , 1 , (def_MBARPC0Q_cfg_pup_avail_dly23 == 1); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b11010 , 1 , (def_MBARPC0Q_cfg_pup_avail_dly26 == 1); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b11101 , 1 , (def_MBARPC0Q_cfg_pup_avail_dly29 == 1); # MBARPC0Q_cfg_pup_avail 36 + 6:10 , 0b00100 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly4 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail - performance enhancemnt + 6:10 , 0b00100 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly4 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail - performance enhancemnt + 6:10 , 0b00101 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly5 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36 + 6:10 , 0b00101 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly5 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36 + 6:10 , 0b00110 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly6 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36 + 6:10 , 0b00110 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly6 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36 + 6:10 , 0b00111 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly7 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36 + 6:10 , 0b00111 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly7 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36 + 6:10 , 0b01000 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly8 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36 + 6:10 , 0b01000 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly8 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36 + 6:10 , 0b01101 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly13 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36 + 6:10 , 0b01101 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly13 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36 + 6:10 , 0b10000 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly16 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36 + 6:10 , 0b10000 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly16 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36 + 6:10 , 0b10100 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly20 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36 + 6:10 , 0b10100 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly20 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36 + 6:10 , 0b10111 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly23 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36 + 6:10 , 0b10111 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly23 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36 + 6:10 , 0b11010 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly26 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36 + 6:10 , 0b11010 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly26 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36 + 6:10 , 0b11101 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly29 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36 + 6:10 , 0b11101 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly29 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36 11:15 , 0b00011 , 1 , (def_MBARPC0Q_cfg_pdn_pup_dly3 == 1); # MBARPC0Q_cfg_pup_pup 37 11:15 , 0b00100 , 1 , (def_MBARPC0Q_cfg_pdn_pup_dly4 == 1); # MBARPC0Q_cfg_pup_pup 37 11:15 , 0b00101 , 1 , (def_MBARPC0Q_cfg_pdn_pup_dly5 == 1); # MBARPC0Q_cfg_pup_pup 37 @@ -2009,7 +2039,9 @@ scom 0x03010434 { 16:20 , 0b00100 , 1 , (def_MBARPC0Q_cfg_pup_pdn_dly4 == 1); # MBARPC0Q_cfg_pup_pdn 38 16:20 , 0b00101 , 1 , (def_MBARPC0Q_cfg_pup_pdn_dly5 == 1); # MBARPC0Q_cfg_pup_pdn 38 16:20 , 0b00110 , 1 , (def_MBARPC0Q_cfg_pup_pdn_dly6 == 1); # MBARPC0Q_cfg_pup_pdn 38 -# 22 , 0b1 , 1 , any; # cfg_min_domain_reduction_enable set to 1 to enable power controls + 22 , 0b0 , 1 , any; # cfg_min_domain_reduction_enable set to 1 to enable power controls + 23:32 , 0b0000000011, 1 , any; # Set min doman reduction time to 30.7 us (10.245us * 3) + 43 , 0b0 , 1 , any; # Use 1 in 8k 2:1 cycle pulses for min domain reduction time interval } # MBAPC1Q power control settings reg 1 diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config.xml b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config.xml index 2b78bb57f..ec2dbd275 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config.xml +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- COPYRIGHT International Business Machines Corp. 2013,2014 --> <!-- --> <!-- p1 --> <!-- --> @@ -20,11 +20,753 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<hwpErrors> -<!-- $Id: memory_mss_eff_config.xml,v 1.1 2013/06/19 18:27:53 bellows Exp $ --> +<!-- $Id: memory_mss_eff_config.xml,v 1.2 2014/04/01 17:07:22 asaetow Exp $ --> <!-- For file ../../ipl/fapi/mss_eff_config.C --> <!-- // *! OWNER NAME : Anuwat Saetow Email: asaetow@us.ibm.com --> <!-- // *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com --> +<hwpErrors> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_LRDIMM_INVALID_EXEC</rc> + <description>Invalid exec of mss_lrdimm_eff_config function in + mss_eff_config </description> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_INVALID_TERM_EXEC</rc> + <description>Invalid exec of mss_eff_config_termination function in + mss_eff_config </description> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_DDR4_INVALID_EXEC</rc> + <description>Invalid exec of mss_eff_config_ddr4 function in + mss_eff_config </description> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_MISMATCH_EMPTY</rc> + <description>Plug rule violation, one position is empty but other are present + </description> + <FFDC>TARGET_MBA</FFDC> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_0</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_1</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_0</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_1</ffdc> + <callout> + <procedure>MEMORY_PLUGGING_ERROR</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_MISMATCH_SIDE</rc> + <description>Plug rule violation, sides do not match + </description> + <FFDC>TARGET_MBA</FFDC> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_0</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_1</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_0</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_1</ffdc> + + <callout> + <procedure>MEMORY_PLUGGING_ERROR</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_MISMATCH_TOP</rc> + <description>Plug rule violation, top and bottom do not match + </description> + <FFDC>TARGET_MBA</FFDC> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_0</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_1</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_0</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_1</ffdc> + + <callout> + <procedure>MEMORY_PLUGGING_ERROR</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_INCOMPATABLE_DRAM_GEN</rc> + <description>Incompatable DRAM generation + </description> + <FFDC>TARGET_MBA</FFDC> + <ffdc>DRAM_DEVICE_TYPE_0_0</ffdc> + <ffdc>DRAM_DEVICE_TYPE_0_1</ffdc> + <ffdc>DRAM_DEVICE_TYPE_1_0</ffdc> + <ffdc>DRAM_DEVICE_TYPE_1_1</ffdc> + + <callout> + <procedure>MEMORY_PLUGGING_ERROR</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_INCOMPATABLE_DIMM_TYPE</rc> + <description>Incompatable DIMM type + </description> + <FFDC>TARGET_MBA</FFDC> + <ffdc>MODULE_TYPE_0_0</ffdc> + <ffdc>MODULE_TYPE_0_1</ffdc> + <ffdc>MODULE_TYPE_1_0</ffdc> + <ffdc>MODULE_TYPE_1_1</ffdc> + + <callout> + <procedure>MEMORY_PLUGGING_ERROR</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_INCOMPATABLE_DIMM_RANKS</rc> + <description>Incompatable DIMM ranks + </description> + <FFDC>TARGET_MBA</FFDC> + <ffdc>NUM_RANKS_0_0</ffdc> + <ffdc>NUM_RANKS_0_1</ffdc> + <ffdc>NUM_RANKS_1_0</ffdc> + <ffdc>NUM_RANKS_1_1</ffdc> + + <callout> + <procedure>MEMORY_PLUGGING_ERROR</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_INCOMPATABLE_DIMM_BANKS</rc> + <description>Incompatable DIMM banks + </description> + <FFDC>TARGET_MBA</FFDC> + <ffdc>SDRAM_BANKS_0_0</ffdc> + <ffdc>SDRAM_BANKS_0_1</ffdc> + <ffdc>SDRAM_BANKS_1_0</ffdc> + <ffdc>SDRAM_BANKS_1_1</ffdc> + + <callout> + <procedure>MEMORY_PLUGGING_ERROR</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_INCOMPATABLE_DIMM_ROWS</rc> + <description>Incompatable DIMM rows + </description> + <FFDC>TARGET_MBA</FFDC> + <ffdc>SDRAM_ROWS_0_0</ffdc> + <ffdc>SDRAM_ROWS_0_1</ffdc> + <ffdc>SDRAM_ROWS_1_0</ffdc> + <ffdc>SDRAM_ROWS_1_1</ffdc> + + <callout> + <procedure>MEMORY_PLUGGING_ERROR</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_INCOMPATABLE_DIMM_COLUMNS</rc> + <description>Incompatable DIMM columns + </description> + <FFDC>TARGET_MBA</FFDC> + <ffdc>SDRAM_COLS_0_0</ffdc> + <ffdc>SDRAM_COLS_0_1</ffdc> + <ffdc>SDRAM_COLS_1_0</ffdc> + <ffdc>SDRAM_COLS_1_1</ffdc> + + <callout> + <procedure>MEMORY_PLUGGING_ERROR</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_INCOMPATABLE_DRAM_BUS_WIDTH</rc> + <description>Incompatable DRAM primary bus width + </description> + <FFDC>TARGET_MBA</FFDC> + <ffdc>BUS_WIDTH_0_0</ffdc> + <ffdc>BUS_WIDTH_0_1</ffdc> + <ffdc>BUS_WIDTH_1_0</ffdc> + <ffdc>BUS_WIDTH_1_1</ffdc> + + <callout> + <procedure>MEMORY_PLUGGING_ERROR</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_UNSUPPORTED_MODULE_MEMORY_BUS_WIDTH</rc> + <description>Unsupported DRAM bus width, only 64bit with ECC extension is allowed + </description> + <ffdc>MODULE_MEMORY_BUS_WIDTH</ffdc> + <FFDC>TARGET_MBA</FFDC> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_INCOMPATABLE_DRAM_WIDTH</rc> + <description>Incompatable DRAM width + </description> + <FFDC>TARGET_MBA</FFDC> + <ffdc>DRAM_WIDTH_0_0</ffdc> + <ffdc>DRAM_WIDTH_0_1</ffdc> + <ffdc>DRAM_WIDTH_1_0</ffdc> + <ffdc>DRAM_WIDTH_1_1</ffdc> + + <callout> + <procedure>MEMORY_PLUGGING_ERROR</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_DRAM_DEVICE_ERROR</rc> + <description>Unknown DRAM type + </description> + <ffdc>DRAM_DEVICE_TYPE</ffdc> + <FFDC>TARGET_MBA</FFDC> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_MOD_TYPE_ERROR</rc> + <description>Unknown DIMM type + </description> + <ffdc>MOD_TYPE</ffdc> + <FFDC>TARGET_MBA</FFDC> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_SDRAM_BANK_ERROR</rc> + <description>Unknown DRAM bank + </description> + <ffdc>SDRAM_BANKS</ffdc> + <FFDC>TARGET_MBA</FFDC> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_SDRAM_ROWS_ERROR</rc> + <description>Unknown DRAM rows + </description> + <ffdc>SDRAM_ROWS</ffdc> + <FFDC>TARGET_MBA</FFDC> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_SDRAM_COLS_ERROR</rc> + <description>Unknown DRAM cols + </description> + <ffdc>SDRAM_COLS</ffdc> + <FFDC>TARGET_MBA</FFDC> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_DRAM_WIDTH_16_ERROR</rc> + <description>Unsupported DRAM width x16 + </description> + <ffdc>DRAM_WIDTH</ffdc> + <FFDC>TARGET_MBA</FFDC> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_DRAM_WIDTH_32_ERROR</rc> + <description>Unsupported DRAM width x32 + </description> + <ffdc>DRAM_WIDTH</ffdc> + <FFDC>TARGET_MBA</FFDC> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_DRAM_WIDTH_ERROR</rc> + <description>Unknown DRAM width + </description> + <FFDC>DRAM_WIDTH</FFDC> + <FFDC>TARGET_MBA</FFDC> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_DRAM_DENSITY_ERR</rc> + <description>Unsupported DRAM density + </description> + <ffdc>SDRAM_DENSITY</ffdc> + <FFDC>TARGET_MBA</FFDC> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_CWL_CALC_ERR</rc> + <description>Error calculating CWL + </description> + <ffdc>CWL_VAL</ffdc> + <FFDC>TARGET_MBA</FFDC> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_RDIMM_UNSUPPORTED_TYPE</rc> + <description>Currently unsupported IBM_TYPE + </description> + <ffdc>UNSUPPORTED_VAL</ffdc> + <FFDC>TARGET_MBA</FFDC> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_UDIMM_UNSUPPORTED_TYPE</rc> + <description>Currently unsupported IBM_TYPE + </description> + <ffdc>UNSUPPORTED_VAL</ffdc> + <FFDC>TARGET_MBA</FFDC> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_DIMM_UNSUPPORTED_TYPE</rc> + <description>Currently unsupported IBM_TYPE + </description> + <ffdc>UNSUPPORTED_VAL</ffdc> + <FFDC>TARGET_MBA</FFDC> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_MSS_FREQ</rc> + <description>Invalid ATTR_MSS_FREQ + </description> + <FFDC>TARGET_MBA</FFDC> + <ffdc>FREQ_VAL</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> + + <gard> + <target>TARGET_MBA</target> + <priority>HIGH</priority> + </gard> +</hwpError> </hwpErrors> diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config_rank_group.xml b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config_rank_group.xml index e643c0456..8c6bbd573 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config_rank_group.xml +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config_rank_group.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- COPYRIGHT International Business Machines Corp. 2013,2014 --> <!-- --> <!-- p1 --> <!-- --> @@ -20,18 +20,74 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<hwpErrors> -<!-- $Id: memory_mss_eff_config_rank_group.xml,v 1.1 2013/06/19 18:27:57 bellows Exp $ --> +<!-- $Id: memory_mss_eff_config_rank_group.xml,v 1.2 2014/04/01 17:06:22 asaetow Exp $ --> <!-- For file ../../ipl/fapi/mss_eff_config_rank_group.C --> <!-- // *! OWNER NAME : Anuwat Saetow Email: asaetow@us.ibm.com --> <!-- // *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com --> <!-- // | | | Changed BACKUP to Mark Bellows. --> -<!-- Original Source for RC_ERROR_001A memory_errors.xml --> +<hwpErrors> +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_RANK_GROUP_NON_MATCH_RANKS</rc> + <description>Plug rule violation in mss_eff_config_rank_group + due to num_ranks_per_dimm not matching.</description> + <FFDC>TARGET_MBA</FFDC> + <callout> + <procedure>MEMORY_PLUGGING_ERROR</procedure> + <priority>HIGH</priority> + </callout> + + <callout> + <target>TARGET_MBA</target> + <priority>MEDIUM</priority> + </callout> + + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> +</hwpError> + +<!-- *********************************************************************** --> <hwpError> - <rc>RC_MSS_EFF_CONFIG_RC_ERROR_001A</rc> - <description>Plug rule violation in EFF_CONFIG.</description> + <rc>RC_MSS_EFF_CONFIG_RANK_GROUP_NUM_RANKS_NEQ1</rc> + <description>Plug rule violation in mss_eff_config_rank_group + due to num_ranks_per_dimm not being set correctly.</description> + <FFDC>TARGET_MBA</FFDC> + <callout> + <procedure>MEMORY_PLUGGING_ERROR</procedure> + <priority>HIGH</priority> + </callout> + + <callout> + <target>TARGET_MBA</target> + <priority>MEDIUM</priority> + </callout> + + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> </hwpError> +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_RANK_GROUP_NO_MATCH</rc> + <description>Plug rule violation in mss_eff_config_rank_group + due to no matching case.</description> + <FFDC>TARGET_MBA</FFDC> + <callout> + <procedure>MEMORY_PLUGGING_ERROR</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET_MBA</target> + <priority>MEDIUM</priority> + </callout> + + <deconfigure> + <target>TARGET_MBA</target> + </deconfigure> +</hwpError> +<!-- *********************************************************************** --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C index f1659572e..e6e56574b 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_config.C,v 1.38 2014/01/22 16:49:01 asaetow Exp $ +// $Id: mss_eff_config.C,v 1.43 2014/04/04 14:44:32 jdsloat Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/ // centaur/working/procedures/ipl/fapi/mss_eff_config.C,v $ //------------------------------------------------------------------------------ @@ -44,6 +44,17 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.44 | jdsloat |04-APR-14| Fixed DDR4 ifdef flag +// 1.43 | | | +// 1.42 | asaetow |31-MAR-14| Added ifdef for three #include from Thi and Jake FW Code review. +// | | | Added back in bus_width_extension check from SPD byte8[4:3]. +// | | | NOTE: Only 64bit with ECC extension is allowed. +// | | | Added FFDC error callout from Andrea's FW RAS review. +// | | | NOTE: Do NOT pickup without memory_mss_eff_config.xml v1.2 +// | | | Added comments for commended out code. +// 1.41 | jdsloat |20-MAR-14| FASTEXIT settings in mba_def.initfile are causing fails. Workaround to use SLOWEXIT. SW249561 +// 1.40 | kcook |14-MAR-14| Added call to DDR4 function support +// 1.39 | dcadiga |04-MAR-14| Added isdimm support pass 1 // 1.38 | asaetow |17-JAN-14| Removed mss_eff_config_cke_map, now empty, data from vpd. // | | | Removed mss_eff_config_termination from normal/FW code flow. // | | | Added mss_eff_config_termination to lab only code flow. @@ -161,9 +172,17 @@ #include <mss_eff_config_rank_group.H> #include <mss_eff_config_shmoo.H> -#include <mss_lrdimm_funcs.H> +#ifdef FAPI_MSSLABONLY #include <mss_eff_config_termination.H> +#endif + +#ifdef FAPI_LRDIMM +#include <mss_lrdimm_funcs.H> +#endif +#ifdef FAPI_DDR4 +#include <mss_eff_config_ddr4.H> +#endif //------------------------------------------------------------------------------ @@ -191,20 +210,31 @@ fapi::ReturnCode mss_lrdimm_eff_config( const Target& i_target_mba, ReturnCode rc; FAPI_ERR("Invalid exec of LRDIMM function on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_LRDIMM_INVALID_EXEC); return rc; } #endif - #ifndef FAPI_MSSLABONLY fapi::ReturnCode mss_eff_config_termination( const Target& i_target_mba) { ReturnCode rc; FAPI_ERR("Invalid exec of MSSLABONLY function on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INVALID_TERM_EXEC); + return rc; + +} +#endif + +#ifndef FAPI_DDR4 +fapi::ReturnCode mss_eff_config_ddr4( const Target& i_target_mba) +{ + ReturnCode rc; + + FAPI_ERR("Invalid exec of DDR4 function on %s!", i_target_mba.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_DDR4_INVALID_EXEC); return rc; } @@ -275,10 +305,12 @@ struct mss_eff_config_spd_data uint8_t twtrmin[PORT_SIZE][DIMM_SIZE]; uint8_t trtpmin[PORT_SIZE][DIMM_SIZE]; uint32_t tfawmin[PORT_SIZE][DIMM_SIZE]; + + // Not needed for GA1 CDIMM, will need to enable check for ISDIMM. //uint8_t sdram_optional_features[PORT_SIZE][DIMM_SIZE]; - //uint8_t sdram_thermal_and_refresh_options[PORT_SIZE] - // [DIMM_SIZE]; + //uint8_t sdram_thermal_and_refresh_options[PORT_SIZE][DIMM_SIZE]; //uint8_t module_thermal_sensor[PORT_SIZE][DIMM_SIZE]; + uint8_t fine_offset_tckmin[PORT_SIZE][DIMM_SIZE]; uint8_t fine_offset_taamin[PORT_SIZE][DIMM_SIZE]; uint8_t fine_offset_trcdmin[PORT_SIZE][DIMM_SIZE]; @@ -286,22 +318,20 @@ struct mss_eff_config_spd_data uint8_t fine_offset_trcmin[PORT_SIZE][DIMM_SIZE]; //uint8_t module_specific_section[PORT_SIZE][DIMM_SIZE][57]; - //uint32_t module_id_module_manufacturers_jedec_id_code - // [PORT_SIZE][DIMM_SIZE]; - //uint8_t module_id_module_manufacturing_location[PORT_SIZE] - // [DIMM_SIZE]; - //uint32_t module_id_module_manufacturing_date[PORT_SIZE] - // [DIMM_SIZE]; - //uint32_t module_id_module_serial_number[PORT_SIZE] - // [DIMM_SIZE]; + + // See "svpdMFGtool --inventory" + //uint32_t module_id_module_manufacturers_jedec_id_code[PORT_SIZE][DIMM_SIZE]; + //uint8_t module_id_module_manufacturing_location[PORT_SIZE][DIMM_SIZE]; + //uint32_t module_id_module_manufacturing_date[PORT_SIZE][DIMM_SIZE]; + //uint32_t module_id_module_serial_number[PORT_SIZE][DIMM_SIZE]; //uint32_t cyclical_redundancy_code[PORT_SIZE][DIMM_SIZE]; - // HERE uint8_t module_part_number[PORT_SIZE][DIMM_SIZE][ - // SPD_ATTR_SIZE_18]; + //uint8_t module_part_number[PORT_SIZE][DIMM_SIZE][SPD_ATTR_SIZE_18]; //uint32_t module_revision_code[PORT_SIZE][DIMM_SIZE]; - //uint32_t dram_manufacturer_jedec_id_code[PORT_SIZE] - // [DIMM_SIZE]; - // HERE uint8_t bad_dq_data[PORT_SIZE][DIMM_SIZE] - // [SPD_ATTR_SIZE_80]; + //uint32_t dram_manufacturer_jedec_id_code[PORT_SIZE][DIMM_SIZE]; + + // See VPD parser #A keyword + //uint8_t bad_dq_data[PORT_SIZE][DIMM_SIZE][SPD_ATTR_SIZE_80]; + uint32_t vpd_version[PORT_SIZE][DIMM_SIZE]; }; @@ -313,7 +343,7 @@ struct mss_eff_config_spd_data struct mss_eff_config_atts { uint8_t eff_dimm_ranks_configed[PORT_SIZE][DIMM_SIZE]; - // AST HERE: Needs SPD byte68:76 + // AST HERE: Needs SPD byte68:76, deferred to GA2 for full ISDIMM support uint64_t eff_dimm_rcd_cntl_word_0_15[PORT_SIZE][DIMM_SIZE]; uint8_t eff_dimm_size[PORT_SIZE][DIMM_SIZE]; uint8_t eff_dimm_type; @@ -322,8 +352,10 @@ struct mss_eff_config_atts uint8_t eff_dram_asr; uint8_t eff_dram_bl; uint8_t eff_dram_banks; + // See mss_freq.C //uint8_t eff_dram_cl; + uint8_t eff_dram_cols; uint8_t eff_dram_cwl; uint8_t eff_dram_density; @@ -358,12 +390,16 @@ struct mss_eff_config_atts uint32_t eff_memcal_interval; uint8_t eff_mpr_loc; uint8_t eff_mpr_mode; - // AST HERE: Needs SPD byte33[6:4], currently hard coded to 0 - uint8_t eff_num_dies_per_package[PORT_SIZE][DIMM_SIZE]; + + // AST HERE: Needs SPD byte33[6:4], currently hard coded to 0, removed for GA1 + //uint8_t eff_num_dies_per_package[PORT_SIZE][DIMM_SIZE]; + uint8_t eff_num_drops_per_port; uint8_t eff_num_master_ranks_per_dimm[PORT_SIZE][DIMM_SIZE]; - // AST HERE: Needs source data, currently hard coded to 0 - uint8_t eff_num_packages_per_rank[PORT_SIZE][DIMM_SIZE]; + + // AST HERE: Needs source data, currently hard coded to 0, removed for GA1 + //uint8_t eff_num_packages_per_rank[PORT_SIZE][DIMM_SIZE]; + uint8_t eff_num_ranks_per_dimm[PORT_SIZE][DIMM_SIZE]; uint8_t eff_schmoo_mode; @@ -516,9 +552,12 @@ fapi::ReturnCode mss_eff_config_read_spd_data(fapi::Target i_target_dimm, rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_COLUMNS, &i_target_dimm, p_o_spd_data->sdram_columns[i_port][i_dimm]); if(rc) break; + + // See mss_volt.C //rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_NOMINAL_VOLTAGE, &i_target_dimm, //p_o_spd_data->module_nominal_voltage[i_port][i_dimm]); //if(rc) break; + rc = FAPI_ATTR_GET(ATTR_SPD_NUM_RANKS, &i_target_dimm, p_o_spd_data->num_ranks[i_port][i_dimm]); if(rc) break; @@ -540,6 +579,8 @@ fapi::ReturnCode mss_eff_config_read_spd_data(fapi::Target i_target_dimm, rc = FAPI_ATTR_GET(ATTR_SPD_MTB_DIVISOR, &i_target_dimm, p_o_spd_data->mtb_divisor[i_port][i_dimm]); if(rc) break; + + // See mss_freq.C //rc = FAPI_ATTR_GET(ATTR_SPD_TCKMIN, &i_target_dimm, //p_o_spd_data->tckmin[i_port][i_dimm]); //if(rc) break; @@ -549,6 +590,7 @@ fapi::ReturnCode mss_eff_config_read_spd_data(fapi::Target i_target_dimm, //rc = FAPI_ATTR_GET(ATTR_SPD_TAAMIN, &i_target_dimm, //p_o_spd_data->taamin[i_port][i_dimm]); //if(rc) break; + rc = FAPI_ATTR_GET(ATTR_SPD_TWRMIN, &i_target_dimm, p_o_spd_data->twrmin[i_port][i_dimm]); if(rc) break; @@ -579,6 +621,8 @@ fapi::ReturnCode mss_eff_config_read_spd_data(fapi::Target i_target_dimm, rc = FAPI_ATTR_GET(ATTR_SPD_TFAWMIN, &i_target_dimm, p_o_spd_data->tfawmin[i_port][i_dimm]); if(rc) break; + + // Not needed for GA1 CDIMM, will need to enable check for ISDIMM. //rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_OPTIONAL_FEATURES, &i_target_dimm, //p_o_spd_data->sdram_optional_features[i_port][i_dimm]); //if(rc) break; @@ -589,6 +633,7 @@ fapi::ReturnCode mss_eff_config_read_spd_data(fapi::Target i_target_dimm, //rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_THERMAL_SENSOR, &i_target_dimm, //p_o_spd_data->module_thermal_sensor[i_port][i_dimm]); //if(rc) break; + rc = FAPI_ATTR_GET(ATTR_SPD_FINE_OFFSET_TCKMIN, &i_target_dimm, p_o_spd_data->fine_offset_tckmin[i_port][i_dimm]); if(rc) break; @@ -610,6 +655,8 @@ fapi::ReturnCode mss_eff_config_read_spd_data(fapi::Target i_target_dimm, //&i_target_dimm, //p_o_spd_data->module_specific_section[i_port][i_dimm]); //if(rc) break; + + // See "svpdMFGtool --inventory" //rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_ID_MODULE_MANUFACTURERS_ //JEDEC_ID_CODE, //&i_target_dimm, @@ -634,7 +681,7 @@ fapi::ReturnCode mss_eff_config_read_spd_data(fapi::Target i_target_dimm, //&i_target_dimm, //p_o_spd_data->cyclical_redundancy_code[i_port][i_dimm]); //if(rc) break; - // HERE rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_PART_NUMBER, + //rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_PART_NUMBER, //&i_target_dimm, //p_o_spd_data->module_part_number[i_port][i_dimm]); //if(rc) break; @@ -646,7 +693,9 @@ fapi::ReturnCode mss_eff_config_read_spd_data(fapi::Target i_target_dimm, //&i_target_dimm, //p_o_spd_data->dram_manufacturer_jedec_id_code[i_port][i_dimm]); //if(rc) break; - // HERE rc = FAPI_ATTR_GET(ATTR_SPD_BAD_DQ_DATA, &i_target_dimm, + + // See VPD parser #A keyword + //rc = FAPI_ATTR_GET(ATTR_SPD_BAD_DQ_DATA, &i_target_dimm, //p_o_spd_data->bad_dq_data[i_port][i_dimm]); //if(rc) break; @@ -696,7 +745,6 @@ fapi::ReturnCode mss_eff_config_get_spd_data( if(rc) { FAPI_ERR("Error retrieving assodiated dimms"); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); break; } //------------------------------------------------------------------------------ @@ -709,7 +757,6 @@ fapi::ReturnCode mss_eff_config_get_spd_data( if(rc) { FAPI_ERR("Error retrieving ATTR_MBA_PORT"); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); break; } //------------------------------------------------------------------------------ @@ -718,7 +765,6 @@ fapi::ReturnCode mss_eff_config_get_spd_data( if(rc) { FAPI_ERR("Error retrieving ATTR_MBA_DIMM"); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); break; } //------------------------------------------------------------------------------ @@ -730,7 +776,6 @@ fapi::ReturnCode mss_eff_config_get_spd_data( if(rc) { FAPI_ERR("Error retrieving functional fapi attribute"); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); break; } //------------------------------------------------------------------------------ @@ -747,7 +792,6 @@ fapi::ReturnCode mss_eff_config_get_spd_data( if(rc) { FAPI_ERR("Error reading spd data from caller"); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); break; } } @@ -776,6 +820,15 @@ fapi::ReturnCode mss_eff_config_verify_plug_rules( mss_eff_config_atts *p_i_atts) { fapi::ReturnCode rc; + const fapi::Target& TARGET_MBA = i_target_mba; + uint8_t& CUR_DIMM_SPD_VALID_U8ARRAY_0_0 = + p_i_mss_eff_config_data->cur_dimm_spd_valid_u8array[0][0]; + uint8_t& CUR_DIMM_SPD_VALID_U8ARRAY_0_1 = + p_i_mss_eff_config_data->cur_dimm_spd_valid_u8array[0][1]; + uint8_t& CUR_DIMM_SPD_VALID_U8ARRAY_1_0 = + p_i_mss_eff_config_data->cur_dimm_spd_valid_u8array[1][0]; + uint8_t& CUR_DIMM_SPD_VALID_U8ARRAY_1_1 = + p_i_mss_eff_config_data->cur_dimm_spd_valid_u8array[1][1]; // Identify/Verify DIMM plug rule if ( @@ -795,7 +848,7 @@ fapi::ReturnCode mss_eff_config_verify_plug_rules( ) { FAPI_ERR("Plug rule violation on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_MISMATCH_EMPTY); return rc; } if ( ( @@ -811,7 +864,7 @@ fapi::ReturnCode mss_eff_config_verify_plug_rules( ) && (p_i_mss_eff_config_data->allow_single_port == fapi::ENUM_ATTR_MSS_ALLOW_SINGLE_PORT_FALSE) ) { FAPI_ERR("Plug rule violation on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_MISMATCH_SIDE); return rc; } if ( ( @@ -824,7 +877,7 @@ fapi::ReturnCode mss_eff_config_verify_plug_rules( ) && (p_i_mss_eff_config_data->allow_single_port == fapi::ENUM_ATTR_MSS_ALLOW_SINGLE_PORT_TRUE) ) { FAPI_ERR("Plug rule violation on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_MISMATCH_TOP); return rc; } if ((p_i_mss_eff_config_data-> @@ -871,6 +924,7 @@ fapi::ReturnCode mss_eff_config_verify_spd_data( mss_eff_config_spd_data *p_i_data) { fapi::ReturnCode rc; + const fapi::Target& TARGET_MBA = i_target_mba; // Start Identify/Verify/Assigning values to attributes // Identify/Verify DIMM compatability @@ -895,7 +949,11 @@ fapi::ReturnCode mss_eff_config_verify_spd_data( { FAPI_ERR("Incompatable DRAM generation on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + uint8_t& DRAM_DEVICE_TYPE_0_0 = p_i_data->dram_device_type[0][0]; + uint8_t& DRAM_DEVICE_TYPE_0_1 = p_i_data->dram_device_type[0][1]; + uint8_t& DRAM_DEVICE_TYPE_1_0 = p_i_data->dram_device_type[1][0]; + uint8_t& DRAM_DEVICE_TYPE_1_1 = p_i_data->dram_device_type[1][1]; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DRAM_GEN); return rc; } //------------------------------------------------------------------------------ @@ -918,7 +976,11 @@ fapi::ReturnCode mss_eff_config_verify_spd_data( ) { FAPI_ERR("Incompatable DIMM type on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + uint8_t& MODULE_TYPE_0_0 = p_i_data->module_type[0][0]; + uint8_t& MODULE_TYPE_0_1 = p_i_data->module_type[0][1]; + uint8_t& MODULE_TYPE_1_0 = p_i_data->module_type[1][0]; + uint8_t& MODULE_TYPE_1_1 = p_i_data->module_type[1][1]; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DIMM_TYPE); return rc; } //------------------------------------------------------------------------------ @@ -941,7 +1003,11 @@ fapi::ReturnCode mss_eff_config_verify_spd_data( ) { FAPI_ERR("Incompatable DIMM ranks on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + uint8_t& NUM_RANKS_0_0 = p_i_data->num_ranks[0][0]; + uint8_t& NUM_RANKS_0_1 = p_i_data->num_ranks[0][1]; + uint8_t& NUM_RANKS_1_0 = p_i_data->num_ranks[1][0]; + uint8_t& NUM_RANKS_1_1 = p_i_data->num_ranks[1][1]; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DIMM_RANKS); return rc; } //------------------------------------------------------------------------------ @@ -964,7 +1030,11 @@ fapi::ReturnCode mss_eff_config_verify_spd_data( ) { FAPI_ERR("Incompatable DIMM banks on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + uint8_t& SDRAM_BANKS_0_0 = p_i_data->sdram_banks[0][0]; + uint8_t& SDRAM_BANKS_0_1 = p_i_data->sdram_banks[0][1]; + uint8_t& SDRAM_BANKS_1_0 = p_i_data->sdram_banks[1][0]; + uint8_t& SDRAM_BANKS_1_1 = p_i_data->sdram_banks[1][1]; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DIMM_BANKS); return rc; } //------------------------------------------------------------------------------ @@ -987,7 +1057,11 @@ fapi::ReturnCode mss_eff_config_verify_spd_data( ) { FAPI_ERR("Incompatable DIMM rows on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + uint8_t& SDRAM_ROWS_0_0 = p_i_data->sdram_rows[0][0]; + uint8_t& SDRAM_ROWS_0_1 = p_i_data->sdram_rows[0][1]; + uint8_t& SDRAM_ROWS_1_0 = p_i_data->sdram_rows[1][0]; + uint8_t& SDRAM_ROWS_1_1 = p_i_data->sdram_rows[1][1]; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DIMM_ROWS); return rc; } //------------------------------------------------------------------------------ @@ -1010,7 +1084,11 @@ fapi::ReturnCode mss_eff_config_verify_spd_data( ) { FAPI_ERR("Incompatable DIMM cols on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + uint8_t& SDRAM_COLS_0_0 = p_i_data->sdram_columns[0][0]; + uint8_t& SDRAM_COLS_0_1 = p_i_data->sdram_columns[0][1]; + uint8_t& SDRAM_COLS_1_0 = p_i_data->sdram_columns[1][0]; + uint8_t& SDRAM_COLS_1_1 = p_i_data->sdram_columns[1][1]; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DIMM_COLUMNS); return rc; } //------------------------------------------------------------------------------ @@ -1034,51 +1112,24 @@ fapi::ReturnCode mss_eff_config_verify_spd_data( { FAPI_ERR("Incompatable DRAM primary bus width on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + uint8_t& BUS_WIDTH_0_0 = p_i_data->module_memory_bus_width[0][0]; + uint8_t& BUS_WIDTH_0_1 = p_i_data->module_memory_bus_width[0][1]; + uint8_t& BUS_WIDTH_1_0 = p_i_data->module_memory_bus_width[1][0]; + uint8_t& BUS_WIDTH_1_1 = p_i_data->module_memory_bus_width[1][1]; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DRAM_BUS_WIDTH); return rc; } //------------------------------------------------------------------------------ - /* AST HERE: Needs SPD byte8[4:3] - if ( - (p_i_data->spd_module_memory_bus_width_extension_u8array[0][0] - != p_i_data->spd_module_memory_bus_width_extension_u8array[1][0]) - || - ( - (p_i_atts->eff_num_drops_per_port - == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) - && - ( - (p_i_data->spd_module_memory_bus_width_extension_u8array[0][1] - != p_i_data->spd_module_memory_bus_width_extension_u8array[1][1]) - ) - || - ( - (p_i_data->spd_module_memory_bus_width_extension_u8array[0][0] - != p_i_data->spd_module_memory_bus_width_extension_u8array[0][1]) - ) - ) - ) - { - FAPI_ERR("Incompatable DRAM bus width extension on %s!", - i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); - return rc; - } -//------------------------------------------------------------------------------ - if ( - (p_i_data->module_memory_bus_width[0][0] - != fapi::ENUM_ATTR_SPD_MODULE_MEMORY_BUS_WIDTH_W64) - || - (p_i_data->spd_module_memory_bus_width_extension_u8array[0][0] - != fapi::ENUM_ATTR_SPD_MODULE_MEMORY_BUS_WIDTH_EXTENSION_W8) - ) + // ATTR_SPD_MODULE_MEMORY_BUS_WIDTH, SPD byte8[4:3], only 64bit with ECC extension is allowed + if ( p_i_data->module_memory_bus_width[0][0] != + fapi::ENUM_ATTR_SPD_MODULE_MEMORY_BUS_WIDTH_WE64 ) { FAPI_ERR("Unsupported DRAM bus width on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + uint8_t& MODULE_MEMORY_BUS_WIDTH = p_i_data->module_memory_bus_width[0][0]; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_UNSUPPORTED_MODULE_MEMORY_BUS_WIDTH); return rc; } - */ //------------------------------------------------------------------------------ if ( (p_i_data->dram_width[0][0] @@ -1099,7 +1150,11 @@ fapi::ReturnCode mss_eff_config_verify_spd_data( ) { FAPI_ERR("Incompatable DRAM width on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + uint8_t& DRAM_WIDTH_0_0 = p_i_data->dram_width[0][0]; + uint8_t& DRAM_WIDTH_0_1 = p_i_data->dram_width[0][1]; + uint8_t& DRAM_WIDTH_1_0 = p_i_data->dram_width[1][0]; + uint8_t& DRAM_WIDTH_1_1 = p_i_data->dram_width[1][1]; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DRAM_WIDTH); return rc; } //------------------------------------------------------------------------------ @@ -1128,10 +1183,11 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( mss_eff_config_atts *p_o_atts) { fapi::ReturnCode rc; + const fapi::Target& TARGET_MBA = i_target_mba; // set select atts members to non-zero p_o_atts->eff_dram_al = fapi::ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_1; // Always use AL = CL - 1. - p_o_atts->eff_dram_dll_ppd = fapi::ENUM_ATTR_EFF_DRAM_DLL_PPD_FASTEXIT; // Always use fast exit. + p_o_atts->eff_dram_dll_ppd = fapi::ENUM_ATTR_EFF_DRAM_DLL_PPD_SLOWEXIT; // FASTEXIT settings in mba_def.initfile are causing fails. Workaround to use SLOWEXIT. p_o_atts->eff_dram_dll_reset = fapi::ENUM_ATTR_EFF_DRAM_DLL_RESET_YES; // Always reset DLL at start of IPL. p_o_atts->eff_dram_srt = fapi::ENUM_ATTR_EFF_DRAM_SRT_EXTEND; // Always use extended operating temp range. p_o_atts->mss_cal_step_enable = 0xFF; // Always run all cal steps @@ -1163,8 +1219,9 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( p_o_atts->eff_dram_gen = fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4; break; default: + uint8_t& DRAM_DEVICE_TYPE=p_i_data->dram_device_type[0][0]; FAPI_ERR("Unknown DRAM type on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_DRAM_DEVICE_ERROR); return rc; } //------------------------------------------------------------------------------ @@ -1192,7 +1249,8 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( break; default: FAPI_ERR("Unknown DIMM type on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + uint8_t& MOD_TYPE = p_i_data->module_type[0][0]; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_MOD_TYPE_ERROR); return rc; } //------------------------------------------------------------------------------ @@ -1219,7 +1277,8 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( break; default: FAPI_ERR("Unknown DRAM banks on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + uint8_t& SDRAM_BANKS= p_i_data->sdram_banks[0][0]; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_SDRAM_BANK_ERROR); return rc; } //------------------------------------------------------------------------------ @@ -1242,7 +1301,8 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( break; default: FAPI_ERR("Unknown DRAM rows on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + uint8_t& SDRAM_ROWS= p_i_data->sdram_rows[0][0]; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_SDRAM_ROWS_ERROR); return rc; } //------------------------------------------------------------------------------ @@ -1262,10 +1322,12 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( break; default: FAPI_ERR("Unknown DRAM cols on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + uint8_t& SDRAM_COLS= p_i_data->sdram_columns[0][0]; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_SDRAM_COLS_ERROR); return rc; } //------------------------------------------------------------------------------ + uint8_t& DRAM_WIDTH= p_i_data->dram_width[0][0]; if (p_i_data->dram_width[0][0] == fapi::ENUM_ATTR_SPD_DRAM_WIDTH_W4) { @@ -1290,7 +1352,7 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( p_o_atts->eff_dram_width = fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X16; FAPI_ERR("Unsupported DRAM width x16 on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_DRAM_WIDTH_16_ERROR); return rc; } else if (p_i_data->dram_width[0][0] @@ -1299,14 +1361,14 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( p_o_atts->eff_dram_width = fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X32; FAPI_ERR("Unsupported DRAM width x32 on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_DRAM_WIDTH_32_ERROR); return rc; } else { FAPI_ERR("Unknown DRAM width on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_DRAM_WIDTH_ERROR); return rc; } //------------------------------------------------------------------------------ @@ -1348,11 +1410,12 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( } else { + uint8_t& SDRAM_DENSITY = p_i_data->sdram_density[l_cur_mba_port][l_cur_mba_dimm]; p_i_mss_eff_config_data->cur_dram_density = 1; if (p_i_mss_eff_config_data->allow_single_port == fapi::ENUM_ATTR_MSS_ALLOW_SINGLE_PORT_FALSE) { FAPI_ERR("Unsupported DRAM density on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_DRAM_DENSITY_ERR); return rc; } } @@ -1606,8 +1669,9 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( } else { + const uint16_t& CWL_VAL = (TWO_MHZ/p_i_mss_eff_config_data->mss_freq); FAPI_ERR("Error calculating CWL"); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_CWL_CALC_ERR); return rc; } //------------------------------------------------------------------------------ @@ -1692,6 +1756,7 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE; } + uint8_t& UNSUPPORTED_VAL = p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm]; // AST HERE: Needed SPD byte33[7,1:0], for expanded IBM_TYPE if ( p_o_atts->eff_dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM ) { if (p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 1) { @@ -1703,7 +1768,7 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( } else { p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_UNDEFINED; FAPI_ERR("Currently unsupported IBM_TYPE on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_RDIMM_UNSUPPORTED_TYPE); return rc; } } else if (( p_o_atts->eff_dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM ) && ( p_o_atts->eff_custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES )) { if (p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 1) { @@ -1713,7 +1778,7 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( } else { p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_UNDEFINED; FAPI_ERR("Currently unsupported IBM_TYPE on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_UDIMM_UNSUPPORTED_TYPE); return rc; } } else if ( p_o_atts->eff_dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { FAPI_INF("Will set LR atts after orig eff_config functions"); @@ -1721,7 +1786,7 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( } else { p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_UNDEFINED; FAPI_ERR("Currently unsupported DIMM_TYPE on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_DIMM_UNSUPPORTED_TYPE); return rc; } } else { p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port] @@ -1868,10 +1933,12 @@ fapi::ReturnCode mss_eff_config_write_eff_atts( rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_BL, &i_target_mba, p_i_atts->eff_dram_bl); if(rc) break; + // See mss_freq.C //rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_CL, &i_target_mba, //p_i_atts->eff_dram_cl); //if(rc) break; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_COLS, &i_target_mba, p_i_atts->eff_dram_cols); if(rc) break; @@ -1965,18 +2032,24 @@ fapi::ReturnCode mss_eff_config_write_eff_atts( rc = FAPI_ATTR_SET(ATTR_EFF_MPR_MODE, &i_target_mba, p_i_atts->eff_mpr_mode); if(rc) break; - rc = FAPI_ATTR_SET(ATTR_EFF_NUM_DIES_PER_PACKAGE, &i_target_mba, - p_i_atts->eff_num_dies_per_package); - if(rc) break; + + // AST HERE: Needs SPD byte33[6:4], currently hard coded to 0, removed for GA1 + //rc = FAPI_ATTR_SET(ATTR_EFF_NUM_DIES_PER_PACKAGE, &i_target_mba, + // p_i_atts->eff_num_dies_per_package); + //if(rc) break; + rc = FAPI_ATTR_SET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba, p_i_atts->eff_num_drops_per_port); if(rc) break; rc = FAPI_ATTR_SET(ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, &i_target_mba, p_i_atts->eff_num_master_ranks_per_dimm); if(rc) break; - rc = FAPI_ATTR_SET(ATTR_EFF_NUM_PACKAGES_PER_RANK, &i_target_mba, - p_i_atts->eff_num_packages_per_rank); - if(rc) break; + + // AST HERE: Needs source data, currently hard coded to 0, removed for GA1 + //rc = FAPI_ATTR_SET(ATTR_EFF_NUM_PACKAGES_PER_RANK, &i_target_mba, + // p_i_atts->eff_num_packages_per_rank); + //if(rc) break; + rc = FAPI_ATTR_SET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, p_i_atts->eff_num_ranks_per_dimm); if(rc) break; @@ -2084,6 +2157,17 @@ fapi::ReturnCode mss_eff_config_write_eff_atts( //------------------------------------------------------------------------------ fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba) { + const fapi::Target& TARGET_MBA = i_target_mba; +#ifdef FAPI_DDR4 + fapi::ReturnCode rc; + rc = mss_eff_config_ddr4(i_target_mba); + if(rc) + { + FAPI_ERR("Error from mss_eff_config_ddr4()"); + return rc; + } +#endif +#ifndef FAPI_DDR4 /* Initialize Variables */ const char * const PROCEDURE_NAME = "mss_eff_config"; fapi::ReturnCode rc; @@ -2105,11 +2189,25 @@ fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba) FAPI_INF("STARTING %s on %s \n", PROCEDURE_NAME, i_target_mba.toEcmdString()); + do + { + FAPI_INF("Setup and VPD attributes if needbe\n"); + +#ifdef FAPI_MSSLABONLY + FAPI_INF("Lab only: Setup and VPD attributes if needbe\n"); + + rc = mss_eff_config_termination_vpd(i_target_mba); if(rc) break; + if(rc) + { + FAPI_ERR("Error from mss_eff_config_termination_vpd()"); + break; + } +#endif + // Added call to mss_eff_pre_config() for Mike Pardeik (power/thermal). rc = mss_eff_pre_config(i_target_mba); if(rc) return rc; - do - { + //------------------------------------------------------------------------------ // Grab allow single port data rc = FAPI_ATTR_GET(ATTR_MSS_ALLOW_SINGLE_PORT, &i_target_mba, p_l_mss_eff_config_data->allow_single_port); @@ -2131,7 +2229,8 @@ fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba) FAPI_ERR("Invalid ATTR_MSS_FREQ = %d on %s!", p_l_mss_eff_config_data->mss_freq, i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + uint32_t& FREQ_VAL = p_l_mss_eff_config_data->mss_freq; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_MSS_FREQ); break; } FAPI_INF("mss_freq = %d, tCK_in_ps= %d on %s.", @@ -2149,7 +2248,6 @@ fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba) if(rc) { FAPI_ERR("Error from mss_eff_config_get_spd_data()"); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); break; } @@ -2159,7 +2257,6 @@ fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba) if(rc) { FAPI_ERR("Error from mss_eff_config_verify_plug_rules()"); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); break; } @@ -2173,7 +2270,6 @@ fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba) if(rc) { FAPI_ERR("Error from mss_eff_config_verify_spd_data()"); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); break; } } @@ -2184,7 +2280,6 @@ fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba) if(rc) { FAPI_ERR("Error from mss_eff_config_setup_eff_atts()"); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); break; } @@ -2194,7 +2289,6 @@ fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba) if(rc) { FAPI_ERR("Error from mss_eff_config_write_eff_atts()"); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); break; } @@ -2210,7 +2304,6 @@ fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba) if(rc) { FAPI_ERR("Error from mss_lrdimm_eff_config()"); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); break; } } @@ -2226,7 +2319,6 @@ fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba) if(rc) { FAPI_ERR("Error from mss_eff_config_termination()"); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); break; } } @@ -2246,7 +2338,7 @@ fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba) delete p_l_mss_eff_config_data; delete p_l_spd_data; delete p_l_atts; - +#endif return rc; } // end mss_eff_config() } // extern "C" diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C index 2e7772ab5..f85f04984 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_config_rank_group.C,v 1.11 2013/08/16 13:45:45 kcook Exp $ +// $Id: mss_eff_config_rank_group.C,v 1.12 2014/04/01 17:10:21 asaetow Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_rank_group.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -46,6 +46,9 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.13 | | | +// 1.12 | asaetow |31-MAR-13| Added FFDC error callout from Andrea's FW RAS review. +// | | | NOTE: Do NOT pickup without memory_mss_eff_config_rank_group.xml v1.2 // 1.11 | kcook |16-AUG-13| Added LRDIMM support. // 1.10 | asaetow |17-APR-13| Removed 32G CDIMM 1R dualdrop workaround. // | | | NOTE: Needs mss_draminit_training.C v1.57 or newer. @@ -106,6 +109,7 @@ extern "C" { fapi::ReturnCode mss_eff_config_rank_group(const fapi::Target i_target_mba) { fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS; const char * const PROCEDURE_NAME = "mss_eff_config_rank_group"; + const fapi::Target& TARGET_MBA = i_target_mba; FAPI_INF("*** Running %s on %s ... ***", PROCEDURE_NAME, i_target_mba.toEcmdString()); const uint8_t PORT_SIZE = 2; @@ -254,7 +258,7 @@ fapi::ReturnCode mss_eff_config_rank_group(const fapi::Target i_target_mba) { if (num_ranks_per_dimm_u8array[cur_port][0] != num_ranks_per_dimm_u8array[cur_port][1]) { FAPI_ERR("%s: FAILED!", PROCEDURE_NAME); FAPI_ERR("Plug rule violation, num_ranks_per_dimm=%d[0],%d[1] on %s PORT%d!", num_ranks_per_dimm_u8array[cur_port][0], num_ranks_per_dimm_u8array[cur_port][1], i_target_mba.toEcmdString(), cur_port); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_RANK_GROUP_NON_MATCH_RANKS); return rc; } primary_rank_group0_u8array[cur_port] = 0; @@ -278,7 +282,7 @@ fapi::ReturnCode mss_eff_config_rank_group(const fapi::Target i_target_mba) { } else if (num_ranks_per_dimm_u8array[cur_port][0] != 1) { FAPI_ERR("%s: FAILED!", PROCEDURE_NAME); FAPI_ERR("Plug rule violation, num_ranks_per_dimm=%d[0],%d[1] on %s PORT%d!", num_ranks_per_dimm_u8array[cur_port][0], num_ranks_per_dimm_u8array[cur_port][1], i_target_mba.toEcmdString(), cur_port); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_RANK_GROUP_NUM_RANKS_NEQ1); return rc; } } else if ((num_ranks_per_dimm_u8array[cur_port][0] == 0) && (num_ranks_per_dimm_u8array[cur_port][1] == 0)) { @@ -293,7 +297,7 @@ fapi::ReturnCode mss_eff_config_rank_group(const fapi::Target i_target_mba) { } else { FAPI_ERR("%s: FAILED!", PROCEDURE_NAME); FAPI_ERR("Plug rule violation, num_ranks_per_dimm=%d[0],%d[1] on %s PORT%d!", num_ranks_per_dimm_u8array[cur_port][0], num_ranks_per_dimm_u8array[cur_port][1], i_target_mba.toEcmdString(), cur_port); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_RANK_GROUP_NO_MATCH); return rc; } tertiary_rank_group0_u8array[cur_port] = INVALID; diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C index 6de49b088..2d184c7dc 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_config_termination.C,v 1.44 2014/03/07 20:59:06 mjjones Exp $ +// $Id: mss_eff_config_termination.C,v 1.46 2014/03/14 17:08:42 kcook Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_termination.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -42,6 +42,8 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.46 | kcook |14-MAR-14| Fixed create_db_ddr4 stub function definition +// 1.45 | kcook |14-MAR-14| Added DDR4 support // 1.44 | mjjones |07-MAR-14| Only compile if FAPI_MSSLABONLY defined // 1.43 | dcadiga |04-MAR-14| Added in ISDimm support for KG // 1.42 | asaetow |22-JAN-14| Fixed target "const fapi::Target" to "const fapi::Target&" for mss_eff_config.C v1.38 and mss_eff_config_termination.H v1.2 @@ -107,6 +109,9 @@ #include <fapi.H> #include <mss_lrdimm_funcs.H> +#include <mss_ddr4_funcs.H> +#include <mss_lrdimm_ddr4_funcs.H> + using namespace fapi; @@ -135,6 +140,36 @@ ReturnCode mss_lrdimm_term_atts(const Target& i_target_mba) } #endif +#ifndef FAPI_DDR4 +fapi::ReturnCode mss_create_rcd_ddr4(const Target& i_target_mba) +{ + ReturnCode rc; + + FAPI_ERR("Invalid exec of mss_create_rcd_ddr4 on %s!", i_target_mba.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + return rc; + +} +fapi::ReturnCode mss_create_db_ddr4(const Target& i_target_mba) +{ + ReturnCode rc; + + FAPI_ERR("Invalid exec of mss_create_db_ddr4 on %s!", i_target_mba.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + return rc; + +} +fapi::ReturnCode mss_lrdimm_ddr4_term_atts(const Target& i_target_mba) +{ + ReturnCode rc; + + FAPI_ERR("Invalid exec of mss_lrdimm_ddr4_term_atts on %s!", i_target_mba.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + return rc; + +} +#endif + //---------------------------------------------------------------------- // ENUMs and CONSTs //---------------------------------------------------------------------- @@ -252,6 +287,14 @@ uint32_t cdimm_rca_1r_1600_mba0[STORE_ARRAY_SIZE] = //RCB4 +uint32_t cdimm_rcb4_2r_1600_mba0[210] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD68625,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD68625,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,24,24,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,93,91,90,92,4,5,5,4,0,0,4,2,5,4,10,3,6,3,5,10,9,8,11,12,11,11,11,12,10,0,27,0,2,0,0,0,6,0,10,0,29,0,16,0,0,0,8,0,91,98,93,98,11,8,12,4,1,0,3,0,10,4,12,5,10,8,6,10,7,6,11,13,16,13,7,5,10,0,30,0,8,0,0,0,7,0,12,0,31,0,10,0,0,0,4,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE +}; + +uint32_t cdimm_rcb4_2r_1600_mba1[210] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD68625,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD68625,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,24,24,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,108,117,108,117,18,18,17,22,21,22,24,24,28,17,15,18,17,20,18,15,19,21,14,14,18,14,15,14,10,0,55,0,15,0,0,0,0,0,13,0,56,0,0,0,0,0,13,0,117,114,117,113,21,22,26,22,23,24,25,24,25,27,18,26,20,24,26,20,21,22,19,20,17,18,24,29,0,0,53,0,1,0,0,0,0,0,0,0,52,0,11,0,0,0,1,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE +}; + //RCC /* @@ -549,6 +592,31 @@ uint32_t rdimm_kg3_1600_r4_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100 uint32_t rdimm_kg3_1600_r4_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; +//KG4 + +uint32_t rdimm_kg4_1600_r1_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,24,24,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE +}; + +uint32_t rdimm_kg4_1600_r1_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,24,24,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE +}; + +uint32_t rdimm_kg4_1600_r2b_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,24,24,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE +}; + +uint32_t rdimm_kg4_1600_r2b_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,24,24,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE +}; + +uint32_t rdimm_kg4_1600_r2e_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,24,24,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE +}; + +uint32_t rdimm_kg4_1600_r2e_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,24,24,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE +}; + +uint32_t rdimm_kg4_1600_r4_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x40,0x80,0x00,0x00,0x00,0x00,0x40,0x80,0x40,0x80,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,24,24,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE +}; + +uint32_t rdimm_kg4_1600_r4_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x40,0x80,0x00,0x00,0x00,0x00,0x40,0x80,0x40,0x80,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,24,24,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE +}; //Base Array Which Is Used For Looper To Setup Data uint32_t base_var_array[210]; @@ -595,8 +663,8 @@ extern "C" { rc = FAPI_ATTR_GET(ATTR_MSS_BLUEWATERFALL_BROKEN, &l_target_centaur, l_bluewaterfall_broken); if(rc) return rc; // Look up a lab only attribute in non-host boot environments #ifdef FAPIECMD - //rc = FAPI_ATTR_GET(ATTR_LAB_ONLY_RAW_CARD, NULL, l_lab_raw_card_u8); if(rc) return rc; - l_lab_raw_card_u8 = fapi::ENUM_ATTR_LAB_ONLY_RAW_CARD_KG3; + rc = FAPI_ATTR_GET(ATTR_LAB_ONLY_RAW_CARD, NULL, l_lab_raw_card_u8); if(rc) return rc; + //l_lab_raw_card_u8 = fapi::ENUM_ATTR_LAB_ONLY_RAW_CARD_KG3; #endif @@ -809,12 +877,111 @@ extern "C" { } #endif + else if ( (l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4) && ( (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) ) { + //KG4 + if( l_target_mba_pos == 0){ + if ( l_mss_freq <= 1733 ) { // 1600Mbps + if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { + //Removed Width Check, use settings for either x8 or x4 + memcpy(base_var_array,rdimm_kg4_1600_r1_mba0,210*sizeof(uint32_t)); + FAPI_INF("LRDIMM: Base - KG4 RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){ + //Removed Width Check, use settings for either x8 or x4 + memcpy(base_var_array,rdimm_kg4_1600_r1_mba0,210*sizeof(uint32_t)); + FAPI_INF("KG4 r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 4)){ + + memcpy(base_var_array,rdimm_kg4_1600_r2e_mba0,210*sizeof(uint32_t)); + FAPI_INF("KG4 r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + + } + else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 8)){ + memcpy(base_var_array,rdimm_kg4_1600_r2b_mba0,210*sizeof(uint32_t)); + FAPI_INF("KG4 r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){ + memcpy(base_var_array,rdimm_kg4_1600_r4_mba0,210*sizeof(uint32_t)); + FAPI_INF("KG4 r40 %d MBA%s Using 1333 Settings\n",l_mss_freq,i_target_mba.toEcmdString()); + } + + else{ + FAPI_ERR("Invalid Dimm Type KG4 FREQ %d MBA0\n",l_mss_freq); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + // memcpy(base_var_array,cdimm_rcb4_2r_1600_mba0,210*sizeof(uint32_t)); + // FAPI_INF("CDIMM rcb4_2r_1600 MBA0 \n"); + }//1600 + }//MBA0 + else{ + if ( l_mss_freq <= 1733 ) { // 1600Mbps + if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { + //Removed Width Check, use settings for either x8 or x4 + memcpy(base_var_array,rdimm_kg4_1600_r1_mba1,210*sizeof(uint32_t)); + FAPI_INF("LRDIMM: Base - KG4 RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){ + //Removed Width Check, use settings for either x8 or x4 + memcpy(base_var_array,rdimm_kg4_1600_r1_mba1,210*sizeof(uint32_t)); + FAPI_INF("KG4 r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 4)){ + + memcpy(base_var_array,rdimm_kg4_1600_r2e_mba1,210*sizeof(uint32_t)); + FAPI_INF("KG4 r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + + } + else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 8)){ + memcpy(base_var_array,rdimm_kg4_1600_r2b_mba1,210*sizeof(uint32_t)); + FAPI_INF("KG4 r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){ + memcpy(base_var_array,rdimm_kg4_1600_r4_mba1,210*sizeof(uint32_t)); + FAPI_INF("KG4 r40 %d MBA%s Using 1333 Settings\n",l_mss_freq,i_target_mba.toEcmdString()); + } + + else{ + FAPI_ERR("Invalid Dimm Type KG4 FREQ %d MBA0\n",l_mss_freq); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + }//1600 + }//MBA1 + } + else if((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM) || (l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)){ if(l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) { //This is a CDIMM! - memcpy(base_var_array,cdimm_default,210*sizeof(uint32_t)); + if(l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4) { + //2R Cdimm RCB4 + l_dimm_rc_u8 = 2; + if ( l_mss_freq <= 1733 ) { // 1600Mbps + if(l_target_mba_pos == 0){ + memcpy(base_var_array,cdimm_rcb4_2r_1600_mba0,210*sizeof(uint32_t)); + FAPI_INF("CDIMM rcb4_2r_1600 MBA0 \n"); + //memcpy(base_var_array,cdimm_rcb_2r_1600_mba0,210*sizeof(uint32_t)); + //FAPI_INF("CDIMM rcb4 Running with RCB DDR3 Settings MBA0\n"); + + } + else if(l_target_mba_pos == 1){ + memcpy(base_var_array,cdimm_rcb4_2r_1600_mba1,210*sizeof(uint32_t)); + FAPI_INF("CDIMM rcb4_2r_1600 MBA1 \n"); + //memcpy(base_var_array,cdimm_rcb_2r_1600_mba1,210*sizeof(uint32_t)); + //FAPI_INF("CDIMM rcb4 Running with RCB DDR3 Settings MBA1\n"); + + + } + else{ + FAPI_ERR("Invalid Dimm Type CDIMM RCB4 FREQ %d\n",l_mss_freq); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + } + }//CDIMM RCB4 + else { + memcpy(base_var_array,cdimm_default,210*sizeof(uint32_t)); + } }//End CDIMM else{ //This is a UDIMM! @@ -1091,8 +1258,8 @@ extern "C" { attr_eff_dimm_rcd_mirror_mode[1][1] = base_var_array[i++]; // keep 7 - //Fix for VPD Mode for lab rdimm - if(((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM)) && (l_lab_raw_card_u8 != fapi::ENUM_ATTR_LAB_ONLY_RAW_CARD_KG3)){ + //Fix for VPD Mode for lab rdimm + if(((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) || ( l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4) ) && (l_lab_raw_card_u8 != fapi::ENUM_ATTR_LAB_ONLY_RAW_CARD_KG3)){ FAPI_INF("RON i %d SHOULD NOT BE HERE\n",i); attr_vpd_dram_ron[0][0] = base_var_array[i++]; attr_vpd_dram_ron[0][1] = base_var_array[i++]; @@ -1296,7 +1463,7 @@ extern "C" { } #ifdef FAPIECMD - if(l_lab_raw_card_u8 == fapi::ENUM_ATTR_LAB_ONLY_RAW_CARD_KG3){ + if(l_lab_raw_card_u8 == fapi::ENUM_ATTR_LAB_ONLY_RAW_CARD_KG3 ){ FAPI_INF("In KG3 Incrementing I for ron i is %d\n",i); attr_vpd_dram_ron[0][0] = base_var_array[i++]; attr_vpd_dram_ron[0][1] = base_var_array[i++]; @@ -1521,7 +1688,24 @@ extern "C" { //Now Setup the RCD - Done Here to Steal Code From Anuwats Version Of Eff Config Termination - if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM ) { + if ( l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4 && + ( (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || + (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) ) { + + rc = mss_create_rcd_ddr4(i_target_mba); + + if (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) { + rc = mss_create_db_ddr4(i_target_mba); + } + + if (rc) + { + FAPI_ERR("Setting DDR4 RCD words failed \n"); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + + } + else if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM ) { for( int l_port = 0; l_port < PORT_SIZE; l_port += 1 ) { for( int l_dimm = 0; l_dimm < DIMM_SIZE; l_dimm += 1 ) { uint64_t l_mss_freq_mask = 0xFFFFFFFFFFCFFFFFLL; @@ -1600,7 +1784,7 @@ extern "C" { // For DDR4 uint8_t l_attr_eff_dram_lpasr = ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_NORMAL; // 0 - uint8_t l_attr_eff_write_crc = ENUM_ATTR_EFF_WRITE_CRC_ENABLE; // 0; change ENUMS: DISABLE=0, ENABLE=1 + uint8_t l_attr_eff_write_crc = ENUM_ATTR_EFF_WRITE_CRC_DISABLE; // 0; change ENUMS: DISABLE=0, ENABLE=1 uint8_t l_attr_eff_mpr_page = 0; // 0; maybe add ENUMS: PG0=0, PG1=1, PG2=2, PG3=3 for more readability? uint8_t l_attr_eff_geardown_mode = ENUM_ATTR_EFF_GEARDOWN_MODE_HALF; // 0 uint8_t l_attr_eff_per_dram_access = ENUM_ATTR_EFF_PER_DRAM_ACCESS_DISABLE; // 1; change ENUMS: DISABLE=0; ENABLE=1 @@ -1626,7 +1810,7 @@ extern "C" { uint8_t l_attr_eff_write_dbi = ENUM_ATTR_EFF_WRITE_DBI_DISABLE; // 0 uint8_t l_attr_eff_read_dbi = ENUM_ATTR_EFF_READ_DBI_DISABLE; // 0 // uint8_t l_attr_tccd_l = ENUM_ATTR_TCCD_L_5NCK; // 5; maybe add ENUMS: 4NCK=4, 5NCK=5, 6NCK=6; 7NCK=7, 8NCK=8 for better readability - uint8_t l_attr_tccd_l = 5; // 5; maybe add ENUMS: 4NCK=4, 5NCK=5, 6NCK=6; 7NCK=7, 8NCK=8 for better readability + // uint8_t l_attr_tccd_l = 5; // 5; maybe add ENUMS: 4NCK=4, 5NCK=5, 6NCK=6; 7NCK=7, 8NCK=8 for better readability /* * Remove Before COMMIT @@ -1708,6 +1892,15 @@ extern "C" { attr_eff_gpo[0] = (uint8_t)5; attr_eff_gpo[1] = (uint8_t)5; */ + if ( l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4 ) { + // Set for CDIMM B4 + attr_eff_rlo[0] = (uint8_t)0; + attr_eff_rlo[1] = (uint8_t)0; + attr_eff_wlo[0] = (uint8_t)0; + attr_eff_wlo[1] = (uint8_t)0; + attr_eff_gpo[0] = (uint8_t)5; + attr_eff_gpo[1] = (uint8_t)5; + } } else if(l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM){ @@ -1724,11 +1917,18 @@ extern "C" { } else if(l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM){ //LRDIMM - attr_eff_rlo[0] = (uint8_t)6; - attr_eff_rlo[1] = (uint8_t)6; - //Set WLO and GPO - attr_eff_wlo[0] = (uint8_t)255; // WLO = -1, 2's complement - attr_eff_wlo[1] = (uint8_t)255; + if ( l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4 ) { + attr_eff_rlo[0] = (uint8_t)5; + attr_eff_rlo[1] = (uint8_t)5; + attr_eff_wlo[0] = (uint8_t)1; + attr_eff_wlo[1] = (uint8_t)1; + } + else { + attr_eff_rlo[0] = (uint8_t)6; + attr_eff_rlo[1] = (uint8_t)6; + attr_eff_wlo[0] = (uint8_t)255; // WLO = -1, 2's complement + attr_eff_wlo[1] = (uint8_t)255; + } attr_eff_gpo[0] = (uint8_t)7; attr_eff_gpo[1] = (uint8_t)7; @@ -1774,12 +1974,14 @@ extern "C" { rc = FAPI_ATTR_SET(ATTR_VREF_DQ_TRAIN_VALUE, &i_target_mba, l_attr_vref_dq_train_value); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_VREF_DQ_TRAIN_RANGE, &i_target_mba, l_attr_vref_dq_train_range); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_VREF_DQ_TRAIN_ENABLE, &i_target_mba, l_attr_vref_dq_train_enable); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_TCCD_L, &i_target_mba, l_attr_tccd_l); if(rc) return rc; + // rc = FAPI_ATTR_SET(ATTR_TCCD_L, &i_target_mba, l_attr_tccd_l); if(rc) return rc; FAPI_INF("Set some attributes, setting more\n"); // Set attributes rc = FAPI_ATTR_SET(ATTR_MSS_CAL_STEP_ENABLE, &i_target_mba, l_attr_mss_cal_step_enable); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc; + if(l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) { // do not override DDR4 RCD + rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc; + } rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_IBT, &i_target_mba, attr_eff_dimm_rcd_ibt); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_MIRROR_MODE, &i_target_mba, attr_eff_dimm_rcd_mirror_mode); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, attr_eff_cen_rd_vref); if(rc) return rc; @@ -1811,11 +2013,14 @@ extern "C" { FAPI_INF("Setting more VPD ATTRS\n"); - //Fix for VPD Mode for lab rdimm - if((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM)){ + //Fix for VPD Mode for lab rdimm and CDIMM B4 + if((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) + || (l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4) ){ FAPI_INF("IN RDIMM ATTR SETTING\n"); rc = FAPI_ATTR_SET(ATTR_MSS_CAL_STEP_ENABLE, &i_target_mba, l_attr_mss_cal_step_enable); if(rc) return rc; - rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc; + if(l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) { // do not override DDR4 RCD + rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc; + } rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_IBT, &i_target_mba, attr_eff_dimm_rcd_ibt); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_MIRROR_MODE, &i_target_mba, attr_eff_dimm_rcd_mirror_mode); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, attr_eff_cen_rd_vref); if(rc) return rc; @@ -1973,8 +2178,16 @@ extern "C" { if(l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) - { - rc = mss_lrdimm_term_atts(i_target_mba); + { + if(l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) + { + rc = mss_lrdimm_term_atts(i_target_mba); + } + else + { + rc = mss_lrdimm_ddr4_term_atts(i_target_mba); + } + if (rc) { FAPI_ERR("Setting LR term atts failed \n"); @@ -2020,13 +2233,13 @@ extern "C" { spd_custom); if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_DEVICE_TYPE, &l_target_dimm_array[l_dimm_index], + rc = FAPI_ATTR_GET(ATTR_SPD_DRAM_DEVICE_TYPE, &l_target_dimm_array[l_dimm_index], spd_device_type); if(rc) break; } if(rc) break; - if ((spd_custom == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_NO) || spd_device_type == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4) { + if ((spd_custom == fapi::ENUM_ATTR_SPD_CUSTOM_NO) || spd_device_type == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) { // update soem constants for ISDIMMs |
