diff options
| author | Van Lee <vanlee@us.ibm.com> | 2012-11-06 15:36:52 -0600 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2012-11-15 15:06:54 -0600 |
| commit | 23e85eef437248ac55ad710b5dff0a62db997f71 (patch) | |
| tree | 2e7bc226155d2105990610111457b5fd60f8360f /src/usr/targeting/common/xmltohb/simics_MURANO.system.xml | |
| parent | 888aada9569eb455f31ae4bc59a0372ac4665fd8 (diff) | |
| download | talos-hostboot-23e85eef437248ac55ad710b5dff0a62db997f71.tar.gz talos-hostboot-23e85eef437248ac55ad710b5dff0a62db997f71.zip | |
Add PCIE attributes support
Change-Id: Icfd0639cf694622a9f2bdb23a48b7fb9f5b41961
RTC: 42175
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2242
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/targeting/common/xmltohb/simics_MURANO.system.xml')
| -rw-r--r-- | src/usr/targeting/common/xmltohb/simics_MURANO.system.xml | 384 |
1 files changed, 384 insertions, 0 deletions
diff --git a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml index 60b92a9fe..40b269637 100644 --- a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml +++ b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml @@ -326,6 +326,102 @@ <default>0</default> </attribute> <!-- End pm_attributes_all_plat.xml --> + + <!-- PROC_PCIE_ attributes --> + <attribute> + <id>PROC_PCIE_IOP_G2_PLL_CONTROL0</id> + <default> + 0x18F4,0x18F4 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_G3_PLL_CONTROL0</id> + <default> + 0x086C,0x086C + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_PCS_CONTROL0</id> + <default> + 0x3AE8,0x3AE8 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_PCS_CONTROL1</id> + <default> + 0x5CB9,0x5CB9 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0</id> + <default> + 0x146,0x146 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1</id> + <default> + 0x6D7,0x6D7 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_RX_PEAK</id> + <default> + 0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_RX_SDL</id> + <default> + 0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_RX_VGA_CONTROL2</id> + <default> + 0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_TX_BWLOSS1</id> + <default> + 0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_TX_FIFO_OFFSET</id> + <default> + 0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_TX_RCVRDETCNTL</id> + <default> + 0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_ZCAL_CONTROL</id> + <default> + 0x000,0x000 + </default> + </attribute> + <!-- End PROC_PCIE_ attributes --> + + <!-- The default value of the following three attributes are written by --> + <!-- the FSP. They are included here because VBU/VPO uses faked PNOR. --> + <attribute> + <id>PROC_PCIE_IOP_CONFIG</id> + <default>0</default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_SWAP</id> + <default>0</default> + </attribute> + <attribute> + <id>PROC_PCIE_PHB_ACTIVE</id> + <default>0xE0</default> + </attribute> </targetInstance> <!-- Murano n0p0 EX units --> @@ -927,6 +1023,102 @@ <default>0</default> </attribute> <!-- End pm_attributes_all_plat.xml --> + + <!-- PROC_PCIE_ attributes --> + <attribute> + <id>PROC_PCIE_IOP_G2_PLL_CONTROL0</id> + <default> + 0x18F4,0x18F4 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_G3_PLL_CONTROL0</id> + <default> + 0x086C,0x086C + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_PCS_CONTROL0</id> + <default> + 0x3AE8,0x3AE8 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_PCS_CONTROL1</id> + <default> + 0x5CB9,0x5CB9 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0</id> + <default> + 0x146,0x146 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1</id> + <default> + 0x6D7,0x6D7 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_RX_PEAK</id> + <default> + 0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_RX_SDL</id> + <default> + 0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_RX_VGA_CONTROL2</id> + <default> + 0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_TX_BWLOSS1</id> + <default> + 0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_TX_FIFO_OFFSET</id> + <default> + 0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_TX_RCVRDETCNTL</id> + <default> + 0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_ZCAL_CONTROL</id> + <default> + 0x000,0x000 + </default> + </attribute> + <!-- End PROC_PCIE_ attributes --> + + <!-- The default value of the following three attributes are written by --> + <!-- the FSP. They are included here because VBU/VPO uses faked PNOR. --> + <attribute> + <id>PROC_PCIE_IOP_CONFIG</id> + <default>0</default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_SWAP</id> + <default>0</default> + </attribute> + <attribute> + <id>PROC_PCIE_PHB_ACTIVE</id> + <default>0xE0</default> + </attribute> </targetInstance> <!-- Murano n0p1 EX units --> @@ -1529,6 +1721,102 @@ <default>0</default> </attribute> <!-- End pm_attributes_all_plat.xml --> + + <!-- PROC_PCIE_ attributes --> + <attribute> + <id>PROC_PCIE_IOP_G2_PLL_CONTROL0</id> + <default> + 0x18F4,0x18F4 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_G3_PLL_CONTROL0</id> + <default> + 0x086C,0x086C + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_PCS_CONTROL0</id> + <default> + 0x3AE8,0x3AE8 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_PCS_CONTROL1</id> + <default> + 0x5CB9,0x5CB9 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0</id> + <default> + 0x146,0x146 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1</id> + <default> + 0x6D7,0x6D7 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_RX_PEAK</id> + <default> + 0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_RX_SDL</id> + <default> + 0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_RX_VGA_CONTROL2</id> + <default> + 0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_TX_BWLOSS1</id> + <default> + 0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_TX_FIFO_OFFSET</id> + <default> + 0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_TX_RCVRDETCNTL</id> + <default> + 0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_ZCAL_CONTROL</id> + <default> + 0x000,0x000 + </default> + </attribute> + <!-- End PROC_PCIE_ attributes --> + + <!-- The default value of the following three attributes are written by --> + <!-- the FSP. They are included here because VBU/VPO uses faked PNOR. --> + <attribute> + <id>PROC_PCIE_IOP_CONFIG</id> + <default>0</default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_SWAP</id> + <default>0</default> + </attribute> + <attribute> + <id>PROC_PCIE_PHB_ACTIVE</id> + <default>0xE0</default> + </attribute> </targetInstance> <!-- Murano n0p2 EX units --> @@ -2132,6 +2420,102 @@ <default>0</default> </attribute> <!-- End pm_attributes_all_plat.xml --> + + <!-- PROC_PCIE_ attributes --> + <attribute> + <id>PROC_PCIE_IOP_G2_PLL_CONTROL0</id> + <default> + 0x18F4,0x18F4 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_G3_PLL_CONTROL0</id> + <default> + 0x086C,0x086C + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_PCS_CONTROL0</id> + <default> + 0x3AE8,0x3AE8 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_PCS_CONTROL1</id> + <default> + 0x5CB9,0x5CB9 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0</id> + <default> + 0x146,0x146 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1</id> + <default> + 0x6D7,0x6D7 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_RX_PEAK</id> + <default> + 0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B,0xB1B + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_RX_SDL</id> + <default> + 0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A,0x294A + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_RX_VGA_CONTROL2</id> + <default> + 0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451,0x9451 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_TX_BWLOSS1</id> + <default> + 0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_TX_FIFO_OFFSET</id> + <default> + 0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294,0x4294 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_TX_RCVRDETCNTL</id> + <default> + 0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151,0x2151 + </default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_ZCAL_CONTROL</id> + <default> + 0x000,0x000 + </default> + </attribute> + <!-- End PROC_PCIE_ attributes --> + + <!-- The default value of the following three attributes are written by --> + <!-- the FSP. They are included here because VBU/VPO uses faked PNOR. --> + <attribute> + <id>PROC_PCIE_IOP_CONFIG</id> + <default>0</default> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_SWAP</id> + <default>0</default> + </attribute> + <attribute> + <id>PROC_PCIE_PHB_ACTIVE</id> + <default>0xE0</default> + </attribute> </targetInstance> <!-- Murano n0p3 EX units --> |
