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authorJoe McGill <jmcgill@us.ibm.com>2016-05-27 08:51:42 -0500
committerDaniel M. Crowell <dcrowell@us.ibm.com>2016-08-25 10:05:10 -0400
commit76d3403f3d6a5a562fbe781bbe937383e02b28bb (patch)
tree4cb50a0ae0de173f882bb4851b7d00bb4dbe9e39 /src/usr/isteps/istep14/makefile
parentc635eea80f96c8fdf078605d9533ba783c209db6 (diff)
downloadtalos-hostboot-76d3403f3d6a5a562fbe781bbe937383e02b28bb.tar.gz
talos-hostboot-76d3403f3d6a5a562fbe781bbe937383e02b28bb.zip
L2 HWP -- p9_setup_bars
p9_setup_bars initial relase -- program FSP/PSI/NPU BARs & configure MCD nest_attributes proc_setup_bars_attributes adjust scope of BAR base address attributes from chip->system change to reflect offset from base of chip address range, rather than absolute address p9_fbc_utils modify p9_fbc_utils_get_chip_base_address() to output base of each on chip region, consider policy affecting placement of mirrrored memory p9_mss_eff_grouping p9_sbe_load_bootloader p9_sbe_mcs_setup adapt to p9_fbc_utils_get_chip_base_address() changes p9_sbe_scominit adapt to p9_fbc_utils_get_chip_base_address() / attribute scope changes add placeholder for FIR register initialization p9_pcie_config adapt to p9_fbc_utils_get_chip_base_address() / attribute scope changes skip programming of INT resources Change-Id: I62e1766fbe8366168cc3f1b9b43c64f48659aec0 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27841 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Peng Fei Gou <shgoupf@cn.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27850 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr/isteps/istep14/makefile')
-rw-r--r--src/usr/isteps/istep14/makefile23
1 files changed, 19 insertions, 4 deletions
diff --git a/src/usr/isteps/istep14/makefile b/src/usr/isteps/istep14/makefile
index 836edad78..075e197ea 100644
--- a/src/usr/isteps/istep14/makefile
+++ b/src/usr/isteps/istep14/makefile
@@ -52,17 +52,32 @@ OBJS += call_proc_exit_cache_contained.o
OBJS += call_host_mpipl_service.o
include ${ROOTPATH}/procedure.rules.mk
-include ${PROCEDURE_PATH}/hwp/nest/p9_htm_setup.mk
-include ${PROCEDURE_PATH}/hwp/nest/p9_pcie_config.mk
include ${PROCEDURE_PATH}/hwp/nest/p9_exit_cache_contained.mk
-include ${PROCEDURE_PATH}/hwp/nest/p9_setup_bars.mk
include ${PROCEDURE_PATH}/hwp/nest/p9_mss_setup_bars.mk
+
+# TODO: RTC 159164: Multiple definition linker errors on HWPs that include the
+# same *.o file in their *.mk files
+# ---- Workaround: Compile the HWP directly below
+OBJS += p9_htm_setup.o
+OBJS += p9_htm_start.o
+OBJS += p9_htm_reset.o
+OBJS += p9_htm_adu_ctrl.o
+OBJS += p9_adu_coherent_utils.o
+OBJS += p9_pcie_config.o
+OBJS += p9_setup_bars.o
+OBJS += p9_fbc_utils.o
+OBJS += p9_fbc_smp_utils.o
+
+#include ${PROCEDURE_PATH}/hwp/nest/p9_htm_setup.mk
+#include ${PROCEDURE_PATH}/hwp/nest/p9_pcie_config.mk
+#include ${PROCEDURE_PATH}/hwp/nest/p9_setup_bars.mk
+# ---- End workaround
+
# include ${PROCEDURE_PATH}/hwp/memory/p9_mss_memdiag.mk
# include ${PROCEDURE_PATH}/hwp/memory/p9_mss_thermal_init.mk
include ${PROCEDURE_PATH}/hwp/memory/p9_mss_power_cleanup.mk
include ${ROOTPATH}/config.mk
-
VPATH += ${PROCEDURE_PATH}/hwp/nest/ ${PROCEDURE_PATH}/hwp/memory/
VPATH += ${PROCEDURE_PATH}/hwp/memory/lib/eff_config/
VPATH += ${PROCEDURE_PATH}/hwp/memory/lib/utils/
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