L2 HWP -- p9_setup_bars

p9_setup_bars
  initial relase -- program FSP/PSI/NPU BARs & configure MCD

nest_attributes
proc_setup_bars_attributes
  adjust scope of BAR base address attributes from chip->system
  change to reflect offset from base of chip address range, rather than
  absolute address

p9_fbc_utils
  modify p9_fbc_utils_get_chip_base_address() to output base of each on
  chip region, consider policy affecting placement of mirrrored memory

p9_mss_eff_grouping
p9_sbe_load_bootloader
p9_sbe_mcs_setup
  adapt to p9_fbc_utils_get_chip_base_address() changes

p9_sbe_scominit
  adapt to p9_fbc_utils_get_chip_base_address() / attribute scope changes
  add placeholder for FIR register initialization

p9_pcie_config
  adapt to p9_fbc_utils_get_chip_base_address() / attribute scope changes
  skip programming of INT resources

Change-Id: I62e1766fbe8366168cc3f1b9b43c64f48659aec0
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27841
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Peng Fei Gou <shgoupf@cn.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27850
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

4 files changed, 539 insertions, 132 deletions

diff --git a/src/usr/isteps/istep14/call_proc_setup_bars.C b/src/usr/isteps/istep14/call_proc_setup_bars.C
index fb316c455..8e24c1b8b 100644
--- a/src/usr/isteps/istep14/call_proc_setup_bars.C
+++ b/src/usr/isteps/istep14/call_proc_setup_bars.C
@@ -56,8 +56,6 @@ void* call_proc_setup_bars (void *io_pArgs)
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                "call_proc_setup_bars entry" );
 
-
-    // @@@@@    CUSTOM BLOCK:   @@@@@
     // Get all Centaur targets
     TARGETING::TargetHandleList l_cpuTargetList;
     getAllChips(l_cpuTargetList, TARGETING::TYPE_PROC );
@@ -108,32 +106,41 @@ void* call_proc_setup_bars (void *io_pArgs)
         //----------------------------------------------------------------------
         //  run proc_setup_bars on all CPUs
         //----------------------------------------------------------------------
-        std::vector<fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>> l_proc_chips;
-
-        for(uint8_t i = 0; i < l_cpuTargetList.size(); i++)
+        for (auto l_procChip : l_cpuTargetList)
         {
-          l_proc_chips.push_back(l_cpuTargetList[i]);
-        }
-
             TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                       "call p9_setup_bars");
+                       "call p9_setup_bars: Target HUID  %.8X",
+                       TARGETING::get_huid(l_procChip) );
 
-            //  call the HWP with each fapi::Target
-            FAPI_INVOKE_HWP( l_errl, p9_setup_bars, l_proc_chips, BAR_SETUP_PHASE1 );
+            // Call the HWP with each fapi::Target
+            FAPI_INVOKE_HWP( l_errl, p9_setup_bars, l_procChip );
 
             if ( l_errl )
             {
+                // Capture the target data in the elog
+                ErrlUserDetailsTarget(l_procChip).addToLog( l_errl );
+
+                // Create IStep error log and cross reference to error that occurred
+                l_stepError.addErrorDetails( l_errl );
+
+                // Commit Error
+                errlCommit( l_errl, HWPF_COMP_ID );
+
                 TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
                           "ERROR : p9_setup_bars" );
+
+                // break and return with error
+                break;
+
             }
             else
             {
                 TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                            "SUCCESS : p9_setup_bars" );
             }
-    }   // end if !l_errl
+        }
 
-    // @@@@@    END CUSTOM BLOCK:   @@@@@
+    }   // end if !l_errl
 
     if ( l_errl )
     {
diff --git a/src/usr/isteps/istep14/makefile b/src/usr/isteps/istep14/makefile
index 836edad78..075e197ea 100644
--- a/src/usr/isteps/istep14/makefile
+++ b/src/usr/isteps/istep14/makefile
@@ -52,17 +52,32 @@ OBJS += call_proc_exit_cache_contained.o
 OBJS += call_host_mpipl_service.o
 
 include ${ROOTPATH}/procedure.rules.mk
-include ${PROCEDURE_PATH}/hwp/nest/p9_htm_setup.mk
-include ${PROCEDURE_PATH}/hwp/nest/p9_pcie_config.mk
 include ${PROCEDURE_PATH}/hwp/nest/p9_exit_cache_contained.mk
-include ${PROCEDURE_PATH}/hwp/nest/p9_setup_bars.mk
 include ${PROCEDURE_PATH}/hwp/nest/p9_mss_setup_bars.mk
+
+# TODO: RTC 159164: Multiple definition linker errors on HWPs that include the
+# same *.o file in their *.mk files
+# ---- Workaround: Compile the HWP directly below
+OBJS += p9_htm_setup.o
+OBJS += p9_htm_start.o
+OBJS += p9_htm_reset.o
+OBJS += p9_htm_adu_ctrl.o
+OBJS += p9_adu_coherent_utils.o
+OBJS += p9_pcie_config.o
+OBJS += p9_setup_bars.o
+OBJS += p9_fbc_utils.o
+OBJS += p9_fbc_smp_utils.o
+
+#include ${PROCEDURE_PATH}/hwp/nest/p9_htm_setup.mk
+#include ${PROCEDURE_PATH}/hwp/nest/p9_pcie_config.mk
+#include ${PROCEDURE_PATH}/hwp/nest/p9_setup_bars.mk
+# ---- End workaround
+
 # include ${PROCEDURE_PATH}/hwp/memory/p9_mss_memdiag.mk
 # include ${PROCEDURE_PATH}/hwp/memory/p9_mss_thermal_init.mk
 include ${PROCEDURE_PATH}/hwp/memory/p9_mss_power_cleanup.mk
 include ${ROOTPATH}/config.mk
 
-
 VPATH    += ${PROCEDURE_PATH}/hwp/nest/ ${PROCEDURE_PATH}/hwp/memory/
 VPATH    += ${PROCEDURE_PATH}/hwp/memory/lib/eff_config/
 VPATH    += ${PROCEDURE_PATH}/hwp/memory/lib/utils/
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 9d9fba78a..88504d8d5 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -3213,42 +3213,6 @@
 
 <!-- ===== Processor Chip Attributes ===== -->
 
-<enumerationType>
-    <id>NPU_MMIO_BAR_ENABLE</id>
-    <description>Enumeration indicating whether MMIO BAR is enabled or not to be
-        used with ATTR_PROC_NPU_MMIO_BAR_ENABLE</description>
-    <enumerator>
-        <name>DISABLE</name>
-        <value>0</value>
-    </enumerator>
-    <enumerator>
-        <name>ENABLE</name>
-        <value>1</value>
-    </enumerator>
-</enumerationType>
-
-<attribute>
-    <id>NPU_MMIO_BAR_ENABLE</id>
-    <description>NPU MMIO BAR enables
-        creator: platform
-        consumer: proc_setup_bars
-        firmware notes: none
-            first dimension: unit number (0:3)
-            second dimension: BAR number (0:1)
-    </description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>4,2</array>
-    </simpleType>
-    <persistency>non-volatile</persistency>
-    <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_PROC_NPU_MMIO_BAR_ENABLE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
 <attribute>
     <id>NPU_MMIO_BAR_BASE_ADDR</id>
     <description>NPU MMIO BAR base address values
@@ -3361,23 +3325,6 @@
 </attribute>
 
 <attribute>
-    <id>FSP_MMIO_MASK_SIZE</id>
-    <description>MMIO Mask for FSP IO Region</description>
-    <simpleType>
-        <uint64_t>
-            <!-- @fixme : what is this value? -->
-            <default>0x0000000100000000</default>
-        </uint64_t>
-    </simpleType>
-    <persistency>non-volatile</persistency>
-    <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_PROC_FSP_MMIO_MASK_SIZE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
     <id>PSI_BRIDGE_BASE_ADDR</id>
     <description>Base Address of PSI Bridge Logic</description>
     <simpleType>
@@ -22152,19 +22099,18 @@ DEPRECATED!!!!
     <id>PROC_PCIE_BAR_ENABLE</id>
     <!-- TARGET_TYPE_PHB -->
     <description>
-        PCIE MMIO BAR enable
-        creator: platform
-        consumer: p9_setup_bars
-        firmware notes:
-          Array index: BAR number (0:2)
-          index 0~1 for BAR0/1
-          index 2 for PHB
-          index 3 for interrupt
+      PCIE MMIO BAR enable
+      creator: platform
+      consumer: p9_pcie_config
+      firmware notes:
+        Array index: BAR number (0:2)
+        index 0~1 for MMIO BAR0/1
+        index 2 for PHB register space
         DISABLE = 0x0, ENABLE = 0x1
     </description>
     <simpleType>
         <uint8_t></uint8_t>
-        <array>4</array>
+        <array>3</array>
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
@@ -22204,62 +22150,58 @@ DEPRECATED!!!!
     <id>PROC_PCIE_BAR_SIZE</id>
     <!-- TARGET_TYPE_PHB -->
     <description>
-        PCIE MMIO BAR size value
+        PCIE MMIO BAR size values
         creator: platform
-        consumer: p9_setup_bars
+        consumer: p9_pcie_config
         firmware notes:
-        Array index: BAR number (0:2)
-        NOTE: supported BAR0/1 sizes are from 64KB-32PB
-        NOTE: only supported BAR2 size is 16KB
-        index 0~1 for BAR0/1
-        index 2 for PHB, actually not used
-        index 3 for interrupt, actually not used
-
-        32_PB = 0x0000008000000000,
-        16_PB = 0x000000C000000000,
-        8_PB = 0x000000E000000000,
-        4_PB = 0x000000F000000000,
-        2_PB = 0x000000F800000000,
-        1_PB = 0x000000FC00000000,
-        512_TB = 0x000000FE00000000,
-        256_TB = 0x000000FF00000000,
-        128_TB = 0x000000FF80000000,
-        64_TB = 0x000000FFC0000000,
-        32_TB = 0x000000FFE0000000,
-        16_TB = 0x000000FFF0000000,
-        8_TB = 0x000000FFF8000000,
-        4_TB = 0x000000FFFC000000,
-        2_TB = 0x000000FFFE000000,
-        1_TB = 0x000000FFFF000000,
-        512_GB = 0x000000FFFF800000,
-        256_GB = 0x000000FFFFC00000,
-        128_GB = 0x000000FFFFE00000,
-        64_GB = 0x000000FFFFF00000,
-        32_GB = 0x000000FFFFF80000,
-        16_GB = 0x000000FFFFFC0000,
-        8_GB = 0x000000FFFFFE0000,
-        4_GB = 0x000000FFFFFF0000,
-        2_GB = 0x000000FFFFFF8000,
-        1_GB = 0x000000FFFFFFC000,
-        512_MB = 0x000000FFFFFFE000,
-        256_MB = 0x000000FFFFFFF000,
-        128_MB = 0x000000FFFFFFF800,
-        64_MB = 0x000000FFFFFFFC00,
-        32_MB = 0x000000FFFFFFFE00,
-        16_MB = 0x000000FFFFFFFF00,
-        8_MB = 0x000000FFFFFFFF80,
-        4_MB = 0x000000FFFFFFFFC0,
-        2_MB = 0x000000FFFFFFFFE0,
-        1_MB = 0x000000FFFFFFFFF0,
-        512_KB = 0x000000FFFFFFFFF8,
-        256_KB = 0x000000FFFFFFFFFC,
-        128_KB = 0x000000FFFFFFFFFE,
-        64_KB = 0x000000FFFFFFFFFF,
-        16_KB = 0xFFFFFFFFFFFFFFFF
+          Array index: BAR number (0:2)
+          NOTE: supported MMIO BAR0/1 sizes are from 64KB-32PB
+          NOTE: only supported PHB register size is 16KB
+         32_PB = 0x8000000000000000,
+         16_PB = 0xC000000000000000,
+          8_PB = 0xE000000000000000,
+          4_PB = 0xF000000000000000,
+          2_PB = 0xF800000000000000,
+          1_PB = 0xFC00000000000000,
+        512_TB = 0xFE00000000000000,
+        256_TB = 0xFF00000000000000,
+        128_TB = 0xFF80000000000000,
+         64_TB = 0xFFC0000000000000,
+         32_TB = 0xFFE0000000000000,
+         16_TB = 0xFFF0000000000000,
+          8_TB = 0xFFF8000000000000,
+          4_TB = 0xFFFC000000000000,
+          2_TB = 0xFFFE000000000000,
+          1_TB = 0xFFFF000000000000,
+        512_GB = 0xFFFF800000000000,
+        256_GB = 0xFFFFC00000000000,
+        128_GB = 0xFFFFE00000000000,
+         64_GB = 0xFFFFF00000000000,
+         32_GB = 0xFFFFF80000000000,
+         16_GB = 0xFFFFFC0000000000,
+          8_GB = 0xFFFFFE0000000000,
+          4_GB = 0xFFFFFF0000000000,
+          2_GB = 0xFFFFFF8000000000,
+          1_GB = 0xFFFFFFC000000000,
+        512_MB = 0xFFFFFFE000000000,
+        256_MB = 0xFFFFFFF000000000,
+        128_MB = 0xFFFFFFF800000000,
+         64_MB = 0xFFFFFFFC00000000,
+         32_MB = 0xFFFFFFFE00000000,
+         16_MB = 0xFFFFFFFF00000000,
+          8_MB = 0xFFFFFFFF80000000,
+          4_MB = 0xFFFFFFFFC0000000,
+          2_MB = 0xFFFFFFFFE0000000,
+          1_MB = 0xFFFFFFFFF0000000,
+        512_KB = 0xFFFFFFFFF8000000,
+        256_KB = 0xFFFFFFFFFC000000,
+        128_KB = 0xFFFFFFFFFE000000,
+         64_KB = 0xFFFFFFFFFF000000,
+         16_KB = 0xFFFFFFFFFFFFFFFF
     </description>
     <simpleType>
         <uint64_t></uint64_t>
-        <array>4</array>
+        <array>3</array>
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
@@ -30093,4 +30035,418 @@ DEPRECATED!!!!
     </hwpfToHbAttrMap>
 </attribute>
 
+<!-- p9_setup_bars - Begin -->
+
+<attribute>
+  <id>PROC_PCIE_MMIO_BAR0_BASE_ADDR_OFFSET</id>
+  <description>
+      PCIE MMIO0 BAR base address offset
+      Attribute holds offset (relative to chip MMIO origin) to program into
+      chip address range field of BAR -- RA bits 8:47
+      (excludes system/memory select/group/chip fields)
+      Array index: PHB number (0:5)
+  </description>
+  <simpleType>
+    <uint64_t>
+    </uint64_t>
+    <array>6</array>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_PCIE_MMIO_BAR0_BASE_ADDR_OFFSET</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_PCIE_MMIO_BAR1_BASE_ADDR_OFFSET</id>
+  <description>
+      PCIE MMIO1 BAR base address offset
+      Attribute holds offset (relative to chip MMIO origin) to program into
+      chip address range field of BAR -- RA bits 8:47
+      (excludes system/memory select/group/chip fields)
+      Array index: PHB number (0:5)
+  </description>
+  <simpleType>
+    <uint64_t>
+    </uint64_t>
+    <array>6</array>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_PCIE_MMIO_BAR1_BASE_ADDR_OFFSET</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_PCIE_REGISTER_BAR_BASE_ADDR_OFFSET</id>
+  <description>
+      PCIE PHB register space BAR base address offset
+      chip address range field of BAR -- RA bits 8:49
+      (excludes system/memory select/group/chip fields)
+      Array index: PHB number (0:5)
+  </description>
+  <simpleType>
+    <uint64_t>
+    </uint64_t>
+    <array>6</array>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_PCIE_REGISTER_BAR_BASE_ADDR_OFFSET</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_XSCOM_BAR_BASE_ADDR_OFFSET</id>
+  <description>
+      XSCOM BAR base address offset
+      Defines 16GB range (size implied) mapped for XSCOM usage
+      Attribute holds offset (relative to chip MMIO origin) to program into
+      chip address range field of BAR -- RA bits 22:29
+      (excludes system/memory select/group/chip fields)
+  </description>
+  <simpleType>
+    <uint64_t>
+    </uint64_t>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_LPC_BAR_BASE_ADDR_OFFSET</id>
+  <description>
+      LPC BAR base address offset
+      Defines 4GB range (size implied) mapped for LPC usage
+      Attribute holds offset (relative to chip MMIO origin) to program into
+      chip address range field of BAR -- RA bits 22:31
+      (excludes system/memory select/group/chip fields)
+  </description>
+  <simpleType>
+    <uint64_t>
+    </uint64_t>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_FSP_BAR_BASE_ADDR_OFFSET</id>
+  <description>
+      FSP BAR
+      Defines range mapped for FSP MMIO
+      Attribute holds offset (relative to chip MMIO origin) to program into
+      chip address range field of BAR -- RA bits 22:43
+  </description>
+  <simpleType>
+    <uint64_t>
+    </uint64_t>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_FSP_BAR_BASE_ADDR_OFFSET</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_FSP_MMIO_MASK_SIZE</id>
+  <description>
+      FSP MMIO mask size value AND mask applied to RA 32:35 when transmitting
+      address to FSP
+      NOTE: RA 8:31 are always replaced with zero
+        4_GB = 0x00F0000000000000,
+        2_GB = 0x0070000000000000,
+        1_GB = 0x0030000000000000,
+      512_MB = 0x0010000000000000,
+      256_MB = 0x0000000000000000
+  </description>
+  <simpleType>
+    <uint64_t>
+    </uint64_t>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_FSP_MMIO_MASK_SIZE</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_PSI_BRIDGE_BAR_BASE_ADDR_OFFSET</id>
+  <description>
+      PSI Bridge BAR base address offset
+      Defines 1MB range (size implied) mapped for PSI host-bridge
+      Attribute holds offset (relative to chip MMIO origin) to program into
+      chip address range field of BAR -- RA bits 22:43
+      (excludes system/memory select/group/chip fields)
+  </description>
+  <simpleType>
+    <uint64_t>
+    </uint64_t>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR_OFFSET</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_NPU_PHY0_BAR_ENABLE</id>
+  <description>
+      NPU PHY0 (stack0) BAR enable
+      DISABLE = 0x0, ENABLE = 0x1
+  </description>
+  <simpleType>
+    <uint8_t>
+    </uint8_t>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_NPU_PHY0_BAR_ENABLE</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_NPU_PHY0_BAR_BASE_ADDR_OFFSET</id>
+  <description>
+      NPU PHY0 (stack0) BAR
+      Defines 2MB range (size implied) mapped to PHY0 registers
+      Attribute holds offset (relative to chip MMIO origin) to program into
+      chip address range field of BAR -- RA bits 22:42
+      (excludes system/memory select/group/chip fields)
+  </description>
+  <simpleType>
+    <uint64_t>
+    </uint64_t>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_NPU_PHY0_BAR_BASE_ADDR_OFFSET</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_NPU_PHY1_BAR_ENABLE</id>
+  <description>
+      NPU PHY1 (stack1) BAR enable
+      DISABLE = 0x0, ENABLE = 0x1
+  </description>
+  <simpleType>
+    <uint8_t>
+    </uint8_t>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_NPU_PHY1_BAR_ENABLE</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_NPU_PHY1_BAR_BASE_ADDR_OFFSET</id>
+  <description>
+      NPU PHY1 (stack1) BAR
+      Defines 2MB range (size implied) mapped to PHY1 registers
+      Attribute holds offset (relative to chip MMIO origin) to program into
+      chip address range field of BAR -- RA bits 22:42
+      (excludes system/memory select/group/chip fields)
+  </description>
+  <simpleType>
+    <uint64_t>
+    </uint64_t>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_NPU_PHY1_BAR_BASE_ADDR_OFFSET</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_NPU_MMIO_BAR_ENABLE</id>
+  <description>
+      NPU MMIO (stack2) BAR enable
+      DISABLE = 0x0, ENABLE = 0x1
+  </description>
+  <simpleType>
+    <uint8_t>
+    </uint8_t>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_NPU_MMIO_BAR_ENABLE</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_NPU_MMIO_BAR_BASE_ADDR_OFFSET</id>
+  <description>
+      NPU MMIO (stack2) BAR
+      Defines 16MB range mapped to all NPU registers
+      Attribute holds offset (relative to chip MMIO origin) to program into
+      chip address range field of BAR -- RA bits 22:39
+      (excludes system/memory select/group/chip fields)
+  </description>
+  <simpleType>
+    <uint64_t>
+    </uint64_t>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR_OFFSET</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_NX_RNG_BAR_ENABLE</id>
+  <description>
+      NX RNG BAR enable
+      DISABLE = 0x0, ENABLE = 0x1
+  </description>
+  <simpleType>
+    <uint8_t>
+    </uint8_t>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_NX_RNG_BAR_ENABLE</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_NX_RNG_BAR_BASE_ADDR_OFFSET</id>
+  <description>
+      NX RNG BAR
+      Defines 8KB range (size implied) mapped for NX RNG function
+      Attribute holds offset (relative to chip MMIO origin) to program into
+      chip address range field of BAR -- RA bits 22:51
+      (excludes system/memory select/group/chip fields)
+  </description>
+  <simpleType>
+    <uint64_t>
+    </uint64_t>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_NX_RNG_BAR_BASE_ADDR_OFFSET</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<!-- p9_setup_bars - End -->
+
+<attribute>
+  <id>PROC_NX_RNG_FAILED_INT_ENABLE</id>
+  <description>
+      Enable optional post of interrupt when both NX RNG noise
+      sources have failed.
+      DISABLE = 0x0, ENABLE = 0x1
+  </description>
+  <simpleType>
+    <uint8_t>
+    </uint8_t>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_NX_RNG_FAILED_INT_ENABLE</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_NX_RNG_FAILED_INT_ADDR</id>
+  <description>
+      Address used to post interrupt when both NX RNG noise sources have failed
+      creator: platform
+      consumer: p9_rng_init_phase2
+      firmware notes:
+        64-bit address representing RA
+        NOTE: register covers RA 8:51
+  </description>
+  <simpleType>
+    <uint64_t>
+    </uint64_t>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_NX_RNG_FAILED_INT_ADDR</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_NX_RNG_BIST_ENABLE</id>
+  <description>
+      Enable NX RNG BIST
+      creator: platform
+      consumer: p9_rng_init_phase1
+      firmware notes: none
+      DISABLE = 0x0, ENABLE = 0x1
+  </description>
+  <simpleType>
+    <uint8_t>
+    </uint8_t>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_NX_RNG_BIST_ENABLE</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_NX_RNG_BIST_THRESHOLD</id>
+  <description>
+      BIST threshold attribute
+      creator: platform
+      consumer: p9_rng_init_phase1
+      firmware notes: none
+  </description>
+  <simpleType>
+    <uint8_t>
+    </uint8_t>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_NX_RNG_BIST_THRESHOLD</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
 </attributes>
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index b401a4296..e9a4debcc 100755
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -814,6 +814,22 @@
     <attribute><id>MSS_VPP_PROGRAM</id></attribute>
     <attribute><id>MSS_VDDR_PROGRAM</id></attribute>
 
+<!-- p9_setup_bars - Begin -->
+    <attribute><id>PROC_PCIE_MMIO_BAR0_BASE_ADDR_OFFSET</id></attribute>
+    <attribute><id>PROC_PCIE_MMIO_BAR1_BASE_ADDR_OFFSET</id></attribute>
+    <attribute><id>PROC_PCIE_REGISTER_BAR_BASE_ADDR_OFFSET</id></attribute>
+    <attribute><id>PROC_XSCOM_BAR_BASE_ADDR_OFFSET</id></attribute>
+    <attribute><id>PROC_LPC_BAR_BASE_ADDR_OFFSET</id></attribute>
+    <attribute><id>PROC_PCIE_BAR_SIZE</id></attribute>
+    <attribute><id>PROC_FSP_BAR_BASE_ADDR_OFFSET</id></attribute>
+    <attribute><id>PROC_PSI_BRIDGE_BAR_BASE_ADDR_OFFSET</id></attribute>
+    <attribute><id>PROC_NPU_PHY0_BAR_BASE_ADDR_OFFSET</id></attribute>
+    <attribute><id>PROC_NPU_PHY1_BAR_BASE_ADDR_OFFSET</id></attribute>
+    <attribute><id>PROC_NPU_MMIO_BAR_BASE_ADDR_OFFSET</id></attribute>
+    <attribute><id>PROC_NX_RNG_BAR_BASE_ADDR_OFFSET</id></attribute>
+    <attribute><id>PROC_FSP_MMIO_MASK_SIZE</id></attribute>
+<!-- p9_setup_bars - End -->
+
 </targetType>
 
 <!-- enc-node-power9 -->
@@ -881,12 +897,10 @@
     </attribute>
 
     <!-- From PHYP Memory Map -->
-    <attribute><id>NPU_MMIO_BAR_ENABLE</id></attribute>
     <attribute><id>NPU_MMIO_BAR_BASE_ADDR</id></attribute>
     <attribute><id>NPU_MMIO_BAR_SIZE</id></attribute>
     <attribute><id>FSP_BASE_ADDR</id></attribute>
     <attribute><id>FSP_BAR_SIZE</id></attribute>
-    <attribute><id>FSP_MMIO_MASK_SIZE</id></attribute>
     <attribute><id>PSI_BRIDGE_BASE_ADDR</id></attribute>
     <attribute><id>INTP_BASE_ADDR</id></attribute>
     <attribute><id>PHB_BASE_ADDRS</id></attribute>
@@ -1122,6 +1136,21 @@
     <attribute><id>LPC_BASE_ADDR</id></attribute>
     <attribute><id>BOOT_FREQ_MHZ</id></attribute>
 
+<!-- p9_setup_bars - Begin -->
+    <attribute><id>PROC_NPU_PHY0_BAR_ENABLE</id></attribute>
+    <attribute><id>PROC_NPU_PHY1_BAR_ENABLE</id></attribute>
+    <attribute><id>PROC_NPU_MMIO_BAR_ENABLE</id></attribute>
+    <attribute><id>PROC_NX_RNG_BAR_ENABLE</id></attribute>
+    <attribute><id>PROC_FSP_BAR_ENABLE</id></attribute>
+    <attribute><id>PROC_PSI_BRIDGE_BAR_ENABLE</id></attribute>
+<!-- p9_setup_bars - End -->
+
+    <attribute><id>PROC_NX_RNG_FAILED_INT_ENABLE</id></attribute>
+    <attribute><id>PROC_NX_RNG_FAILED_INT_ADDR</id></attribute>
+    <attribute><id>PROC_NX_RNG_BIST_ENABLE</id></attribute>
+    <attribute><id>PROC_NX_RNG_BIST_THRESHOLD</id></attribute>
+
+
 </targetType>
 
 <!-- chip-processor-nimbus -->