diff options
| author | Mark Wenning <wenning@us.ibm.com> | 2012-06-18 18:06:12 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2012-07-12 17:19:53 -0500 |
| commit | 7f482f9ad23bd7689fdee5982ad91f8506b2dfb8 (patch) | |
| tree | c519dd9a5712982bed3fc30c02d6c14c2bb17f0e /src/usr/hwpf/hwp | |
| parent | 3b9899c9969d46d2faddca8f3d35fa5074e3097c (diff) | |
| download | talos-hostboot-7f482f9ad23bd7689fdee5982ad91f8506b2dfb8.tar.gz talos-hostboot-7f482f9ad23bd7689fdee5982ad91f8506b2dfb8.zip | |
Attribute Support for proc_setup_bars and mss_setup_bars
RTC: 42296
Change-Id: I9f470f9e41c22ed28bd0365aec23b91414258945
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1235
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Reviewed-by: Mark W. Wenning <wenning@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf/hwp')
17 files changed, 7962 insertions, 209 deletions
diff --git a/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C b/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C index b6e41b75c..518bc8784 100644 --- a/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C +++ b/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C @@ -46,6 +46,7 @@ // targeting support #include <targeting/common/commontargeting.H> +#include <targeting/common/util.H> #include <targeting/common/utilFilter.H> // fapi support @@ -60,7 +61,8 @@ // #include "mss_memdiag/mss_memdiag.H" // #include "mss_scrub/mss_scrub.H" // #include "mss_thermal_init/mss_thermal_init.H" -// #include "proc_setup_bars/proc_setup_bars.H" +#include "proc_setup_bars/mss_setup_bars.H" +#include "proc_setup_bars/proc_setup_bars.H" // #include "proc_pbus_epsilon/proc_pbus_epsilon.H" #include "proc_exit_cache_contained/proc_exit_cache_contained.H" @@ -136,24 +138,24 @@ void call_mss_extent_setup( void *io_pArgs ) { errlHndl_t l_errl = NULL; - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_extent_setup entry" ); - // call the HWP + // call the HWP FAPI_INVOKE_HWP( l_errl, mss_extent_setup ); if ( l_errl ) { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "ERROR : failed executing mss_extent_setup returning error" ); } else { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "SUCCESS : mss_extent_setup completed ok" ); } - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_extent_setup exit" ); // end task, returning any errorlogs to IStepDisp @@ -305,229 +307,172 @@ void call_proc_setup_bars( void *io_pArgs ) { errlHndl_t l_errl = NULL; + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_setup_bars entry" ); - // @@@@@ TEMPORARY SIMICS HACK for PHYP 6/1 milestone @@@@@ - // loop through all processor targets - // 1) loop on associated MCSs - // a) Get associated logical dimms, sum total size of memory - // b) Write memory base addr/size out to MCFGP 0x02011800 - //Don't do this in VPO -- shouldn't be run anyway, but return as a precaution - if( TARGETING::is_vpo() ) - { - task_end2( l_errl ); - } - - // Get all functional processor targets - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "!!!!!!!!!WORKAROUND Memory BAR setup!!!!!!!!!!!" ); - TARGETING::PredicateIsFunctional l_isFunctional; //functional filter - TARGETING::PredicateCTM l_Filter(CLASS_CHIP, TYPE_PROC); //Proc chip filter - TARGETING::PredicatePostfixExpr l_goodFilter; - l_goodFilter.push(&l_Filter).push(&l_isFunctional).And(); - TARGETING::TargetRangeFilter l_Procs( - TARGETING::targetService().begin(), - TARGETING::targetService().end(), - &l_goodFilter ); - - // Create a Class/Type/Model predicate to look for units - TARGETING::PredicateCTM l_mcsPred(CLASS_UNIT, TYPE_MCS); - TARGETING::PredicatePostfixExpr l_mcsFilter; - l_mcsFilter.push(&l_mcsPred).push(&l_isFunctional).And(); - - // Create a Class/Type/Model predicate to look for dimm cards - TARGETING::PredicateCTM l_dimmPred(CLASS_LOGICAL_CARD,TYPE_DIMM); - TARGETING::PredicatePostfixExpr l_dimmFilter; - l_dimmFilter.push(&l_dimmPred).push(&l_isFunctional).And(); - - // Create a vector of TARGETING::Target pointers - TARGETING::TargetHandleList l_dimmList; - TARGETING::TargetHandleList l_mcsList; - uint64_t base_addr = 0x0; - - - for ( ; l_Procs && !l_errl; ++l_Procs ) - { - const TARGETING::Target * l_pTarget = *l_Procs; - l_mcsList.clear(); + // @@@@@ CUSTOM BLOCK: @@@@@ + // Get all Centaur targets + TARGETING::TargetHandleList l_cpuTargetList; + getAllChips(l_cpuTargetList, TYPE_PROC ); - //Get MCS sub units for this proc - TARGETING::targetService().getAssociated(l_mcsList, l_pTarget, - TARGETING::TargetService::CHILD, - TARGETING::TargetService::ALL, - &l_mcsFilter); - for (uint32_t i = 0; (i < l_mcsList.size()) && !l_errl; i++) + // ----------------------------------------------------------------------- + // run mss_setup_bars on all CPUs. + // ----------------------------------------------------------------------- + for ( size_t i = 0; i < l_cpuTargetList.size(); i++ ) + { + // make a local copy of the target for ease of use + const TARGETING::Target* l_pCpuTarget = l_cpuTargetList[i]; + + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "mss_setup_bars: proc %d", i ); + // dump physical path to targets + EntityPath l_path; + l_path = l_pCpuTarget->getAttr<ATTR_PHYS_PATH>(); + l_path.dump(); + + // cast OUR type of target to a FAPI type of target. + const fapi::Target l_fapi_pCpuTarget( + TARGET_TYPE_PROC_CHIP, + reinterpret_cast<void *> + (const_cast<TARGETING::Target*> + (l_pCpuTarget)) ); + + // call the HWP with each fapi::Target + FAPI_INVOKE_HWP( l_errl, + mss_setup_bars, + l_fapi_pCpuTarget ); + + if ( l_errl ) { - uint32_t mem_size = 0; - l_dimmList.clear(); + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR : mss_setup_bars" ); + // break and return with error + break; + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : mss_setup-bars" ); + } + } // endfor - //Get Dimms for this MCS - TARGETING::targetService().getAssociated(l_dimmList, l_mcsList[i], - TARGETING::TargetService::CHILD_BY_AFFINITY, - TARGETING::TargetService::ALL, &l_dimmFilter); - //Tally up the total dimm size - for(uint32_t j=0; (j < l_dimmList.size()) && !l_errl; j++) - { - uint8_t dimm_den; - size_t l_size = 0x1; - l_errl = deviceRead(l_dimmList[j], &dimm_den, l_size, - DEVICE_SPD_ADDRESS(SPD::DENSITY)); - if (l_errl) - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "WORKAROUND: Memory BAR error getting dimm density"); - - break; - } - - /* - Bit [3, 2, 1, 0] : - 0000 = 256 Mb - 0001 = 512 Mb - 0010 = 1 Gb - 0011 = 2 Gb - 0100 = 4 Gb - 0101 = 8 Gb - 0110 = 16 Gb*/ - mem_size += (1<<dimm_den); //(smallest size is 256MB) + // ---------------------------------------------------------------------- + // @@@@@ TEMPORARY SIMICS HACK for PHYP 6/1 milestone @@@@@ + // ---------------------------------------------------------------------- + if ( !TARGETING::is_vpo() ) + { + //Now need to scom the L3 bar on my EX to trigger Simics cache contained exit + if (!l_errl) + { + // TODO: Remove workaround with RTC: 42922. + nanosleep(1,0); // workaround Simics race condition. - } + TARGETING::Target* procTarget = NULL; + TARGETING::targetService().masterProcChipTargetHandle( procTarget ); - if(l_errl) - { - break; - } + //Base scom address is 0x1001080b, need to place core id from cpuid + //EX chiplet is bits 4:7 of scom addr, EX unit in cpuid is bits 25:28 + uint32_t scom_addr = 0x1001080b | (((task_getcpuid()) & 0x78) << 21); + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "EX L3 BAR1 addr [%08x]", scom_addr); - /*check to see if total centaur siz is less than 4GB multiple - Note that mem_size is in 256MB chunks - 0x0000 0001 -- 256MB - 0x0000 0010 -- 512MB - 0x0000 0100 -- 1GB - 0x0000 1000 -- 2GB - 0x0001 0000 -- 4GB - This is a workaround HACK -- so just emit a warning - */ - if(mem_size & 0xF) - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "WARNING -- CEC memory size less than 4GB on MCS[%08X]\n", - TARGETING::get_huid(l_mcsList[i])); - mem_size = 0x10; - } - uint64_t grp_size = (mem_size >>4)-1; - - /*build up MCFGP contents - 0 -- enable 0b1 - 1:3 -- MCS/group 0x0 - 4:8 -- group id 0x0 - 9:10 -- HW settings 0b11 - 11:23 -- Group size - 4 GB b0000000000000 - 8 GB b0000000000001 - 16 GB b0000000000011 - 32 GB b0000000000111 - 64 GB b0000000001111 - 128 GB b0000000011111 - 256 GB b0000000111111 - 512 GB b0000001111111 - 1 TB b0000011111111 - 2 TB b0000111111111 - 4 TB b0001111111111 - 8 TB b0011111111111 - 24:25 -- HW settings 0b11 - 26:43 -- Base address of group (addr 14:31) - 44:63 -- Reserved 0x00000 - */ - uint64_t scom_data = 0x806000C000000000 | - (grp_size << 40) | (base_addr << 20); + uint64_t scom_data = 0x0; //data doesn't matter, just the write size_t size = sizeof(scom_data); - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "CEC memory base_addr[%lx], grp_size[%lx], scom[%lx]\n", - base_addr, grp_size, scom_data); - - l_errl = deviceWrite( l_mcsList[i], - &scom_data, - size, - DEVICE_SCOM_ADDRESS(0x02011800) ); - if(l_errl) + l_errl = deviceWrite( procTarget, + &scom_data, + size, + DEVICE_SCOM_ADDRESS(scom_addr) ); + if (l_errl) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "Failed to write MCS MCFGP scoms addr\n"); + "Failed to write EX %08x addr\n", scom_addr); } - - base_addr += (mem_size >>4); - } + // @@@@@ end TEMPORARY SIMICS HACK for PHYP 6/1 milestone @@@@@ } - - //Now need to scom the L3 bar on my EX to trigger Simics cache contained exit - if(!l_errl) +// $$ #if 0 + // $$$$$ @todo issue 44948 + // proc_setup_bars crashes simics, remove check when we get it working + if ( !TARGETING::is_vpo() ) { - // TODO: Remove workaround with RTC: 42922. - nanosleep(1,0); // workaround Simics race condition. - - TARGETING::Target* procTarget = NULL; - TARGETING::targetService().masterProcChipTargetHandle( procTarget ); - - //Base scom address is 0x1001080b, need to place core id from cpuid - //EX chiplet is bits 4:7 of scom addr, EX unit in cpuid is bits 25:28 - uint32_t scom_addr = 0x1001080b | (((task_getcpuid()) & 0x78) << 21); TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "EX L3 BAR1 addr [%08x]\n", scom_addr); - - uint64_t scom_data = 0x0; //data doesn't matter, just the write - size_t size = sizeof(scom_data); - - l_errl = deviceWrite( procTarget, - &scom_data, - size, - DEVICE_SCOM_ADDRESS(scom_addr) ); - if(l_errl) - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "Failed to write EX %08x addr\n", scom_addr); - } + "proc_setup_bars is disabled in simics, see issue 44948" ); + task_end2(l_errl); } + // $$$$$ @todo issue 44948 +// $$ #endif -#if 0 - // @@@@@ CUSTOM BLOCK: @@@@@ - // figure out what targets we need - // customize any other inputs - // set up loops to go through all targets (if parallel, spin off a task) - // dump physical path to targets - EntityPath l_path; - l_path = l_@targetN_target->getAttr<ATTR_PHYS_PATH>(); - l_path.dump(); + if ( ! l_errl ) + { + // ----------------------------------------------------------------------- + // run proc_setup_bars on all CPUs + // ----------------------------------------------------------------------- + std::vector<proc_setup_bars_proc_chip> l_proc_chips; - // cast OUR type of target to a FAPI type of target. - const fapi::Target l_fapi_@targetN_target( - TARGET_TYPE_MEMBUF_CHIP, - reinterpret_cast<void *> - (const_cast<TARGETING::Target*>(l_@targetN_target)) ); + for ( size_t i = 0; i < l_cpuTargetList.size(); i++ ) + { + // make a local copy of the target for ease of use + const TARGETING::Target* l_pCpuTarget = l_cpuTargetList[i]; + + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "proc_setup_bars: proc %d", i ); + // dump physical path to targets + EntityPath l_path; + l_path = l_pCpuTarget->getAttr<ATTR_PHYS_PATH>(); + l_path.dump(); + + // cast OUR type of target to a FAPI type of target. + const fapi::Target l_fapi_pCpuTarget( + TARGET_TYPE_MEMBUF_CHIP, + reinterpret_cast<void *> + (const_cast<TARGETING::Target*> + (l_pCpuTarget)) ); + // @todo Create dummy aX targets + const fapi::Target l_a0_chip; + const fapi::Target l_a1_chip; + const fapi::Target l_a2_chip; + + + proc_setup_bars_proc_chip l_proc_chip ; + l_proc_chip.this_chip = l_fapi_pCpuTarget; + l_proc_chip.a0_chip = l_a0_chip; + l_proc_chip.a1_chip = l_a1_chip; + l_proc_chip.a2_chip = l_a2_chip; + l_proc_chip.process_f0 = true; + l_proc_chip.process_f1 = true; + + l_proc_chips.push_back( l_proc_chip ); + + // call the HWP with each fapi::Target + FAPI_INVOKE_HWP( l_errl, + proc_setup_bars, + l_proc_chips, + true ); + + if ( l_errl ) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR : proc_setup_bars" ); + // break out with error + break; + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : proc_setup-bars" ); + } + } // endfor + } // end if !l_errl - // call the HWP with each fapi::Target - FAPI_INVOKE_HWP( l_errl, proc_setup_bars, _args_...); - if ( l_errl ) - { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR : .........." ); - errlCommit( l_errl, HWPF_COMP_ID ); - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : .........." ); - } // @@@@@ END CUSTOM BLOCK: @@@@@ -#endif TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_setup_bars exit" ); diff --git a/src/usr/hwpf/hwp/dram_initialization/makefile b/src/usr/hwpf/hwp/dram_initialization/makefile index 8cc0cfc28..319309256 100644 --- a/src/usr/hwpf/hwp/dram_initialization/makefile +++ b/src/usr/hwpf/hwp/dram_initialization/makefile @@ -42,12 +42,16 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization ## EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/<HWP_dir> EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_contained EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars ## NOTE: add new object files when you add a new HWP OBJS = dram_initialization.o \ proc_exit_cache_contained.o \ - mss_extent_setup.o + mss_extent_setup.o \ + mss_setup_bars.o \ + proc_fab_smp.o \ + proc_setup_bars.o \ ## NOTE: add a new directory onto the vpaths when you add a new HWP @@ -55,6 +59,7 @@ OBJS = dram_initialization.o \ # VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/<HWP_dir> VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_contained VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup +VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars include ${ROOTPATH}/config.mk diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/fapi_sbe_common.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/fapi_sbe_common.H new file mode 100644 index 000000000..eea5054a4 --- /dev/null +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/fapi_sbe_common.H @@ -0,0 +1,70 @@ +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/fapi_sbe_common.H $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ +#ifndef __FAPI_SBE_COMMON_H +#define __FAPI_SBE_COMMON_H + +// $Id: fapi_sbe_common.H,v 1.1 2012/04/16 23:55:37 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/fapi_sbe_common.H,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME : Email: + +/// \file fapi_sbe_common.H +/// \brief Definitions common to FAPI and SBE procedures +/// +/// Several preprocessor macros are required to have different definitions in +/// C, C++ and SBE assembly procedures. These common forms are collected here. + +#if defined __ASSEMBLER__ + +#define CONST_UINT8_T(name, expr) .set name, (expr) +#define CONST_UINT32_T(name, expr) .set name, (expr) +#define CONST_UINT64_T(name, expr) .set name, (expr) + +#define ULL(x) x + +#elif defined __cplusplus + +#include <stdint.h> + +#define CONST_UINT8_T(name, expr) const uint8_t name = (expr); +#define CONST_UINT32_T(name, expr) const uint32_t name = (expr); +#define CONST_UINT64_T(name, expr) const uint64_t name = (expr); + +#define ULL(x) x##ull + +#else // C code + +// CONST_UINT[8,3,64]_T() can't be used in C code/headers; Use +// +// #define <symbol> <value> [ or ULL(<value>) for 64-bit constants + +#define ULL(x) x##ull + +#endif // __ASSEMBLER__ + +#endif // __FAPI_SBE_COMMON_H diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C new file mode 100644 index 000000000..ebc941ce8 --- /dev/null +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C @@ -0,0 +1,285 @@ +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2012 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : mss_setup_bars.C +// *! DESCRIPTION : see additional comments below +//------------------------------------------------------------------------------ +// Don't forget to create CVS comments when you check in your changes! +//------------------------------------------------------------------------------ +//Owner :- Girisankar paulraj +//Back-up owner :- Mark bellows +// +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version:| Author: | Date: | Comment: +//---------|----------|---------|----------------------------------------------- +// 1.1 | gpaulraj | 03-19-12| First drop for centaur +// 1.2 | gpaulraj | 05-07-12| 256 group configuration in +// 1.3 | gpaulraj | 05-22-12| 2MCS/group supported for 128GB CDIMM +// 1.4 | bellows | 06-05-12| Updates to Match First Configuration, work for P8 and Murano +//---------------------------------------------------------------------- +// Includes +//---------------------------------------------------------------------- + +#include <mss_setup_bars.H> + +extern "C" { + +// PLAN:--- +// Parameter of the populated Dimm details for each MCS looper +// Starts with Zero MCS base address. Identifies Dimm parameters belong to MCS +// Configure the Group primary MCS0 Registers +// Configure the Group seconary MCS0 Registers /// identifies it base address based on the Primary group size +// Identify Mirror details setup accordingly +// Set up each translation registry accordingly +// SIM configuration +// -------------------------|-----------------------------------| +// ------- MCS0 ---------|-------------MCS1------------------| +// -------------------------|-----------------------------------| +// --- CH01 --- CH23 -----|-------- CH01 --- CH23 ----------| +// D0- 32GB --- 32GB -----|---- D0- 32GB --- 32GB ----------| +// D1- 32GB --- 32GB ----|-----D1- 32GB --- 32GB ---------| +// -------------------------|-----------------------------------| +// - Base address MCS0 - 0x0 Group Size - 128GB +// - MCS0 - Grouping base address - 0GB Group size - 128GB +// - MCS1 - Grouping base address - 128GB+ Group size - 128GB + +fapi::ReturnCode mss_setup_bars( + const fapi::Target& i_chip_target) +{ + fapi::ReturnCode rc; + std::vector<fapi::Target> l_mcs_chiplets; + ecmdDataBufferBase MCFGP_data(64); + + // platform attributes which define base addresses for this chip: + uint64_t mem_base; + uint64_t mirror_base; + + // storage for output attributes: + uint64_t mem_bases[8]; + uint64_t l_memory_sizes[8]; + uint64_t mirror_bases[4]; + uint64_t l_mirror_sizes[4]; + uint8_t groups[8]; + + do + { + // + // process non-mirrored ranges + // + + // read chip base address attribute + rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASE, &i_chip_target, mem_base); + if (!rc.ok()) + { + FAPI_ERR("Error reading ATTR_PROC_MEM_BASE"); + break; + } + + // base addresses for distinct non-mirrored ranges + mem_bases[0]=mem_base; + mem_bases[1]=0x0; + mem_bases[2]=0x0; + mem_bases[3]=0x0; + mem_bases[4]=0x0; + mem_bases[5]=0x0; + mem_bases[6]=0x0; + mem_bases[7]=0x0; + + FAPI_DBG(" ATTR_PROC_MEM_BASES[0]: %016llx", mem_bases[0]); + FAPI_DBG(" ATTR_PROC_MEM_BASES[1]: %016llx", mem_bases[1]); + FAPI_DBG(" ATTR_PROC_MEM_BASES[2]: %016llx", mem_bases[2]); + FAPI_DBG(" ATTR_PROC_MEM_BASES[3]: %016llx", mem_bases[3]); + FAPI_DBG(" ATTR_PROC_MEM_BASES[4]: %016llx", mem_bases[4]); + FAPI_DBG(" ATTR_PROC_MEM_BASES[5]: %016llx", mem_bases[5]); + FAPI_DBG(" ATTR_PROC_MEM_BASES[6]: %016llx", mem_bases[6]); + FAPI_DBG(" ATTR_PROC_MEM_BASES[7]: %016llx", mem_bases[7]); + + rc = FAPI_ATTR_SET(ATTR_PROC_MEM_BASES, &i_chip_target, mem_bases); + if (!rc.ok()) + { + FAPI_ERR("Error writing ATTR_PROC_MEM_BASES"); + break; + } + + // sizes for distinct non-mirrored ranges + l_memory_sizes[0]=128ULL*0x40000000ULL; + l_memory_sizes[1]=0x0; + l_memory_sizes[2]=0x0; + l_memory_sizes[3]=0x0; + l_memory_sizes[4]=0x0; + l_memory_sizes[5]=0x0; + l_memory_sizes[6]=0x0; + l_memory_sizes[7]=0x0; + + FAPI_DBG(" ATTR_PROC_MEM_SIZES[0]: %016llx", l_memory_sizes[0]); + FAPI_DBG(" ATTR_PROC_MEM_SIZES[1]: %016llx", l_memory_sizes[1]); + FAPI_DBG(" ATTR_PROC_MEM_SIZES[2]: %016llx", l_memory_sizes[2]); + FAPI_DBG(" ATTR_PROC_MEM_SIZES[3]: %016llx", l_memory_sizes[3]); + FAPI_DBG(" ATTR_PROC_MEM_SIZES[4]: %016llx", l_memory_sizes[4]); + FAPI_DBG(" ATTR_PROC_MEM_SIZES[5]: %016llx", l_memory_sizes[5]); + FAPI_DBG(" ATTR_PROC_MEM_SIZES[6]: %016llx", l_memory_sizes[6]); + FAPI_DBG(" ATTR_PROC_MEM_SIZES[7]: %016llx", l_memory_sizes[7]); + + rc = FAPI_ATTR_SET(ATTR_PROC_MEM_SIZES, &i_chip_target, l_memory_sizes); + if (!rc.ok()) + { + FAPI_ERR("Error writing ATTR_PROC_MEM_SIZES"); + break; + } + + + // + // process mirrored ranges + // + + // read chip base address attribute + rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASE, &i_chip_target, mirror_base); + if (!rc.ok()) + { + FAPI_ERR("Error reading ATTR_PROC_MIRROR_BASE"); + break; + } + + // base addresses for distinct mirrored ranges + mirror_bases[0] = mirror_base; + mirror_bases[1] = 0x0; + mirror_bases[2] = 0x0; + mirror_bases[3] = 0x0; + + FAPI_DBG(" ATTR_PROC_MIRROR_BASES[0]: %016llx", mirror_bases[0]); + FAPI_DBG(" ATTR_PROC_MIRROR_BASES[1]: %016llx", mirror_bases[1]); + FAPI_DBG(" ATTR_PROC_MIRROR_BASES[2]: %016llx", mirror_bases[2]); + FAPI_DBG(" ATTR_PROC_MIRROR_BASES[3]: %016llx", mirror_bases[3]); + + rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_BASES, &i_chip_target, mirror_bases); + if (!rc.ok()) + { + FAPI_ERR("Error writing ATTR_PROC_MIRROR_BASES"); + break; + } + + // sizes for distinct mirrored ranges + l_mirror_sizes[0]=0; + l_mirror_sizes[1]=0; + l_mirror_sizes[2]=0; + l_mirror_sizes[3]=0; + + FAPI_DBG(" ATTR_PROC_MIRROR_SIZES[0]: %016llx", l_mirror_sizes[0]); + FAPI_DBG(" ATTR_PROC_MIRROR_SIZES[1]: %016llx", l_mirror_sizes[1]); + FAPI_DBG(" ATTR_PROC_MIRROR_SIZES[2]: %016llx", l_mirror_sizes[2]); + FAPI_DBG(" ATTR_PROC_MIRROR_SIZES[3]: %016llx", l_mirror_sizes[3]); + + rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_SIZES, &i_chip_target, l_mirror_sizes); + if (!rc.ok()) + { + FAPI_ERR("Error writing ATTR_PROC_MIRROR_SIZES"); + break; + } + + + // + // process group configuration + // + + groups[0]=0x0C; + groups[1]=0x00; + groups[2]=0x00; + groups[3]=0x00; + groups[4]=0x00; + groups[5]=0x00; + groups[6]=0x00; + groups[7]=0x00; + rc = FAPI_ATTR_SET(ATTR_MSS_MEM_MC_IN_GROUP, &i_chip_target, groups); + if (!rc.ok()) + { + FAPI_ERR("Error writing ATTR_MSS_MEM_MC_IN_GROUP"); + break; + } + + + // + // write HW registers + // + + // get child MCS chiplets + rc = fapiGetChildChiplets(i_chip_target, + fapi::TARGET_TYPE_MCS_CHIPLET, + l_mcs_chiplets, + fapi::TARGET_STATE_FUNCTIONAL); + if (!rc.ok()) + { + FAPI_ERR("Error from fapiGetChildChiplets"); + break; + } + + // loop through & set configuration of each child + for (std::vector<fapi::Target>::iterator iter = l_mcs_chiplets.begin(); + iter != l_mcs_chiplets.end(); + iter++) + { + uint8_t mcs_pos = 0x0; + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*iter), mcs_pos); + if (!rc.ok()) + { + FAPI_ERR("Error reading ATTR_CHIP_UNIT_POS"); + break; + } + + // set configuration registers (static to match VBU model for now) + if (mcs_pos == 4) + { + MCFGP_data.setDoubleWord(0, 0x90601FC000000000ULL); + } + else if (mcs_pos == 5) + { + MCFGP_data.setDoubleWord(0, 0x90E01FC000000000ULL); + } + else + { + MCFGP_data.setDoubleWord(0, 0x0060008000000000ULL); + } + + // write MCFGP register + FAPI_DBG("Writing MCS %d MCFGP = 0x%llx", + mcs_pos, MCFGP_data.getDoubleWord(0)); + + rc = fapiPutScom(*iter, MCS_MCFGP_0x02011800, MCFGP_data); + if (!rc.ok()) + { + FAPI_ERR("Error from fapiPutScom (MCS_MCFGP_0x02011800)"); + break; + } + } + } while(0); + + return rc; +} + + +} // extern "C" diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.H new file mode 100644 index 000000000..2affbd35f --- /dev/null +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.H @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.H $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : mss_setup_bars.H +// *! DESCRIPTION : see additional comments below +// *! OWNER NAME : Girisankar Paulraj Email: gpaulraj@in.ibm.com +// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com +// *! ADDITIONAL COMMENTS : +// +// Header file for mss_setup_bars. +// +//------------------------------------------------------------------------------ +// Don't forget to create CVS comments when you check in your changes! +//------------------------------------------------------------------------------ +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version:| Author: | Date: | Comment: +//---------|----------|---------|----------------------------------------------- +// 1.1 | gpaulraj | 03/19/12| Updated + +#ifndef MSS_SETUP_BARS_H_ +#define MSS_SETUP_BARS_H_ + +#include <fapi.H> +#include "p8_scom_addresses.H" + +typedef fapi::ReturnCode (*mss_setup_bars_FP_t)(const fapi::Target&); + +extern "C" +{ + +fapi::ReturnCode mss_setup_bars(const fapi::Target& i_chip_target); + +} // extern "C" + +#endif // MSS_SETUP_BARS_H_ diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/p8_scom_addresses.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/p8_scom_addresses.H new file mode 100755 index 000000000..1db4c4a9d --- /dev/null +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/p8_scom_addresses.H @@ -0,0 +1,1677 @@ +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/p8_scom_addresses.H $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ +// $Id: p8_scom_addresses.H,v 1.77 2012/06/09 19:24:39 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/p8_scom_addresses.H,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : p8_scom_addresses.H +// *! DESCRIPTION : Defines for P8 scom addresses +// *! OWNER NAME : Jeshua Smith Email: jeshua@us.ibm.com +// *! BACKUP NAME : Email: @us.ibm.com +// #! ADDITIONAL COMMENTS : +// +// The purpose of this header is to define scom addresses for use by procedures. +// This will help catch address typos at compile time, and will make it easy +// to track down which procedures use each address +// + +#ifndef P8_SCOM_ADDRESSES +#define P8_SCOM_ADDRESSES + +//---------------------------------------------------------------------- +// Scom address overview +//---------------------------------------------------------------------- +// P8 uses 64-bit scom addresses, which are classified into two formats: +// +// "Normal" (legacy) format +// +// 111111 11112222 22222233 33333333 44444444 44555555 55556666 +// 01234567 89012345 67890123 45678901 23456789 01234567 89012345 67890123 +// -------- -------- -------- -------- -------- -------- -------- -------- +// 00000000 00000000 00000000 00000000 0MCCCCCC ????PPPP 00LLLLLL LLLLLLLL +// || | | +// || | `-> Local Address* +// || | +// || `-> Port +// || +// |`-> Chiplet ID** +// | +// `-> Multicast bit +// +// * Local address is composed of "00" + 4-bit ring + 10-bit ID +// The 10-bit ID is usually 4-bit sat_id and 6-bit reg_id +// +// ** Chiplet ID turns into multicast operation type and group number +// if the multicast bit is set +// +// "Indirect" format +// +// +// 111111 11112222 22222233 33333333 44444444 44555555 55556666 +// 01234567 89012345 67890123 45678901 23456789 01234567 89012345 67890123 +// -------- -------- -------- -------- -------- -------- -------- -------- +// 10000000 0000IIII IIIIIGGG GGGLLLLL 0MCCCCCC ????PPPP 00LLLLLL LLLLLLLL +// | | | || | | +// | | | || | `-> Local Address* +// | | | || | +// | | | || `-> Port +// | | | || +// | | | |`-> Chiplet ID** +// | | | | +// | | | `-> Multicast bit +// | | | +// | | `-> Lane ID +// | | +// | `-> RX or TX Group ID +// | +// `-> Indirect Register Address +// +// * Local address is composed of "00" + 4-bit ring + 4-bit sat_id + "111111" +// +// ** Chiplet ID turns into multicast operation type and group number +// if the multicast bit is set +// + +#include "common_scom_addresses.H" +#include "fapi_sbe_common.H" + +/******************************************************************************/ +/********************************** CHIPLET *********************************/ +/******************************************************************************/ +// use for lpcs P0, <chipletID> +CONST_UINT64_T( X_BUS_CHIPLET_0x04000000 , ULL(0x04000000) ); +CONST_UINT64_T( PCIE_CHIPLET_0x08000000 , ULL(0x08000000) ); +CONST_UINT64_T( A_BUS_CHIPLET_0x09000000 , ULL(0x09000000) ); +// EX00_CHIPLET - EX15_CHIPLET defined in the EX CHIPLET section +// "Multicast" chiplets +CONST_UINT64_T( ALL_CHIPLETS_OR_0x40000000 , ULL(0x40000000) ); +CONST_UINT64_T( ALL_CHIPLETS_AND_0x48000000 , ULL(0x48000000) ); +CONST_UINT64_T( ALL_CHIPLETS_BITX_0x50000000 , ULL(0x50000000) ); +CONST_UINT64_T( ALL_CHIPLETS_COMP_0x60000000 , ULL(0x60000000) ); +CONST_UINT64_T( ALL_CHIPLETS_WRITE_0x68000000 , ULL(0x68000000) ); + +CONST_UINT64_T( ALL_EXS_OR_0x41000000 , ULL(0x41000000) ); +CONST_UINT64_T( ALL_EXS_AND_0x49000000 , ULL(0x49000000) ); +CONST_UINT64_T( ALL_EXS_BITX_0x51000000 , ULL(0x51000000) ); +CONST_UINT64_T( ALL_EXS_COMP_0x61000000 , ULL(0x61000000) ); +CONST_UINT64_T( ALL_EXS_WRITE_0x69000000 , ULL(0x69000000) ); + +CONST_UINT64_T( ALL_CORES_OR_0x42000000 , ULL(0x42000000) ); +CONST_UINT64_T( ALL_CORES_AND_0x4A000000 , ULL(0x4A000000) ); +CONST_UINT64_T( ALL_CORES_BITX_0x52000000 , ULL(0x52000000) ); +CONST_UINT64_T( ALL_CORES_COMP_0x62000000 , ULL(0x62000000) ); +CONST_UINT64_T( ALL_CORES_WRITE_0x6A000000 , ULL(0x6A000000) ); + + +/******************************************************************************/ +/******************************** TP CHIPLET ********************************/ +/******************************************************************************/ + +//------------------------------------------------------------------------------ +// OTPROM +//------------------------------------------------------------------------------ +CONST_UINT64_T( ECID_PART_0_0x00018000 , ULL(0x00018000) ); +CONST_UINT64_T( ECID_PART_1_0x00018001 , ULL(0x00018001) ); + +//------------------------------------------------------------------------------ +// PORE-GPE0 +//------------------------------------------------------------------------------ +CONST_UINT64_T( PORE_GPE0_0x00060000 , ULL(0x00060000) ); +CONST_UINT64_T( PORE_GPE0_STATUS_0x00060000 , ULL(0x00060000) ); +CONST_UINT64_T( PORE_GPE0_CONTROL_0x00060001 , ULL(0x00060001) ); +CONST_UINT64_T( PORE_GPE0_RESET_0x00060002 , ULL(0x00060002) ); +CONST_UINT64_T( PORE_GPE0_ERROR_MASK_0x00060003 , ULL(0x00060003) ); +CONST_UINT64_T( PORE_GPE0_PRV_BASE_ADDRESS0_0x00060004 , ULL(0x00060004) ); +CONST_UINT64_T( PORE_GPE0_PRV_BASE_ADDRESS1_0x00060005 , ULL(0x00060005) ); +CONST_UINT64_T( PORE_GPE0_OCI_BASE_ADDRESS0_0x00060006 , ULL(0x00060006) ); +CONST_UINT64_T( PORE_GPE0_OCI_BASE_ADDRESS1_0x00060007 , ULL(0x00060007) ); +CONST_UINT64_T( PORE_GPE0_TABLE_BASE_ADDR_0x00060008 , ULL(0x00060008) ); +CONST_UINT64_T( PORE_GPE0_EXE_TRIGGER_0x00060009 , ULL(0x00060009) ); +CONST_UINT64_T( PORE_GPE0_SCRATCH0_0x0006000A , ULL(0x0006000A) ); +CONST_UINT64_T( PORE_GPE0_SCRATCH1_0x0006000B , ULL(0x0006000B) ); +CONST_UINT64_T( PORE_GPE0_SCRATCH2_0x0006000C , ULL(0x0006000C) ); +CONST_UINT64_T( PORE_GPE0_IBUF_01_0x0006000D , ULL(0x0006000D) ); +CONST_UINT64_T( PORE_GPE0_IBUF_2_0x0006000E , ULL(0x0006000E) ); +CONST_UINT64_T( PORE_GPE0_DBG0_0x0006000F , ULL(0x0006000F) ); +CONST_UINT64_T( PORE_GPE0_DBG1_0x00060010 , ULL(0x00060010) ); +CONST_UINT64_T( PORE_GPE0_PC_STACK0_0x00060011 , ULL(0x00060011) ); +CONST_UINT64_T( PORE_GPE0_PC_STACK1_0x00060012 , ULL(0x00060012) ); +CONST_UINT64_T( PORE_GPE0_PC_STACK2_0x00060013 , ULL(0x00060013) ); +CONST_UINT64_T( PORE_GPE0_ID_FLAGS_0x00060014 , ULL(0x00060014) ); +CONST_UINT64_T( PORE_GPE0_DATA0_0x00060015 , ULL(0x00060015) ); +CONST_UINT64_T( PORE_GPE0_MEMORY_RELOC_0x00060016 , ULL(0x00060016) ); +CONST_UINT64_T( PORE_GPE0_I2C_E0_PARAM_0x00060017 , ULL(0x00060017) ); +CONST_UINT64_T( PORE_GPE0_I2C_E1_PARAM_0x00060018 , ULL(0x00060018) ); +CONST_UINT64_T( PORE_GPE0_I2C_E2_PARAM_0x00060019 , ULL(0x00060019) ); + +//------------------------------------------------------------------------------ +// PORE-GPE1 +//------------------------------------------------------------------------------ +CONST_UINT64_T( PORE_GPE1_0x00060020 , ULL(0x00060020) ); +CONST_UINT64_T( PORE_GPE1_STATUS_0x00060020 , ULL(0x00060020) ); +CONST_UINT64_T( PORE_GPE1_CONTROL_0x00060021 , ULL(0x00060021) ); +CONST_UINT64_T( PORE_GPE1_RESET_0x00060022 , ULL(0x00060022) ); +CONST_UINT64_T( PORE_GPE1_ERROR_MASK_0x00060023 , ULL(0x00060023) ); +CONST_UINT64_T( PORE_GPE1_PRV_BASE_ADDRESS0_0x00060024 , ULL(0x00060024) ); +CONST_UINT64_T( PORE_GPE1_PRV_BASE_ADDRESS1_0x00060025 , ULL(0x00060025) ); +CONST_UINT64_T( PORE_GPE1_OCI_BASE_ADDRESS0_0x00060026 , ULL(0x00060026) ); +CONST_UINT64_T( PORE_GPE1_OCI_BASE_ADDRESS1_0x00060027 , ULL(0x00060027) ); +CONST_UINT64_T( PORE_GPE1_TABLE_BASE_ADDR_0x00060028 , ULL(0x00060028) ); +CONST_UINT64_T( PORE_GPE1_EXE_TRIGGER_0x00060029 , ULL(0x00060029) ); +CONST_UINT64_T( PORE_GPE1_SCRATCH0_0x0006002A , ULL(0x0006002A) ); +CONST_UINT64_T( PORE_GPE1_SCRATCH1_0x0006002B , ULL(0x0006002B) ); +CONST_UINT64_T( PORE_GPE1_SCRATCH2_0x0006002C , ULL(0x0006002C) ); +CONST_UINT64_T( PORE_GPE1_IBUF_01_0x0006002D , ULL(0x0006002D) ); +CONST_UINT64_T( PORE_GPE1_IBUF_2_0x0006002E , ULL(0x0006002E) ); +CONST_UINT64_T( PORE_GPE1_DBG0_0x0006002F , ULL(0x0006002F) ); +CONST_UINT64_T( PORE_GPE1_DBG1_0x00060030 , ULL(0x00060030) ); +CONST_UINT64_T( PORE_GPE1_PC_STACK0_0x00060031 , ULL(0x00060031) ); +CONST_UINT64_T( PORE_GPE1_PC_STACK1_0x00060032 , ULL(0x00060032) ); +CONST_UINT64_T( PORE_GPE1_PC_STACK2_0x00060033 , ULL(0x00060033) ); +CONST_UINT64_T( PORE_GPE1_ID_FLAGS_0x00060034 , ULL(0x00060034) ); +CONST_UINT64_T( PORE_GPE1_DATA0_0x00060035 , ULL(0x00060035) ); +CONST_UINT64_T( PORE_GPE1_MEMORY_RELOC_0x00060036 , ULL(0x00060036) ); +CONST_UINT64_T( PORE_GPE1_I2C_E0_PARAM_0x00060037 , ULL(0x00060037) ); +CONST_UINT64_T( PORE_GPE1_I2C_E1_PARAM_0x00060038 , ULL(0x00060038) ); +CONST_UINT64_T( PORE_GPE1_I2C_E2_PARAM_0x00060039 , ULL(0x00060039) ); + +//------------------------------------------------------------------------------ +// PORE-SLW +//------------------------------------------------------------------------------ +CONST_UINT64_T( PORE_SLW_0x00068000 , ULL(0x00068000) ); +CONST_UINT64_T( PORE_SLW_STATUS_0x00068000 , ULL(0x00068000) ); +CONST_UINT64_T( PORE_SLW_CONTROL_0x00068001 , ULL(0x00068001) ); +CONST_UINT64_T( PORE_SLW_RESET_0x00068002 , ULL(0x00068002) ); +CONST_UINT64_T( PORE_SLW_ERROR_MASK_0x00068003 , ULL(0x00068003) ); +CONST_UINT64_T( PORE_SLW_PRV_BASE_ADDRESS0_0x00068004 , ULL(0x00068004) ); +CONST_UINT64_T( PORE_SLW_PRV_BASE_ADDRESS1_0x00068005 , ULL(0x00068005) ); +CONST_UINT64_T( PORE_SLW_OCI_BASE_ADDRESS0_0x00068006 , ULL(0x00068006) ); +CONST_UINT64_T( PORE_SLW_OCI_BASE_ADDRESS1_0x00068007 , ULL(0x00068007) ); +CONST_UINT64_T( PORE_SLW_TABLE_BASE_ADDR_0x00068008 , ULL(0x00068008) ); +CONST_UINT64_T( PORE_SLW_EXE_TRIGGER_0x00068009 , ULL(0x00068009) ); +CONST_UINT64_T( PORE_SLW_SCRATCH0_0x0006800A , ULL(0x0006800A) ); +CONST_UINT64_T( PORE_SLW_SCRATCH1_0x0006800B , ULL(0x0006800B) ); +CONST_UINT64_T( PORE_SLW_SCRATCH2_0x0006800C , ULL(0x0006800C) ); +CONST_UINT64_T( PORE_SLW_IBUF_01_0x0006800D , ULL(0x0006800D) ); +CONST_UINT64_T( PORE_SLW_IBUF_2_0x0006800E , ULL(0x0006800E) ); +CONST_UINT64_T( PORE_SLW_DBG0_0x0006800F , ULL(0x0006800F) ); +CONST_UINT64_T( PORE_SLW_DBG1_0x00068010 , ULL(0x00068010) ); +CONST_UINT64_T( PORE_SLW_PC_STACK0_0x00068011 , ULL(0x00068011) ); +CONST_UINT64_T( PORE_SLW_PC_STACK1_0x00068012 , ULL(0x00068012) ); +CONST_UINT64_T( PORE_SLW_PC_STACK2_0x00068013 , ULL(0x00068013) ); +CONST_UINT64_T( PORE_SLW_ID_FLAGS_0x00068014 , ULL(0x00068014) ); +CONST_UINT64_T( PORE_SLW_DATA0_0x00068015 , ULL(0x00068015) ); +CONST_UINT64_T( PORE_SLW_MEMORY_RELOC_0x00068016 , ULL(0x00068016) ); +CONST_UINT64_T( PORE_SLW_I2C_E0_PARAM_0x00068017 , ULL(0x00068017) ); +CONST_UINT64_T( PORE_SLW_I2C_E1_PARAM_0x00068018 , ULL(0x00068018) ); +CONST_UINT64_T( PORE_SLW_I2C_E2_PARAM_0x00068019 , ULL(0x00068019) ); + +//------------------------------------------------------------------------------ +// OCC/OCB +//------------------------------------------------------------------------------ + +CONST_UINT64_T( OCC_CONTROL_0x0006B000 , ULL(0x0006B000) ); +CONST_UINT64_T( OCC_CONTROL_AND_0x0006B001 , ULL(0x0006B001) ); +CONST_UINT64_T( OCC_CONTROL_OR_0x0006B002 , ULL(0x0006B002) ); +CONST_UINT64_T( OCC_DEBUG_MODE_0x0006B003 , ULL(0x0006B003) ); + +CONST_UINT64_T( OCB0_ADDRESS_0x0006B010 , ULL(0x0006B010) ); +CONST_UINT64_T( OCB0_STATUS_CONTROL_0x0006B011 , ULL(0x0006B011) ); +CONST_UINT64_T( OCB0_STATUS_CONTROL_AND_0x0006B012 , ULL(0x0006B012) ); +CONST_UINT64_T( OCB0_STATUS_CONTROL_OR_0x0006B013 , ULL(0x0006B013) ); +CONST_UINT64_T( OCB0_ERROR_STATUS_0x0006B014 , ULL(0x0006B014) ); +CONST_UINT64_T( OCB0_DATA_0x0006B015 , ULL(0x0006B015) ); +CONST_UINT64_T( OCB0_PULL_BASE_0x0006A200 , ULL(0x0006A200) ); +CONST_UINT64_T( OCB0_PULL_STATUS_CONTROL_0x0006A201 , ULL(0x0006A201) ); +CONST_UINT64_T( OCB0_PUSH_BASE_0x0006A203 , ULL(0x0006A203) ); +CONST_UINT64_T( OCB0_PUSH_STATUS_CONTROL_0x0006A204 , ULL(0x0006A204) ); +CONST_UINT64_T( OCB0_STREAM_ERR_STATUS_0x0006A206 , ULL(0x0006A206) ); +CONST_UINT64_T( OCB0_UNTRUSTED_CONTROL_0x0006A207 , ULL(0x0006A207) ); +CONST_UINT64_T( OCB0_LIN_WINDOW_CONTROL_0x0006A208 , ULL(0x0006A208) ); +CONST_UINT64_T( OCB0_LIN_WINDOW_BASE_0x0006A20C , ULL(0x0006A20C) ); + +CONST_UINT64_T( OCB1_ADDRESS_0x0006B030 , ULL(0x0006B030) ); +CONST_UINT64_T( OCB1_STATUS_CONTROL_0x0006B031 , ULL(0x0006B031) ); +CONST_UINT64_T( OCB1_STATUS_CONTROL_AND_0x0006B032 , ULL(0x0006B032) ); +CONST_UINT64_T( OCB1_STATUS_CONTROL_OR_0x0006B033 , ULL(0x0006B033) ); +CONST_UINT64_T( OCB1_ERROR_STATUS_0x0006B034 , ULL(0x0006B034) ); +CONST_UINT64_T( OCB1_DATA_0x0006B035 , ULL(0x0006B035) ); +CONST_UINT64_T( OCB1_PULL_BASE_0x0006A210 , ULL(0x0006A210) ); +CONST_UINT64_T( OCB1_PULL_STATUS_CONTROL_0x0006A211 , ULL(0x0006A211) ); +CONST_UINT64_T( OCB1_PUSH_BASE_0x0006A213 , ULL(0x0006A213) ); +CONST_UINT64_T( OCB1_PUSH_STATUS_CONTROL_0x0006A214 , ULL(0x0006A214) ); +CONST_UINT64_T( OCB1_STREAM_ERR_STATUS_0x0006A216 , ULL(0x0006A216) ); +CONST_UINT64_T( OCB1_UNTRUSTED_CONTROL_0x0006A217 , ULL(0x0006A217) ); +CONST_UINT64_T( OCB1_LIN_WINDOW_CONTROL_0x0006A218 , ULL(0x0006A218) ); +CONST_UINT64_T( OCB1_LIN_WINDOW_BASE_0x0006A21C , ULL(0x0006A21C) ); + +CONST_UINT64_T( OCB2_ADDRESS_0x0006B050 , ULL(0x0006B050) ); +CONST_UINT64_T( OCB2_STATUS_CONTROL_0x0006B051 , ULL(0x0006B051) ); +CONST_UINT64_T( OCB2_STATUS_CONTROL_AND_0x0006B052 , ULL(0x0006B052) ); +CONST_UINT64_T( OCB2_STATUS_CONTROL_OR_0x0006B053 , ULL(0x0006B053) ); +CONST_UINT64_T( OCB2_ERROR_STATUS_0x0006B054 , ULL(0x0006B054) ); +CONST_UINT64_T( OCB2_DATA_0x0006B055 , ULL(0x0006B055) ); +CONST_UINT64_T( OCB2_PULL_BASE_0x0006A220 , ULL(0x0006A220) ); +CONST_UINT64_T( OCB2_PULL_STATUS_CONTROL_0x0006A221 , ULL(0x0006A221) ); +CONST_UINT64_T( OCB2_PUSH_BASE_0x0006A223 , ULL(0x0006A223) ); +CONST_UINT64_T( OCB2_PUSH_STATUS_CONTROL_0x0006A224 , ULL(0x0006A224) ); +CONST_UINT64_T( OCB2_STREAM_ERR_STATUS_0x0006A226 , ULL(0x0006A226) ); +CONST_UINT64_T( OCB2_UNTRUSTED_CONTROL_0x0006A227 , ULL(0x0006A227) ); +CONST_UINT64_T( OCB2_LIN_WINDOW_CONTROL_0x0006A228 , ULL(0x0006A228) ); +CONST_UINT64_T( OCB2_LIN_WINDOW_BASE_0x0006A22C , ULL(0x0006A22C) ); + +CONST_UINT64_T( OCB3_ADDRESS_0x0006B070 , ULL(0x0006B070) ); +CONST_UINT64_T( OCB3_STATUS_CONTROL_0x0006B071 , ULL(0x0006B071) ); +CONST_UINT64_T( OCB3_STATUS_CONTROL_AND_0x0006B072 , ULL(0x0006B072) ); +CONST_UINT64_T( OCB3_STATUS_CONTROL_OR_0x0006B073 , ULL(0x0006B073) ); +CONST_UINT64_T( OCB3_ERROR_STATUS_0x0006B074 , ULL(0x0006B074) ); +CONST_UINT64_T( OCB3_DATA_0x0006B075 , ULL(0x0006B075) ); +CONST_UINT64_T( OCB3_PULL_BASE_0x0006A230 , ULL(0x0006A230) ); +CONST_UINT64_T( OCB3_PULL_STATUS_CONTROL_0x0006A231 , ULL(0x0006A231) ); +CONST_UINT64_T( OCB3_PUSH_BASE_0x0006A233 , ULL(0x0006A233) ); +CONST_UINT64_T( OCB3_PUSH_STATUS_CONTROL_0x0006A234 , ULL(0x0006A234) ); +CONST_UINT64_T( OCB3_STREAM_ERR_STATUS_0x0006A236 , ULL(0x0006A236) ); +CONST_UINT64_T( OCB3_UNTRUSTED_CONTROL_0x0006A237 , ULL(0x0006A237) ); +CONST_UINT64_T( OCB3_LIN_WINDOW_CONTROL_0x0006A238 , ULL(0x0006A238) ); +CONST_UINT64_T( OCB3_LIN_WINDOW_BASE_0x0006A23C , ULL(0x0006A23C) ); + +// sram registers +CONST_UINT64_T( OCC_SRAM_BOOT_VEC0_0x00066004 , ULL(0x00066004) ); +CONST_UINT64_T( OCC_SRAM_BOOT_VEC1_0x00066005 , ULL(0x00066005) ); +CONST_UINT64_T( OCC_SRAM_BOOT_VEC2_0x00066006 , ULL(0x00066006) ); +CONST_UINT64_T( OCC_SRAM_BOOT_VEC3_0x00066007 , ULL(0x00066007) ); + +//------------------------------------------------------------------------------ +// PMC +//------------------------------------------------------------------------------ +// todo: the full set needs to be added. The ones below are for SLW at this time + +// PIB Space Addresses + + +CONST_UINT64_T( PMC_SPIV_CTRL_REG0A_0x00062040 , ULL(0x00062040) ); +CONST_UINT64_T( PMC_SPIV_CTRL_REG0B_0x00062041 , ULL(0x00062041) ); +CONST_UINT64_T( PMC_SPIV_CTRL_REG1_0x00062042 , ULL(0x00062042) ); +CONST_UINT64_T( PMC_SPIV_CTRL_REG2_0x00062043 , ULL(0x00062043) ); +CONST_UINT64_T( PMC_SPIV_CTRL_REG3_0x00062044 , ULL(0x00062044) ); +CONST_UINT64_T( PMC_SPIV_CTRL_REG4_0x00062045 , ULL(0x00062045) ); +CONST_UINT64_T( PMC_SPIV_STATUS_REG_0x00062046 , ULL(0x00062046) ); +CONST_UINT64_T( PMC_SPIV_COMMAND_REG_0x00062047 , ULL(0x00062047) ); + + +CONST_UINT64_T( PMC_O2S_CTRL_REG0A_0x00062050 , ULL(0x00062050) ); +CONST_UINT64_T( PMC_O2S_CTRL_REG0B_0x00062051 , ULL(0x00062051) ); +CONST_UINT64_T( PMC_O2S_CTRL_REG1_0x00062052 , ULL(0x00062052) ); +CONST_UINT64_T( PMC_O2S_CTRL_REG2_0x00062053 , ULL(0x00062053) ); +CONST_UINT64_T( PMC_O2S_CTRL_REG4_0x00062055 , ULL(0x00062055) ); +CONST_UINT64_T( PMC_O2S_STATUS_REG_0x00062056 , ULL(0x00062056) ); +CONST_UINT64_T( PMC_O2S_COMMAND_REG_0x00062057 , ULL(0x00062057) ); +CONST_UINT64_T( PMC_O2S_WDATA_REG_0x00062058 , ULL(0x00062058) ); +CONST_UINT64_T( PMC_O2S_RDATA_REG_0x00062059 , ULL(0x00062059) ); + +CONST_UINT64_T( PMC_PORE_REQ_STAT_REG_0x00062090 , ULL(0x00062090) ); +CONST_UINT64_T( PMC_MODE_REG_0x00062000 , ULL(0x00062000) ); + + + + +CONST_UINT64_T( SPIPSS_ADC_CTRL_REG0_0x00070000 , ULL(0x00070000) ); +CONST_UINT64_T( SPIPSS_ADC_CTRL_REG1_0x00070001 , ULL(0x00070001) ); +CONST_UINT64_T( SPIPSS_ADC_CTRL_REG2_0x00070002 , ULL(0x00070002) ); +CONST_UINT64_T( SPIPSS_ADC_STATUS_REG_0x00070003 , ULL(0x00070003) ); +CONST_UINT64_T( SPIPSS_ADC_CMD_REG_0x00070004 , ULL(0x00070004) ); +CONST_UINT64_T( SPIPSS_ADC_WDATA_REG_0x00070010 , ULL(0x00070010) ); +CONST_UINT64_T( SPIPSS_ADC_RDATA_REG0_0x00070020 , ULL(0x00070020) ); +CONST_UINT64_T( SPIPSS_ADC_RDATA_REG1_0x00070021 , ULL(0x00070021) ); +CONST_UINT64_T( SPIPSS_ADC_RDATA_REG2_0x00070022 , ULL(0x00070022) ); +CONST_UINT64_T( SPIPSS_ADC_RDATA_REG3_0x00070023 , ULL(0x00070023) ); +CONST_UINT64_T( SPIPSS_100NS_REG_0x00070028 , ULL(0x00070028) ); +CONST_UINT64_T( SPIPSS_P2S_CTRL_REG0_0x00070040 , ULL(0x00070040) ); +CONST_UINT64_T( SPIPSS_P2S_CTRL_REG1_0x00070041 , ULL(0x00070041) ); +CONST_UINT64_T( SPIPSS_P2S_CTRL_REG2_0x00070042 , ULL(0x00070042) ); +CONST_UINT64_T( SPIPSS_P2S_STATUS_REG_0x00070043 , ULL(0x00070043) ); +CONST_UINT64_T( SPIPSS_P2S_COMMAND_REG_0x00070044 , ULL(0x00070044) ); +CONST_UINT64_T( SPIPSS_P2S_WDATA_REG_0x00070050 , ULL(0x00070050) ); +CONST_UINT64_T( SPIPSS_P2S_RDATA_REG_0x00070060 , ULL(0x00070060) ); +CONST_UINT64_T( SPIPSS_ADC_RESET_REGISTER_0x00070005 , ULL(0x00070005) ); +CONST_UINT64_T( SPIPSS_P2S_RESET_REGISTER_0x00070045 , ULL(0x00070045) ); + + +// OCI Space Addresses +CONST_UINT32_T( OCI_PMC_PORE_REQ_STAT_REG_0x40010480 , ULL(0x40010480) ); + + +//------------------------------------------------------------------------------ +// SPIADC +//------------------------------------------------------------------------------ +CONST_UINT64_T( SPIADC_0x00070000 , ULL(0x00070000) ); + +//------------------------------------------------------------------------------ +// PIB-ATTACHED MEMORY +//------------------------------------------------------------------------------ +CONST_UINT64_T( PIBMEM0_0x00080000 , ULL(0x00080000) ); + +CONST_UINT64_T( PIBMEM_CONTROL_0x00088000 , ULL(0x00088000) ); +CONST_UINT64_T( PIBMEM_ADDRESS_0x00088001 , ULL(0x00088001) ); +CONST_UINT64_T( PIBMEM_DATA_0x00088002 , ULL(0x00088002) ); +CONST_UINT64_T( PIBMEM_DATA_INC_0x00088003 , ULL(0x00088003) ); +CONST_UINT64_T( PIBMEM_DATA_DEC_0x00088004 , ULL(0x00088004) ); +CONST_UINT64_T( PIBMEM_STATUS_0x00088005 , ULL(0x00088005) ); +CONST_UINT64_T( PIBMEM_RESET_0x00088006 , ULL(0x00088006) ); +CONST_UINT64_T( PIBMEM_REPAIR_LOAD_0x00088007 , ULL(0x00088007) ); + +//------------------------------------------------------------------------------ +// I2C MASTER (MEMS1) +//------------------------------------------------------------------------------ +CONST_UINT64_T( I2CMS_MEMS1_CONTROL_0x000A0020 , ULL(0x000A0020) ); +CONST_UINT64_T( I2CMS_MEMS1_RESET_0x000A0021 , ULL(0x000A0021) ); +CONST_UINT64_T( I2CMS_MEMS1_STATUS_0x000A0022 , ULL(0x000A0022) ); +CONST_UINT64_T( I2CMS_MEMS1_DATA_0x000A0023 , ULL(0x000A0023) ); +CONST_UINT64_T( I2CMS_MEMS1_COMMAND_0x000A0025 , ULL(0x000A0025) ); + +//------------------------------------------------------------------------------ +// I2C MASTER (PCI) +//------------------------------------------------------------------------------ +CONST_UINT64_T( I2CMS_PCI_0x000A0040 , ULL(0x000A0040) ); +CONST_UINT64_T( I2CMS_PCI_CONTROL_0x000A0040 , ULL(0x000A0040) ); +CONST_UINT64_T( I2CMS_PCI_RESET_0x000A0041 , ULL(0x000A0041) ); +CONST_UINT64_T( I2CMS_PCI_STATUS_0x000A0042 , ULL(0x000A0042) ); +CONST_UINT64_T( I2CMS_PCI_DATA_0x000A0043 , ULL(0x000A0043) ); +CONST_UINT64_T( I2CMS_PCI_COMMAND_0x000A0045 , ULL(0x000A0045) ); + +//------------------------------------------------------------------------------ +// PORE-SBE +//------------------------------------------------------------------------------ +CONST_UINT64_T( PORE_SBE_0x000E0000 , ULL(0x000E0000) ); +CONST_UINT64_T( PORE_SBE_STATUS_0x000E0000 , ULL(0x000E0000) ); +CONST_UINT64_T( PORE_SBE_CONTROL_0x000E0001 , ULL(0x000E0001) ); +CONST_UINT64_T( PORE_SBE_RESET_0x000E0002 , ULL(0x000E0002) ); +CONST_UINT64_T( PORE_SBE_ERROR_MASK_0x000E0003 , ULL(0x000E0003) ); +CONST_UINT64_T( PORE_SBE_PRV_BASE_ADDRESS0_0x000E0004 , ULL(0x000E0004) ); +CONST_UINT64_T( PORE_SBE_PRV_BASE_ADDRESS1_0x000E0005 , ULL(0x000E0005) ); +CONST_UINT64_T( PORE_SBE_OCI_BASE_ADDRESS0_0x000E0006 , ULL(0x000E0006) ); +CONST_UINT64_T( PORE_SBE_OCI_BASE_ADDRESS1_0x000E0007 , ULL(0x000E0007) ); +CONST_UINT64_T( PORE_SBE_TABLE_BASE_ADDR_0x000E0008 , ULL(0x000E0008) ); +CONST_UINT64_T( PORE_SBE_EXE_TRIGGER_0x000E0009 , ULL(0x000E0009) ); +CONST_UINT64_T( PORE_SBE_SCRATCH0_0x000E000A , ULL(0x000E000A) ); +CONST_UINT64_T( PORE_SBE_SCRATCH1_0x000E000B , ULL(0x000E000B) ); +CONST_UINT64_T( PORE_SBE_SCRATCH2_0x000E000C , ULL(0x000E000C) ); +CONST_UINT64_T( PORE_SBE_IBUF_01_0x000E000D , ULL(0x000E000D) ); +CONST_UINT64_T( PORE_SBE_IBUF_2_0x000E000E , ULL(0x000E000E) ); +CONST_UINT64_T( PORE_SBE_DBG0_0x000E000F , ULL(0x000E000F) ); +CONST_UINT64_T( PORE_SBE_DBG1_0x000E0010 , ULL(0x000E0010) ); +CONST_UINT64_T( PORE_SBE_PC_STACK0_0x000E0011 , ULL(0x000E0011) ); +CONST_UINT64_T( PORE_SBE_PC_STACK1_0x000E0012 , ULL(0x000E0012) ); +CONST_UINT64_T( PORE_SBE_PC_STACK2_0x000E0013 , ULL(0x000E0013) ); +CONST_UINT64_T( PORE_SBE_ID_FLAGS_0x000E0014 , ULL(0x000E0014) ); +CONST_UINT64_T( PORE_SBE_DATA0_0x000E0015 , ULL(0x000E0015) ); +CONST_UINT64_T( PORE_SBE_MEMORY_RELOC_0x000E0016 , ULL(0x000E0016) ); +CONST_UINT64_T( PORE_SBE_I2C_E0_PARAM_0x000E0017 , ULL(0x000E0017) ); +CONST_UINT64_T( PORE_SBE_I2C_E1_PARAM_0x000E0018 , ULL(0x000E0018) ); +CONST_UINT64_T( PORE_SBE_I2C_E2_PARAM_0x000E0019 , ULL(0x000E0019) ); + +//------------------------------------------------------------------------------ +// TP SCOM +// ring 1 = Trace +// ring 2 = OCC +// ring 3 = PIB +// ring 15 = OCCSEC +//------------------------------------------------------------------------------ + + +/******************************************************************************/ +/******************************* NEST CHIPLET *******************************/ +/******************************************************************************/ + +//------------------------------------------------------------------------------ +// NEST SCOM +// ring 1 = Trace +// ring 2 = TCBR +// ring 3 = PB +// ring 6 = MCL +// MC0 MCS0 = 0x02011800 +// MC0 MCS1 = 0x02011880 +// MC1 MCS0 = 0x02011900 +// MC1 MCS0 = 0x02011980 +// IOMC0 = 0x02011A00 +// ring 7 = MCR +// MC2 MCS0 = 0x02011C00 +// MC2 MCS1 = 0x02011C80 +// MC3 MCS0 = 0x02011D00 +// MC3 MCS1 = 0x02011D80 +// IOMC1 = 0x02011E00 +// ring 8 = PCIS0 +// ring 9 = PCIS1 +// ring 10 = PCIS2 +// ring 11 = PCIS3 +// ring 12 = NX +// ring 13 = MCD +// ring 15 = TCBRSEC +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// NEST TRACE +//------------------------------------------------------------------------------ +CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T1_0x02010440 , ULL(0x02010440) ); +CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T1_0x02010441 , ULL(0x02010441) ); +CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T2_0x02010480 , ULL(0x02010480) ); +CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T2_0x02010481 , ULL(0x02010481) ); +CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T3_0x020104C0 , ULL(0x020104C0) ); +CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T3_0x020104C1 , ULL(0x020104C1) ); +CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T4_0x02010500 , ULL(0x02010500) ); +CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T4_0x02010501 , ULL(0x02010501) ); +CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T5_0x02010540 , ULL(0x02010540) ); +CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T5_0x02010541 , ULL(0x02010541) ); +CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T6_0x02010580 , ULL(0x02010580) ); +CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T6_0x02010581 , ULL(0x02010581) ); +CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T7_0x020105C0 , ULL(0x020105C0) ); +CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T7_0x020105C1 , ULL(0x020105C1) ); +CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T8_0x02010600 , ULL(0x02010600) ); +CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T8_0x02010601 , ULL(0x02010601) ); +CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T9_0x02010640 , ULL(0x02010640) ); +CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T9_0x02010641 , ULL(0x02010641) ); +CONST_UINT64_T( NEST_TRACE_DATA_HI_NX_0x02010A00 , ULL(0x02010A00) ); +CONST_UINT64_T( NEST_TRACE_DATA_LO_NX_0x02010A01 , ULL(0x02010A01) ); + +//------------------------------------------------------------------------------ +// POWERBUS ACCESS BRIDGE (PBA) +//------------------------------------------------------------------------------ +CONST_UINT64_T( PBA_CC_SYNC_CONF_0x02030000 , ULL(0x02030000) ); + +CONST_UINT64_T( PBA_FIR_0x02010840 , ULL(0x02010840) ); +CONST_UINT64_T( PBA_FIR_AND_0x02010841 , ULL(0x02010841) ); +CONST_UINT64_T( PBA_FIR_OR_0x02010842 , ULL(0x02010842) ); +CONST_UINT64_T( PBA_FIR_MASK_0x02010843 , ULL(0x02010843) ); +CONST_UINT64_T( PBA_FIR_MASK_AND_0x02010844 , ULL(0x02010844) ); +CONST_UINT64_T( PBA_FIR_MASK_OR_0x02010845 , ULL(0x02010845) ); +CONST_UINT64_T( PBA_FIR_ACTION0_0x02010846 , ULL(0x02010846) ); +CONST_UINT64_T( PBA_FIR_ACTION1_0x02010847 , ULL(0x02010847) ); + +CONST_UINT64_T( PBA_OCC_ACTION_0x0201084A , ULL(0x0201084A) ); +CONST_UINT64_T( PBA_CONFIG_0x0201084B , ULL(0x0201084B) ); +CONST_UINT64_T( PBA_ERR_RPT0_0x0201084C , ULL(0x0201084C) ); +CONST_UINT64_T( PBA_ERR_RPT1_0x0201084D , ULL(0x0201084D) ); +CONST_UINT64_T( PBA_ERR_RPT2_0x0201084E , ULL(0x0201084E) ); +CONST_UINT64_T( PBA_RBUFVAL0_0x02010850 , ULL(0x02010850) ); +CONST_UINT64_T( PBA_RBUFVAL1_0x02010851 , ULL(0x02010851) ); +CONST_UINT64_T( PBA_RBUFVAL2_0x02010852 , ULL(0x02010852) ); +CONST_UINT64_T( PBA_RBUFVAL3_0x02010853 , ULL(0x02010853) ); +CONST_UINT64_T( PBA_RBUFVAL4_0x02010854 , ULL(0x02010854) ); +CONST_UINT64_T( PBA_RBUFVAL5_0x02010855 , ULL(0x02010855) ); +CONST_UINT64_T( PBA_WBUFVAL0_0x02010858 , ULL(0x02010858) ); +CONST_UINT64_T( PBA_WBUFVAL1_0x02010859 , ULL(0x02010859) ); + +CONST_UINT64_T( PBA_MODE_0x00064000 , ULL(0x00064000) ); +CONST_UINT64_T( PBA_SLVRST_0x00064001 , ULL(0x00064001) ); +CONST_UINT64_T( PBA_SLVCTL0_0x00064004 , ULL(0x00064004) ); +CONST_UINT64_T( PBA_SLVCTL1_0x00064005 , ULL(0x00064005) ); +CONST_UINT64_T( PBA_SLVCTL2_0x00064006 , ULL(0x00064006) ); +CONST_UINT64_T( PBA_SLVCTL3_0x00064007 , ULL(0x00064007) ); +CONST_UINT64_T( PBA_BCDE_CTL_0x00064010 , ULL(0x00064010) ); +CONST_UINT64_T( PBA_BCDE_SET_0x00064011 , ULL(0x00064011) ); +CONST_UINT64_T( PBA_BCDE_STAT_0x00064012 , ULL(0x00064012) ); +CONST_UINT64_T( PBA_BCDE_PBADR_0x00064013 , ULL(0x00064013) ); +CONST_UINT64_T( PBA_BCDE_OCIBAR_0x00064014 , ULL(0x00064014) ); +CONST_UINT64_T( PBA_BCUE_CTL_0x00064015 , ULL(0x00064015) ); +CONST_UINT64_T( PBA_BCUE_SET_0x00064016 , ULL(0x00064016) ); +CONST_UINT64_T( PBA_BCUE_STAT_0x00064017 , ULL(0x00064017) ); +CONST_UINT64_T( PBA_BCUE_PBADR_0x00064018 , ULL(0x00064018) ); +CONST_UINT64_T( PBA_BCUE_OCIBAR_0x00064019 , ULL(0x00064019) ); +CONST_UINT64_T( PBA_PBOCR0_0x00064020 , ULL(0x00064020) ); +CONST_UINT64_T( PBA_PBOCR1_0x00064021 , ULL(0x00064021) ); +CONST_UINT64_T( PBA_PBOCR2_0x00064022 , ULL(0x00064022) ); +CONST_UINT64_T( PBA_PBOCR3_0x00064023 , ULL(0x00064023) ); +CONST_UINT64_T( PBA_PBOCR4_0x00064024 , ULL(0x00064024) ); +CONST_UINT64_T( PBA_PBOCR5_0x00064025 , ULL(0x00064025) ); + +CONST_UINT64_T( PBA_BAR0_0x02013F00 , ULL(0x02013F00) ); +CONST_UINT64_T( PBA_BARMSK0_0x02013F04 , ULL(0x02013F04) ); +CONST_UINT64_T( PBA_BAR1_0x02013F01 , ULL(0x02013F01) ); +CONST_UINT64_T( PBA_BARMSK1_0x02013F05 , ULL(0x02013F05) ); +CONST_UINT64_T( PBA_BAR2_0x02013F02 , ULL(0x02013F02) ); +CONST_UINT64_T( PBA_BARMSK2_0x02013F06 , ULL(0x02013F06) ); +CONST_UINT64_T( PBA_BAR3_0x02013F03 , ULL(0x02013F03) ); +CONST_UINT64_T( PBA_BARMSK3_0x02013F07 , ULL(0x02013F07) ); +CONST_UINT64_T( PBA_TRUSTMODE_0x02013F08 , ULL(0x02013F08) ); + +//------------------------------------------------------------------------------ +// PSI +//------------------------------------------------------------------------------ +CONST_UINT64_T( PSI_BRIDGE_BAR_0x0201090A , ULL(0x0201090A) ); +CONST_UINT64_T( PSI_FSP_BAR_0x0201090B , ULL(0x0201090B) ); +CONST_UINT64_T( PSI_FSP_MMR_0x0201090C , ULL(0x0201090C) ); +CONST_UINT64_T( PSI_BRIDGE_STATUS_CTL_0x0201090E , ULL(0x0201090E) ); + +//------------------------------------------------------------------------------ +// INTERRUPT CONTROL PRESENTER (ICP) +//------------------------------------------------------------------------------ +CONST_UINT64_T( ICP_BAR_0x020109CA , ULL(0x020109CA) ); +CONST_UINT64_T( ICP_INTR_INJECT_0x020109CC , ULL(0x020109CC) ); + + +//------------------------------------------------------------------------------ +// NEST PB EH +//------------------------------------------------------------------------------ +// registers with multiple physical/shadow copies (all must be configured consistently) +// west +CONST_UINT64_T( PB_MODE_WEST_0x02010C0A , ULL(0x02010C0A) ); +CONST_UINT64_T( PB_HP_MODE_NEXT_WEST_0x02010C0B , ULL(0x02010C0B) ); +CONST_UINT64_T( PB_HP_MODE_CURR_WEST_0x02010C0C , ULL(0x02010C0C) ); +CONST_UINT64_T( PB_HPX_MODE_NEXT_WEST_0x02010C0D , ULL(0x02010C0D) ); +CONST_UINT64_T( PB_HPX_MODE_CURR_WEST_0x02010C0E , ULL(0x02010C0E) ); +CONST_UINT64_T( PB_FLMCFG0_WEST_0x02010C12 , ULL(0x02010C12) ); +CONST_UINT64_T( PB_FLMCFG1_WEST_0x02010C13 , ULL(0x02010C13) ); +CONST_UINT64_T( PB_FRMCFG0_WEST_0x02010C14 , ULL(0x02010C14) ); +CONST_UINT64_T( PB_FRMCFG1_WEST_0x02010C15 , ULL(0x02010C15) ); +// center +CONST_UINT64_T( PB_MODE_CENT_0x02010C4A , ULL(0x02010C4A) ); +CONST_UINT64_T( PB_HP_MODE_NEXT_CENT_0x02010C4B , ULL(0x02010C4B) ); +CONST_UINT64_T( PB_HP_MODE_CURR_CENT_0x02010C4C , ULL(0x02010C4C) ); +CONST_UINT64_T( PB_HPX_MODE_NEXT_CENT_0x02010C4D , ULL(0x02010C4D) ); +CONST_UINT64_T( PB_HPX_MODE_CURR_CENT_0x02010C4E , ULL(0x02010C4E) ); +CONST_UINT64_T( PB_FLMCFG0_CENT_0x02010C5E , ULL(0x02010C5E) ); +CONST_UINT64_T( PB_FLMCFG1_CENT_0x02010C5F , ULL(0x02010C5F) ); +CONST_UINT64_T( PB_FRMCFG0_CENT_0x02010C60 , ULL(0x02010C60) ); +CONST_UINT64_T( PB_FRMCFG1_CENT_0x02010C61 , ULL(0x02010C61) ); +// east +CONST_UINT64_T( PB_MODE_EAST_0x02010C8A , ULL(0x02010C8A) ); +CONST_UINT64_T( PB_HP_MODE_NEXT_EAST_0x02010C8B , ULL(0x02010C8B) ); +CONST_UINT64_T( PB_HP_MODE_CURR_EAST_0x02010C8C , ULL(0x02010C8C) ); +CONST_UINT64_T( PB_HPX_MODE_NEXT_EAST_0x02010C8D , ULL(0x02010C8D) ); +CONST_UINT64_T( PB_HPX_MODE_CURR_EAST_0x02010C8E , ULL(0x02010C8E) ); +CONST_UINT64_T( PB_FLMCFG0_EAST_0x02010C92 , ULL(0x02010C92) ); +CONST_UINT64_T( PB_FLMCFG1_EAST_0x02010C93 , ULL(0x02010C93) ); +CONST_UINT64_T( PB_FRMCFG0_EAST_0x02010C94 , ULL(0x02010C94) ); +CONST_UINT64_T( PB_FRMCFG1_EAST_0x02010C95 , ULL(0x02010C95) ); + +// registers without shadow copies +// center +CONST_UINT64_T( PB_PMU_0x02010C4F , ULL(0x02010C4F) ); +CONST_UINT64_T( PB_NMPM_COUNT_0x02010C50 , ULL(0x02010C50) ); +CONST_UINT64_T( PB_LMPM_COUNT_0x02010C51 , ULL(0x02010C51) ); +CONST_UINT64_T( PB_RCMD_INTDAT_COUNT_0x02010C52 , ULL(0x02010C52) ); +CONST_UINT64_T( PB_EXTDAT_COUNT_0x02010C53 , ULL(0x02010C53) ); +CONST_UINT64_T( PB_PMU_COUNT0_0x02010C54 , ULL(0x02010C54) ); +CONST_UINT64_T( PB_PMU_COUNT1_0x02010C55 , ULL(0x02010C55) ); +CONST_UINT64_T( PB_PMU_COUNT2_0x02010C56 , ULL(0x02010C56) ); +CONST_UINT64_T( PB_PMU_COUNT3_0x02010C57 , ULL(0x02010C57) ); +CONST_UINT64_T( PB_RGMCFG00_0x02010C58 , ULL(0x02010C58) ); +CONST_UINT64_T( PB_RGMCFG01_0x02010C59 , ULL(0x02010C59) ); +CONST_UINT64_T( PB_RGMCFG10_0x02010C5A , ULL(0x02010C5A) ); +CONST_UINT64_T( PB_RGMCFGM00_0x02010C5B , ULL(0x02010C5B) ); +CONST_UINT64_T( PB_RGMCFGM01_0x02010C5C , ULL(0x02010C5C) ); +CONST_UINT64_T( PB_RGMCFGM10_0x02010C5D , ULL(0x02010C5D) ); +CONST_UINT64_T( PB_GP_CMD_RATE_DP0_0x02010C62 , ULL(0x02010C62) ); +CONST_UINT64_T( PB_GP_CMD_RATE_DP1_0x02010C63 , ULL(0x02010C63) ); +CONST_UINT64_T( PB_RGP_CMD_RATE_DP0_0x02010C64 , ULL(0x02010C64) ); +CONST_UINT64_T( PB_RGP_CMD_RATE_DP1_0x02010C65 , ULL(0x02010C65) ); +CONST_UINT64_T( PB_SP_CMD_RATE_DP0_0x02010C66 , ULL(0x02010C66) ); +CONST_UINT64_T( PB_SP_CMD_RATE_DP1_0x02010C67 , ULL(0x02010C67) ); +CONST_UINT64_T( PB_EVENT_TRACE_0x02010C68 , ULL(0x02010C68) ); +CONST_UINT64_T( PB_EVENT_COMPA_0x02010C69 , ULL(0x02010C69) ); +CONST_UINT64_T( PB_EVENT_COMPB_0x02010C6A , ULL(0x02010C6A) ); +CONST_UINT64_T( PB_CR_ERROR_0x02010C6B , ULL(0x02010C6B) ); + +//------------------------------------------------------------------------------ +// NEST PB EH FIR +//------------------------------------------------------------------------------ +// west FIR +CONST_UINT64_T( PB_FIR_WEST_0x02010C00 , ULL(0x02010C00) ); +CONST_UINT64_T( PB_FIR_AND_WEST_0x02010C01 , ULL(0x02010C01) ); +CONST_UINT64_T( PB_FIR_OR_WEST_0x02010C02 , ULL(0x02010C02) ); +CONST_UINT64_T( PB_FIR_MASK_WEST_0x02010C03 , ULL(0x02010C03) ); +CONST_UINT64_T( PB_FIR_MASK_AND_WEST_0x02010C04 , ULL(0x02010C04) ); +CONST_UINT64_T( PB_FIR_MASK_OR_WEST_0x02010C05 , ULL(0x02010C05) ); +CONST_UINT64_T( PB_FIR_ACTION0_WEST_0x02010C06 , ULL(0x02010C06) ); +CONST_UINT64_T( PB_FIR_ACTION1_WEST_0x02010C07 , ULL(0x02010C07) ); +// center FIR +CONST_UINT64_T( PB_FIR_CENT_0x02010C40 , ULL(0x02010C40) ); +CONST_UINT64_T( PB_FIR_AND_CENT_0x02010C41 , ULL(0x02010C41) ); +CONST_UINT64_T( PB_FIR_OR_CENT_0x02010C42 , ULL(0x02010C42) ); +CONST_UINT64_T( PB_FIR_MASK_CENT_0x02010C43 , ULL(0x02010C43) ); +CONST_UINT64_T( PB_FIR_MASK_AND_CENT_0x02010C44 , ULL(0x02010C44) ); +CONST_UINT64_T( PB_FIR_MASK_OR_CENT_0x02010C45 , ULL(0x02010C45) ); +CONST_UINT64_T( PB_FIR_ACTION0_CENT_0x02010C46 , ULL(0x02010C46) ); +CONST_UINT64_T( PB_FIR_ACTION1_CENT_0x02010C47 , ULL(0x02010C47) ); +// east FIR +CONST_UINT64_T( PB_FIR_EAST_0x02010C80 , ULL(0x02010C80) ); +CONST_UINT64_T( PB_FIR_AND_EAST_0x02010C81 , ULL(0x02010C81) ); +CONST_UINT64_T( PB_FIR_OR_EAST_0x02010C82 , ULL(0x02010C82) ); +CONST_UINT64_T( PB_FIR_MASK_EAST_0x02010C83 , ULL(0x02010C83) ); +CONST_UINT64_T( PB_FIR_MASK_AND_EAST_0x02010C84 , ULL(0x02010C84) ); +CONST_UINT64_T( PB_FIR_MASK_OR_EAST_0x02010C85 , ULL(0x02010C85) ); +CONST_UINT64_T( PB_FIR_ACTION0_EAST_0x02010C86 , ULL(0x02010C86) ); +CONST_UINT64_T( PB_FIR_ACTION1_EAST_0x02010C87 , ULL(0x02010C87) ); +// RAS FIR +CONST_UINT64_T( PB_RAS_FIR_0x02010C6C , ULL(0x02010C6C) ); +CONST_UINT64_T( PB_RAS_FIR_AND_0x02010C6D , ULL(0x02010C6D) ); +CONST_UINT64_T( PB_RAS_FIR_OR_0x02010C6E , ULL(0x02010C6E) ); +CONST_UINT64_T( PB_RAS_FIR_MASK_0x02010C6F , ULL(0x02010C6F) ); +CONST_UINT64_T( PB_RAS_FIR_MASK_AND_0x02010C70 , ULL(0x02010C70) ); +CONST_UINT64_T( PB_RAS_FIR_MASK_OR_0x02010C71 , ULL(0x02010C71) ); +CONST_UINT64_T( PB_RAS_FIR_ACTION0_0x02010C72 , ULL(0x02010C72) ); +CONST_UINT64_T( PB_RAS_FIR_ACTION1_0x02010C73 , ULL(0x02010C73) ); + +//------------------------------------------------------------------------------ +// MCS +//------------------------------------------------------------------------------ +CONST_UINT64_T( MCS_MCFGP_0x02011800 , ULL(0x02011800) ); + +CONST_UINT64_T( MCS_MCIFIR_0x02011840 , ULL(0x02011840) ); +CONST_UINT64_T( MCS_MCIFIR_AND_0x02011841 , ULL(0x02011841) ); +CONST_UINT64_T( MCS_MCIFIR_OR_0x02011842 , ULL(0x02011842) ); +CONST_UINT64_T( MCS_MCIFIRMASK_0x02011843 , ULL(0x02011843) ); +CONST_UINT64_T( MCS_MCIFIRMASK_AND_0x02011844 , ULL(0x02011844) ); +CONST_UINT64_T( MCS_MCIFIRMASK_OR_0x02011845 , ULL(0x02011845) ); + +CONST_UINT64_T( MCS_MCICFG_0x0201184A , ULL(0x0201184A) ); +CONST_UINT64_T( MCS_MCISTAT_0x0201184B , ULL(0x0201184B) ); + +//------------------------------------------------------------------------------ +// NEST Alter-Diplay Unit (ADU) +//------------------------------------------------------------------------------ +CONST_UINT64_T( ADU_CONTROL_0x02020000 , ULL(0x02020000) ); +CONST_UINT64_T( ADU_COMMAND_0x02020001 , ULL(0x02020001) ); +CONST_UINT64_T( ADU_STATUS_0x02020002 , ULL(0x02020002) ); +CONST_UINT64_T( ADU_DATA_0x02020003 , ULL(0x02020003) ); +CONST_UINT64_T( ADU_XSCOM_BASE_0x02020005 , ULL(0x02020005) ); +CONST_UINT64_T( ADU_FORCE_ECC_0x02020010 , ULL(0x02020010) ); +CONST_UINT64_T( ADU_PMISC_MODE_0x0202000B , ULL(0x0202000B) ); +CONST_UINT64_T( ADU_UNTRUSTED_BAR_0x02020015 , ULL(0x02020015) ); +CONST_UINT64_T( ADU_UNTRUSTED_BAR_MASK_0x02020016 , ULL(0x02020016) ); + +//------------------------------------------------------------------------------ +// PCIe +//------------------------------------------------------------------------------ +CONST_UINT64_T( PCIE0_NODAL_BAR0_0x02012010 , ULL(0x02012010) ); +CONST_UINT64_T( PCIE0_NODAL_BAR1_0x02012011 , ULL(0x02012011) ); +CONST_UINT64_T( PCIE0_GROUP_BAR0_0x02012012 , ULL(0x02012012) ); +CONST_UINT64_T( PCIE0_GROUP_BAR1_0x02012013 , ULL(0x02012013) ); +CONST_UINT64_T( PCIE0_NEAR_BAR_F0_0x02012014 , ULL(0x02012014) ); +CONST_UINT64_T( PCIE0_FAR_BAR_F0_0x02012015 , ULL(0x02012015) ); +CONST_UINT64_T( PCIE0_NEAR_BAR_F1_0x02012016 , ULL(0x02012016) ); +CONST_UINT64_T( PCIE0_FAR_BAR_F1_0x02012017 , ULL(0x02012017) ); +CONST_UINT64_T( PCIE0_IO_BAR0_0x02012040 , ULL(0x02012040) ); +CONST_UINT64_T( PCIE0_IO_BAR1_0x02012041 , ULL(0x02012041) ); +CONST_UINT64_T( PCIE0_IO_BAR2_0x02012042 , ULL(0x02012042) ); +CONST_UINT64_T( PCIE0_IO_MASK0_0x02012043 , ULL(0x02012043) ); +CONST_UINT64_T( PCIE0_IO_MASK1_0x02012044 , ULL(0x02012044) ); +CONST_UINT64_T( PCIE0_IO_BAR_EN_0x02012045 , ULL(0x02012045) ); + +CONST_UINT64_T( PCIE1_NODAL_BAR0_0x02012410 , ULL(0x02012410) ); +CONST_UINT64_T( PCIE1_NODAL_BAR1_0x02012411 , ULL(0x02012411) ); +CONST_UINT64_T( PCIE1_GROUP_BAR0_0x02012412 , ULL(0x02012412) ); +CONST_UINT64_T( PCIE1_GROUP_BAR1_0x02012413 , ULL(0x02012413) ); +CONST_UINT64_T( PCIE1_NEAR_BAR_F0_0x02012414 , ULL(0x02012414) ); +CONST_UINT64_T( PCIE1_FAR_BAR_F0_0x02012415 , ULL(0x02012415) ); +CONST_UINT64_T( PCIE1_NEAR_BAR_F1_0x02012416 , ULL(0x02012416) ); +CONST_UINT64_T( PCIE1_FAR_BAR_F1_0x02012417 , ULL(0x02012417) ); +CONST_UINT64_T( PCIE1_IO_BAR0_0x02012440 , ULL(0x02012440) ); +CONST_UINT64_T( PCIE1_IO_BAR1_0x02012441 , ULL(0x02012441) ); +CONST_UINT64_T( PCIE1_IO_BAR2_0x02012442 , ULL(0x02012442) ); +CONST_UINT64_T( PCIE1_IO_MASK0_0x02012443 , ULL(0x02012443) ); +CONST_UINT64_T( PCIE1_IO_MASK1_0x02012444 , ULL(0x02012444) ); +CONST_UINT64_T( PCIE1_IO_BAR_EN_0x02012445 , ULL(0x02012445) ); + +CONST_UINT64_T( PCIE2_NODAL_BAR0_0x02012810 , ULL(0x02012810) ); +CONST_UINT64_T( PCIE2_NODAL_BAR1_0x02012811 , ULL(0x02012811) ); +CONST_UINT64_T( PCIE2_GROUP_BAR0_0x02012812 , ULL(0x02012812) ); +CONST_UINT64_T( PCIE2_GROUP_BAR1_0x02012813 , ULL(0x02012813) ); +CONST_UINT64_T( PCIE2_NEAR_BAR_F0_0x02012814 , ULL(0x02012814) ); +CONST_UINT64_T( PCIE2_FAR_BAR_F0_0x02012815 , ULL(0x02012815) ); +CONST_UINT64_T( PCIE2_NEAR_BAR_F1_0x02012816 , ULL(0x02012816) ); +CONST_UINT64_T( PCIE2_FAR_BAR_F1_0x02012817 , ULL(0x02012817) ); +CONST_UINT64_T( PCIE2_IO_BAR0_0x02012840 , ULL(0x02012840) ); +CONST_UINT64_T( PCIE2_IO_BAR1_0x02012841 , ULL(0x02012841) ); +CONST_UINT64_T( PCIE2_IO_BAR2_0x02012842 , ULL(0x02012842) ); +CONST_UINT64_T( PCIE2_IO_MASK0_0x02012843 , ULL(0x02012843) ); +CONST_UINT64_T( PCIE2_IO_MASK1_0x02012844 , ULL(0x02012844) ); +CONST_UINT64_T( PCIE2_IO_BAR_EN_0x02012845 , ULL(0x02012845) ); + +//------------------------------------------------------------------------------ +// NX +//------------------------------------------------------------------------------ +CONST_UINT64_T( NX_APC_NODAL_BAR0_0x0201302D , ULL(0x0201302D) ); +CONST_UINT64_T( NX_APC_NODAL_BAR1_0x0201302E , ULL(0x0201302E) ); +CONST_UINT64_T( NX_APC_GROUP_BAR0_0x0201302F , ULL(0x0201302F) ); +CONST_UINT64_T( NX_APC_GROUP_BAR1_0x02013030 , ULL(0x02013030) ); +CONST_UINT64_T( NX_APC_NEAR_BAR_F0_0x02013031 , ULL(0x02013031) ); +CONST_UINT64_T( NX_APC_FAR_BAR_F0_0x02013032 , ULL(0x02013032) ); +CONST_UINT64_T( NX_APC_NEAR_BAR_F1_0x02013033 , ULL(0x02013033) ); +CONST_UINT64_T( NX_APC_FAR_BAR_F1_0x02013034 , ULL(0x02013034) ); +CONST_UINT64_T( NX_MMIO_BAR_0x0201308D , ULL(0x0201308D) ); +CONST_UINT64_T( NX_NODAL_BAR0_0x02013095 , ULL(0x02013095) ); +CONST_UINT64_T( NX_NODAL_BAR1_0x02013096 , ULL(0x02013096) ); +CONST_UINT64_T( NX_GROUP_BAR0_0x02013097 , ULL(0x02013097) ); +CONST_UINT64_T( NX_GROUP_BAR1_0x02013098 , ULL(0x02013098) ); +CONST_UINT64_T( NX_NEAR_BAR_F0_0x02013099 , ULL(0x02013099) ); +CONST_UINT64_T( NX_FAR_BAR_F0_0x0201309A , ULL(0x0201309A) ); +CONST_UINT64_T( NX_NEAR_BAR_F1_0x0201309B , ULL(0x0201309B) ); +CONST_UINT64_T( NX_FAR_BAR_F1_0x0201309C , ULL(0x0201309C) ); + +//------------------------------------------------------------------------------ +// MCD +//------------------------------------------------------------------------------ +CONST_UINT64_T( MCD_CN00_0x0201340C , ULL(0x0201340C) ); +CONST_UINT64_T( MCD_CN01_0x0201340D , ULL(0x0201340D) ); +CONST_UINT64_T( MCD_CN10_0x0201340E , ULL(0x0201340E) ); +CONST_UINT64_T( MCD_CN11_0x0201340F , ULL(0x0201340F) ); + + +/******************************************************************************/ +/****************************** X-BUS CHIPLET *******************************/ +/******************************************************************************/ + +//------------------------------------------------------------------------------ +// X-BUS GPIO +//------------------------------------------------------------------------------ +CONST_UINT64_T( X_GP0_0x04000000 , ULL(0x04000000) ); +CONST_UINT64_T( X_GP1_0x04000001 , ULL(0x04000001) ); +CONST_UINT64_T( X_GP2_0x04000002 , ULL(0x04000002) ); + +//------------------------------------------------------------------------------ +// X-BUS SCOM +// ring 1 = Trace 0 +// ring 2 = Trace 1 +// ring 3 = PBEN +// ring 4 = IOX0 +// ring 5 = IOX1 +// ring 6 = IOX3 +// ring 7 = IOX2 +// ring 9 = IOPSI +//------------------------------------------------------------------------------ +CONST_UINT64_T( X_SCOM_0x04010000 , ULL(0x04010000) ); + +//------------------------------------------------------------------------------ +// X-BUS TRACE +//------------------------------------------------------------------------------ +CONST_UINT64_T( X_TRACE_DATA_HI_T0_0x04010440 , ULL(0x04010440) ); +CONST_UINT64_T( X_TRACE_DATA_LO_T0_0x04010441 , ULL(0x04010441) ); +CONST_UINT64_T( X_TRACE_DATA_HI_T1_0x04010880 , ULL(0x04010880) ); +CONST_UINT64_T( X_TRACE_DATA_LO_T1_0x04010881 , ULL(0x04010881) ); + +//------------------------------------------------------------------------------ +// X-BUS CLOCK CONTROL +//------------------------------------------------------------------------------ +CONST_UINT64_T( X_OPCG_CNTL0_0x04030002 , ULL(0x04030002) ); +CONST_UINT64_T( X_OPCG_CNTL1_0x04030003 , ULL(0x04030003) ); +CONST_UINT64_T( X_OPCG_CNTL2_0x04030004 , ULL(0x04030004) ); +CONST_UINT64_T( X_OPCG_CNTL3_0x04030005 , ULL(0x04030005) ); +CONST_UINT64_T( X_CLK_REGION_0x04030006 , ULL(0x04030006) ); +CONST_UINT64_T( X_CLK_SCANSEL_0x04030007 , ULL(0x04030007) ); +CONST_UINT64_T( X_CLK_STATUS_0x04030008 , ULL(0x04030008) ); + +//------------------------------------------------------------------------------ +// X-BUS FIR +//------------------------------------------------------------------------------ +CONST_UINT64_T( X_XSTOP_0x04040000 , ULL(0x04040000) ); +CONST_UINT64_T( X_RECOV_0x04040001 , ULL(0x04040001) ); +CONST_UINT64_T( X_FIR_MASK_0x04040002 , ULL(0x04040002) ); +CONST_UINT64_T( X_SPATTN_0x04040004 , ULL(0x04040004) ); +CONST_UINT64_T( X_SPATTN_AND_0x04040005 , ULL(0x04040005) ); +CONST_UINT64_T( X_SPATTN_OR_0x04040006 , ULL(0x04040006) ); +CONST_UINT64_T( X_SPATTN_MASK_0x04040007 , ULL(0x04040007) ); +CONST_UINT64_T( X_FIR_MODE_0x04040008 , ULL(0x04040008) ); +CONST_UINT64_T( X_PERV_LFIR_0x0404000A , ULL(0x0404000A) ); +CONST_UINT64_T( X_PERV_LFIR_AND_0x0404000B , ULL(0x0404000B) ); +CONST_UINT64_T( X_PERV_LFIR_OR_0x0404000C , ULL(0x0404000C) ); +CONST_UINT64_T( X_PERV_LFIR_MASK_0x0404000D , ULL(0x0404000D) ); +CONST_UINT64_T( X_PERV_LFIR_MASK_AND_0x0404000E , ULL(0x0404000E) ); +CONST_UINT64_T( X_PERV_LFIR_MASK_OR_0x0404000F , ULL(0x0404000F) ); +CONST_UINT64_T( X_PERV_LFIR_ACT0_0x04040010 , ULL(0x04040010) ); +CONST_UINT64_T( X_PERV_LFIR_ACT1_0x04040011 , ULL(0x04040011) ); + +//------------------------------------------------------------------------------ +// X-BUS THERMAL +//------------------------------------------------------------------------------ +CONST_UINT64_T( X_THERM_0x04050000 , ULL(0x04050000) ); + +//------------------------------------------------------------------------------ +// X-BUS PCB SLAVE +//------------------------------------------------------------------------------ +//Multicast Group Registers +CONST_UINT64_T( X_MCGR1_0x040F0001 , ULL(0x040F0001) ); +CONST_UINT64_T( X_MCGR2_0x040F0002 , ULL(0x040F0002) ); +CONST_UINT64_T( X_MCGR3_0x040F0003 , ULL(0x040F0003) ); +CONST_UINT64_T( X_MCGR4_0x040F0004 , ULL(0x040F0004) ); +//GP0 Register +CONST_UINT64_T( X_GP0_AND_0x04000004 , ULL(0x04000004) ); +CONST_UINT64_T( X_GP0_OR_0x04000005 , ULL(0x04000005) ); +//GP3 Register +CONST_UINT64_T( X_GP3_0x040F0012 , ULL(0x040F0012) ); +CONST_UINT64_T( X_GP3_AND_0x040F0013 , ULL(0x040F0013) ); +CONST_UINT64_T( X_GP3_OR_0x040F0014 , ULL(0x040F0014) ); + +//------------------------------------------------------------------------------ +// X-BUS HANG DETECTION +//------------------------------------------------------------------------------ +CONST_UINT64_T( X_HANG_P0_XBUS_0x040F0020 , ULL(0x040F0020) ); // XBUS : setup hang pulse register0 +CONST_UINT64_T( X_HANG_PRE_XBUS_0x040F0028 , ULL(0x040F0028) ); // XBUS : setup hang precounter (HEX:01) + +//------------------------------------------------------------------------------ +// X-BUS PBEN +//------------------------------------------------------------------------------ +CONST_UINT64_T( X_PB_MODE_0x04010C0A , ULL(0x04010C0A) ); + + +/******************************************************************************/ +/****************************** A-BUS CHIPLET *******************************/ +/******************************************************************************/ +//------------------------------------------------------------------------------ +// A-BUS GPIO +//------------------------------------------------------------------------------ +CONST_UINT64_T( A_GP0_0x08000000 , ULL(0x08000000) ); +CONST_UINT64_T( A_GP1_0x08000001 , ULL(0x08000001) ); +CONST_UINT64_T( A_GP2_0x08000002 , ULL(0x08000002) ); + +//------------------------------------------------------------------------------ +// A-BUS SCOM +// ring 1 = trace +// ring 2 = PBES +// ring 3 = IOA +//------------------------------------------------------------------------------ +CONST_UINT64_T( A_SCOM_0x08010000 , ULL(0x08010000) ); + +//------------------------------------------------------------------------------ +// A-BUS TRACE +//------------------------------------------------------------------------------ +CONST_UINT64_T( A_TRACE_DATA_HI_0x08010440 , ULL(0x08010440) ); +CONST_UINT64_T( A_TRACE_DATA_LO_0x08010441 , ULL(0x08010441) ); + +//------------------------------------------------------------------------------ +// A-BUS CLOCK CONTROL +//------------------------------------------------------------------------------ +CONST_UINT64_T( A_OPCG_CNTL0_0x08030002 , ULL(0x08030002) ); +CONST_UINT64_T( A_OPCG_CNTL1_0x08030003 , ULL(0x08030003) ); +CONST_UINT64_T( A_OPCG_CNTL2_0x08030004 , ULL(0x08030004) ); +CONST_UINT64_T( A_OPCG_CNTL3_0x08030005 , ULL(0x08030005) ); +CONST_UINT64_T( A_CLK_REGION_0x08030006 , ULL(0x08030006) ); +CONST_UINT64_T( A_CLK_SCANSEL_0x08030007 , ULL(0x08030007) ); +CONST_UINT64_T( A_CLK_STATUS_0x08030008 , ULL(0x08030008) ); + +//------------------------------------------------------------------------------ +// A-BUS FIR +//------------------------------------------------------------------------------ +CONST_UINT64_T( A_XSTOP_0x08040000 , ULL(0x08040000) ); +CONST_UINT64_T( A_RECOV_0x08040001 , ULL(0x08040001) ); +CONST_UINT64_T( A_FIR_MASK_0x08040002 , ULL(0x08040002) ); +CONST_UINT64_T( A_SPATTN_0x08040004 , ULL(0x08040004) ); +CONST_UINT64_T( A_SPATTN_AND_0x08040005 , ULL(0x08040005) ); +CONST_UINT64_T( A_SPATTN_OR_0x08040006 , ULL(0x08040006) ); +CONST_UINT64_T( A_SPATTN_MASK_0x08040007 , ULL(0x08040007) ); +CONST_UINT64_T( A_FIR_MODE_0x08040008 , ULL(0x08040008) ); +CONST_UINT64_T( A_PERV_LFIR_0x0804000A , ULL(0x0804000A) ); +CONST_UINT64_T( A_PERV_LFIR_AND_0x0804000B , ULL(0x0804000B) ); +CONST_UINT64_T( A_PERV_LFIR_OR_0x0804000C , ULL(0x0804000C) ); +CONST_UINT64_T( A_PERV_LFIR_MASK_0x0804000D , ULL(0x0804000D) ); +CONST_UINT64_T( A_PERV_LFIR_MASK_AND_0x0804000E , ULL(0x0804000E) ); +CONST_UINT64_T( A_PERV_LFIR_MASK_OR_0x0804000F , ULL(0x0804000F) ); +CONST_UINT64_T( A_PERV_LFIR_ACT0_0x08040010 , ULL(0x08040010) ); +CONST_UINT64_T( A_PERV_LFIR_ACT1_0x08040011 , ULL(0x08040011) ); + +//------------------------------------------------------------------------------ +// A-BUS THERMAL +//------------------------------------------------------------------------------ +CONST_UINT64_T( A_THERM_0x08050000 , ULL(0x08050000) ); + +//------------------------------------------------------------------------------ +// A-BUS PCB SLAVE +//------------------------------------------------------------------------------ +//Multicast Group Registers +CONST_UINT64_T( A_MCGR1_0x080F0001 , ULL(0x080F0001) ); +CONST_UINT64_T( A_MCGR2_0x080F0002 , ULL(0x080F0002) ); +CONST_UINT64_T( A_MCGR3_0x080F0003 , ULL(0x080F0003) ); +CONST_UINT64_T( A_MCGR4_0x080F0004 , ULL(0x080F0004) ); +//GP0 Register +CONST_UINT64_T( A_GP0_AND_0x08000004 , ULL(0x08000004) ); +CONST_UINT64_T( A_GP0_OR_0x08000005 , ULL(0x08000005) ); +//GP3 Register +CONST_UINT64_T( A_GP3_0x080F0012 , ULL(0x080F0012) ); +CONST_UINT64_T( A_GP3_AND_0x080F0013 , ULL(0x080F0013) ); +CONST_UINT64_T( A_GP3_OR_0x080F0014 , ULL(0x080F0014) ); + +//------------------------------------------------------------------------------ +// A-BUS HANG DETECTION +//------------------------------------------------------------------------------ +CONST_UINT64_T( A_HANG_P0_0x080F0020 , ULL(0x080F0020) ); // ABUS : setup hang pulse register0 +CONST_UINT64_T( A_HANG_PRE_0x080F0028 , ULL(0x080F0028) ); // ABUS : setup hang precounter (HEX:01) + +//------------------------------------------------------------------------------ +// A-BUS PBES +//------------------------------------------------------------------------------ +CONST_UINT64_T( A_PB_MODE_0x0801080A , ULL(0x0801080A) ); + + +/******************************************************************************/ +/***************************** PCIE-BUS CHIPLET *****************************/ +/******************************************************************************/ +//------------------------------------------------------------------------------ +// PCIE-BUS GPIO +//------------------------------------------------------------------------------ +CONST_UINT64_T( PCIE_GP0_0x09000000 , ULL(0x09000000) ); +CONST_UINT64_T( PCIE_GP1_0x09000001 , ULL(0x09000001) ); +CONST_UINT64_T( PCIE_GP2_0x09000002 , ULL(0x09000002) ); + +CONST_UINT64_T( PCIE_GP0_AND_0x09000004 , ULL(0x09000004) ); +CONST_UINT64_T( PCIE_GP0_OR_0x09000005 , ULL(0x09000005) ); + +//------------------------------------------------------------------------------ +// PCIE-BUS SCOM +// ring 1 = trace +// ring 2 = PBF +// ring 5 = IOPCI0 +// ring 6 = IOPCI1 +// ring 7 = IOPCI2 +// ring 8 = PCI0 +// ring 9 = PCI1 +// ring 10 = PCI2 +// ring 11 = PCI3 +//------------------------------------------------------------------------------ +CONST_UINT64_T( PCIE_SCOM_0x09010000 , ULL(0x09010000) ); + +//------------------------------------------------------------------------------ +// PCIE-BUS TRACE +//------------------------------------------------------------------------------ +CONST_UINT64_T( PCIE_TRACE_DATA_HI_0x09010400 , ULL(0x09010400) ); +CONST_UINT64_T( PCIE_TRACE_DATA_LO_0x09010401 , ULL(0x09010401) ); + +//------------------------------------------------------------------------------ +// PCIE-BUS BARS +//------------------------------------------------------------------------------ +CONST_UINT64_T( PCIE0_ASB_BAR_0x0901200B , ULL(0x0901200B) ); +CONST_UINT64_T( PCIE1_ASB_BAR_0x0901240B , ULL(0x0901240B) ); +CONST_UINT64_T( PCIE2_ASB_BAR_0x0901280B , ULL(0x0901280B) ); + +//------------------------------------------------------------------------------ +// PCIE-BUS CLOCK CONTROL +//------------------------------------------------------------------------------ +CONST_UINT64_T( PCIE_OPCG_CNTL0_0x09030002 , ULL(0x09030002) ); +CONST_UINT64_T( PCIE_OPCG_CNTL1_0x09030003 , ULL(0x09030003) ); +CONST_UINT64_T( PCIE_OPCG_CNTL2_0x09030004 , ULL(0x09030004) ); +CONST_UINT64_T( PCIE_OPCG_CNTL3_0x09030005 , ULL(0x09030005) ); +CONST_UINT64_T( PCIE_CLK_REGION_0x09030006 , ULL(0x09030006) ); +CONST_UINT64_T( PCIE_CLK_SCANSEL_0x09030007 , ULL(0x09030007) ); +CONST_UINT64_T( PCIE_CLK_STATUS_0x09030008 , ULL(0x09030008) ); + +//------------------------------------------------------------------------------ +// PCIE-BUS FIR +//------------------------------------------------------------------------------ +CONST_UINT64_T( PCIE_XSTOP_0x09040000 , ULL(0x09040000) ); +CONST_UINT64_T( PCIE_RECOV_0x09040001 , ULL(0x09040001) ); +CONST_UINT64_T( PCIE_FIR_MASK_0x09040002 , ULL(0x09040002) ); +CONST_UINT64_T( PCIE_SPATTN_0x09040004 , ULL(0x09040004) ); +CONST_UINT64_T( PCIE_SPATTN_AND_0x09040005 , ULL(0x09040005) ); +CONST_UINT64_T( PCIE_SPATTN_OR_0x09040006 , ULL(0x09040006) ); +CONST_UINT64_T( PCIE_SPATTN_MASK_0x09040007 , ULL(0x09040007) ); +CONST_UINT64_T( PCIE_FIR_MODE_0x09040008 , ULL(0x09040008) ); +CONST_UINT64_T( PCIE_PERV_LFIR_0x0904000A , ULL(0x0904000A) ); +CONST_UINT64_T( PCIE_PERV_LFIR_AND_0x0904000B , ULL(0x0904000B) ); +CONST_UINT64_T( PCIE_PERV_LFIR_OR_0x0904000C , ULL(0x0904000C) ); +CONST_UINT64_T( PCIE_PERV_LFIR_MASK_0x0904000D , ULL(0x0904000D) ); +CONST_UINT64_T( PCIE_PERV_LFIR_MASK_AND_0x0904000E , ULL(0x0904000E) ); +CONST_UINT64_T( PCIE_PERV_LFIR_MASK_OR_0x0904000F , ULL(0x0904000F) ); +CONST_UINT64_T( PCIE_PERV_LFIR_ACT0_0x09040010 , ULL(0x09040010) ); +CONST_UINT64_T( PCIE_PERV_LFIR_ACT1_0x09040011 , ULL(0x09040011) ); + +//------------------------------------------------------------------------------ +// PCIE-BUS THERMAL +//------------------------------------------------------------------------------ +CONST_UINT64_T( PCIE_THERM_0x09050000 , ULL(0x09050000) ); + +//------------------------------------------------------------------------------ +// PCIE-BUS PCB SLAVE +//------------------------------------------------------------------------------ +//Multicast Group Registers +CONST_UINT64_T( PCIE_MCGR1_0x090F0001 , ULL(0x090F0001) ); +CONST_UINT64_T( PCIE_MCGR2_0x090F0002 , ULL(0x090F0002) ); +CONST_UINT64_T( PCIE_MCGR3_0x090F0003 , ULL(0x090F0003) ); +CONST_UINT64_T( PCIE_MCGR4_0x090F0004 , ULL(0x090F0004) ); +//GP3 Register +CONST_UINT64_T( PCIE_GP3_0x090F0012 , ULL(0x090F0012) ); +CONST_UINT64_T( PCIE_GP3_AND_0x090F0013 , ULL(0x090F0013) ); +CONST_UINT64_T( PCIE_GP3_OR_0x090F0014 , ULL(0x090F0014) ); + +//------------------------------------------------------------------------------ +// PCIE-BUS HANG DETECTION +//------------------------------------------------------------------------------ +CONST_UINT64_T( PCIE_HANG_PRE_0x090F0028 , ULL(0x090F0028) ); // PCIE : setup hang precounter (HEX:01) + + +/******************************************************************************/ +/******************************** EX CHIPLET ********************************/ +/******************************************************************************/ +// Note: ECMD will require the use of these addresses, and it will update them +// under the covers to point to the actual EX chiplet in question. +// +// Example: getscom pu.ex 10000001 -c3 ---> scom address 0x13000001 + +//------------------------------------------------------------------------------ +// EX CHIPLET ID +// use for lpcs P0, <chipletID> +//------------------------------------------------------------------------------ +CONST_UINT64_T( EX00_CHIPLET_0x10000000 , ULL(0x10000000) ); +CONST_UINT64_T( EX01_CHIPLET_0x11000000 , ULL(0x11000000) ); +CONST_UINT64_T( EX02_CHIPLET_0x12000000 , ULL(0x12000000) ); +CONST_UINT64_T( EX03_CHIPLET_0x13000000 , ULL(0x13000000) ); +CONST_UINT64_T( EX04_CHIPLET_0x14000000 , ULL(0x14000000) ); +CONST_UINT64_T( EX05_CHIPLET_0x15000000 , ULL(0x15000000) ); +CONST_UINT64_T( EX06_CHIPLET_0x16000000 , ULL(0x16000000) ); +CONST_UINT64_T( EX07_CHIPLET_0x17000000 , ULL(0x17000000) ); +CONST_UINT64_T( EX08_CHIPLET_0x18000000 , ULL(0x18000000) ); +CONST_UINT64_T( EX09_CHIPLET_0x19000000 , ULL(0x19000000) ); +CONST_UINT64_T( EX10_CHIPLET_0x1A000000 , ULL(0x1A000000) ); +CONST_UINT64_T( EX11_CHIPLET_0x1B000000 , ULL(0x1B000000) ); +CONST_UINT64_T( EX12_CHIPLET_0x1C000000 , ULL(0x1C000000) ); +CONST_UINT64_T( EX13_CHIPLET_0x1D000000 , ULL(0x1D000000) ); +CONST_UINT64_T( EX14_CHIPLET_0x1E000000 , ULL(0x1E000000) ); +CONST_UINT64_T( EX15_CHIPLET_0x1F000000 , ULL(0x1F000000) ); + +//------------------------------------------------------------------------------ +// EX GPIO +//------------------------------------------------------------------------------ +CONST_UINT64_T( EX_GP0_0x10000000 , ULL(0x10000000) ); +CONST_UINT64_T( EX_GP0_AND_0x10000004 , ULL(0x10000004) ); +CONST_UINT64_T( EX_GP0_OR_0x10000005 , ULL(0x10000005) ); +CONST_UINT64_T( EX_GP1_0x10000001 , ULL(0x10000001) ); +CONST_UINT64_T( EX_GP2_0x10000002 , ULL(0x10000002) ); + +//------------------------------------------------------------------------------ +// EX SCOM +// ring 1 = ECO trace +// ring 2 = L3 +// ring 3 = NC +// ring 4 = HTM +// ring 8 = L2 trace 0 +// ring 9 = L2 trace 1 +// ring 10 = L2 +// ring 11 = PC trace +// ring 12 = PC +// ring 15 = PC sec +//------------------------------------------------------------------------------ +//L3 +CONST_UINT64_T( EX_L3_MODE_REG1_0x1001080A , ULL(0x1001080A) ); +CONST_UINT64_T( EX_L3_MODE_REG0_0x1001082B , ULL(0x1001082B) ); +//L2 +CONST_UINT64_T( EX_L2_FIR_REG_0x10012800 , ULL(0x10012800) ); +CONST_UINT64_T( EX_L2_CERRS_REG0_0x10012815 , ULL(0x10012815) ); +CONST_UINT64_T( EX_L2_CERRS_REG1_0x10012816 , ULL(0x10012816) ); +CONST_UINT64_T( EX_L2_MODE_REG0_0x1001280A , ULL(0x1001280A) ); +CONST_UINT64_T( EX_L2_PURGE_CMD_PRD_0x1001280E , ULL(0x1001280E) ); +CONST_UINT64_T( EX_L2_PURGE_CMD_PHYP_0x1001280F , ULL(0x1001280F) ); + +//------------------------------------------------------------------------------ +// EX/CORE TRACE +//------------------------------------------------------------------------------ +CONST_UINT64_T( EX_TRACE_DATA_HI_ECO_0x10010400 , ULL(0x10010400) ); +CONST_UINT64_T( EX_TRACE_DATA_LO_ECO_0x10010401 , ULL(0x10010401) ); +CONST_UINT64_T( EX_TRACE_DATA_HI_L2_T0_0x10012000 , ULL(0x10012000) ); +CONST_UINT64_T( EX_TRACE_DATA_LO_L2_T0_0x10012001 , ULL(0x10012001) ); +CONST_UINT64_T( EX_TRACE_DATA_HI_L2_T1_0x10012400 , ULL(0x10012400) ); +CONST_UINT64_T( EX_TRACE_DATA_LO_L2_T1_0x10012401 , ULL(0x10012401) ); +CONST_UINT64_T( EX_TRACE_DATA_HI_CORE_T0_0x10012C00 , ULL(0x10012C00) ); +CONST_UINT64_T( EX_TRACE_DATA_LO_CORE_T0_0x10012C01 , ULL(0x10012C01) ); +CONST_UINT64_T( EX_TRACE_DATA_HI_CORE_T1_0x10012C40 , ULL(0x10012C40) ); +CONST_UINT64_T( EX_TRACE_DATA_LO_CORE_T1_0x10012C41 , ULL(0x10012C41) ); +CONST_UINT64_T( EX_TRACE_DATA_HI_CORE_T2_0x10012C80 , ULL(0x10012C80) ); +CONST_UINT64_T( EX_TRACE_DATA_LO_CORE_T2_0x10012C81 , ULL(0x10012C81) ); +CONST_UINT64_T( EX_TRACE_DATA_HI_CORE_T3_0x10012CC0 , ULL(0x10012CC0) ); +CONST_UINT64_T( EX_TRACE_DATA_LO_CORE_T3_0x10012CC1 , ULL(0x10012CC1) ); +CONST_UINT64_T( EX_TRACE_DATA_HI_CORE_T4_0x10012D00 , ULL(0x10012D00) ); +CONST_UINT64_T( EX_TRACE_DATA_LO_CORE_T4_0x10012D01 , ULL(0x10012D01) ); +CONST_UINT64_T( EX_TRACE_DATA_HI_CORE_T5_0x10012D40 , ULL(0x10012D40) ); +CONST_UINT64_T( EX_TRACE_DATA_LO_CORE_T5_0x10012D41 , ULL(0x10012D41) ); + + +//------------------------------------------------------------------------------ +// EX/CORE PERVASIVE THREAD CONTROLS +// (chiplet/core set by P0 register) +//------------------------------------------------------------------------------ +// TCTL Direct Controls (for each thread) +CONST_UINT64_T( EX_PERV_TCTL0_DIRECT_0x10013000 , ULL(0x10013000) ); +CONST_UINT64_T( EX_PERV_TCTL1_DIRECT_0x10013010 , ULL(0x10013010) ); +CONST_UINT64_T( EX_PERV_TCTL2_DIRECT_0x10013020 , ULL(0x10013020) ); +CONST_UINT64_T( EX_PERV_TCTL3_DIRECT_0x10013030 , ULL(0x10013030) ); +CONST_UINT64_T( EX_PERV_TCTL4_DIRECT_0x10013040 , ULL(0x10013040) ); +CONST_UINT64_T( EX_PERV_TCTL5_DIRECT_0x10013050 , ULL(0x10013050) ); +CONST_UINT64_T( EX_PERV_TCTL6_DIRECT_0x10013060 , ULL(0x10013060) ); +CONST_UINT64_T( EX_PERV_TCTL7_DIRECT_0x10013070 , ULL(0x10013070) ); + +// TCTL RAS Mode (for each thread) +CONST_UINT64_T( EX_PERV_TCTL0_R_MODE_0x10013001 , ULL(0x10013001) ); +CONST_UINT64_T( EX_PERV_TCTL1_R_MODE_0x10013011 , ULL(0x10013011) ); +CONST_UINT64_T( EX_PERV_TCTL2_R_MODE_0x10013021 , ULL(0x10013021) ); +CONST_UINT64_T( EX_PERV_TCTL3_R_MODE_0x10013031 , ULL(0x10013031) ); +CONST_UINT64_T( EX_PERV_TCTL4_R_MODE_0x10013041 , ULL(0x10013041) ); +CONST_UINT64_T( EX_PERV_TCTL5_R_MODE_0x10013051 , ULL(0x10013051) ); +CONST_UINT64_T( EX_PERV_TCTL6_R_MODE_0x10013061 , ULL(0x10013061) ); +CONST_UINT64_T( EX_PERV_TCTL7_R_MODE_0x10013071 , ULL(0x10013071) ); + +// TCTL RAS Status (for each thread) +CONST_UINT64_T( EX_PERV_TCTL0_R_STAT_0x10013002 , ULL(0x10013002) ); +CONST_UINT64_T( EX_PERV_TCTL1_R_STAT_0x10013012 , ULL(0x10013012) ); +CONST_UINT64_T( EX_PERV_TCTL2_R_STAT_0x10013022 , ULL(0x10013022) ); +CONST_UINT64_T( EX_PERV_TCTL3_R_STAT_0x10013032 , ULL(0x10013032) ); +CONST_UINT64_T( EX_PERV_TCTL4_R_STAT_0x10013042 , ULL(0x10013042) ); +CONST_UINT64_T( EX_PERV_TCTL5_R_STAT_0x10013052 , ULL(0x10013052) ); +CONST_UINT64_T( EX_PERV_TCTL6_R_STAT_0x10013062 , ULL(0x10013062) ); +CONST_UINT64_T( EX_PERV_TCTL7_R_STAT_0x10013072 , ULL(0x10013072) ); + +// Thread Active Status +CONST_UINT64_T( EX_PERV_THREAD_ACTIVE_0x1001310E , ULL(0x1001310E) ); + +// RAM Registers +CONST_UINT64_T( EX_PERV_RAM_MODE_0x10013C00 , ULL(0x10013C00) ); +CONST_UINT64_T( EX_PERV_RAM_CTRL_0x10013C01 , ULL(0x10013C01) ); +CONST_UINT64_T( EX_PERV_RAM_STAT_0x10013C02 , ULL(0x10013C02) ); + +// SPRC/SPRD/Scratch +CONST_UINT64_T( EX_PERV_L0_SCOM_SPRC_10013280 , ULL(0x10013280) ); +CONST_UINT64_T( EX_PERV_SPR_MODE_10013281 , ULL(0x10013281) ); +CONST_UINT64_T( EX_PERV_SCRATCH0_10013283 , ULL(0x10013283) ); +CONST_UINT64_T( EX_PERV_SCRATCH1_10013284 , ULL(0x10013284) ); +CONST_UINT64_T( EX_PERV_SCRATCH2_10013285 , ULL(0x10013285) ); +CONST_UINT64_T( EX_PERV_SCRATCH3_10013286 , ULL(0x10013286) ); +CONST_UINT64_T( EX_PERV_SCRATCH4_10013287 , ULL(0x10013287) ); +CONST_UINT64_T( EX_PERV_SCRATCH5_10013288 , ULL(0x10013288) ); +CONST_UINT64_T( EX_PERV_SCRATCH6_10013289 , ULL(0x10013289) ); +CONST_UINT64_T( EX_PERV_SCRATCH7_1001328A , ULL(0x1001328A) ); + +//------------------------------------------------------------------------------ +// EX OHA +//------------------------------------------------------------------------------ +CONST_UINT64_T( EX_SCOM_0x10020000 , ULL(0x10020000) ); +CONST_UINT64_T( EX_OHA_ACTIVITY_SAMPLE_MODE_REG_RWx10020000 , ULL(0x10020000) ); +CONST_UINT64_T( EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003 , ULL(0x10020003) ); +CONST_UINT64_T( EX_OHA_PROXY_REG_0x10020006 , ULL(0x10020006) ); +CONST_UINT64_T( EX_OHA_PROXY_LEGACY_REG_0x10020007 , ULL(0x10020007) ); +CONST_UINT64_T( EX_OHA_SKITTER_CTRL_MODE_REG_0x10020008 , ULL(0x10020008) ); +CONST_UINT64_T( EX_OHA_CPM_CTRL_REG_0x1002000A , ULL(0x1002000A) ); +CONST_UINT64_T( EX_OHA_RO_STATUS_REG_0x1002000B , ULL(0x1002000B) ); +CONST_UINT64_T( EX_OHA_MODE_REG_RWx1002000D , ULL(0x1002000D) ); +CONST_UINT64_T( EX_OHA_ERROR_ERROR_MASK_REG_RWx1002000E , ULL(0x1002000E) ); +CONST_UINT64_T( EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 , ULL(0x10020011) ); +CONST_UINT64_T( EX_OHA_AISS_IO_REG_0x10020014 , ULL(0x10020014) ); + +//------------------------------------------------------------------------------ +// EX CLOCK CONTROL +//------------------------------------------------------------------------------ +CONST_UINT64_T( EX_OPCG_CNTL0_0x10030002 , ULL(0x10030002) ); +CONST_UINT64_T( EX_OPCG_CNTL1_0x10030003 , ULL(0x10030003) ); +CONST_UINT64_T( EX_OPCG_CNTL2_0x10030004 , ULL(0x10030004) ); +CONST_UINT64_T( EX_OPCG_CNTL3_0x10030005 , ULL(0x10030005) ); +CONST_UINT64_T( EX_CLK_REGION_0x10030006 , ULL(0x10030006) ); +CONST_UINT64_T( EX_CLK_SCANSEL_0x10030007 , ULL(0x10030007) ); +CONST_UINT64_T( EX_CLK_STATUS_0x10030008 , ULL(0x10030008) ); + +//------------------------------------------------------------------------------ +// EX FIR +//------------------------------------------------------------------------------ +CONST_UINT64_T( EX_XSTOP_0x10040000 , ULL(0x10040000) ); +CONST_UINT64_T( EX_RECOV_0x10040001 , ULL(0x10040001) ); +CONST_UINT64_T( EX_FIR_MASK_0x10040002 , ULL(0x10040002) ); +CONST_UINT64_T( EX_SPATTN_0x10040004 , ULL(0x10040004) ); +CONST_UINT64_T( EX_SPATTN_AND_0x10040005 , ULL(0x10040005) ); +CONST_UINT64_T( EX_SPATTN_OR_0x10040006 , ULL(0x10040006) ); +CONST_UINT64_T( EX_SPATTN_MASK_0x10040007 , ULL(0x10040007) ); +CONST_UINT64_T( EX_FIR_MODE_0x10040008 , ULL(0x10040008) ); +CONST_UINT64_T( EX_PERV_LFIR_0x1004000A , ULL(0x1004000A) ); +CONST_UINT64_T( EX_PERV_LFIR_AND_0x1004000B , ULL(0x1004000B) ); +CONST_UINT64_T( EX_PERV_LFIR_OR_0x1004000C , ULL(0x1004000C) ); +CONST_UINT64_T( EX_PERV_LFIR_MASK_0x1004000D , ULL(0x1004000D) ); +CONST_UINT64_T( EX_PERV_LFIR_MASK_AND_0x1004000E , ULL(0x1004000E) ); +CONST_UINT64_T( EX_PERV_LFIR_MASK_OR_0x1004000F , ULL(0x1004000F) ); +CONST_UINT64_T( EX_PERV_LFIR_ACT0_0x10040010 , ULL(0x10040010) ); +CONST_UINT64_T( EX_PERV_LFIR_ACT1_0x10040011 , ULL(0x10040011) ); + +//------------------------------------------------------------------------------ +// EX THERMAL +//------------------------------------------------------------------------------ +CONST_UINT64_T( EX_THERM_0x10050000 , ULL(0x10050000) ); + +//------------------------------------------------------------------------------ +// EX PCB SLAVE +//------------------------------------------------------------------------------ +//Generic names (need to add in (cuTarget.chipUnitNum * 0x01000000)) when being used +// special wakeup registers +CONST_UINT64_T( PM_SPECIAL_WKUP_FSP_0x100F010B , ULL(0x100F010B) ); +CONST_UINT64_T( PM_SPECIAL_WKUP_OCC_0x100F010C , ULL(0x100F010C) ); +CONST_UINT64_T( PM_SPECIAL_WKUP_PHYP_0x100F010D , ULL(0x100F010D) ); + +//Multicast Group Registers +CONST_UINT64_T( EX_MCGR1_0x100F0001 , ULL(0x100F0001) ); +CONST_UINT64_T( EX_MCGR2_0x100F0002 , ULL(0x100F0002) ); +CONST_UINT64_T( EX_MCGR3_0x100F0003 , ULL(0x100F0003) ); +CONST_UINT64_T( EX_MCGR4_0x100F0004 , ULL(0x100F0004) ); + +//GP3 Register +CONST_UINT64_T( EX_GP3_0x100F0012 , ULL(0x100F0012) ); +CONST_UINT64_T( EX_GP3_AND_0x100F0013 , ULL(0x100F0013) ); +CONST_UINT64_T( EX_GP3_OR_0x100F0014 , ULL(0x100F0014) ); + +//Chiplet specific names (probably won't ever be used) +CONST_UINT64_T( EX00_GP3_0x100F0012 , ULL(0x100F0012) ); +CONST_UINT64_T( EX00_GP3_AND_0x100F0013 , ULL(0x100F0013) ); +CONST_UINT64_T( EX00_GP3_OR_0x100F0014 , ULL(0x100F0014) ); + +CONST_UINT64_T( EX01_GP3_0x110F0012 , ULL(0x110F0012) ); +CONST_UINT64_T( EX01_GP3_AND_0x110F0013 , ULL(0x110F0013) ); +CONST_UINT64_T( EX01_GP3_OR_0x110F0014 , ULL(0x110F0014) ); + +CONST_UINT64_T( EX02_GP3_0x120F0012 , ULL(0x120F0012) ); +CONST_UINT64_T( EX02_GP3_AND_0x120F0013 , ULL(0x120F0013) ); +CONST_UINT64_T( EX02_GP3_OR_0x120F0014 , ULL(0x120F0014) ); + +CONST_UINT64_T( EX03_GP3_0x130F0012 , ULL(0x130F0012) ); +CONST_UINT64_T( EX03_GP3_AND_0x130F0013 , ULL(0x130F0013) ); +CONST_UINT64_T( EX03_GP3_OR_0x130F0014 , ULL(0x130F0014) ); + +CONST_UINT64_T( EX04_GP3_0x140F0012 , ULL(0x140F0012) ); +CONST_UINT64_T( EX04_GP3_AND_0x140F0013 , ULL(0x140F0013) ); +CONST_UINT64_T( EX04_GP3_OR_0x140F0014 , ULL(0x140F0014) ); + +CONST_UINT64_T( EX05_GP3_0x150F0012 , ULL(0x150F0012) ); +CONST_UINT64_T( EX05_GP3_AND_0x150F0013 , ULL(0x150F0013) ); +CONST_UINT64_T( EX05_GP3_OR_0x150F0014 , ULL(0x150F0014) ); + +CONST_UINT64_T( EX06_GP3_0x160F0012 , ULL(0x160F0012) ); +CONST_UINT64_T( EX06_GP3_AND_0x160F0013 , ULL(0x160F0013) ); +CONST_UINT64_T( EX06_GP3_OR_0x160F0014 , ULL(0x160F0014) ); + +CONST_UINT64_T( EX07_GP3_0x170F0012 , ULL(0x170F0012) ); +CONST_UINT64_T( EX07_GP3_AND_0x170F0013 , ULL(0x170F0013) ); +CONST_UINT64_T( EX07_GP3_OR_0x170F0014 , ULL(0x170F0014) ); + +CONST_UINT64_T( EX08_GP3_0x180F0012 , ULL(0x180F0012) ); +CONST_UINT64_T( EX08_GP3_AND_0x180F0013 , ULL(0x180F0013) ); +CONST_UINT64_T( EX08_GP3_OR_0x180F0014 , ULL(0x180F0014) ); + +CONST_UINT64_T( EX09_GP3_0x190F0012 , ULL(0x190F0012) ); +CONST_UINT64_T( EX09_GP3_AND_0x190F0013 , ULL(0x190F0013) ); +CONST_UINT64_T( EX09_GP3_OR_0x190F0014 , ULL(0x190F0014) ); + +CONST_UINT64_T( EX10_GP3_0x1A0F0012 , ULL(0x1A0F0012) ); +CONST_UINT64_T( EX10_GP3_AND_0x1A0F0013 , ULL(0x1A0F0013) ); +CONST_UINT64_T( EX10_GP3_OR_0x1A0F0014 , ULL(0x1A0F0014) ); + +CONST_UINT64_T( EX11_GP3_0x1B0F0012 , ULL(0x1B0F0012) ); +CONST_UINT64_T( EX11_GP3_AND_0x1B0F0013 , ULL(0x1B0F0013) ); +CONST_UINT64_T( EX11_GP3_OR_0x1B0F0014 , ULL(0x1B0F0014) ); + +CONST_UINT64_T( EX12_GP3_0x1C0F0012 , ULL(0x1C0F0012) ); +CONST_UINT64_T( EX12_GP3_AND_0x1C0F0013 , ULL(0x1C0F0013) ); +CONST_UINT64_T( EX12_GP3_OR_0x1C0F0014 , ULL(0x1C0F0014) ); + +CONST_UINT64_T( EX13_GP3_0x1D0F0012 , ULL(0x1D0F0012) ); +CONST_UINT64_T( EX13_GP3_AND_0x1D0F0013 , ULL(0x1D0F0013) ); +CONST_UINT64_T( EX13_GP3_OR_0x1D0F0014 , ULL(0x1D0F0014) ); + +CONST_UINT64_T( EX14_GP3_0x1E0F0012 , ULL(0x1E0F0012) ); +CONST_UINT64_T( EX14_GP3_AND_0x1E0F0013 , ULL(0x1E0F0013) ); +CONST_UINT64_T( EX14_GP3_OR_0x1E0F0014 , ULL(0x1E0F0014) ); + +CONST_UINT64_T( EX15_GP3_0x1F0F0012 , ULL(0x1F0F0012) ); +CONST_UINT64_T( EX15_GP3_AND_0x1F0F0013 , ULL(0x1F0F0013) ); +CONST_UINT64_T( EX15_GP3_OR_0x1F0F0014 , ULL(0x1F0F0014) ); + +//------------------------------------------------------------------------------ +// EX PCB SLAVE PM +//------------------------------------------------------------------------------ +//Generic names (need to add in (cuTarget.chipUnitNum * 0x01000000)) when being used +//PMGP0 Register +CONST_UINT64_T( EX_PMGP0_0x100F0100 , ULL(0x100F0100) ); +CONST_UINT64_T( EX_PMGP0_AND_0x100F0101 , ULL(0x100F0101) ); +CONST_UINT64_T( EX_PMGP0_OR_0x100F0102 , ULL(0x100F0102) ); +//PMGP1 Register +CONST_UINT64_T( EX_PMGP1_0x100F0103 , ULL(0x100F0103) ); +CONST_UINT64_T( EX_PMGP1_AND_0x100F0104 , ULL(0x100F0104) ); +CONST_UINT64_T( EX_PMGP1_OR_0x100F0105 , ULL(0x100F0105) ); + +CONST_UINT64_T( EX_PFET_CTL_REG_0x100F0106 , ULL(0x100F0106) ); +CONST_UINT64_T( EX_PFET_STAT_REG_0x100F0107 , ULL(0x100F0107) ); +CONST_UINT64_T( EX_PFET_CTL_REG_0x100F010E , ULL(0x100F010E) ); + + +CONST_UINT64_T( EX_IDLEGOTO_0x100F0114 , ULL(0x100F0114) ); +CONST_UINT64_T( EX_FREQCNTL_0x100F0151 , ULL(0x100F0151) ); +CONST_UINT64_T( EX_PMGP1_REG_0_RWXx100F0103 , ULL(0x100F0103) ); +CONST_UINT64_T( EX_PMGP1_REG_0_WANDx100F0104 , ULL(0x100F0104) ); +CONST_UINT64_T( EX_PMGP1_REG_0_WORx100F0105 , ULL(0x100F0105) ); +CONST_UINT64_T( EX_PFVddCntlStat_REG_0x100F0106 , ULL(0x100F0106) ); +CONST_UINT64_T( EX_PFVcsCntlStat_REG_0x100F010E , ULL(0x100F010E) ); +CONST_UINT64_T( EX_PMErrMask_REG_0x100F010A , ULL(0x100F010A) ); +CONST_UINT64_T( EX_PMSpcWkupFSP_REG_0x100F010B , ULL(0x100F010B) ); +CONST_UINT64_T( EX_PMSpcWkupOCC_REG_0x100F010C , ULL(0x100F010C) ); +CONST_UINT64_T( EX_PMSpcWkupPHYP_REG_0x100F010D , ULL(0x100F010D) ); +CONST_UINT64_T( EX_PMSTATEHISTPHYP_REG_0x100F0110 , ULL(0x100F0110) ); +CONST_UINT64_T( EX_PMSTATEHISTFSP_REG_0x100F0111 , ULL(0x100F0111) ); +CONST_UINT64_T( EX_PMSTATEHISTOCC_REG_0x100F0112 , ULL(0x100F0112) ); +CONST_UINT64_T( EX_PMSTATEHISTPERF_REG_0x100F0113 , ULL(0x100F0113) ); +CONST_UINT64_T( EX_IdleFSMGotoCmd_REG_0x100F0114 , ULL(0x100F0114) ); +CONST_UINT64_T( EX_CorePFPUDly_REG_0x100F012C , ULL(0x100F012C) ); +CONST_UINT64_T( EX_CorePFPDDly_REG_0x100F012D , ULL(0x100F012D) ); +CONST_UINT64_T( EX_CorePFVRET_REG_0x100F0130 , ULL(0x100F0130) ); +CONST_UINT64_T( EX_ECOPFPUDly_REG_0x100F014C , ULL(0x100F014C) ); +CONST_UINT64_T( EX_ECOPFPDDly_REG_0x100F014D , ULL(0x100F014D) ); +CONST_UINT64_T( EX_ECOPFVRET_REG_0x100F0150 , ULL(0x100F0150) ); +CONST_UINT64_T( EX_DPLL_CPM_PARM_REG_0x100F0152 , ULL(0x100F0152) ); +CONST_UINT64_T( EX_PCBS_POWER_MANAGEMENT_STATUS_REG_0x100F0153 , ULL(0x100F0153) ); //ROX +CONST_UINT64_T( EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 , ULL(0x100F0154) ); +CONST_UINT64_T( EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155 , ULL(0x100F0155) ); +CONST_UINT64_T( EX_PCBSPM_MODE_REG_0x100F0156 , ULL(0x100F0156) ); +CONST_UINT64_T( EX_PCBS_iVRM_PFETSTR_Sense_Reg_0x100F0157 , ULL(0x100F0157) ); +CONST_UINT64_T( EX_PCBS_Power_Management_Idle_Control_Reg_0x100F0158 , ULL(0x100F0158) ); +CONST_UINT64_T( EX_PCBS_Power_Management_Control_Reg_0x100F0159 , ULL(0x100F0159) ); +CONST_UINT64_T( EX_PCBS_PMC_VF_CTRL_REG_0x100F015A , ULL(0x100F015A) ); +CONST_UINT64_T( EX_PCBS_UNDERVOLTING_REG_0x100F015B , ULL(0x100F015B) ); +CONST_UINT64_T( EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C , ULL(0x100F015C) ); +CONST_UINT64_T( EX_PCBS_Power_Management_Bounds_Reg_0x100F015D , ULL(0x100F015D) ); +CONST_UINT64_T( EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E , ULL(0x100F015E) ); +CONST_UINT64_T( EX_PCBS_PSTATE_TABLE_REG_0x100F015F , ULL(0x100F015F) ); +CONST_UINT64_T( EX_PCBS_Pstate_Step_Target_Register_0x100F0160 , ULL(0x100F0160) ); +CONST_UINT64_T( EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162 , ULL(0x100F0162) ); +CONST_UINT64_T( EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163 , ULL(0x100F0163) ); +CONST_UINT64_T( EX_PCBS_OCC_Heartbeat_Reg_0x100F0164 , ULL(0x100F0164) ); +CONST_UINT64_T( EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165 , ULL(0x100F0165) ); +CONST_UINT64_T( EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166 , ULL(0x100F0166) ); +CONST_UINT64_T( EX_PCBS_Resonant_Clock_Status_Reg_0x100F0167 , ULL(0x100F0167) ); +CONST_UINT64_T( EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168 , ULL(0x100F0168) ); +CONST_UINT64_T( EX_PCBS_FSM_MONITOR2_REG_0x100F0171 , ULL(0x100F0171) ); + +//------------------------------------------------------------------------------ +// MULTICAST REGISTER DEFINITION +//------------------------------------------------------------------------------ +CONST_UINT64_T( EX_WRITE_ALL_EX_PMGP1_REG_0_RWx690F0103 , ULL(0x690F0103) ); // PM GP1 Multicast Group1 +CONST_UINT64_T( EX_WRITE_ALL_EX_PMGP1_REG_0_WANDx690F0104 , ULL(0x690F0104) ); // PM GP1 Multicast Group1 +CONST_UINT64_T( EX_WRITE_ALL_EX_PMGP1_REG_0_WORx690F0105 , ULL(0x690F0105) ); // PM GP1 Multicast Group1 +CONST_UINT64_T( EX_WRITE_ALL_PCBSPM_MODE_REG_0x690F0156 , ULL(0x690F0156) ); // PCBSLV Mode Multicast Group1 +CONST_UINT64_T( EX_WRITE_ALL_PCBS_Power_Management_Bounds_Reg_0x690F015D , ULL(0x690F015D) ); // PCBSLV PM Bounds Multicast Group1 + + + +//******************************************************************************/ +//********* MULTICAST REGISTER DEFINITIONS FOR PERVASIVE INITs ****************/ +//******************************************************************************/ + +CONST_UINT64_T( WRITE_ALL_HPRE0_0x690F0020 , ULL(0x690F0020) ); // hang pulse register 0 +CONST_UINT64_T( WRITE_ALL_HPRE1_0x690F0021 , ULL(0x690F0021) ); // hang pulse register 1 +CONST_UINT64_T( WRITE_ALL_HPRE2_0x690F0022 , ULL(0x690F0022) ); // hang pulse register 2 +CONST_UINT64_T( WRITE_ALL_HPCRE_0x690F0028 , ULL(0x690F0028) ); // hang pulse count register + +CONST_UINT64_T( WRITE_EX_PMGP0_AND_0x690F0101 , ULL(0x690F0101) ); // PM GP0 initialization + +// other multicast constants were moved to common_scom_addresses.H 1/24/2010 mfred + +#endif + + +/* +*************** Do not edit this area *************** +This section is automatically updated by CVS when you check in this file. +Be sure to create CVS comments when you commit so that they can be included here. + +$Log: p8_scom_addresses.H,v $ +Revision 1.77 2012/06/09 19:24:39 jmcgill +add ADU BAR registers + +Revision 1.76 2012/06/05 06:03:04 jmcgill +add ADU XSCOM BAR register + +Revision 1.75 2012/06/01 02:45:26 jmcgill +updates for MCS registers + +Revision 1.74 2012/05/30 12:28:52 kgungl +issues resolved: scom addresses for pba + +Revision 1.73 2012/05/23 16:31:18 karm +added EX core RAS_MODE + +Revision 1.72 2012/05/23 11:04:28 pchatnah +updating pss spivid spwkup registers + +Revision 1.71 2012/05/18 17:59:24 jmcgill +add addresses for proc_setup_bars + +Revision 1.70 2012/05/11 21:15:05 jeshua +Added EX_PCBS_FSM_MONITOR2_REG + +Revision 1.69 2012/05/08 13:31:46 karm +changes to RAM registers in EX PC unit + +Revision 1.68 2012/05/08 11:55:20 stillgs +Added some additional PCBS-PM addresses + +Revision 1.67 2012/05/03 21:36:59 karm +added core thread_active + +Revision 1.66 2012/05/02 21:37:42 jeshua +Added ECID_PART_0 and ECID_PART_1 + +Revision 1.65 2012/05/01 14:30:39 stillgs +Add additional OHA registers + +Revision 1.64 2012/04/27 14:48:20 rmaier +Added RESCLK_status_reg + +Revision 1.63 2012/04/26 22:47:18 karm +added EX_PERV registers for ram and thread ctrl + +Revision 1.62 2012/04/16 23:55:37 bcbrock +Corrected problems related to C/C++ and 32-bit/64-bit portability and Host +Boot after initial review by FW team. + +o Renamed fapi_sbe_common.h to fapi_sbe_common.H +o Renamed p8_scan_compression.[ch] to .[CH] since these are for use by C++ + procedures only (no requirement to execute on OCC). +o Modified sbe_xip_image.c to use the C99 standard way to print uint64_t + variables. +o Added __cplusplus guards to sbe_xip_image.h + +Revision 1.61 2012/04/09 22:35:14 jeshua +Added L2 FIR and CERR registers + +Revision 1.60 2012/03/21 08:15:53 rmaier +Added OHA_ARCH_IDLE_STATE_REG + +Revision 1.59 2012/03/14 11:50:03 stillgs +Added PMC O2S and SPIVID control regs for use by proc_pmc_init.C and proc_sbe_set_pvid.S + +Revision 1.58 2012/03/02 21:41:45 jimyac +added additional OCB Indirect Channel 0-3 Registers + +Revision 1.57 2012/03/01 16:09:20 rmaier +Added PCBS/OHA constants + +Revision 1.56 2012/02/29 22:57:24 bcbrock +Added PIBMEM control registers to p8_scom_addresses.H + +Revision 1.55 2012/02/10 23:09:52 jmcgill +add trace array addresses + +Revision 1.54 2012/01/30 16:08:40 jimyac +added OCC SRAM Boot Vector0-3 registers + +Revision 1.53 2012/01/30 15:59:43 jimyac +added ocb channel0-3 push & pull register and fixed typo in ocb addressed where address in variable name did not match actual address value + +Revision 1.52 2012/01/24 21:59:42 mfred +Moved common multicast address constants to common_scom_accresses.H + +Revision 1.51 2012/01/18 12:55:03 koenig +Added PBA clock sync reg + +Revision 1.50 2012/01/06 22:20:53 jmcgill +move shared/common addresses to common_scom_addresses.H, general cleanup + +Revision 1.49 2012/01/05 22:07:47 jeshua +Updated ring numbers for most chiplets + +Revision 1.48 2012/01/05 21:38:17 jmcgill +adjust EX SCOM ring comments, pervasive thread control/status register addresses + +Revision 1.47 2012/01/05 20:18:16 jmcgill +adjust L2 SCOM addresses + +Revision 1.46 2011/12/15 17:49:30 bcbrock +Added the PIBMEM base address to p8_scom_addresses.H + +Revision 1.45 2011/11/07 23:52:21 bcbrock +Added GENERIC_CLK_SCANDATA0_0x00038000 + +Revision 1.44 2011/11/07 05:49:06 jmcgill +update PBA trusted SCOM ring and PB X mode register addresses, add GP0 and/or addresses for A bus chiplet + +Revision 1.43 2011/09/28 12:49:47 stillgs +Added some PCBS-PM addresses for early PM FAPI work + +Revision 1.42 2011/09/16 16:01:34 jeshua +Added MBOX_SBEVITAL + +Revision 1.41 2011/09/16 16:00:26 jeshua +Undo Ralph's X-bus change. The X-bus is now chiplet 4, not chiplet 3. + +Revision 1.40 2011/09/16 10:28:56 rkoester +wrong X-BUS addresses corrected, changed from 0b04 to 0b03 + +Revision 1.39 2011/09/09 21:00:33 jeshua +X_BUS is now chiplet 4 (as of 051 chip) + +Revision 1.37 2011/09/02 18:45:46 dan +Added scan_time_rep + +Revision 1.36 2011/09/01 20:37:17 jmcgill +add PBA config register, shift L2 scom addresses for HW170113, fix L3 Mode Reg0 address + +Revision 1.35 2011/08/30 22:07:37 jeshua +Added NEST_GP0_AND + +Revision 1.34 2011/08/29 21:11:31 jmcgill +add generic PM GP0 OR constant + +Revision 1.33 2011/08/26 15:51:38 jeshua +Added chiplet defines for multicast operations + +Revision 1.32 2011/08/26 12:53:27 gweber +added constant SCAN_ALLSCANEXPRV_IMM + +Revision 1.31 2011/08/11 20:56:24 dan +removed redundant GENERIC_PMGP0_AND_0x000F0101. +added WRITE_ALL_GP0_AND_0x6B000004, WRITE_ALL_GP0_OR_0x6B000005 + +Revision 1.30 2011/07/28 16:36:30 jmcgill +add comment regarding L2 SCOM addresses which need to be adjusted when model fixes arrive (HW170113) + +Revision 1.29 2011/07/27 12:28:55 dan +Added scan0 defines. + +Revision 1.28 2011/07/25 22:31:03 venton +Added back in global addresses still used in SBe procs from version 1.24 + +Revision 1.27 2011/07/25 20:52:58 jmcgill +temporary workaround for L2 Purge Register SCOM access + +Revision 1.26 2011/07/25 17:30:35 dan +Added some generic registers. + +Revision 1.25 2011/07/25 13:05:09 gweber +moved centaur constants to cen_scom_addresses.H + +Revision 1.23 2011/07/20 15:32:10 gweber +added some centaur constants + +Revision 1.22 2011/07/15 20:50:13 jeshua +Added chiplet and some generic addresses + +Revision 1.21 2011/07/15 20:24:14 jeshua +TP_GP3_0x01000003 should be TP_GP4_0x01000003 + +Revision 1.20 2011/07/08 19:49:01 jeshua +Moved some addresses to their appropriate sections +Fixes some addresses that didn't match their name +Added EX08-15 generics +Removed some non-generic EX01 addresses + +Revision 1.19 2011/07/07 21:36:11 rkoester +more addresses added + +Revision 1.18 2011/07/07 16:27:49 karm +added chiplet_core_pervasive registers for start and status, added chiplet id + +Revision 1.17 2011/07/07 12:24:49 rkoester +addresses added + +Revision 1.16 2011/07/06 20:03:46 jmcgill +updates to handle TP design modifications which changed SCOM access method for subset of PBA facilities + +Revision 1.15 2011/07/06 15:01:36 bcbrock +Fix header file name + +Revision 1.14 2011/07/06 04:06:49 bcbrock +Added a common header for FAPI/SBE #defines, fapi_sbe_common.h + +Revision 1.13 2011/07/01 15:13:16 rkoester +addresses added for mailbox register + +Revision 1.12 2011/06/30 09:50:28 rkoester +private version of .H file released back to LIB, MBOX addresses added + +Revision 1.11 2011/06/15 22:46:26 jeshua +Added Mailbox registers + +Revision 1.10 2011/06/14 15:55:46 rkoester +move SCOM addresses from porinit.C to p8_scom_addresses.H + +Revision 1.9 2011/06/14 04:57:04 bcbrock +Latest version of PGAS and PORE inline tools; Added PORE SCOM addresses + +Revision 1.8 2011/06/07 21:26:49 jeshua +Updated OCB names to have the correct addresses + +Revision 1.7 2011/06/02 14:28:26 jmcgill +add PB EH scom addresses, L3 mode register1 address + +Revision 1.6 2011/05/31 22:09:47 jeshua +Updated the ULL macro, because the previous one didn't work with the assembler + +Revision 1.5 2011/05/27 21:49:13 jeshua +Switch to constants instead of #defines +Added in a macro to allow PORE assembler to use this header as well + +Revision 1.4 2011/05/24 19:01:58 jmcgill +add addresses from OCC/OCB/PBA + +Revision 1.3 2011/04/21 19:48:23 jeshua +Added L2 and L3 Mode Reg 0 + +Revision 1.2 2011/04/06 18:27:01 jmcgill +fixup ADU Control Register name, add ADU PMISC Mode Register address + +Revision 1.1 2011/02/23 17:09:44 jeshua +Initial version + + + +*/ diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.C b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.C new file mode 100644 index 000000000..cf4ed8646 --- /dev/null +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.C @@ -0,0 +1,288 @@ +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.C $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ +// $Id: proc_fab_smp.C,v 1.4 2012/05/18 18:07:44 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_fab_smp.C,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : proc_fab_smp.C +// *! DESCRIPTION : Common fabric structure defintions/utility functions (FAPI) +// *! +// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include "proc_fab_smp.H" + +extern "C" { + +using namespace fapi; +//------------------------------------------------------------------------------ +// Function definitions +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// function: utility function to read & return fabric node ID attribute +// parameters: i_target => pointer to chip target +// o_node_id => structure encapsulating node ID value +// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid, +// RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR if attribute value is +// invalid, +// else FAPI_ATTR_GET return code +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_fab_smp_get_node_id_attr( + const fapi::Target* i_target, + proc_fab_smp_node_id& o_node_id) +{ + // return code + fapi::ReturnCode rc; + // temporary attribute storage used to build procedure data structures + uint8_t node_id_attr; + + // mark function entry + FAPI_DBG("proc_fab_smp_get_node_id_attr: Start"); + + do + { + // retrieve node ID attribute + rc = FAPI_ATTR_GET(ATTR_FABRIC_NODE_ID, + i_target, + node_id_attr); + if (!rc.ok()) + { + FAPI_ERR("proc_fab_smp_get_node_id_attr: Error querying ATTR_FABRIC_NODE_ID"); + break; + } + + // print attribute value + FAPI_DBG("proc_fab_smp_get_node_id_attr: ATTR_FABRIC_NODE_ID = 0x%X", + node_id_attr); + + // translate to enum + switch (node_id_attr) + { + case 0: + o_node_id = FBC_NODE_ID_0; + break; + case 1: + o_node_id = FBC_NODE_ID_1; + break; + case 2: + o_node_id = FBC_NODE_ID_2; + break; + case 3: + o_node_id = FBC_NODE_ID_3; + break; + case 4: + o_node_id = FBC_NODE_ID_4; + break; + case 5: + o_node_id = FBC_NODE_ID_5; + break; + case 6: + o_node_id = FBC_NODE_ID_6; + break; + case 7: + o_node_id = FBC_NODE_ID_7; + break; + default: + FAPI_ERR("proc_fab_smp_get_node_id_attr: Invalid fabric node ID attribute value 0x%02X", + node_id_attr); + const uint8_t& ATTR_DATA = node_id_attr; + FAPI_SET_HWP_ERROR(rc, + RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR); + break; + } + } while(0); + + // mark function exit + FAPI_DBG("proc_fab_smp_get_node_id_attr: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: utility function to read & return fabric chip ID attribute +// parameters: i_target => pointer to chip target +// o_chip_id => structure encapsulating chip ID value +// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid, +// RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR if attribute value is +// invalid, +// else FAPI_ATTR_GET return code +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_fab_smp_get_chip_id_attr( + const fapi::Target* i_target, + proc_fab_smp_chip_id& o_chip_id) +{ + // return code + fapi::ReturnCode rc; + // temporary attribute storage used to build procedure data structures + uint8_t chip_id_attr; + + // mark function entry + FAPI_DBG("proc_fab_smp_get_chip_id_attr: Start"); + + do + { + // retrieve chip ID attribute + rc = FAPI_ATTR_GET(ATTR_FABRIC_CHIP_ID, + i_target, + chip_id_attr); + if (!rc.ok()) + { + FAPI_ERR("proc_fab_smp_get_chip_id_attr: Error querying ATTR_FABRIC_CHIP_ID"); + break; + } + + // print attribute value + FAPI_DBG("proc_fab_smp_get_chip_id_attr: ATTR_FABRIC_CHIP_ID = 0x%X", + chip_id_attr); + + // translate to enum + switch (chip_id_attr) + { + case 0: + o_chip_id = FBC_CHIP_ID_0; + break; + case 1: + o_chip_id = FBC_CHIP_ID_1; + break; + case 2: + o_chip_id = FBC_CHIP_ID_2; + break; + case 3: + o_chip_id = FBC_CHIP_ID_3; + break; + case 4: + o_chip_id = FBC_CHIP_ID_4; + break; + case 5: + o_chip_id = FBC_CHIP_ID_5; + break; + case 6: + o_chip_id = FBC_CHIP_ID_6; + break; + case 7: + o_chip_id = FBC_CHIP_ID_7; + break; + default: + FAPI_ERR("proc_fab_smp_get_chip_id_attr: Invalid fabric chip ID attribute value 0x%02X", + chip_id_attr); + const uint8_t& ATTR_DATA = chip_id_attr; + FAPI_SET_HWP_ERROR(rc, + RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR); + break; + } + } while(0); + + // mark function exit + FAPI_DBG("proc_fab_smp_get_chip_id_attr: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: utility function to read & return PCIe/DSMP mux attribute values +// parameters: i_target => pointer to chip target +// o_pcie_not_f_link => vector of boolean values representing state +// of PCIe/DSMP mux settings (one value per +// foreign link, true=PCIe function, false= +// DSMP function) +// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid, +// RC_PROC_FAB_SMP_PCIE_NOT_F_LINK_ATTR_ERR if attribute value is +// invalid, +// else FAPI_ATTR_GET return code +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_fab_smp_get_pcie_dsmp_mux_attrs( + const fapi::Target* i_target, + bool o_pcie_not_f_link[PROC_FAB_SMP_NUM_F_LINKS]) +{ + // return code + fapi::ReturnCode rc; + // temporary attribute storage used to build procedure data structures + uint8_t pcie_not_f_link_attr[PROC_FAB_SMP_NUM_F_LINKS]; + + // mark function entry + FAPI_DBG("proc_fab_smp_get_pcie_dsmp_mux_attrs: Start"); + + do + { + // retrieve PCIe/DSMP mux attributes + rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_NOT_F_LINK, + i_target, + pcie_not_f_link_attr); + if (!rc.ok()) + { + FAPI_ERR("proc_fab_smp_get_pcie_dsmp_mux_attrs: Error querying ATTR_PROC_PCIE_NOT_F_LINK"); + break; + } + + // loop over all links + for (uint8_t l = 0; + l < PROC_FAB_SMP_NUM_F_LINKS; + l++) + { + // print attribute value + FAPI_DBG("proc_fab_smp_get_pcie_dsmp_mux_attrs: ATTR_PROC_PCIE_NOT_F_LINK[%d] = 0x%X", + l, pcie_not_f_link_attr[l]); + + // validate attribute value + switch (pcie_not_f_link_attr[l]) + { + case 0: + o_pcie_not_f_link[l] = false; + break; + case 1: + o_pcie_not_f_link[l] = true; + break; + default: + FAPI_ERR("proc_fab_smp_get_pcie_dsmp_mux_attrs: Invalid PCIe/DSMP mux attribute value 0x%02X", + pcie_not_f_link_attr[l]); + const uint8_t& ATTR_DATA = pcie_not_f_link_attr[l]; + FAPI_SET_HWP_ERROR(rc, + RC_PROC_FAB_SMP_PCIE_NOT_F_LINK_ATTR_ERR); + break; + } + if (!rc.ok()) + { + break; + } + } + } while(0); + + // mark function exit + FAPI_DBG("proc_fab_smp_get_pcie_dsmp_mux_attrs: End"); + return rc; +} + + +} // extern "C" diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.H new file mode 100644 index 000000000..bf5383199 --- /dev/null +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.H @@ -0,0 +1,143 @@ +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.H $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ +// $Id: proc_fab_smp.H,v 1.3 2012/05/18 18:07:49 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_fab_smp.H,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : proc_fab_smp.H +// *! DESCRIPTION : Common fabric structure defintions/utility functions (FAPI) +// *! +// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! +//------------------------------------------------------------------------------ + +#ifndef _PROC_FAB_SMP_H_ +#define _PROC_FAB_SMP_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <fapi.H> + + +//------------------------------------------------------------------------------ +// Structure definitions +//------------------------------------------------------------------------------ + +// define set of supported fabric node ID values +enum proc_fab_smp_node_id +{ + FBC_NODE_ID_0 = 0, + FBC_NODE_ID_1 = 1, + FBC_NODE_ID_2 = 2, + FBC_NODE_ID_3 = 3, + FBC_NODE_ID_4 = 4, + FBC_NODE_ID_5 = 5, + FBC_NODE_ID_6 = 6, + FBC_NODE_ID_7 = 7 +}; + +// define set of supported fabric chip ID values +enum proc_fab_smp_chip_id +{ + FBC_CHIP_ID_0 = 0, + FBC_CHIP_ID_1 = 1, + FBC_CHIP_ID_2 = 2, + FBC_CHIP_ID_3 = 3, + FBC_CHIP_ID_4 = 4, + FBC_CHIP_ID_5 = 5, + FBC_CHIP_ID_6 = 6, + FBC_CHIP_ID_7 = 7 +}; + + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + +// largest representable fabric real address given HW implementation +const uint64_t PROC_FAB_SMP_MAX_ADDRESS = ((1ULL << 50)-1ULL); + +// number of F links supported per chip +const uint8_t PROC_FAB_SMP_NUM_F_LINKS = 2; + + +extern "C" +{ + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// function: utility function to read & return fabric node ID attribute +// parameters: i_target => pointer to P8 chip target +// o_node_id => structure encapsulating node ID value +// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid, +// RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR if attribute value is +// invalid, +// else FAPI_ATTR_GET return code +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_fab_smp_get_node_id_attr( + const fapi::Target* i_target, + proc_fab_smp_node_id& o_node_id); + +//------------------------------------------------------------------------------ +// function: utility function to read & return fabric chip ID attribute +// parameters: i_target => pointer to P8 chip target +// o_chip_id => structure encapsulating chip ID value +// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid, +// RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR if attribute value is +// invalid, +// else FAPI_ATTR_GET return code +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_fab_smp_get_chip_id_attr( + const fapi::Target* i_target, + proc_fab_smp_chip_id& o_chip_id); + +//------------------------------------------------------------------------------ +// function: utility function to read & return PCIe/DSMP mux attribute values +// parameters: i_target => pointer to P8 chip target +// o_pcie_not_f_link => vector of boolean values representing state +// of PCIe/DSMP mux settings (one value per +// foreign link, true=PCIe function, false= +// DSMP function) +// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid, +// RC_PROC_FAB_SMP_PCIE_NOT_F_LINK_ATTR_ERR if attribute value is +// invalid, +// else FAPI_ATTR_GET return code +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_fab_smp_get_pcie_dsmp_mux_attrs( + const fapi::Target* i_target, + bool o_pcie_not_f_link[PROC_FAB_SMP_NUM_F_LINKS]); + + +} // extern "C" + +#endif // _PROC_FAB_SMP_H_ diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp_errors.xml b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp_errors.xml new file mode 100644 index 000000000..5d590c998 --- /dev/null +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp_errors.xml @@ -0,0 +1,41 @@ +<!-- IBM_PROLOG_BEGIN_TAG + This is an automatically generated prolog. + + $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp_errors.xml $ + + IBM CONFIDENTIAL + + COPYRIGHT International Business Machines Corp. 2012 + + p1 + + Object Code Only (OCO) source materials + Licensed Internal Code Source Materials + IBM HostBoot Licensed Internal Code + + The source code for this program is not published or other- + wise divested of its trade secrets, irrespective of what has + been deposited with the U.S. Copyright Office. + + Origin: 30 + + IBM_PROLOG_END_TAG --> +<!-- Error definitions for proc_fab_smp --> +<hwpErrors> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_FAB_SMP_PCIE_NOT_F_LINK_ATTR_ERR</rc> + <description>Invalid definition for PCIe/DSMP mux attribute value.</description> + <ffdc>ATTR_DATA</ffdc> + </hwpError> + <hwpError> + <rc>RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR</rc> + <description>Invalid definition for fabric node ID attribute value.</description> + <ffdc>ATTR_DATA</ffdc> + </hwpError> + <hwpError> + <rc>RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR</rc> + <description>Invalid definition for fabric chip ID attribute value.</description> + <ffdc>ATTR_DATA</ffdc> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp_fabric_attributes.xml b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp_fabric_attributes.xml new file mode 100644 index 000000000..ac9ab578c --- /dev/null +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp_fabric_attributes.xml @@ -0,0 +1,54 @@ +<!-- IBM_PROLOG_BEGIN_TAG + This is an automatically generated prolog. + + $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp_fabric_attributes.xml $ + + IBM CONFIDENTIAL + + COPYRIGHT International Business Machines Corp. 2012 + + p1 + + Object Code Only (OCO) source materials + Licensed Internal Code Source Materials + IBM HostBoot Licensed Internal Code + + The source code for this program is not published or other- + wise divested of its trade secrets, irrespective of what has + been deposited with the U.S. Copyright Office. + + Origin: 30 + + IBM_PROLOG_END_TAG --> +<!-- proc_fab_smp_fabric_attributes.xml --> +<attributes> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_FREQ_CORE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + firmware notes: + Nominal processor's core DPLL frequency (MHz). + Default value provided by Machine Readable Workbook. + This attribute is the current value. + </description> + <valueType>uint32</valueType> + <writeable/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_PCIE_NOT_F_LINK</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + firmware notes: + Set IPL time mux/switch between PCIE PHB/F link function + (one per foreign link) + </description> + <valueType>uint8</valueType> + <array>2</array> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> +</attributes>
\ No newline at end of file diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C new file mode 100644 index 000000000..e64236331 --- /dev/null +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C @@ -0,0 +1,3253 @@ +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ +// $Id: proc_setup_bars.C,v 1.3 2012/06/12 02:44:04 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars.C,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : proc_setup_bars.C +// *! DESCRIPTION : Program nest base address registers (BARs) (FAPI) +// *! +// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include "proc_setup_bars.H" + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + +// logical size->physical encoding translation maps +const std::map<uint64_t, uint64_t> proc_setup_bars_nf_bar_size::xlate_map = + proc_setup_bars_nf_bar_size::create_map(); + +const std::map<uint64_t, uint64_t> proc_setup_bars_f_bar_size::xlate_map = + proc_setup_bars_f_bar_size::create_map(); + +const std::map<uint64_t, uint64_t> proc_setup_bars_fsp_bar_size::xlate_map = + proc_setup_bars_fsp_bar_size::create_map(); + +const std::map<uint64_t, uint64_t> proc_setup_bars_fsp_mmio_mask_size::xlate_map = + proc_setup_bars_fsp_mmio_mask_size::create_map(); + +const std::map<uint64_t, uint64_t> proc_setup_bars_nx_mmio_bar_size::xlate_map = + proc_setup_bars_nx_mmio_bar_size::create_map(); + +const std::map<uint64_t, uint64_t> proc_setup_bars_mcd_bar_size::xlate_map = + proc_setup_bars_mcd_bar_size::create_map(); + +const std::map<uint64_t, uint64_t> proc_setup_bars_pcie_bar_size::xlate_map = + proc_setup_bars_pcie_bar_size::create_map(); + + +extern "C" { + +//------------------------------------------------------------------------------ +// Function definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// function: utility function to display address range/BAR information and +// check properties +// parameters: i_bar_def => structure encapsulating address range/BAR +// properties +// i_bar_addr_range => structure encapsulating address range +// returns: true if any properties specified by i_bar_def are violated, +// false otherwise +//------------------------------------------------------------------------------ +bool proc_setup_bars_common_check_bar( + const proc_setup_bars_bar_def& i_bar_def, + const proc_setup_bars_addr_range& i_bar_addr_range) +{ + // return code + fapi::ReturnCode rc; + // set if error should be logged at end of function + bool error = false; + + do + { + // print range information + i_bar_addr_range.print(); + + // only check if BAR enable attribute is set + if (i_bar_addr_range.enabled) + { + // ensure that address range lies in fabric real address space + if (!i_bar_addr_range.is_in_fbc_range()) + { + FAPI_ERR("proc_setup_bars_common_check_bar: BAR range is not wholly contained in FBC real address space"); + error = true; + break; + } + // ensure that base address value lies in implemented address space + if (i_bar_addr_range.base_addr & + i_bar_def.base_addr_mask) + { + FAPI_ERR("proc_setup_bars_common_check_bar: BAR base address attribute value is out-of-range"); + error = true; + break; + } + // ensure that address range size is in range + if ((i_bar_addr_range.size < i_bar_def.size_min) || + (i_bar_addr_range.size > i_bar_def.size_max)) + { + FAPI_ERR("proc_setup_bars_common_check_bar: BAR size attribute value is out-of-range"); + error = true; + break; + } + // check that base address range and mask are aligned + if (i_bar_def.check_aligned && + !i_bar_addr_range.is_aligned()) + { + FAPI_ERR("proc_setup_bars_common_check_bar: BAR base address/size range values are not aligned"); + error = true; + break; + } + } + } while(0); + + return error; +} + + +//------------------------------------------------------------------------------ +// function: utility function to check for overlapping address ranges +// parameters: i_ranges => vector of pointers to address range structures that +// should be checked +// returns: true if any ranges overlap, false otherwise +//------------------------------------------------------------------------------ +bool proc_setup_bars_common_do_ranges_overlap( + const std::vector<proc_setup_bars_addr_range*> i_ranges) +{ + bool overlap = false; + FAPI_DBG("proc_setup_bars_common_do_ranges_overlap: Start"); + + // check that ranges are non-overlapping + if (i_ranges.size() > 1) + { + for (uint8_t r = 0; (r < i_ranges.size()-1) && !overlap; r++) + { + for (uint8_t x = r+1; x < i_ranges.size(); x++) + { + if (i_ranges[r]->overlaps(*(i_ranges[x]))) + { + overlap = true; + break; + } + } + } + } + + FAPI_DBG("proc_setup_bars_common_do_ranges_overlap: End"); + return overlap; +} + + +//------------------------------------------------------------------------------ +// function: retrieve attributes defining non-mirrored memory range +// parameters: i_target => pointer to chip target +// io_addr_range => address range structure encapsulating attribute +// values (size will be rounded up to nearest +// power of two) +// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values +// are valid, +// RC_PROC_SETUP_BARS_NON_MIRRORED_RANGE_ATTR_ERR if chip non-mirrored +// attribute content violates expected behavior, +// RC_PROC_SETUP_BARS_NON_MIRRORED_RANGE_OVERLAP_ATTR_ERR if chip +// non-mirrored range attributes specify overlapping ranges, +// RC_PROC_SETUP_BARS_NON_MIRRORED_RANGE_ERR if chip non-mirrored +// processed range content violates expected behavior, +// else FAPI_ATTR_GET return code +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_setup_bars_memory_get_non_mirrored_attrs( + const fapi::Target* i_target, + proc_setup_bars_addr_range& io_addr_range) +{ + // return code + fapi::ReturnCode rc; + // temporary attribute storage used to build procedure data structures + uint64_t non_mirrored_base_attrs[PROC_SETUP_BARS_NUM_NON_MIRRORED_RANGES]; + uint64_t non_mirrored_size_attrs[PROC_SETUP_BARS_NUM_NON_MIRRORED_RANGES]; + proc_setup_bars_addr_range non_mirrored_ranges[PROC_SETUP_BARS_NUM_NON_MIRRORED_RANGES]; + + // mark function entry + FAPI_DBG("proc_setup_bars_memory_get_non_mirrored_attrs: Start"); + + do + { + // retrieve non-mirrored memory base address/size attributes + rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASES, + i_target, + non_mirrored_base_attrs); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_memory_get_non_mirrored_attrs: Error querying ATTR_PROC_MEM_BASES"); + break; + } + rc = FAPI_ATTR_GET(ATTR_PROC_MEM_SIZES, + i_target, + non_mirrored_size_attrs); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_memory_get_non_mirrored_attrs: Error querying ATTR_PROC_MEM_SIZES"); + break; + } + + // process attributes into range structures + for (uint8_t r = 0; r < PROC_SETUP_BARS_NUM_NON_MIRRORED_RANGES; r++) + { + // build range content + non_mirrored_ranges[r].base_addr = non_mirrored_base_attrs[r]; + non_mirrored_ranges[r].size = non_mirrored_size_attrs[r]; + // consider range enabled if size is non-zero + non_mirrored_ranges[r].enabled = (non_mirrored_size_attrs[r] != 0x0); + // check attribute content + FAPI_DBG("proc_setup_bars_memory_get_non_mirrored_attrs: Range %d", r); + if (proc_setup_bars_common_check_bar( + non_mirrored_range_def, + non_mirrored_ranges[r]) != false) + { + FAPI_ERR("proc_setup_bars_memory_get_non_mirrored_attrs: Error from proc_setup_bars_common_check_bar"); + const uint64_t& BASE_ADDR = non_mirrored_ranges[r].base_addr; + const uint64_t& SIZE = non_mirrored_ranges[r].size; + FAPI_SET_HWP_ERROR(rc, + RC_PROC_SETUP_BARS_NON_MIRRORED_RANGE_ATTR_ERR); + break; + } + } + if (!rc.ok()) + { + break; + } + + // check that ranges are non-overlapping + std::vector<proc_setup_bars_addr_range*> check_ranges; + for (uint8_t r = 0; r < PROC_SETUP_BARS_NUM_NON_MIRRORED_RANGES; r++) + { + check_ranges.push_back(&non_mirrored_ranges[r]); + } + if (proc_setup_bars_common_do_ranges_overlap(check_ranges)) + { + FAPI_ERR("proc_setup_bars_memory_get_non_mirrored_attrs: Non-mirrored range attributes specify overlapping address regions"); + FAPI_SET_HWP_ERROR(rc, + RC_PROC_SETUP_BARS_NON_MIRRORED_RANGE_OVERLAP_ATTR_ERR); + break; + } + + // ranges are non-overlapping, merge to single range + for (uint8_t r = 0; r < PROC_SETUP_BARS_NUM_NON_MIRRORED_RANGES; r++) + { + // merge to build single range + io_addr_range.merge(non_mirrored_ranges[r]); + } + + // ensure range is power of 2 aligned + if (io_addr_range.enabled && !io_addr_range.is_power_of_2()) + { + io_addr_range.round_next_power_of_2(); + } + + // check final range content + if (proc_setup_bars_common_check_bar( + non_mirrored_range_def, + io_addr_range) != false) + { + FAPI_ERR("proc_setup_bars_memory_get_non_mirrored_attrs: Error from proc_setup_bars_common_check_bar"); + const uint64_t& BASE_ADDR = io_addr_range.base_addr; + const uint64_t& SIZE = io_addr_range.size; + FAPI_SET_HWP_ERROR(rc, + RC_PROC_SETUP_BARS_NON_MIRRORED_RANGE_ERR); + break; + } + } while(0); + + // mark function exit + FAPI_DBG("proc_setup_bars_memory_get_non_mirrored_attrs: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: retrieve attributes defining mirrored memory range +// parameters: i_target => pointer to chip target +// io_addr_range => address range structure encapsulating attribute +// values (ranges will be merged and size rounded +// up to the nearest power of two) +// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values +// are valid, +// RC_PROC_SETUP_BARS_MIRRORED_RANGE_ATTR_ERR if individual chip +// mirrored range attribute content violates expected behavior, +// RC_PROC_SETUP_BARS_MIRRORED_RANGE_OVERLAP_ATTR_ERR if chip mirrored +// range attributes specify overlapping ranges, +// RC_PROC_SETUP_BARS_MIRRORED_RANGE_ERR if chip mirrored processed +// range content violates expected behavior, +// else FAPI_ATTR_GET return code +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_setup_bars_memory_get_mirrored_attrs( + const fapi::Target* i_target, + proc_setup_bars_addr_range& io_addr_range) +{ + // return code + fapi::ReturnCode rc; + // temporary attribute storage used to build procedure data structures + uint64_t mirrored_base_attrs[PROC_SETUP_BARS_NUM_MIRRORED_RANGES]; + uint64_t mirrored_size_attrs[PROC_SETUP_BARS_NUM_MIRRORED_RANGES]; + proc_setup_bars_addr_range mirrored_ranges[PROC_SETUP_BARS_NUM_MIRRORED_RANGES]; + + // mark function entry + FAPI_DBG("proc_setup_bars_memory_get_mirrored_attrs: Start"); + + do + { + // retrieve mirrored memory base address/size attributes + rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASES, + i_target, + mirrored_base_attrs); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_memory_get_mirrored_attrs: Error querying ATTR_PROC_MIRROR_BASE"); + break; + } + rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_SIZES, + i_target, + mirrored_size_attrs); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_memory_get_mirrored_attrs: Error querying ATTR_PROC_MIRROR_SIZE"); + break; + } + + // process attributes into range structures + for (uint8_t r = 0; r < PROC_SETUP_BARS_NUM_MIRRORED_RANGES; r++) + { + // build range content + mirrored_ranges[r].base_addr = mirrored_base_attrs[r]; + mirrored_ranges[r].size = mirrored_size_attrs[r]; + // consider range enabled if size is non-zero + mirrored_ranges[r].enabled = (mirrored_size_attrs[r] != 0x0); + // check attribute content + FAPI_DBG("proc_setup_bars_memory_get_mirrored_attrs: Range %d", r); + if (proc_setup_bars_common_check_bar( + mirrored_range_def, + mirrored_ranges[r]) != false) + { + FAPI_ERR("proc_setup_bars_memory_get_mirrored_attrs: Error from proc_setup_bars_common_check_bar"); + const uint64_t& BASE_ADDR = mirrored_ranges[r].base_addr; + const uint64_t& SIZE = mirrored_ranges[r].size; + FAPI_SET_HWP_ERROR(rc, + RC_PROC_SETUP_BARS_MIRRORED_RANGE_ATTR_ERR); + break; + } + } + if (!rc.ok()) + { + break; + } + + // check that ranges are non-overlapping + std::vector<proc_setup_bars_addr_range*> check_ranges; + for (uint8_t r = 0; r < PROC_SETUP_BARS_NUM_MIRRORED_RANGES; r++) + { + check_ranges.push_back(&mirrored_ranges[r]); + } + if (proc_setup_bars_common_do_ranges_overlap(check_ranges)) + { + FAPI_ERR("proc_setup_bars_memory_get_mirrored_attrs: Mirrored range attributes specify overlapping address regions"); + FAPI_SET_HWP_ERROR(rc, + RC_PROC_SETUP_BARS_MIRRORED_RANGE_OVERLAP_ATTR_ERR); + break; + } + + // ranges are non-overlapping, merge to single range + for (uint8_t r = 0; r < PROC_SETUP_BARS_NUM_MIRRORED_RANGES; r++) + { + // merge to build single range + io_addr_range.merge(mirrored_ranges[r]); + } + + // ensure range is power of 2 aligned + if (io_addr_range.enabled && !io_addr_range.is_power_of_2()) + { + io_addr_range.round_next_power_of_2(); + } + + // check final range content + if (proc_setup_bars_common_check_bar( + mirrored_range_def, + io_addr_range) != false) + { + FAPI_ERR("proc_setup_bars_memory_get_mirrored_attrs: Error from proc_setup_bars_common_check_bar"); + const uint64_t& BASE_ADDR = io_addr_range.base_addr; + const uint64_t& SIZE = io_addr_range.size; + FAPI_SET_HWP_ERROR(rc, + RC_PROC_SETUP_BARS_MIRRORED_RANGE_ERR); + break; + } + } while(0); + + // mark function exit + FAPI_DBG("proc_setup_bars_memory_get_mirrored_attrs: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: retrieve attributes defining foreign near memory range +// parameters: i_target => pointer to chip target +// io_addr_ranges => array of address range structures +// encapsulating attribute values +// (one per foreign link) +// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values +// are valid, +// RC_PROC_SETUP_BARS_FOREIGN_NEAR_RANGE_ATTR_ERR if individual chip +// foriegn near range attribute content violates expected behavior, +// else FAPI_ATTR_GET return code +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_setup_bars_memory_get_foreign_near_attrs( + const fapi::Target* i_target, + proc_setup_bars_addr_range io_addr_ranges[PROC_FAB_SMP_NUM_F_LINKS]) +{ + // return code + fapi::ReturnCode rc; + // temporary attribute storage used to build procedure data structures + uint64_t foreign_near_base_attr[PROC_FAB_SMP_NUM_F_LINKS]; + uint64_t foreign_near_size_attr[PROC_FAB_SMP_NUM_F_LINKS]; + + // mark function entry + FAPI_DBG("proc_setup_bars_memory_get_foreign_near_attrs: Start"); + + do + { + // retrieve foreign near base address/size attributes + rc = FAPI_ATTR_GET(ATTR_PROC_FOREIGN_NEAR_BASE, + i_target, + foreign_near_base_attr); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_memory_get_foreign_near_attrs: Error querying ATTR_PROC_FOREIGN_NEAR_BASE"); + break; + } + rc = FAPI_ATTR_GET(ATTR_PROC_FOREIGN_NEAR_SIZE, + i_target, + foreign_near_size_attr); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_memory_get_foreign_near_attrs: Error querying ATTR_PROC_FOREIGN_NEAR_SIZE"); + break; + } + + // process attributes into range structures + for (uint8_t r = 0; r < PROC_FAB_SMP_NUM_F_LINKS; r++) + { + // build range content + io_addr_ranges[r].base_addr = foreign_near_base_attr[r]; + io_addr_ranges[r].size = foreign_near_size_attr[r]; + io_addr_ranges[r].enabled = (foreign_near_size_attr[r] != 0x0); + + // check attribute content + FAPI_DBG("proc_setup_bars_memory_get_foreign_near_attrs: Link %d", r); + if (proc_setup_bars_common_check_bar( + common_f_scope_bar_def, + io_addr_ranges[r]) != false) + { + FAPI_ERR("proc_setup_bars_memory_get_foreign_near_attrs: Error from proc_setup_bars_common_check_bar"); + const uint64_t& BASE_ADDR = io_addr_ranges[r].base_addr; + const uint64_t& SIZE = io_addr_ranges[r].size; + FAPI_SET_HWP_ERROR(rc, + RC_PROC_SETUP_BARS_FOREIGN_NEAR_RANGE_ATTR_ERR); + break; + } + } + } while(0); + // mark function entry + FAPI_DBG("proc_setup_bars_memory_get_foreign_near_attrs: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: retrieve attributes defining foreign far memory range +// parameters: i_target => pointer to chip target +// io_addr_ranges => array of address range structures +// encapsulating attribute values +// (one per foreign link) +// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values +// are valid, +// RC_PROC_SETUP_BARS_FOREIGN_FAR_RANGE_ATTR_ERR if individual chip +// foreign far range attribute content violates expected behavior, +// else FAPI_ATTR_GET return code +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_setup_bars_memory_get_foreign_far_attrs( + const fapi::Target* i_target, + proc_setup_bars_addr_range io_addr_ranges[PROC_FAB_SMP_NUM_F_LINKS]) +{ + // return code + fapi::ReturnCode rc; + // temporary attribute storage used to build procedure data structures + uint64_t foreign_far_base_attr[PROC_FAB_SMP_NUM_F_LINKS]; + uint64_t foreign_far_size_attr[PROC_FAB_SMP_NUM_F_LINKS]; + + // mark function entry + FAPI_DBG("proc_setup_bars_memory_get_foreign_far_attrs: Start"); + + do + { + // retrieve foreign far base address/size attributes + rc = FAPI_ATTR_GET(ATTR_PROC_FOREIGN_FAR_BASE, + i_target, + foreign_far_base_attr); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_memory_get_foreign_far_attrs: Error querying ATTR_PROC_FOREIGN_FAR_BASE"); + break; + } + rc = FAPI_ATTR_GET(ATTR_PROC_FOREIGN_FAR_SIZE, + i_target, + foreign_far_size_attr); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_memory_get_foreign_far_attrs: Error querying ATTR_PROC_FOREIGN_FAR_SIZE"); + break; + } + + // process attributes into range structures + for (uint8_t r = 0; r < PROC_FAB_SMP_NUM_F_LINKS; r++) + { + // build range content + io_addr_ranges[r].base_addr = foreign_far_base_attr[r]; + io_addr_ranges[r].size = foreign_far_size_attr[r]; + io_addr_ranges[r].enabled = (foreign_far_size_attr[r] != 0x0); + + // check attribute content + FAPI_DBG("proc_setup_bars_memory_get_foreign_far_attrs: Link %d", r); + if (proc_setup_bars_common_check_bar( + common_f_scope_bar_def, + io_addr_ranges[r]) != false) + { + FAPI_ERR("proc_setup_bars_memory_get_foreign_far_attrs: Error from proc_setup_bars_common_check_bar"); + const uint64_t& BASE_ADDR = io_addr_ranges[r].base_addr; + const uint64_t& SIZE = io_addr_ranges[r].size; + FAPI_SET_HWP_ERROR(rc, + RC_PROC_SETUP_BARS_FOREIGN_FAR_RANGE_ATTR_ERR); + break; + } + } + } while(0); + + // mark function exit + FAPI_DBG("proc_setup_bars_memory_get_foreign_far_attrs: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: retrieve attributes defining PSI BAR programming +// parameters: i_target => pointer to chip target +// io_addr_range => address range structure encapsulating +// attribute values +// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values +// are valid, +// RC_PROC_SETUP_BARS_PSI_BAR_ATTR_ERR if chip PSI range +// attribute content violates expected behavior, +// else FAPI_ATTR_GET return code +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_setup_bars_psi_get_bar_attrs( + const fapi::Target* i_target, + proc_setup_bars_addr_range& io_addr_range) +{ + // return code + fapi::ReturnCode rc; + uint8_t bar_enabled; + + FAPI_DBG("proc_setup_bars_psi_get_bar_attrs: Start"); + do + { + // BAR base address + rc = FAPI_ATTR_GET(ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR, + i_target, + io_addr_range.base_addr); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_psi_get_bar_attrs: Error querying ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR"); + break; + } + + // BAR enable + rc = FAPI_ATTR_GET(ATTR_PROC_PSI_BRIDGE_BAR_ENABLE, + i_target, + bar_enabled); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_psi_get_bar_attrs: Error querying ATTR_PROC_PSI_BRIDGE_BAR_ENABLE"); + break; + } + io_addr_range.enabled = (bar_enabled == 0x1); + + // BAR size (implied to be 1MB) + io_addr_range.size = PROC_SETUP_BARS_SIZE_1_MB; + + // check BAR attribute content + if (proc_setup_bars_common_check_bar( + psi_bridge_bar_def, + io_addr_range) != false) + { + FAPI_ERR("proc_setup_bars_psi_get_bar_attrs: Error from proc_setup_bars_common_check_bar"); + const uint64_t& BASE_ADDR = io_addr_range.base_addr; + const uint64_t& SIZE = io_addr_range.size; + FAPI_SET_HWP_ERROR(rc, + RC_PROC_SETUP_BARS_PSI_BAR_ATTR_ERR); + break; + } + } while(0); + + FAPI_DBG("proc_setup_bars_psi_get_bar_attrs: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: retrieve attributes defining FSP BAR programming +// parameters: i_target => pointer to chip target +// io_addr_range => address range structure encapsulating +// attribute values +// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values +// are valid, +// RC_PROC_SETUP_BARS_FSP_BAR_ATTR_ERR if chip FSP range +// attribute content violates expected behavior, +// else FAPI_ATTR_GET return code +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_setup_bars_fsp_get_bar_attrs( + const fapi::Target* i_target, + proc_setup_bars_addr_range& io_addr_range) +{ + // return code + fapi::ReturnCode rc; + uint8_t bar_enabled; + + FAPI_DBG("proc_setup_bars_fsp_get_bar_attrs: Start"); + do + { + // BAR base address + rc = FAPI_ATTR_GET(ATTR_PROC_FSP_BAR_BASE_ADDR, + i_target, + io_addr_range.base_addr); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_fsp_get_bar_attrs: Error querying ATTR_PROC_FSP_BAR_BASE_ADDR"); + break; + } + + // BAR enable + rc = FAPI_ATTR_GET(ATTR_PROC_FSP_BAR_ENABLE, + i_target, + bar_enabled); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_fsp_get_bar_attrs: Error querying ATTR_PROC_FSP_BAR_ENABLE"); + break; + } + io_addr_range.enabled = (bar_enabled == 0x1); + + // BAR size + rc = FAPI_ATTR_GET(ATTR_PROC_FSP_BAR_SIZE, + i_target, + io_addr_range.size); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_fsp_get_bar_attrs: Error querying ATTR_PROC_FSP_BAR_SIZE"); + break; + } + + // check BAR attribute content + if (proc_setup_bars_common_check_bar( + fsp_bar_def, + io_addr_range) != false) + { + FAPI_ERR("proc_setup_bars_fsp_get_bar_attrs: Error from proc_setup_bars_common_check_bar"); + const uint64_t& BASE_ADDR = io_addr_range.base_addr; + const uint64_t& SIZE = io_addr_range.size; + FAPI_SET_HWP_ERROR(rc, + RC_PROC_SETUP_BARS_FSP_BAR_ATTR_ERR); + break; + } + } while(0); + + FAPI_DBG("proc_setup_bars_fsp_get_bar_attrs: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: retrieve attributes defining FSP MMIO mask programming +// parameters: i_target => pointer to chip target +// io_addr_range => address range structure encapsulating +// attribute values +// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values +// are valid, +// RC_PROC_SETUP_BARS_FSP_MMIO_MASK_ATTR_ERR if chip MMIO mask +// attribute content violates expected behavior, +// else FAPI_ATTR_GET return code +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_setup_bars_fsp_get_mmio_mask_attrs( + const fapi::Target* i_target, + proc_setup_bars_addr_range& io_addr_range) +{ + // return code + fapi::ReturnCode rc; + + FAPI_DBG("proc_setup_bars_fsp_get_mmio_mask_attrs: Start"); + do + { + // BAR base address (unused) + io_addr_range.base_addr = 0x0ULL; + + // BAR enable (unused) + io_addr_range.enabled = true; + + // BAR size + rc = FAPI_ATTR_GET(ATTR_PROC_FSP_MMIO_MASK_SIZE, + i_target, + io_addr_range.size); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_fsp_get_mmio_mask_attrs: Error querying ATTR_PROC_FSP_MMIO_MASK_SIZE"); + break; + } + + // check BAR attribute content + if (proc_setup_bars_common_check_bar( + fsp_mmio_mask_def, + io_addr_range) != false) + { + FAPI_ERR("proc_setup_bars_fsp_get_mmio_mask_attrs: Error from proc_setup_bars_common_check_bar"); + const uint64_t& SIZE = io_addr_range.size; + FAPI_SET_HWP_ERROR(rc, + RC_PROC_SETUP_BARS_FSP_MMIO_MASK_ATTR_ERR); + break; + } + } while(0); + + FAPI_DBG("proc_setup_bars_fsp_get_mmio_mask_attrs: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: retrieve attributes defining INTP BAR programming +// parameters: i_target => pointer to chip target +// io_addr_range => address range structure encapsulating +// attribute values +// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values +// are valid, +// RC_PROC_SETUP_BARS_INTP_BAR_ATTR_ERR if chip INTP range +// attribute content violates expected behavior, +// else FAPI_ATTR_GET return code +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_setup_bars_intp_get_bar_attrs( + const fapi::Target* i_target, + proc_setup_bars_addr_range& io_addr_range) +{ + // return code + fapi::ReturnCode rc; + uint8_t bar_enabled; + + FAPI_DBG("proc_setup_bars_intp_get_bar_attrs: Start"); + do + { + // BAR base address + rc = FAPI_ATTR_GET(ATTR_PROC_INTP_BAR_BASE_ADDR, + i_target, + io_addr_range.base_addr); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_intp_get_bar_attrs: Error querying ATTR_PROC_INTP_BAR_BASE_ADDR"); + break; + } + + // BAR enable + rc = FAPI_ATTR_GET(ATTR_PROC_INTP_BAR_ENABLE, + i_target, + bar_enabled); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_intp_get_bar_attrs: Error querying ATTR_PROC_INTP_BAR_ENABLE"); + break; + } + io_addr_range.enabled = (bar_enabled == 0x1); + + // BAR size (implied to be 1MB) + io_addr_range.size = PROC_SETUP_BARS_SIZE_1_MB; + + // check BAR attribute content + if (proc_setup_bars_common_check_bar( + intp_bar_def, + io_addr_range) != false) + { + FAPI_ERR("proc_setup_bars_intp_get_bar_attrs: Error from proc_setup_bars_common_check_bar"); + const uint64_t& BASE_ADDR = io_addr_range.base_addr; + const uint64_t& SIZE = io_addr_range.size; + FAPI_SET_HWP_ERROR(rc, + RC_PROC_SETUP_BARS_INTP_BAR_ATTR_ERR); + break; + } + } while(0); + + FAPI_DBG("proc_setup_bars_intp_get_bar_attrs: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: retrieve attributes defining NX MMIO BAR programming +// parameters: i_target => pointer to chip target +// io_addr_range => address range structure encapsulating +// attribute values +// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values +// are valid, +// RC_PROC_SETUP_BARS_NX_MMIO_BAR_ATTR_ERR if chip NX MMIO range +// attribute content violates expected behavior, +// else FAPI_ATTR_GET return code +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_setup_bars_nx_get_mmio_bar_attrs( + const fapi::Target* i_target, + proc_setup_bars_addr_range& io_addr_range) +{ + // return code + fapi::ReturnCode rc; + uint8_t bar_enabled; + + FAPI_DBG("proc_setup_bars_nx_get_mmio_bar_attrs: Start"); + do + { + // BAR base address + rc = FAPI_ATTR_GET(ATTR_PROC_NX_MMIO_BAR_BASE_ADDR, + i_target, + io_addr_range.base_addr); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_nx_get_mmio_bar_attrs: Error querying ATTR_PROC_NX_MMIO_BAR_BASE_ADDR"); + break; + } + + // BAR enable + rc = FAPI_ATTR_GET(ATTR_PROC_NX_MMIO_BAR_ENABLE, + i_target, + bar_enabled); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_nx_get_mmio_bar_attrs: Error querying ATTR_PROC_NX_MMIO_BAR_ENABLE"); + break; + } + io_addr_range.enabled = (bar_enabled == 0x1); + + // BAR size + rc = FAPI_ATTR_GET(ATTR_PROC_NX_MMIO_BAR_SIZE, + i_target, + io_addr_range.size); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_fsp_get_bar_attrs: Error querying ATTR_PROC_NX_MMIO_BAR_SIZE"); + break; + } + + // check BAR attribute content + if (proc_setup_bars_common_check_bar( + nx_mmio_bar_def, + io_addr_range) != false) + { + FAPI_ERR("proc_setup_bars_nx_get_mmio_bar_attrs: Error from proc_setup_bars_common_check_bar"); + const uint64_t& BASE_ADDR = io_addr_range.base_addr; + const uint64_t& SIZE = io_addr_range.size; + FAPI_SET_HWP_ERROR(rc, + RC_PROC_SETUP_BARS_NX_MMIO_BAR_ATTR_ERR); + break; + } + } while(0); + + FAPI_DBG("proc_setup_bars_nx_get_mmio_bar_attrs: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: retrieve attributes defining PCIe IO BAR programming +// parameters: i_target => pointer to chip target +// io_addr_ranges => 2D array of address range structures +// encapsulating attribute values +// (first dimension = unit, second dimension = +// links per unit) +// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values +// are valid, +// RC_PROC_SETUP_BARS_PCIE_BAR_ATTR_ERR if individual chip PCIe IO +// range attribute content violates expected behavior, +// else FAPI_ATTR_GET return code +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_setup_bars_pcie_get_bar_attrs( + const fapi::Target* i_target, + proc_setup_bars_addr_range io_addr_ranges[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT]) +{ + // return code + fapi::ReturnCode rc; + // temporary attribute storage used to build procedure data structures + uint64_t pcie_bar_addr[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT]; + uint64_t pcie_bar_size[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT]; + uint8_t pcie_bar_en[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT]; + + FAPI_DBG("proc_setup_bars_pcie_get_bar_attrs: Start"); + do + { + // IO BAR base addresses + rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_BAR_BASE_ADDR, + i_target, + pcie_bar_addr); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_pcie_get_bar_attrs: Error querying ATTR_PROC_PCIE_BAR_BASE_ADDR"); + break; + } + + // IO BAR enable + rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_BAR_ENABLE, + i_target, + pcie_bar_en); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_pcie_get_bar_attrs: Error querying ATTR_PROC_PCIE_BAR_ENABLE"); + break; + } + + // IO BAR sizes + rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_BAR_SIZE, + i_target, + pcie_bar_size); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_pcie_get_bar_attrs: Error querying ATTR_PROC_PCIE_BAR_SIZE"); + break; + } + + // loop over all units + for (uint8_t u = 0; + (u < PROC_SETUP_BARS_PCIE_NUM_UNITS) && (rc.ok()); + u++) + { + for (uint8_t r = 0; + r < PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT; + r++) + { + // fill chip range structures + io_addr_ranges[u][r].base_addr = pcie_bar_addr[u][r]; + io_addr_ranges[u][r].size = pcie_bar_size[u][r]; + io_addr_ranges[u][r].enabled = pcie_bar_en[u][r]; + // check BAR attribute content + FAPI_DBG("proc_setup_bars_pcie_get_bar_attrs: Unit %d Range %d", + u, r); + if (proc_setup_bars_common_check_bar( + ((PROC_SETUP_BARS_PCIE_RANGE_TYPE_MMIO[r])? + (pcie_mmio_bar_def): + (pcie_phb_bar_def)), + io_addr_ranges[u][r]) != false) + { + FAPI_ERR("proc_setup_bars_pcie_get_bar_attrs: Error from proc_setup_bars_common_check_bar"); + const uint8_t& UNIT = u; + const uint8_t& RANGE = r; + const uint64_t& BASE_ADDR = io_addr_ranges[u][r].base_addr; + const uint64_t& SIZE = io_addr_ranges[u][r].size; + FAPI_SET_HWP_ERROR(rc, + RC_PROC_SETUP_BARS_PCIE_BAR_ATTR_ERR); + break; + } + } + } + } while(0); + + FAPI_DBG("proc_setup_bars_pcie_get_bar_attrs: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: wrapper function to call all BAR attribute query functions +// parameters: io_smp_chip => structure encapsulating single chip in SMP +// topology (containing target for attribute +// query and storage for all address ranges) +// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values +// are valid, +// else failing return code from attribute query function +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_setup_bars_get_bar_attrs( + proc_setup_bars_smp_chip& io_smp_chip) +{ + // return code + fapi::ReturnCode rc; + + // mark function entry + FAPI_DBG("proc_setup_bars_get_bar_attrs: Start"); + + do + { + FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for non-mirrored memory range"); + rc = proc_setup_bars_memory_get_non_mirrored_attrs( + &(io_smp_chip.chip->this_chip), + io_smp_chip.non_mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_memory_get_non_mirrored_attrs"); + break; + } + + FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for mirrored memory range"); + rc = proc_setup_bars_memory_get_mirrored_attrs( + &(io_smp_chip.chip->this_chip), + io_smp_chip.mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_memory_get_mirrored_attrs"); + break; + } + + FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for foreign near memory ranges"); + rc = proc_setup_bars_memory_get_foreign_near_attrs( + &(io_smp_chip.chip->this_chip), + io_smp_chip.foreign_near_ranges); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_memory_get_foreign_near_attrs"); + break; + } + + FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for foreign far memory ranges"); + rc = proc_setup_bars_memory_get_foreign_far_attrs( + &(io_smp_chip.chip->this_chip), + io_smp_chip.foreign_far_ranges); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_memory_get_foreign_far_attrs"); + break; + } + + FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for PSI address range"); + rc = proc_setup_bars_psi_get_bar_attrs( + &(io_smp_chip.chip->this_chip), + io_smp_chip.psi_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_psi_get_bar_attrs"); + break; + } + + FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for FSP address range"); + rc = proc_setup_bars_fsp_get_bar_attrs( + &(io_smp_chip.chip->this_chip), + io_smp_chip.fsp_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_fsp_get_bar_attrs"); + break; + } + + FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for FSP MMIO mask"); + rc = proc_setup_bars_fsp_get_mmio_mask_attrs( + &(io_smp_chip.chip->this_chip), + io_smp_chip.fsp_mmio_mask_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_fsp_get_mmio_mask_attrs"); + break; + } + + FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for INTP address range"); + rc = proc_setup_bars_intp_get_bar_attrs( + &(io_smp_chip.chip->this_chip), + io_smp_chip.intp_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_intp_get_bar_attrs"); + break; + } + + FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for NX MMIO address range"); + rc = proc_setup_bars_nx_get_mmio_bar_attrs( + &(io_smp_chip.chip->this_chip), + io_smp_chip.nx_mmio_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_intp_get_bar_attrs"); + break; + } + + FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for PCIe address ranges"); + rc = proc_setup_bars_pcie_get_bar_attrs( + &(io_smp_chip.chip->this_chip), + io_smp_chip.pcie_ranges); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_pcie_get_bar_attrs"); + break; + } + } while(0); + + // mark function exit + FAPI_DBG("proc_setup_bars_get_bar_attrs: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: wrapper function to call all chip attribute query functions +// (fabric configuration/node/position/BARs) +// parameters: i_proc_chip => pointer to HWP input structure for this chip +// io_smp_chip => fully specified structure encapsulating +// single chip in SMP topology +// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values +// are valid, +// else failing return code from attribute query function +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_setup_bars_process_chip( + proc_setup_bars_proc_chip* i_proc_chip, + proc_setup_bars_smp_chip& io_smp_chip) +{ + // return code + fapi::ReturnCode rc; + + // mark function entry + FAPI_DBG("proc_setup_bars_process_chip: Start"); + + do + { + // set HWP input pointer + io_smp_chip.chip = i_proc_chip; + + // display target information for this chip + FAPI_DBG("proc_setup_bars_process_chip: Target: %s", + io_smp_chip.chip->this_chip.toEcmdString()); + + // get PCIe/DSMP mux attributes + FAPI_DBG("proc_setup_bars_process_chip: Querying PCIe/DSMP mux attribute"); + rc = proc_fab_smp_get_pcie_dsmp_mux_attrs(&(io_smp_chip.chip->this_chip), + io_smp_chip.pcie_not_f_link); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_process_chip: Error from proc_fab_smp_get_pcie_dsmp_mux_attrs"); + break; + } + + // get node ID attribute + FAPI_DBG("proc_setup_bars_process_chip: Querying node ID attribute"); + rc = proc_fab_smp_get_node_id_attr(&(io_smp_chip.chip->this_chip), + io_smp_chip.node_id); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_process_chip: Error from proc_fab_smp_get_node_id_attr"); + break; + } + + // get chip ID attribute + FAPI_DBG("proc_setup_bars_process_chip: Querying chip ID attribute"); + rc = proc_fab_smp_get_chip_id_attr(&(io_smp_chip.chip->this_chip), + io_smp_chip.chip_id); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_process_chip: Error from proc_fab_smp_get_chip_id_attr"); + break; + } + + // get BAR attributes + rc = proc_setup_bars_get_bar_attrs(io_smp_chip); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_process_chip: Error from proc_fab_smp_get_mem_attrs"); + break; + } + } while(0); + + // mark function exit + FAPI_DBG("proc_setup_bars_process_chip: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: insert chip structure into proper position within SMP model based +// on its fabric node/chip ID +// chip non-mirrored/mirrored range information will be merged +// with those of its enclosing node +// parameters: i_smp_chip => structure encapsulating single chip in SMP topology +// io_smp => structure encapsulating full SMP +// returns: FAPI_RC_SUCCESS if insertion is successful and merged node ranges +// are valid, +// RC_PROC_SETUP_BARS_NODE_ADD_INTERNAL_ERR if node map insert fails, +// RC_PROC_SETUP_BARS_DUPLICATE_FABRIC_ID_ERR if chips with duplicate +// fabric node/chip IDs are detected, +// RC_PROC_SETUP_BARS_NODE_NON_MIRRORED_RANGE_OVERLAP_ERR if overlap +// is detected between existing node non-mirrored range +// and that of new chip being processed, +// RC_PROC_SETUP_BARS_NODE_MIRRORED_RANGE_OVERLAP_ERR if overlap +// is detected between existing node mirrored range +// and that of new chip being processed +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_setup_bars_insert_chip( + proc_setup_bars_smp_chip& i_smp_chip, + proc_setup_bars_smp_system& io_smp) +{ + // return code + fapi::ReturnCode rc; + // node/chip ID + proc_fab_smp_node_id node_id = i_smp_chip.node_id; + proc_fab_smp_chip_id chip_id = i_smp_chip.chip_id; + + // mark function entry + FAPI_DBG("proc_setup_bars_insert_chip: Start"); + + do + { + FAPI_DBG("proc_setup_bars_insert_chip: Inserting n%d p%d", + node_id, chip_id); + + // search to see if node structure already exists for the node ID + // associated with this chip + std::map<proc_fab_smp_node_id, proc_setup_bars_smp_node>::iterator + n_iter; + n_iter = io_smp.nodes.find(node_id); + // no matching node found, create one + if (n_iter == io_smp.nodes.end()) + { + FAPI_DBG("proc_setup_bars_insert_chip: No matching node found, inserting new node structure"); + proc_setup_bars_smp_node n; + std::pair< + std::map<proc_fab_smp_node_id, proc_setup_bars_smp_node>::iterator, + bool> ret; + ret = io_smp.nodes.insert( + std::pair<proc_fab_smp_node_id, proc_setup_bars_smp_node> + (node_id, n)); + n_iter = ret.first; + if (!ret.second) + { + FAPI_ERR("proc_setup_bars_insert_chip: Error encountered adding node to SMP"); + FAPI_SET_HWP_ERROR(rc, + RC_PROC_SETUP_BARS_NODE_ADD_INTERNAL_ERR); + break; + } + } + + // search to see if match exists in this node for the chip ID associated + // with this chip + std::map<proc_fab_smp_chip_id, proc_setup_bars_smp_chip>::iterator + p_iter; + p_iter = io_smp.nodes[node_id].chips.find(chip_id); + // matching chip ID & node ID already found, flag an error + if (p_iter != io_smp.nodes[node_id].chips.end()) + { + FAPI_ERR("proc_setup_bars_insert_chip: Duplicate fabric node ID / chip ID found"); + const uint8_t& NODE_ID = node_id; + const uint8_t& CHIP_ID = chip_id; + FAPI_SET_HWP_ERROR(rc, + RC_PROC_SETUP_BARS_DUPLICATE_FABRIC_ID_ERR); + break; + } + // insert chip into SMP + io_smp.nodes[node_id].chips[chip_id] = i_smp_chip; + + // update node address regions + // before merging, check that non-mirrored & mirrored ranges + // are non-overlapping with new ranges from this chip + FAPI_DBG("proc_setup_bars_insert_chip: Non-mirrored ranges prior to merging:"); + io_smp.nodes[node_id].non_mirrored_range.print(); + i_smp_chip.non_mirrored_range.print(); + if (io_smp.nodes[node_id].non_mirrored_range.overlaps( + i_smp_chip.non_mirrored_range)) + { + FAPI_ERR("proc_setup_bars_insert_chip: Existing node non-mirrored range overlaps chip non-mirrored range"); + const uint64_t& NODE_BASE_ADDR = + io_smp.nodes[node_id].non_mirrored_range.base_addr; + const uint64_t& NODE_SIZE = + io_smp.nodes[node_id].non_mirrored_range.size; + const uint64_t& CHIP_BASE_ADDR = + i_smp_chip.non_mirrored_range.base_addr; + const uint64_t& CHIP_SIZE = + i_smp_chip.non_mirrored_range.size; + FAPI_SET_HWP_ERROR(rc, + RC_PROC_SETUP_BARS_NODE_NON_MIRRORED_RANGE_OVERLAP_ERR); + break; + } + + FAPI_DBG("proc_setup_bars_insert_chip: Mirrored ranges prior to merging:"); + io_smp.nodes[node_id].mirrored_range.print(); + i_smp_chip.mirrored_range.print(); + if (io_smp.nodes[node_id].mirrored_range.overlaps( + i_smp_chip.mirrored_range)) + { + FAPI_ERR("proc_setup_bars_insert_chip: Existing node mirrored range overlaps chip mirrored range"); + const uint64_t& NODE_BASE_ADDR = + io_smp.nodes[node_id].mirrored_range.base_addr; + const uint64_t& NODE_SIZE = + io_smp.nodes[node_id].mirrored_range.size; + const uint64_t& CHIP_BASE_ADDR = + i_smp_chip.mirrored_range.base_addr; + const uint64_t& CHIP_SIZE = + i_smp_chip.mirrored_range.size; + FAPI_SET_HWP_ERROR(rc, + RC_PROC_SETUP_BARS_NODE_MIRRORED_RANGE_OVERLAP_ERR); + break; + } + + // update node address ranges (non-mirrored & mirrored) + FAPI_DBG("proc_setup_bars_insert_chip: Ranges after merging:"); + io_smp.nodes[node_id].non_mirrored_range.merge( + i_smp_chip.non_mirrored_range); + io_smp.nodes[node_id].non_mirrored_range.print(); + + io_smp.nodes[node_id].mirrored_range.merge( + i_smp_chip.mirrored_range); + io_smp.nodes[node_id].mirrored_range.print(); + } while(0); + + // mark function exit + FAPI_DBG("proc_setup_bars_insert_chip: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: wrapper function to process all HWP input structures and build +// SMP data structure +// parameters: i_proc_chips => vector of HWP input structures (one entry per +// chip in SMP) +// io_smp => fully specified structure encapsulating full SMP +// returns: FAPI_RC_SUCCESS if all processing is successful, +// else failing return code from chip processing/insertion wrapper +// functions +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_setup_bars_process_chips( + std::vector<proc_setup_bars_proc_chip>& i_proc_chips, + proc_setup_bars_smp_system& io_smp) +{ + // return code + fapi::ReturnCode rc; + + // mark function entry + FAPI_DBG("proc_setup_bars_process_chips: Start"); + + // loop over all chips passed from platform to HWP + std::vector<proc_setup_bars_proc_chip>::iterator iter; + for (iter = i_proc_chips.begin(); + iter != i_proc_chips.end(); + iter++) + { + // process platform provided data in chip argument, + // query chip specific attributes + proc_setup_bars_smp_chip smp_chip; + rc = proc_setup_bars_process_chip(&(*iter), + smp_chip); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_process_chips: Error from proc_setup_bars_process_chip"); + break; + } + + // insert chip into SMP data structure given node & chip ID + rc = proc_setup_bars_insert_chip(smp_chip, + io_smp); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_process_chips: Error from proc_setup_bars_insert_chip"); + break; + } + } + + // mark function exit + FAPI_DBG("proc_setup_bars_process_chips: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: utility function to write HW BAR register given address range +// structure and register definition structure +// parameters: i_target => chip target +// i_scom_addr => BAR SCOM address +// i_bar_reg_def => structure defining rules to format address +// range content into register layout +// i_addr_range => structure defining BAR address range +// (enable/base/size) +// returns: FAPI_RC_SUCCESS if register write is successful, +// RC_PROC_SETUP_BARS_INVALID_BAR_REG_DEF if BAR register definition +// structure is invalid, +// RC_PROC_SETUP_BARS_SIZE_XLATE_ERR if logical->physical size +// translation is unsuccessful, +// else failing return code from SCOM/data buffer manipulation +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_setup_bars_common_write_bar_reg( + const fapi::Target& i_target, + const uint32_t& i_scom_addr, + const proc_setup_bars_bar_reg_def& i_bar_reg_def, + const proc_setup_bars_addr_range& i_addr_range) +{ + // return code + fapi::ReturnCode rc; + uint32_t rc_ecmd = 0; + // BAR register data buffer + ecmdDataBufferBase bar_data(64); + ecmdDataBufferBase bar_data_mask(64); + ecmdDataBufferBase size_data(64); + ecmdDataBufferBase static_data(64); + ecmdDataBufferBase static_data_mask(64); + + FAPI_DBG("proc_setup_bars_common_write_bar_reg: Start"); + do + { + // write base address + if (i_bar_reg_def.has_base) + { + // previous checking ensures zeroes for all non-implemented bits + rc_ecmd |= bar_data.setDoubleWord(0, i_addr_range.base_addr); + // shift position to proper location in register + if (i_bar_reg_def.base_shift == PROC_SETUP_BARS_SHIFT_LEFT) + { + rc_ecmd |= bar_data.shiftLeft(i_bar_reg_def.base_shift_amount); + } + else if (i_bar_reg_def.base_shift == PROC_SETUP_BARS_SHIFT_RIGHT) + { + rc_ecmd |= bar_data.shiftRight(i_bar_reg_def.base_shift_amount); + } + else if (i_bar_reg_def.base_shift != PROC_SETUP_BARS_SHIFT_NONE) + { + FAPI_ERR("proc_setup_bars_common_write_bar_reg: Invalid base shift value in register definition"); + FAPI_SET_HWP_ERROR( + rc, + RC_PROC_SETUP_BARS_INVALID_BAR_REG_DEF); + break; + } + // set mask + rc_ecmd |= bar_data_mask.setBit(i_bar_reg_def.base_start_bit, + (i_bar_reg_def.base_end_bit - + i_bar_reg_def.base_start_bit + 1)); + } + + // write enable bit + if (i_bar_reg_def.has_enable) + { + rc_ecmd |= bar_data.writeBit(i_bar_reg_def.enable_bit, + i_addr_range.enabled ? 1 : 0); + rc_ecmd |= bar_data_mask.setBit(i_bar_reg_def.enable_bit); + } + + // write size field + if (i_bar_reg_def.has_size) + { + // encoded size value for register programming + std::map<uint64_t, uint64_t>::const_iterator s; + uint64_t size_xlate; + // translate size into register encoding + s = i_bar_reg_def.xlate_map->find(i_addr_range.size); + if (s == i_bar_reg_def.xlate_map->end()) + { + FAPI_ERR("proc_setup_bars_common_write_bar_reg: Unsupported BAR size 0x%016llX", + i_addr_range.size); + const uint64_t& SIZE = i_addr_range.size; + FAPI_SET_HWP_ERROR(rc, RC_PROC_SETUP_BARS_SIZE_XLATE_ERR); + break; + } + size_xlate = s->second; + + rc_ecmd |= size_data.setDoubleWord(0, size_xlate); + rc_ecmd |= size_data.shiftLeft(63 - i_bar_reg_def.size_end_bit); + rc_ecmd |= bar_data.merge(size_data); + rc_ecmd |= bar_data_mask.setBit(i_bar_reg_def.size_start_bit, + (i_bar_reg_def.size_end_bit - + i_bar_reg_def.size_start_bit + 1)); + } + + // merge static data & mask + rc_ecmd |= static_data.setDoubleWord( + 0, + i_bar_reg_def.static_data); + rc_ecmd |= static_data_mask.setDoubleWord( + 0, + i_bar_reg_def.static_data_mask); + + rc_ecmd |= bar_data.merge(static_data); + rc_ecmd |= bar_data_mask.merge(static_data_mask); + + // check buffer manipulation return codes + if (rc_ecmd) + { + FAPI_ERR("proc_setup_bars_common_write_bar_reg: Error 0x%X setting up BAR data buffer", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + // write BAR register with updated content + rc = fapiPutScomUnderMask(i_target, + i_scom_addr, + bar_data, + bar_data_mask); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_common_f_scope_write_bar_reg: fapiPutScomUnderMask error (%08X)", + i_scom_addr); + break; + } + } while(0); + + FAPI_DBG("proc_setup_bars_common_write_bar_reg: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: write L3 BAR attributes (consumed by winkle image creation +// procedures) specific to enabled local chip +// non-mirrored/mirrored memory ranges +// parameters: i_target => chip target +// i_is_non_mirrored_range => boolean idenitfying range type +// (true=non-mirrored, false=mirrored) +// i_addr_range => structure representing chip +// non-mirrored/mirrored range +// returns: FAPI_RC_SUCCESS if attribute writes are successful, +// RC_PROC_SETUP_BARS_SIZE_XLATE_ERR if logical->physical size +// translation is unsuccessful, +// else failing return code from attribute/data buffer manipulation +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_setup_bars_l3_write_local_chip_memory_bar_attr( + const fapi::Target* i_target, + const bool& i_is_non_mirrored_range, + const proc_setup_bars_addr_range& i_addr_range) +{ + // return code + fapi::ReturnCode rc; + uint32_t rc_ecmd = 0; + // BAR1 register data buffer + ecmdDataBufferBase bar_data(64); + ecmdDataBufferBase bar_size_data(64); + uint64_t bar_attr_data; + + FAPI_DBG("proc_setup_bars_l3_write_local_chip_memory_bar_attr: Start"); + do + { + // previous checking ensures zeroes for all non-implemented bits + rc_ecmd |= bar_data.setDoubleWord(0, i_addr_range.base_addr); + rc_ecmd |= bar_data.shiftLeft(L3_BAR12_BASE_ADDR_LEFT_SHIFT_AMOUNT); + + // encoded size value for register programming + std::map<uint64_t, uint64_t>::const_iterator s; + uint64_t size_xlate; + // translate size into register encoding + s = proc_setup_bars_nf_bar_size::xlate_map.find(i_addr_range.size); + if (s == proc_setup_bars_nf_bar_size::xlate_map.end()) + { + FAPI_ERR("proc_setup_bars_l3_write_local_chip_memory_bar_attr: Unsupported BAR size 0x%016llX", + i_addr_range.size); + const uint64_t& SIZE = i_addr_range.size; + FAPI_SET_HWP_ERROR(rc, RC_PROC_SETUP_BARS_SIZE_XLATE_ERR); + break; + } + size_xlate = s->second; + rc_ecmd |= bar_size_data.setDoubleWord(0, size_xlate); + rc_ecmd |= bar_size_data.shiftLeft(63 - L3_BAR12_SIZE_END_BIT); + rc_ecmd |= bar_data.merge(bar_size_data); + + // enable bit only in BAR2 + if (!i_is_non_mirrored_range) + { + rc_ecmd |= bar_data.writeBit(L3_BAR2_ENABLE_BIT, + i_addr_range.enabled ? 1 : 0); + } + + // check buffer manipulation return codes + if (rc_ecmd) + { + FAPI_ERR("proc_setup_bars_l3_write_local_chip_memory_bar_attr: Error 0x%X setting up BAR data buffer", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + // set data for attribute push + bar_attr_data = bar_data.getDoubleWord(0); + + if (i_is_non_mirrored_range) + { + // L3 BAR1 (non-mirrored) + FAPI_DBG("proc_setup_bars_l3_write_local_chip_memory_bar_attr: Setting ATTR_PROC_L3_BAR1_REG = %016llX", + bar_attr_data); + rc = FAPI_ATTR_SET(ATTR_PROC_L3_BAR1_REG, + i_target, + bar_attr_data); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_l3_write_local_chip_memory_bar_attr: Error setting ATTR_PROC_L3_BAR1_REG"); + break; + } + } + else + { + // L3 BAR2 (mirrored) + FAPI_DBG("proc_setup_bars_l3_write_local_chip_memory_bar_attr: Setting ATTR_PROC_L3_BAR2_REG = %016llX", + bar_attr_data); + rc = FAPI_ATTR_SET(ATTR_PROC_L3_BAR2_REG, + i_target, + bar_attr_data); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_l3_write_local_chip_memory_bar_attr: Error setting ATTR_PROC_L3_BAR2_REG"); + break; + } + } + } while(0); + + FAPI_DBG("proc_setup_bars_l3_write_local_chip_memory_bar_attr: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: wrapper function to write PCIe BARs specific to enabled local +// chip non-mirrored/mirrored memory ranges +// parameters: i_target => chip target +// i_non_mirrored_range => structure representing chip non-mirrored +// address range +// i_mirrored_range => structure representing chip mirrored +// address range +// returns: FAPI_RC_SUCCESS if all register writes are successful, +// else failing return code from common BAR write function +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_setup_bars_pcie_write_local_chip_memory_bars( + const fapi::Target& i_target, + const proc_setup_bars_addr_range& i_non_mirrored_range, + const proc_setup_bars_addr_range& i_mirrored_range) +{ + // return code + fapi::ReturnCode rc; + + FAPI_DBG("proc_setup_bars_pcie_write_local_chip_memory_bars: Start"); + // loop over all units + for (uint8_t u = 0; + u < PROC_SETUP_BARS_PCIE_NUM_UNITS; + u++) + { + if (i_non_mirrored_range.enabled) + { + FAPI_DBG("proc_setup_bars_pcie_write_local_chip_memory_bars: Writing PCIe %d Nodal Non-Mirrored BAR register", + u); + rc = proc_setup_bars_common_write_bar_reg( + i_target, + PROC_SETUP_BARS_PCIE_CHIP_NON_MIRRORED_BAR[u], + common_nf_scope_bar_reg_def, + i_non_mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_pcie_write_local_chip_memory_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + if (i_mirrored_range.enabled) + { + FAPI_DBG("proc_setup_bars_pcie_write_local_chip_memory_bars: Writing PCIe %d Nodal Mirrored BAR register", + u); + rc = proc_setup_bars_common_write_bar_reg( + i_target, + PROC_SETUP_BARS_PCIE_CHIP_MIRRORED_BAR[u], + common_nf_scope_bar_reg_def, + i_mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_pcie_write_local_chip_memory_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + } + + FAPI_DBG("proc_setup_bars_pcie_write_local_chip_memory_bars: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: write L3 BAR attributes (consumed by winkle image creation +// procedures) specific to enabled local node +// non-mirrored/mirrored memory ranges +// parameters: i_target => chip target +// i_is_non_mirrored_range => boolean idenitfying range type +// (true=non-mirrored, false=mirrored) +// i_node_addr_range => structure representing node +// non-mirrored/mirrored range +// i_chip_addr_range => structure representing chip +// non-mirrored/mirrored range +// returns: FAPI_RC_SUCCESS if attribute writes are successful, +// else failing return code from attribute/data buffer manipulation +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_setup_bars_l3_write_local_node_memory_bar_attr( + const fapi::Target* i_target, + const bool& i_is_non_mirrored_range, + const proc_setup_bars_addr_range& i_node_addr_range, + const proc_setup_bars_addr_range& i_chip_addr_range) +{ + // return code + fapi::ReturnCode rc; + uint32_t rc_ecmd = 0; + ecmdDataBufferBase base(64); + ecmdDataBufferBase diff(64); + ecmdDataBufferBase mask(64); + uint64_t mask_attr = 0x0; + + FAPI_DBG("proc_setup_bars_l3_write_local_node_memory_bar_attr: Start"); + + do + { + // retrieve mask register attribute + rc = FAPI_ATTR_GET(ATTR_PROC_L3_BAR_GROUP_MASK_REG, + i_target, + mask_attr); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_l3_write_local_node_memory_bar_attr: Error querying ATTR_PROC_L3_BAR_GROUP_MASK_REG"); + break; + } + FAPI_DBG("proc_setup_bars_l3_write_local_node_memory_bar_attr: Read ATTR_PROC_L3_BAR_GROUP_MASK_REG = %016llX", + mask_attr); + // push current value into data buffer + rc_ecmd |= mask.setDoubleWord(0, mask_attr); + + // set group mask based on first difference between + // node start/end addresses + uint32_t first_diff_bit = 0; + // load base address + rc_ecmd |= base.setDoubleWord(0, i_node_addr_range.base_addr); + // load end address + rc_ecmd |= diff.setDoubleWord(0, i_node_addr_range.end_addr()); + // XOR base/end address + rc_ecmd |= diff.setXor(base, 0, 64); + + // walk range of XOR result over group mask, stop at first 1 found + bool match_found = false; + for (first_diff_bit = L3_BAR_GROUP_MASK_RA_DIFF_START_BIT; + first_diff_bit <= L3_BAR_GROUP_MASK_RA_DIFF_END_BIT; + first_diff_bit++) + { + if (diff.getBit(first_diff_bit)) + { + match_found = true; + break; + } + } + + if (match_found) + { + // set all group mask bits to a 1, starting from first bit which + // was found to be different, to the end of the mask range + uint32_t mask_set_start_bit = (i_is_non_mirrored_range)? + L3_BAR_GROUP_MASK_NON_MIRROR_MASK_START_BIT: + L3_BAR_GROUP_MASK_MIRROR_MASK_START_BIT; + + mask_set_start_bit += (first_diff_bit- + L3_BAR_GROUP_MASK_RA_DIFF_START_BIT); + + uint32_t mask_set_num_bits = (i_is_non_mirrored_range)? + L3_BAR_GROUP_MASK_NON_MIRROR_MASK_END_BIT: + L3_BAR_GROUP_MASK_MIRROR_MASK_END_BIT; + + mask_set_num_bits -= (mask_set_start_bit-1); + + rc_ecmd |= mask.setBit(mask_set_start_bit, + mask_set_num_bits); + } + + // enable bit only for mirorred region + if (!i_is_non_mirrored_range) + { + rc_ecmd |= mask.writeBit(L3_BAR_GROUP_MASK_MIRROR_ENABLE_BIT, + i_node_addr_range.enabled ? 1 : 0); + } + + // check buffer manipulation return codes + if (rc_ecmd) + { + FAPI_ERR("proc_setup_bars_l3_write_local_node_memory_bar_attr: Error 0x%X setting up BAR mask data buffer", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + // push current data buffer state back into attribute + mask_attr = mask.getDoubleWord(0); + FAPI_DBG("proc_setup_bars_l3_write_local_node_memory_bar_attr: Setting ATTR_PROC_L3_BAR_GROUP_MASK_REG = %016llX", + mask_attr); + rc = FAPI_ATTR_SET(ATTR_PROC_L3_BAR_GROUP_MASK_REG, + i_target, + mask_attr); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_l3_write_local_node_memory_bar_attr: Error setting ATTR_PROC_L3_BAR_GROUP_MASK_REG"); + break; + } + + // if no memory is installed on the local chip, fill the shared + // BAR address with the node base + if (!i_chip_addr_range.enabled) + { + // clear size mask + proc_setup_bars_addr_range base_addr_range = i_node_addr_range; + base_addr_range.size = PROC_SETUP_BARS_SIZE_4_GB; + + rc = proc_setup_bars_l3_write_local_chip_memory_bar_attr( + i_target, + i_is_non_mirrored_range, + base_addr_range); + + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_l3_write_local_node_memory_bar_attr: Error from proc_setup_bars_l3_write_local_chip_memory_bar_attr"); + break; + } + } + } while(0); + + + FAPI_DBG("proc_setup_bars_l3_write_local_node_memory_bar_attr: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: wrapper function to write PCIe BARs specific to enabled local +// node non-mirrored/mirrored memory ranges +// parameters: i_target => chip target +// i_non_mirrored_range => structure representing node non-mirrored +// address range +// i_mirrored_range => structure representing node mirrored +// address range +// returns: FAPI_RC_SUCCESS if all register writes are successful, +// else failing return code from common BAR write function +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_setup_bars_pcie_write_local_node_memory_bars( + const fapi::Target& i_target, + const proc_setup_bars_addr_range& i_non_mirrored_range, + const proc_setup_bars_addr_range& i_mirrored_range) +{ + // return code + fapi::ReturnCode rc; + + FAPI_DBG("proc_setup_bars_pcie_write_local_node_memory_bars: Start"); + // loop over all units + for (uint8_t u = 0; + u < PROC_SETUP_BARS_PCIE_NUM_UNITS; + u++) + { + if (i_non_mirrored_range.enabled) + { + FAPI_DBG("proc_setup_bars_pcie_write_local_node_memory_bars: Writing PCIe %d Group Non-Mirrored BAR register", + u); + rc = proc_setup_bars_common_write_bar_reg( + i_target, + PROC_SETUP_BARS_PCIE_NODE_NON_MIRRORED_BAR[u], + common_nf_scope_bar_reg_def, + i_non_mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_pcie_write_local_node_memory_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + if (i_mirrored_range.enabled) + { + FAPI_DBG("proc_setup_bars_pcie_write_local_node_memory_bars: Writing PCIe %d Group Mirrored BAR register", + u); + rc = proc_setup_bars_common_write_bar_reg( + i_target, + PROC_SETUP_BARS_PCIE_NODE_MIRRORED_BAR[u], + common_nf_scope_bar_reg_def, + i_mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_pcie_write_local_node_memory_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + } + + FAPI_DBG("proc_setup_bars_pcie_write_local_node_memory_bars: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: wrapper function to write PCIe BARs specific to enabled local +// chip near/far foreign memory ranges +// NOTE: only links which are marked for processing will be acted on +// parameters: i_target => chip target +// i_process_links => array of boolean values dictating which +// links should be acted on (one per link) +// i_foreign_near_ranges => array of structures representing +// near foreign address range (one per link) +// i_foreign_far_ranges => array of structures representing +// far foreign address range (one per link) +// returns: FAPI_RC_SUCCESS if all register writes are successful, +// else failing return code from common BAR write function +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_setup_bars_pcie_write_foreign_memory_bars( + const fapi::Target& i_target, + const bool i_process_links[PROC_FAB_SMP_NUM_F_LINKS], + const proc_setup_bars_addr_range i_foreign_near_ranges[PROC_FAB_SMP_NUM_F_LINKS], + const proc_setup_bars_addr_range i_foreign_far_ranges[PROC_FAB_SMP_NUM_F_LINKS]) +{ + // return code + fapi::ReturnCode rc; + + FAPI_DBG("proc_setup_bars_pcie_write_foreign_memory_bars: Start"); + + // loop over all units + for (uint8_t u = 0; + (u < PROC_SETUP_BARS_PCIE_NUM_UNITS) && (rc.ok()); + u++) + { + // process ranges + for (uint8_t r = 0; + (r < PROC_FAB_SMP_NUM_F_LINKS) && (rc.ok()); + r++) + { + if (i_foreign_near_ranges[r].enabled && i_process_links[r]) + { + FAPI_DBG("proc_setup_bars_pcie_write_foreign_memory_bars: Writing PCIe %d Foreign F%d Near BAR register", + u, r); + rc = proc_setup_bars_common_write_bar_reg( + i_target, + PROC_SETUP_BARS_PCIE_FOREIGN_NEAR_BAR[u][r], + common_f_scope_bar_reg_def, + i_foreign_near_ranges[r]); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_pcie_write_foreign_memory_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + if (i_foreign_far_ranges[r].enabled && i_process_links[r]) + { + FAPI_DBG("proc_setup_bars_pcie_write_foreign_memory_bars: Writing PCIe %d Foreign F%d Far BAR register", + u, r); + rc = proc_setup_bars_common_write_bar_reg( + i_target, + PROC_SETUP_BARS_PCIE_FOREIGN_FAR_BAR[u][r], + common_f_scope_bar_reg_def, + i_foreign_far_ranges[r]); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_pcie_write_foreign_memory_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + } + } + + FAPI_DBG("proc_setup_bars_pcie_write_foreign_memory_bars: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: wrapper function to write enabled PCIe IO BARs +// parameters: i_target => chip target +// io_addr_ranges => 2D array of address range structures +// encapsulating attribute values +// (first dimension = unit, second dimension = +// links per unit) +// returns: FAPI_RC_SUCCESS if all register writes are successful, +// else failing return code from common BAR write function or +// data buffer manipulation +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_setup_bars_pcie_write_io_bar_regs( + const fapi::Target& i_target, + const proc_setup_bars_addr_range addr_ranges[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT]) +{ + // return code + fapi::ReturnCode rc; + uint32_t rc_ecmd = 0; + + FAPI_DBG("proc_setup_bars_pcie_write_io_bar_regs: Start"); + // loop over all units + for (uint8_t u = 0; + u < PROC_SETUP_BARS_PCIE_NUM_UNITS; + u++) + { + // enable bit/mask bit per range + ecmdDataBufferBase enable_data(64); + ecmdDataBufferBase enable_mask(64); + + // loop over all ranges + for (uint8_t r = 0; + r < PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT; + r++) + { + if (addr_ranges[u][r].enabled) + { + // MMIO range (BAR + mask) + if (PROC_SETUP_BARS_PCIE_RANGE_TYPE_MMIO[r]) + { + // write BAR register + FAPI_DBG("proc_setup_bars_pcie_write_io_bar_regs: Writing PCIe %d MMIO BAR%d register", + u, r); + rc = proc_setup_bars_common_write_bar_reg( + i_target, + PROC_SETUP_BARS_PCIE_BAR_REGS_MMIO[u][r], + pcie_mmio_bar_reg_def, + addr_ranges[u][r]); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_pcie_write_io_bar_regs: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + + // write BAR mask register + FAPI_DBG("proc_setup_bars_pcie_write_io_bar_regs: Writing PCIe %d MMIO BAR%d Mask register", + u, r); + rc = proc_setup_bars_common_write_bar_reg( + i_target, + PROC_SETUP_BARS_PCIE_BAR_MASK_REGS_MMIO[u][r], + pcie_mmio_bar_mask_reg_def, + addr_ranges[u][r]); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_pcie_write_io_bar_regs: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + // PHB range (only BAR, mask is implied) + else + { + for (uint8_t i = 0; + i < PROC_SETUP_BARS_PCIE_REGS_PER_PHB_RANGE; + i++) + { + FAPI_DBG("proc_setup_bars_pcie_write_io_bar_regs: Writing PCIe %d PHB BAR (%s) register", + u, (i == 0)?("Nest"):("PCIe")); + rc = proc_setup_bars_common_write_bar_reg( + i_target, + PROC_SETUP_BARS_PCIE_BAR_REGS_PHB[u][i], + pcie_phb_bar_reg_def, + addr_ranges[u][r]); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_pcie_write_io_bar_regs: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + } + // set enable bit data/mask + rc_ecmd |= enable_data.setBit( + PROC_SETUP_BARS_PCIE_BAR_EN_BIT[r]); + rc_ecmd |= enable_mask.setBit( + PROC_SETUP_BARS_PCIE_BAR_EN_BIT[r]); + // check buffer manipulation return codes + if (rc_ecmd) + { + FAPI_ERR("proc_setup_bars_pcie_write_io_bar_regs: Error 0x%X setting up BAR Enable data buffer", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + } + } + if (!rc.ok()) + { + break; + } + + if (enable_data.getDoubleWord(0) != 0x0ULL) + { + // set static data field with BAR enable bits + proc_setup_bars_bar_reg_def pcie_bar_en_reg_def = + { + false, // base: other reg + PROC_SETUP_BARS_SHIFT_NONE, + 0, + 0, + 0, + false, // enable: static data + 0, + false, // size: other reg + 0, + 0, + NULL, + enable_data.getDoubleWord(0), + enable_mask.getDoubleWord(0) + }; + proc_setup_bars_addr_range pcie_bar_en_dummy_range; + + // write BAR enable register (do last, when all unit BAR content is set) + rc = proc_setup_bars_common_write_bar_reg( + i_target, + PROC_SETUP_BARS_PCIE_BAR_EN_REGS[u], + pcie_bar_en_reg_def, + pcie_bar_en_dummy_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_pcie_write_io_bar_regs: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + } + + FAPI_DBG("proc_setup_bars_pcie_write_io_bar_regs: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: wrapper function to write all BARs tied to local chip region +// (non-mirrored/mirrored/MMIO regions) +// parameters: i_smp_chip => structure encapsulating single chip in SMP topology +// returns: FAPI_RC_SUCCESS if all register writes are successful, +// else failing return code from common BAR write function +//------------------------------------------------------------------------------ +// +// Local chip region BARs: +// +// PSI/FSP +// PSI Bridge BAR (PSI_BRIDGE_BAR_0x0201090A) +// FSP BAR (PSI_FSP_BAR_0x0201090B) +// FSP Memory Mask (PSI_FSP_MMR_0x0201090C) +// FSP MMIO Mask (PSI_BRIDGE_STATUS_CTL_0x0201090E) +// +// INTP +// INTP BAR (ICP_BAR_0x020109CA) +// +// L3 (transmitted via attributes) +// L3 BAR1 (Non-Mirrored) (EX_L3_BAR1_0x1001080B) +// L3 BAR2 (Mirrored) (EX_L3_BAR2_0x10010813) +// +// NX +// NX MMIO BAR (NX_MMIO_BAR_0x0201308D) +// NX APC Nodal Non-Mirrored BAR (NX_APC_NODAL_BAR0_0x0201302D) +// NX Nodal Non-Mirrored BAR (NX_NODAL_BAR0_0x02013095) +// NX APC Nodal Mirrored BAR (NX_APC_NODAL_BAR1_0x0201302E) +// NX Nodal Mirrored BAR (NX_NODAL_BAR1_0x02013096) +// +// MCD +// MCD Configuration 0 (Non-Mirrored) (MCD_CN00_0x0201340C) +// MCD Configuration 1 (Mirrored) (MCD_CN01_0x0201340D) +// +// PCIe +// PCIE0 Nodal Non-Mirrored BAR (PCIE0_NODAL_BAR0_0x02012010) +// PCIE0 Nodal Mirrored BAR (PCIE0_NODAL_BAR1_0x02012011) +// PCIE0 IO BAR0 (PCIE0_IO_BAR0_0x02012040) +// PCIE0 IO BAR0 Mask (PCIE0_IO_MASK0_0x02012043) +// PCIE0 IO BAR1 (PCIE0_IO_BAR1_0x02012041) +// PCIE0 IO BAR1 Mask (PCIE0_IO_MASK1_0x02012044) +// PCIE0 IO BAR2 (PCIE0_IO_BAR2_0x02012042) +// PCIE0 IO BAR Enable (PCIE0_IO_BAR_EN_0x02012045) +// +// PCIE1 Nodal Non-Mirrored BAR (PCIE1_NODAL_BAR0_0x02012410) +// PCIE1 Nodal Mirrored BAR (PCIE1_NODAL_BAR1_0x02012411) +// PCIE1_IO BAR0 (PCIE1_IO_BAR0_0x02012440) +// PCIE1_IO BAR0 Mask (PCIE1_IO_MASK0_0x02012443) +// PCIE1_IO BAR1 (PCIE1_IO_BAR1_0x02012441) +// PCIE1_IO BAR1 Mask (PCIE1_IO_MASK1_0x02012444) +// PCIE1_IO BAR2 (PCIE1_IO_BAR2_0x02012442) +// PCIE1_IO BAR Enable (PCIE1_IO_BAR_EN_0x02012445) +// +// PCIE2 Nodal Non-Mirrored BAR (PCIE2_NODAL_BAR0_0x02012810) +// PCIE2 Nodal Mirrored BAR (PCIE2_NODAL_BAR1_0x02012811) +// PCIE2 IO BAR0 (PCIE2_IO_BAR0_0x02012840) +// PCIE2 IO BAR0 Mask (PCIE2_IO_MASK0_0x02012843) +// PCIE2 IO BAR1 (PCIE2_IO_BAR1_0x02012841) +// PCIE2 IO BAR1 Mask (PCIE2_IO_MASK1_0x02012844) +// PCIE2 IO BAR2 (PCIE2_IO_BAR2_0x02012842) +// PCIE2 IO BAR Enable (PCIE2_IO_BAR_EN_0x02012845) +// +//------------------------------------------------------------------------------ +fapi::ReturnCode +proc_setup_bars_write_local_chip_region_bars( + proc_setup_bars_smp_chip& i_smp_chip) +{ + // return code + fapi::ReturnCode rc; + + FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Start"); + + do + { + // PSI + if (i_smp_chip.psi_range.enabled) + { + FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing PSI Bridge BAR register"); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + PSI_BRIDGE_BAR_0x0201090A, + psi_bridge_bar_reg_def, + i_smp_chip.psi_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + + // FSP + if (i_smp_chip.fsp_range.enabled) + { + FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing FSP BAR register"); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + PSI_FSP_BAR_0x0201090B, + fsp_bar_reg_def, + i_smp_chip.fsp_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + + FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing FSP Memory Mask register"); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + PSI_FSP_MMR_0x0201090C, + fsp_bar_mask_reg_def, + i_smp_chip.fsp_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + + FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing PSI Bridge Status Control register (FSP BAR enable)"); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + PSI_BRIDGE_STATUS_CTL_0x0201090E, + fsp_bar_en_reg_def, + i_smp_chip.fsp_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + + if (i_smp_chip.fsp_mmio_mask_range.enabled) + { + FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing PSI Bridge Status Control register (FSP MMIO mask)"); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + PSI_BRIDGE_STATUS_CTL_0x0201090E, + fsp_mmio_mask_reg_def, + i_smp_chip.fsp_mmio_mask_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + } + + // INTP + if (i_smp_chip.intp_range.enabled) + { + FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing INTP BAR register"); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + ICP_BAR_0x020109CA, + intp_bar_reg_def, + i_smp_chip.intp_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + + // NX (MMIO) + if (i_smp_chip.nx_mmio_range.enabled) + { + FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NX MMIO BAR register"); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + NX_MMIO_BAR_0x0201308D, + nx_mmio_bar_reg_def, + i_smp_chip.nx_mmio_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + + // NX (non-mirrored) + if (i_smp_chip.non_mirrored_range.enabled) + { + FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NX APC Nodal Non-Mirrored BAR register"); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + NX_APC_NODAL_BAR0_0x0201302D, + common_nf_scope_bar_reg_def, + i_smp_chip.non_mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + + FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NX Nodal Non-Mirrored BAR register"); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + NX_NODAL_BAR0_0x02013095, + common_nf_scope_bar_reg_def, + i_smp_chip.non_mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + + // NX (mirrored) + if (i_smp_chip.mirrored_range.enabled) + { + FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NX APC Nodal Mirrored BAR register"); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + NX_APC_NODAL_BAR1_0x0201302E, + common_nf_scope_bar_reg_def, + i_smp_chip.mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + + FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NX Nodal Mirrored BAR register"); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + NX_NODAL_BAR1_0x02013096, + common_nf_scope_bar_reg_def, + i_smp_chip.mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + + // MCD (non-mirrored) + // TODO: potential optimization if DSMP links are known to be disabled? + if (i_smp_chip.non_mirrored_range.enabled) + { + FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing MCD Configuration 0 (Non-Mirrored) register"); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + MCD_CN00_0x0201340C, + mcd_nf_bar_reg_def, + i_smp_chip.non_mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + + // MCD (mirrored) + // TODO: potential optimization if DSMP links are known to be disabled? + if (i_smp_chip.mirrored_range.enabled) + { + FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing MCD Configuration 1 (Mirrored) register"); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + MCD_CN01_0x0201340D, + mcd_nf_bar_reg_def, + i_smp_chip.mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + + // L3 (non-mirrored) + if (i_smp_chip.non_mirrored_range.enabled) + { + FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing L3 BAR1 (Non-Mirrored) attribute"); + rc = proc_setup_bars_l3_write_local_chip_memory_bar_attr( + &(i_smp_chip.chip->this_chip), + true, + i_smp_chip.non_mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_l3_write_local_chip_memory_bar_attr"); + break; + } + } + + // L3 (mirrored) + if (i_smp_chip.mirrored_range.enabled) + { + FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing L3 BAR2 (Mirrored) attribute"); + rc = proc_setup_bars_l3_write_local_chip_memory_bar_attr( + &(i_smp_chip.chip->this_chip), + false, + i_smp_chip.mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_l3_write_local_chip_memory_bar_attr"); + break; + } + } + + // PCIe (non-mirrored/mirrored) + rc = proc_setup_bars_pcie_write_local_chip_memory_bars( + i_smp_chip.chip->this_chip, + i_smp_chip.non_mirrored_range, + i_smp_chip.mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_pcie_write_local_chip_memory_bars"); + break; + } + + // PCIe (IO) + rc = proc_setup_bars_pcie_write_io_bar_regs( + i_smp_chip.chip->this_chip, + i_smp_chip.pcie_ranges); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_pcie_write_io_bar_regs"); + break; + } + } while(0); + + FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: wrapper function to write all BARs tied to local node region +// (non-mirrored/mirrored regions) +// parameters: i_smp_chip => structure encapsulating single chip in SMP topology +// i_smp_node => structure encapsulating node which this chip +// resides in +// returns: FAPI_RC_SUCCESS if all register writes are successful, +// else failing return code from common BAR write function +//------------------------------------------------------------------------------ +// +// Local node region BARs: +// +// L3 (transmitted via attributes) +// L3 BAR Group Mask (EX_L3_BAR_GROUP_MASK_0x10010816) +// +// NX +// NX APC Group Non-Mirorred BAR (NX_APC_GROUP_BAR0_0x0201302F) +// NX Group Non-Mirorred BAR (NX_GROUP_BAR0_0x02013097) +// NX APC Group Mirrored BAR (NX_APC_GROUP_BAR1_0x02013030) +// NX Group Mirrored BAR (NX_GROUP_BAR1_0x02013098) +// +// PCIe +// PCIE0 Group Non-Mirrored BAR (PCIE0_GROUP_BAR0_0x02012012) +// PCIE0 Group Mirrored BAR (PCIE0_GROUP_BAR1_0x02012013) +// +// PCIE1 Group Non-Mirrored BAR (PCIE1_GROUP_BAR0_0x02012412) +// PCIE1 Group Mirrored BAR (PCIE1_GROUP_BAR1_0x02012413) +// +// PCIE2 Group Non-Mirrored BAR (PCIE2_GROUP_BAR0_0x02012812) +// PCIE2 Group Mirrored BAR (PCIE2_GROUP_BAR1_0x02012813) +// +//------------------------------------------------------------------------------ +fapi::ReturnCode +proc_setup_bars_write_local_node_region_bars( + proc_setup_bars_smp_chip& i_smp_chip, + proc_setup_bars_smp_node& i_smp_node) +{ + // return code + fapi::ReturnCode rc; + + FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Start"); + + do + { + // NX (non-mirrored) + if (i_smp_node.non_mirrored_range.enabled) + { + FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NX APC Group Non-Mirrored BAR register"); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + NX_APC_GROUP_BAR0_0x0201302F, + common_nf_scope_bar_reg_def, + i_smp_node.non_mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + + FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NX Group Non-Mirrored BAR register"); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + NX_GROUP_BAR0_0x02013097, + common_nf_scope_bar_reg_def, + i_smp_node.non_mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + + // NX (mirrored) + if (i_smp_node.mirrored_range.enabled) + { + FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NX APC Group Mirrored BAR register"); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + NX_APC_GROUP_BAR1_0x02013030, + common_nf_scope_bar_reg_def, + i_smp_node.mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + + FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NX Group Mirrored BAR register"); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + NX_GROUP_BAR1_0x02013098, + common_nf_scope_bar_reg_def, + i_smp_node.mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + + // L3 (non-mirrored) + if (i_smp_node.non_mirrored_range.enabled) + { + rc = proc_setup_bars_l3_write_local_node_memory_bar_attr( + &(i_smp_chip.chip->this_chip), + true, + i_smp_node.non_mirrored_range, + i_smp_chip.non_mirrored_range); + + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_l3_write_local_node_memory_bar_attr"); + break; + } + } + + // L3 (mirrored) + if (i_smp_node.mirrored_range.enabled) + { + rc = proc_setup_bars_l3_write_local_node_memory_bar_attr( + &(i_smp_chip.chip->this_chip), + false, + i_smp_node.mirrored_range, + i_smp_chip.mirrored_range); + + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_l3_write_local_node_memory_bar_attr"); + break; + } + } + + // PCIe (non-mirrored/mirrored) + rc = proc_setup_bars_pcie_write_local_node_memory_bars( + i_smp_chip.chip->this_chip, + i_smp_node.non_mirrored_range, + i_smp_node.mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_pcie_write_local_node_memory_bars"); + break; + } + } while(0); + + FAPI_DBG("proc_setup_bars_write_local_node_region_bars: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: wrapper function to write all BARs tied to remote node regions +// (non-mirrored/mirrored regions) +// parameters: i_smp_chip => structure encapsulating single chip in SMP +// topology +// i_smp_node_a0 => structure encapsulating node reachable from +// A0 link on this chip +// i_smp_node_a1 => structure encapsulating node reachable from +// A1 link on this chip +// i_smp_node_a2 => structure encapsulating node reachable from +// A2 link on this chip +// returns: FAPI_RC_SUCCESS if all register writes are successful, +// else failing return code from common BAR write function +//------------------------------------------------------------------------------ +// +// Remote node region BARs: +// +// PB +// PB Remote Group (A0) Non-Mirrored BAR (PB_RGMCFG00_0x02010C58) +// PB Remote Group (A0) Mirrored BAR (PB_RGMCFGM00_0x02010C5B) +// PB Remote Group (A1) Non-Mirrored BAR (PB_RGMCFG01_0x02010C59) +// PB Remote Group (A1) Mirrored BAR (PB_RGMCFGM01_0x02010C5C) +// PB Remote Group (A2) Non-Mirrored BAR (PB_RGMCFG10_0x02010C5A) +// PB Remote Group (A2) Mirrored BAR (PB_RGMCFGM10_0x02010C5D) +// +//------------------------------------------------------------------------------ +fapi::ReturnCode +proc_setup_bars_write_remote_node_region_bars( + proc_setup_bars_smp_chip& i_smp_chip, + proc_setup_bars_smp_node& i_smp_node_a0, + proc_setup_bars_smp_node& i_smp_node_a1, + proc_setup_bars_smp_node& i_smp_node_a2) +{ + // return code + fapi::ReturnCode rc; + + FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: Start"); + + do + { + // A0 (non-mirrored) + if (i_smp_node_a0.non_mirrored_range.enabled) + { + FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: Writing PB Remote Group (A0) Non-Mirrored Configuration register"); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + PB_RGMCFG00_0x02010C58, + common_nf_scope_bar_reg_def, + i_smp_node_a0.non_mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_remote_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + + // A0 (mirrored) + if (i_smp_node_a0.mirrored_range.enabled) + { + FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: Writing PB Remote Group (A0) Mirrored Configuration register"); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + PB_RGMCFGM00_0x02010C5B, + common_nf_scope_bar_reg_def, + i_smp_node_a0.mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_remote_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + + // A1 (non-mirrored) + if (i_smp_node_a1.non_mirrored_range.enabled) + { + FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: Writing PB Remote Group (A1) Non-Mirrored Configuration register"); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + PB_RGMCFG01_0x02010C59, + common_nf_scope_bar_reg_def, + i_smp_node_a1.non_mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_remote_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + + // A1 (mirrored) + if (i_smp_node_a1.mirrored_range.enabled) + { + FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: Writing PB Remote Group (A1) Mirrored Configuration register"); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + PB_RGMCFGM01_0x02010C5C, + common_nf_scope_bar_reg_def, + i_smp_node_a1.mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_remote_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + + // A2 (non-mirrored) + if (i_smp_node_a2.non_mirrored_range.enabled) + { + FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: Writing PB Remote Group (A2) Non-Mirrored Configuration register"); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + PB_RGMCFG10_0x02010C5A, + common_nf_scope_bar_reg_def, + i_smp_node_a2.non_mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_remote_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + + // A2 (mirrored) + if (i_smp_node_a2.mirrored_range.enabled) + { + FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: Writing PB Remote Group (A2) Mirrored Configuration register"); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + PB_RGMCFGM10_0x02010C5D, + common_nf_scope_bar_reg_def, + i_smp_node_a2.mirrored_range); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_remote_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + } while(0); + + FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: wrapper function to write all BARs tied to local chip foreign +// regions (near/far) +// parameters: i_smp_chip => structure encapsulating single chip in SMP +// topology +// returns: FAPI_RC_SUCCESS if all register writes are successful, +// else failing return code from common BAR write function +//------------------------------------------------------------------------------ +// +// Foreign region BARs: +// +// PB +// PB F0 Near BAR (West) (PB_FLMCFG0_WEST_0x02010C12) +// PB F0 Near BAR (Center) (PB_FLMCFG0_CENT_0x02010C5E) +// PB F0 Near BAR (East) (PB_FLMCFG0_EAST_0x02010C92) +// PB F0 Far BAR (West) (PB_FRMCFG0_WEST_0x02010C14) +// PB F0 Far BAR (Center) (PB_FRMCFG0_CENT_0x02010C60) +// PB F0 Far BAR (East) (PB_FRMCFG0_EAST_0x02010C94) +// PB F1 Near BAR (West) (PB_FLMCFG1_WEST_0x02010C13) +// PB F1 Near BAR (Center) (PB_FLMCFG1_CENT_0x02010C5F) +// PB F1 Near BAR (East) (PB_FLMCFG1_EAST_0x02010C93) +// PB F1 Far BAR (West) (PB_FRMCFG1_WEST_0x02010C15) +// PB F1 Far BAR (Center) (PB_FRMCFG1_CENT_0x02010C61) +// PB F1 Far BAR (East) (PB_FRMCFG1_EAST_0x02010C95) +// +// NX +// NX APC F0 Near BAR (NX_APC_NEAR_BAR_F0_0x02013031) +// NX APC F0 Far BAR (NX_APC_FAR_BAR_F0_0x02013032) +// NX APC F1 Near BAR (NX_APC_NEAR_BAR_F1_0x02013033) +// NX APC F1 Far BAR (NX_APC_FAR_BAR_F1_0x02013034) +// NX F0 Near BAR (NX_NEAR_BAR_F0_0x02013099) +// NX F0 Far BAR (NX_FAR_BAR_F0_0x0201309A) +// NX F1 Near BAR (NX_NEAR_BAR_F1_0x0201309B) +// NX F1 Far BAR (NX_FAR_BAR_F1_0x0201309C) +// +// MCD +// MCD Configuration 2 (F0) (MCD_CN10_0x0201340E) +// MCD Configuration 3 (F1) (MCD_CN11_0x0201340F) +// +// PCIe +// PCIE0 F0 Near BAR (PCIE0_NEAR_BAR_F0_0x02012014) +// PCIE0 F0 Far BAR (PCIE0_FAR_BAR_F0_0x02012015) +// PCIE0 F1 Near BAR (PCIE0_NEAR_BAR_F1_0x02012016) +// PCIE0 F1 Far BAR (PCIE0_FAR_BAR_F1_0x02012017) +// +// PCIE1 F0 Near BAR (PCIE1_NEAR_BAR_F0_0x02012414) +// PCIE1 F0 Far BAR (PCIE1_FAR_BAR_F0_0x02012415) +// PCIE1 F1 Near BAR (PCIE1_NEAR_BAR_F1_0x02012416) +// PCIE1 F1 Far BAR (PCIE1_FAR_BAR_F1_0x02012417) +// +// PCIE2 F0 Near BAR (PCIE2_NEAR_BAR_F0_0x02012484) +// PCIE2 F0 Far BAR (PCIE2_FAR_BAR_F0_0x02012815) +// PCIE2 F1 Near BAR (PCIE2_NEAR_BAR_F1_0x02012816) +// PCIE2 F1 Far BAR (PCIE2_FAR_BAR_F1_0x02012817) +// +//------------------------------------------------------------------------------ +fapi::ReturnCode +proc_setup_bars_write_foreign_region_bars( + proc_setup_bars_smp_chip& i_smp_chip) +{ + // return code + fapi::ReturnCode rc; + + FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Start"); + + do + { + bool process_links[PROC_FAB_SMP_NUM_F_LINKS] = + { + i_smp_chip.chip->process_f0, + i_smp_chip.chip->process_f1 + }; + + // PCIe (near/far) + rc = proc_setup_bars_pcie_write_foreign_memory_bars( + i_smp_chip.chip->this_chip, + process_links, + i_smp_chip.foreign_near_ranges, + i_smp_chip.foreign_far_ranges); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_pcie_write_foreign_memory_bars"); + break; + } + + // process ranges + for (uint8_t r = 0; + (r < PROC_FAB_SMP_NUM_F_LINKS) && (rc.ok()); + r++) + { + // near + if (process_links[r] && + i_smp_chip.foreign_near_ranges[r].enabled) + { + // PB (near, west) + FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing PB F%d Near BAR (West) register", + r); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + (r == 0)? + PB_FLMCFG0_WEST_0x02010C12: + PB_FLMCFG1_WEST_0x02010C13, + common_f_scope_bar_reg_def, + i_smp_chip.foreign_near_ranges[r]); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + + // PB (near, cent) + FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing PB F%d Near BAR (Center) register", + r); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + (r == 0)? + PB_FLMCFG0_CENT_0x02010C5E: + PB_FLMCFG1_CENT_0x02010C5F, + common_f_scope_bar_reg_def, + i_smp_chip.foreign_near_ranges[r]); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + + // PB (near, east) + FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing PB F%d Near BAR (East) register", + r); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + (r == 0)? + PB_FLMCFG0_EAST_0x02010C92: + PB_FLMCFG1_EAST_0x02010C93, + common_f_scope_bar_reg_def, + i_smp_chip.foreign_near_ranges[r]); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + + // NX APC (near) + FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX APC F%d Near BAR register", + r); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + (r == 0)? + NX_APC_NEAR_BAR_F0_0x02013031: + NX_APC_NEAR_BAR_F1_0x02013033, + common_f_scope_bar_reg_def, + i_smp_chip.foreign_near_ranges[r]); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + + // NX (near) + FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX F%d Near BAR register", + r); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + (r == 0)? + NX_NEAR_BAR_F0_0x02013099: + NX_NEAR_BAR_F1_0x0201309B, + common_f_scope_bar_reg_def, + i_smp_chip.foreign_near_ranges[r]); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + + // MCD (near only) + FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing MCD Configuration %d (F%d) register", + r+1, r); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + (r == 0)? + MCD_CN10_0x0201340E: + MCD_CN11_0x0201340F, + (r == 0)? + mcd_f0_bar_reg_def: + mcd_f1_bar_reg_def, + i_smp_chip.foreign_near_ranges[r]); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + + // far + if (process_links[r] && + i_smp_chip.foreign_near_ranges[r].enabled) + { + // PB (far, west) + FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing PB F%d Far BAR (West) register", + r); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + (r == 0)? + PB_FRMCFG0_WEST_0x02010C14: + PB_FRMCFG1_WEST_0x02010C15, + common_f_scope_bar_reg_def, + i_smp_chip.foreign_far_ranges[r]); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + + // PB (far, center) + FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing PB F%d Far BAR (Center) register", + r); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + (r == 0)? + PB_FRMCFG0_CENT_0x02010C60: + PB_FRMCFG1_CENT_0x02010C61, + common_f_scope_bar_reg_def, + i_smp_chip.foreign_far_ranges[r]); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + + // PB (far, east) + FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing PB F%d Far BAR (East) register", + r); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + (r == 0)? + PB_FRMCFG0_EAST_0x02010C94: + PB_FRMCFG1_EAST_0x02010C95, + common_f_scope_bar_reg_def, + i_smp_chip.foreign_far_ranges[r]); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + + // NX APC (far) + FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX APC F%d Far BAR register", + r); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + (r == 0)? + NX_APC_FAR_BAR_F0_0x02013032: + NX_APC_FAR_BAR_F1_0x02013034, + common_f_scope_bar_reg_def, + i_smp_chip.foreign_far_ranges[r]); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + + // NX (far) + FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX F%d Far BAR register", + r); + rc = proc_setup_bars_common_write_bar_reg( + i_smp_chip.chip->this_chip, + (r == 0)? + NX_FAR_BAR_F0_0x0201309A: + NX_FAR_BAR_F1_0x0201309C, + common_f_scope_bar_reg_def, + i_smp_chip.foreign_far_ranges[r]); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); + break; + } + } + } + } while(0); + + FAPI_DBG("proc_setup_bars_write_foreign_region_bars: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: utility function to find node structure associated with a given +// target +// parameters: i_target => chip target +// i_smp => structure encapsulating SMP topology +// o_node => node structure associated with chip target input +// returns: FAPI_RC_SUCCESS if matching node is found +// RC_PROC_SETUP_BARS_NODE_FIND_INTERNAL_ERR if node map lookup is +// unsuccessful, +// else failing return code from node ID attribute query function +//------------------------------------------------------------------------------ +fapi::ReturnCode +proc_setup_bars_find_node( + const fapi::Target& i_target, + proc_setup_bars_smp_system& i_smp, + proc_setup_bars_smp_node& o_node) +{ + // return code + fapi::ReturnCode rc; + proc_fab_smp_node_id node_id; + + FAPI_DBG("proc_setup_bars_find_node: Start"); + + do + { + // get node ID attribute + FAPI_DBG("proc_setup_find_node: Querying node ID attribute"); + rc = proc_fab_smp_get_node_id_attr(&(i_target), + node_id); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_process_chip: Error from proc_fab_smp_get_node_id_attr"); + break; + } + + // search to see if node structure already exists for the node ID + // associated with this chip + std::map<proc_fab_smp_node_id, proc_setup_bars_smp_node>::iterator + n_iter; + n_iter = i_smp.nodes.find(node_id); + // no match node found, exit + if (n_iter == i_smp.nodes.end()) + { + FAPI_ERR("proc_setup_bars_process_chip: insert_chip: Error encountered finding node in SMP"); + FAPI_SET_HWP_ERROR(rc, + RC_PROC_SETUP_BARS_NODE_FIND_INTERNAL_ERR); + break; + } + o_node = n_iter->second; + } while(0); + + FAPI_DBG("proc_setup_bars_find_node: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: wrapper function to write all chip BARs +// parameters: i_smp => structure encapsulating fully +// specified SMP topology +// i_init_local_chip_local_node => boolean qualifying application +// of local chip/local node range +// specific BAR resources +// returns: FAPI_RC_SUCCESS if all register writes are successful, +// else failing return code from lower level BAR write/node search +// functions +//------------------------------------------------------------------------------ +fapi::ReturnCode +proc_setup_bars_write_bars( + proc_setup_bars_smp_system& i_smp, + const bool& i_init_local_chip_local_node) +{ + // return code + fapi::ReturnCode rc; + std::map<proc_fab_smp_node_id, proc_setup_bars_smp_node>::iterator n_iter; + std::map<proc_fab_smp_chip_id, proc_setup_bars_smp_chip>::iterator p_iter; + + FAPI_DBG("proc_setup_bars_write_bars: Start"); + + do + { + for (n_iter = i_smp.nodes.begin(); + (n_iter != i_smp.nodes.end()) && (rc.ok()); + n_iter++) + { + for (p_iter = n_iter->second.chips.begin(); + (p_iter != n_iter->second.chips.end()) && (rc.ok()); + p_iter++) + { + // init local chip/local node resources? + if (i_init_local_chip_local_node) + { + rc = proc_setup_bars_write_local_chip_region_bars( + p_iter->second); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_bars: Error from proc_setup_bars_write_local_chip_region_bars"); + break; + } + + rc = proc_setup_bars_write_local_node_region_bars( + p_iter->second, + n_iter->second); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_bars: Error from proc_setup_bars_write_local_node_region_bars"); + break; + } + } + + // determine which remote node ranges should be initialized + proc_setup_bars_smp_node smp_node_a0; + proc_setup_bars_smp_node smp_node_a1; + proc_setup_bars_smp_node smp_node_a2; + if (p_iter->second.chip->a0_chip.getType() != fapi::TARGET_TYPE_NONE) + { + rc = proc_setup_bars_find_node( + p_iter->second.chip->a0_chip, + i_smp, + smp_node_a0); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_write_bars: Error from proc_setup_bars_find_node"); + break; + } + } + if (p_iter->second.chip->a1_chip.getType() != fapi::TARGET_TYPE_NONE) + { + rc = proc_setup_bars_find_node( + p_iter->second.chip->a1_chip, + i_smp, + smp_node_a1); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_write_bars: Error from proc_setup_bars_find_node"); + break; + } + } + if (p_iter->second.chip->a2_chip.getType() != fapi::TARGET_TYPE_NONE) + { + rc = proc_setup_bars_find_node( + p_iter->second.chip->a2_chip, + i_smp, + smp_node_a2); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_write_bars: Error from proc_setup_bars_find_node"); + break; + } + } + + // initialize remote node related ranges + rc = proc_setup_bars_write_remote_node_region_bars( + p_iter->second, + smp_node_a0, + smp_node_a1, + smp_node_a2); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_bars: Error from proc_setup_bars_write_remote_node_region_bars"); + break; + } + + // initialize foreign link related regions + rc = proc_setup_bars_write_foreign_region_bars( + p_iter->second); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars_write_bars: Error from proc_setup_bars_write_foreign_region_bars"); + break; + } + } + } + } while(0); + + FAPI_DBG("proc_setup_bars_write_bars: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: proc_setup_bars HWP entry point +// NOTE: see comments above function prototype in header +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_setup_bars( + std::vector<proc_setup_bars_proc_chip>& i_proc_chips, + const bool& i_init_local_chip_local_node) +{ + // return code + fapi::ReturnCode rc; + // SMP model + proc_setup_bars_smp_system smp; + + // mark HWP entry + FAPI_IMP("proc_setup_bars: Entering ..."); + + do + { + // process all chips passed from platform to HWP, query chip + // specific attributes and insert into system SMP data structure + // given logical node & chip ID + rc = proc_setup_bars_process_chips(i_proc_chips, + smp); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars: Error from proc_setup_bars_process_chips"); + break; + } + + // TODO: add more extensive range checking + + // write BAR registers + rc = proc_setup_bars_write_bars(smp, + i_init_local_chip_local_node); + if (!rc.ok()) + { + FAPI_ERR("proc_setup_bars: Error from proc_setup_bars_write_bars"); + break; + } + + } while(0); + + // log function exit + FAPI_IMP("proc_setup_bars: Exiting ..."); + return rc; +} + + +} // extern "C" diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H new file mode 100644 index 000000000..439bfe21d --- /dev/null +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H @@ -0,0 +1,1184 @@ +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ +// $Id: proc_setup_bars.H,v 1.2 2012/06/12 02:44:02 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars.H,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : proc_setup_bars.H +// *! DESCRIPTION : Program nest base address registers (BARs) (FAPI) +// *! +// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! +// *! ADDITIONAL COMMENTS: +// *! +// *! Program nest unit BAR registers, driven by attributes representing system +// *! memory map (including MMIO). +// *! +// *! High level execution flow: +// *! proc_setup_bars() +// *! proc_setup_bars_process_chips() +// *! proc_setup_bars_process_chip() +// *! proc_fab_smp_get_pcie_dsmp_mux_attrs() +// *! proc_fab_smp_get_node_id_attr() +// *! proc_fab_smp_get_chip_id_attr() +// *! proc_setup_bars_get_bar_attrs() +// *! proc_setup_bars_memory_get_non_mirrored_attrs() +// *! proc_setup_bars_memory_get_mirrored_attrs() +// *! proc_setup_bars_memory_get_foreign_near_attrs() +// *! proc_setup_bars_memory_get_foreign_far_attrs() +// *! proc_setup_bars_psi_get_bar_attrs() +// *! proc_setup_bars_fsp_get_bar_attrs() +// *! proc_setup_bars_fsp_get_mmio_mask_attrs() +// *! proc_setup_bars_intp_get_bar_attrs() +// *! proc_setup_bars_pcie_get_bar_attrs() +// *! proc_setup_bars_insert_chip() +// *! proc_setup_bars_write_bars() +// *! proc_setup_bars_write_local_chip_region_bars() +// *! proc_setup_bars_write_local_node_region_bars() +// *! proc_setup_bars_find_remote_node() +// *! proc_setup_bars_write_remote_node_region_bars() +// *! proc_setup_bars_write_foreign_region_bars() +// *! +// *! Platform Notes: +// *! This HWP has multiple IPL use cases. In all cases the HWP input +// *! is expected to contain an entry for each chip in the SMP at the +// *! time/scope of the invocation: +// *! +// *! 1. HBI (drawer scope): +// *! All local chip/local node resources should be initialized +// *! at this time (HWP boolean flag controlling this function +// *! set to true). +// *! +// *! All A links active in the scope of the drawer should be +// *! reflected in the per-chip HWP input structures. +// *! +// *! 2. FSP (drawer integration): +// *! All local chip/local node resources should already have +// *! been initialized in each drawer, so the HWP boolean flag +// *! controlling this function should be set to false. +// *! +// *! Only 'new' A links which cross previously initialized +// *! drawers should be reflected in the per-chip HWP input +// *! structures. +// *! +//------------------------------------------------------------------------------ + +#ifndef _PROC_SETUP_BARS_H_ +#define _PROC_SETUP_BARS_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <vector> +#include <map> +#include <fapi.H> +#include "proc_fab_smp.H" +#include "p8_scom_addresses.H" + + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + +// address range size definition constants +const uint64_t PROC_SETUP_BARS_SIZE_1_PB = 0x0004000000000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_512_TB = 0x0002000000000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_256_TB = 0x0001000000000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_128_TB = 0x0000800000000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_64_TB = 0x0000400000000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_32_TB = 0x0000200000000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_16_TB = 0x0000100000000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_8_TB = 0x0000080000000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_4_TB = 0x0000040000000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_2_TB = 0x0000020000000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_1_TB = 0x0000010000000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_512_GB = 0x0000008000000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_256_GB = 0x0000004000000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_128_GB = 0x0000002000000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_64_GB = 0x0000001000000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_32_GB = 0x0000000800000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_16_GB = 0x0000000400000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_8_GB = 0x0000000200000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_4_GB = 0x0000000100000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_2_GB = 0x0000000080000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_1_GB = 0x0000000040000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_512_MB = 0x0000000020000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_256_MB = 0x0000000010000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_128_MB = 0x0000000008000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_64_MB = 0x0000000004000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_32_MB = 0x0000000002000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_16_MB = 0x0000000001000000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_8_MB = 0x0000000000800000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_4_MB = 0x0000000000400000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_2_MB = 0x0000000000200000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_1_MB = 0x0000000000100000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_512_KB = 0x0000000000080000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_256_KB = 0x0000000000040000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_128_KB = 0x0000000000020000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_64_KB = 0x0000000000010000ULL; +const uint64_t PROC_SETUP_BARS_SIZE_4_KB = 0x0000000000001000ULL; + +// memory (non-mirrored/mirrored) constants +const uint8_t PROC_SETUP_BARS_NUM_NON_MIRRORED_RANGES = 8; +const uint8_t PROC_SETUP_BARS_NUM_MIRRORED_RANGES = 4; + +// PCIe unit contstants +const uint8_t PROC_SETUP_BARS_PCIE_NUM_UNITS = 3; +const uint8_t PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT = 3; + + +//------------------------------------------------------------------------------ +// Structure definitions +//------------------------------------------------------------------------------ + +// HWP argument structure defining properties of this chip +// and links which should be considered in this invocation (A/F) +struct proc_setup_bars_proc_chip +{ + // target for this chip + fapi::Target this_chip; + + // targets defining A link connected chips + // qualify which remote node based BAR resources should be initalized on + // this chip + fapi::Target a0_chip; + fapi::Target a1_chip; + fapi::Target a2_chip; + + // init F link related BARs for this chip? + bool process_f0; + bool process_f1; +}; + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode +(*proc_setup_bars_FP_t)(std::vector<proc_setup_bars_proc_chip>&, + const bool&); + +// structure to represent range of FBC real address space +struct proc_setup_bars_addr_range +{ + // default constructor (mark range disabled) + proc_setup_bars_addr_range() : + enabled(false), + base_addr(0), + size(0) + { + } + + // constructor + proc_setup_bars_addr_range( + const uint64_t& range_base_addr, + const uint64_t& range_size) : + enabled(range_size != 0), + base_addr(range_base_addr), + size(range_size) + { + } + + // determine if region size is power of 2 aligned + bool is_power_of_2() const + { + return ((size != 0) && !(size & (size - 1))); + } + + // round region size to next largest power of 2 + void round_next_power_of_2() + { + uint64_t size_round; + // if size is zero/one, leave as is + if ((size != 0) && (size != 1)) + { + // shift until new size is greater than or + // equal to existing size + for (size_round = 0x1ULL; + size_round < size; + size_round = (size_round << 1)) + { + } + size = size_round; + } + } + + // return ending address of range + uint64_t end_addr() const + { + return(base_addr + size - 1); + } + + // check for overlapping ranges + bool overlaps(const proc_setup_bars_addr_range& range_compare) const + { + // if either range is disabled, consider them non-overlapping + return(!(!enabled || + !range_compare.enabled || + ((end_addr() < range_compare.base_addr) || + (base_addr > range_compare.end_addr())))); + } + + // merge two ranges (span breadth of both ranges) + void merge(const proc_setup_bars_addr_range& range_new) + { + // if range is disabled, set values to track those of new + // range (which may also be disabled) + if (!enabled) + { + enabled = range_new.enabled; + base_addr = range_new.base_addr; + size = range_new.size; + } + // if new range is disabled, leave as-is + // otherwise merge two valid ranges + else if (range_new.enabled) + { + uint64_t new_start_addr; + uint64_t new_end_addr; + + // calculate new base address (smaller of the two start addresses) + if (base_addr < range_new.base_addr) + { + new_start_addr = base_addr; + } + else + { + new_start_addr = range_new.base_addr; + } + // calculate new end address (larger of the two end addresses) + if (end_addr() > range_new.end_addr()) + { + new_end_addr = end_addr(); + } + else + { + new_end_addr = range_new.end_addr(); + } + // set new range values + base_addr = new_start_addr; + size = (new_end_addr - new_start_addr + 1); + } + } + + // check that if region size aligns exactly to base address range + // (i.e., no overlap between BAR and size) + bool is_aligned() const + { + return ((base_addr & (size - 1)) == 0x0ULL); + } + + // does range lie completely within FBC address range? + bool is_in_fbc_range() const + { + return ((base_addr < PROC_FAB_SMP_MAX_ADDRESS) && + (end_addr() < PROC_FAB_SMP_MAX_ADDRESS)); + } + + // utility function to display address range information + void print() const + { + FAPI_DBG("proc_setup_bars_print_addr_range: %s :: [ %016llX-%016llX ]", + (enabled)?("E"):("D"), + base_addr, + end_addr()); + } + + bool enabled; + uint64_t base_addr; + uint64_t size; +}; + +// structure to represent fabric connectivty & properites for a single chip +// in the SMP topology +struct proc_setup_bars_smp_chip +{ + // associated HWP input structure + proc_setup_bars_proc_chip* chip; + + // chip properties/attributes: + // fabric chip/node ID + proc_fab_smp_chip_id chip_id; + proc_fab_smp_node_id node_id; + // select for PCIe/DSMP mux (one per link) + bool pcie_not_f_link[PROC_FAB_SMP_NUM_F_LINKS]; + // real address ranges covered by resources on this chip + proc_setup_bars_addr_range non_mirrored_range; + proc_setup_bars_addr_range mirrored_range; + proc_setup_bars_addr_range foreign_near_ranges[PROC_FAB_SMP_NUM_F_LINKS]; + proc_setup_bars_addr_range foreign_far_ranges[PROC_FAB_SMP_NUM_F_LINKS]; + proc_setup_bars_addr_range psi_range; + proc_setup_bars_addr_range fsp_range; + proc_setup_bars_addr_range fsp_mmio_mask_range; + proc_setup_bars_addr_range intp_range; + proc_setup_bars_addr_range nx_mmio_range; + proc_setup_bars_addr_range pcie_ranges[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT]; +}; + +// structure to represent properties for a single node in the SMP topology +struct proc_setup_bars_smp_node +{ + // chips which reside in this node + std::map<proc_fab_smp_chip_id, proc_setup_bars_smp_chip> chips; + + // node properties/attributes: + // fabric node ID + proc_fab_smp_node_id node_id; + // real address ranges covered for mirrored & non-mirrored regions + // considering all chips in node) + proc_setup_bars_addr_range non_mirrored_range; + proc_setup_bars_addr_range mirrored_range; +}; + +// structure to represent collection of nodes in SMP topology +struct proc_setup_bars_smp_system +{ + // nodes which reside in this SMP + std::map<proc_fab_smp_node_id, proc_setup_bars_smp_node> nodes; +}; + +// define set of shared design non-foreign BAR sizes +struct proc_setup_bars_nf_bar_size +{ + static std::map<uint64_t, uint64_t> create_map() + { + std::map<uint64_t, uint64_t> m; + m[PROC_SETUP_BARS_SIZE_64_TB] = 0x3FFFULL; + m[PROC_SETUP_BARS_SIZE_32_TB] = 0x1FFFULL; + m[PROC_SETUP_BARS_SIZE_16_TB] = 0x0FFFULL; + m[PROC_SETUP_BARS_SIZE_8_TB] = 0x07FFULL; + m[PROC_SETUP_BARS_SIZE_4_TB] = 0x03FFULL; + m[PROC_SETUP_BARS_SIZE_2_TB] = 0x01FFULL; + m[PROC_SETUP_BARS_SIZE_1_TB] = 0x00FFULL; + m[PROC_SETUP_BARS_SIZE_512_GB] = 0x007FULL; + m[PROC_SETUP_BARS_SIZE_256_GB] = 0x003FULL; + m[PROC_SETUP_BARS_SIZE_128_GB] = 0x001FULL; + m[PROC_SETUP_BARS_SIZE_64_GB] = 0x000FULL; + m[PROC_SETUP_BARS_SIZE_32_GB] = 0x0007ULL; + m[PROC_SETUP_BARS_SIZE_16_GB] = 0x0003ULL; + m[PROC_SETUP_BARS_SIZE_8_GB] = 0x0001ULL; + m[PROC_SETUP_BARS_SIZE_4_GB] = 0x0000ULL; + return m; + } + static const std::map<uint64_t, uint64_t> xlate_map; +}; + +// define set of shared design foreign BAR sizes +struct proc_setup_bars_f_bar_size +{ + static std::map<uint64_t, uint64_t> create_map() + { + std::map<uint64_t, uint64_t> m; + m[PROC_SETUP_BARS_SIZE_8_TB] = 0x7FFFFULL; + m[PROC_SETUP_BARS_SIZE_4_TB] = 0x3FFFFULL; + m[PROC_SETUP_BARS_SIZE_2_TB] = 0x1FFFFULL; + m[PROC_SETUP_BARS_SIZE_1_TB] = 0x0FFFFULL; + m[PROC_SETUP_BARS_SIZE_512_GB] = 0x07FFFULL; + m[PROC_SETUP_BARS_SIZE_256_GB] = 0x03FFFULL; + m[PROC_SETUP_BARS_SIZE_128_GB] = 0x01FFFULL; + m[PROC_SETUP_BARS_SIZE_64_GB] = 0x00FFFULL; + m[PROC_SETUP_BARS_SIZE_32_GB] = 0x007FFULL; + m[PROC_SETUP_BARS_SIZE_16_GB] = 0x003FFULL; + m[PROC_SETUP_BARS_SIZE_8_GB] = 0x001FFULL; + m[PROC_SETUP_BARS_SIZE_4_GB] = 0x000FFULL; + m[PROC_SETUP_BARS_SIZE_2_GB] = 0x0007FULL; + m[PROC_SETUP_BARS_SIZE_1_GB] = 0x0003FULL; + m[PROC_SETUP_BARS_SIZE_512_MB] = 0x0001FULL; + m[PROC_SETUP_BARS_SIZE_256_MB] = 0x0000FULL; + m[PROC_SETUP_BARS_SIZE_128_MB] = 0x00007ULL; + m[PROC_SETUP_BARS_SIZE_64_MB] = 0x00003ULL; + m[PROC_SETUP_BARS_SIZE_32_MB] = 0x00001ULL; + m[PROC_SETUP_BARS_SIZE_16_MB] = 0x00000ULL; + return m; + } + static const std::map<uint64_t, uint64_t> xlate_map; +}; + +// define set of FSP BAR sizes +struct proc_setup_bars_fsp_bar_size +{ + static std::map<uint64_t, uint64_t> create_map() + { + std::map<uint64_t, uint64_t> m; + m[PROC_SETUP_BARS_SIZE_4_GB] = 0x000ULL; + m[PROC_SETUP_BARS_SIZE_2_GB] = 0x800ULL; + m[PROC_SETUP_BARS_SIZE_1_GB] = 0xC00ULL; + m[PROC_SETUP_BARS_SIZE_512_MB] = 0xE00ULL; + m[PROC_SETUP_BARS_SIZE_256_MB] = 0xF00ULL; + m[PROC_SETUP_BARS_SIZE_128_MB] = 0xF80ULL; + m[PROC_SETUP_BARS_SIZE_64_MB] = 0xFC0ULL; + m[PROC_SETUP_BARS_SIZE_32_MB] = 0xFE0ULL; + m[PROC_SETUP_BARS_SIZE_16_MB] = 0xFF0ULL; + m[PROC_SETUP_BARS_SIZE_8_MB] = 0xFF8ULL; + m[PROC_SETUP_BARS_SIZE_4_MB] = 0xFFCULL; + m[PROC_SETUP_BARS_SIZE_2_MB] = 0xFFEULL; + m[PROC_SETUP_BARS_SIZE_1_MB] = 0xFFFULL; + return m; + } + static const std::map<uint64_t, uint64_t> xlate_map; +}; + +// define set of FSP MMIO mask sizes +struct proc_setup_bars_fsp_mmio_mask_size +{ + static std::map<uint64_t, uint64_t> create_map() + { + std::map<uint64_t, uint64_t> m; + m[PROC_SETUP_BARS_SIZE_4_GB] = 0xF; + m[PROC_SETUP_BARS_SIZE_2_GB] = 0x7; + m[PROC_SETUP_BARS_SIZE_1_GB] = 0x3; + m[PROC_SETUP_BARS_SIZE_512_MB] = 0x1; + m[PROC_SETUP_BARS_SIZE_256_MB] = 0x0; + return m; + } + static const std::map<uint64_t, uint64_t> xlate_map; +}; + +// define set of NX MMIO mask sizes +struct proc_setup_bars_nx_mmio_bar_size +{ + static std::map<uint64_t, uint64_t> create_map() + { + std::map<uint64_t, uint64_t> m; + m[PROC_SETUP_BARS_SIZE_16_GB] = 0x2; + m[PROC_SETUP_BARS_SIZE_16_MB] = 0x4; + m[PROC_SETUP_BARS_SIZE_1_MB] = 0x3; + m[PROC_SETUP_BARS_SIZE_64_KB] = 0x1; + m[PROC_SETUP_BARS_SIZE_4_KB] = 0x0; + return m; + } + static const std::map<uint64_t, uint64_t> xlate_map; +}; + +// define set of MCD BAR sizes +struct proc_setup_bars_mcd_bar_size +{ + static std::map<uint64_t, uint64_t> create_map() + { + std::map<uint64_t, uint64_t> m; + m[PROC_SETUP_BARS_SIZE_32_TB] = 0x1FFFFFULL; + m[PROC_SETUP_BARS_SIZE_16_TB] = 0x0FFFFFULL; + m[PROC_SETUP_BARS_SIZE_8_TB] = 0x07FFFFULL; + m[PROC_SETUP_BARS_SIZE_4_TB] = 0x03FFFFULL; + m[PROC_SETUP_BARS_SIZE_2_TB] = 0x01FFFFULL; + m[PROC_SETUP_BARS_SIZE_1_TB] = 0x00FFFFULL; + m[PROC_SETUP_BARS_SIZE_512_GB] = 0x007FFFULL; + m[PROC_SETUP_BARS_SIZE_256_GB] = 0x003FFFULL; + m[PROC_SETUP_BARS_SIZE_128_GB] = 0x001FFFULL; + m[PROC_SETUP_BARS_SIZE_64_GB] = 0x000FFFULL; + m[PROC_SETUP_BARS_SIZE_32_GB] = 0x0007FFULL; + m[PROC_SETUP_BARS_SIZE_16_GB] = 0x0003FFULL; + m[PROC_SETUP_BARS_SIZE_8_GB] = 0x0001FFULL; + m[PROC_SETUP_BARS_SIZE_4_GB] = 0x0000FFULL; + m[PROC_SETUP_BARS_SIZE_2_GB] = 0x00007FULL; + m[PROC_SETUP_BARS_SIZE_1_GB] = 0x00003FULL; + m[PROC_SETUP_BARS_SIZE_512_MB] = 0x00001FULL; + m[PROC_SETUP_BARS_SIZE_256_MB] = 0x00000FULL; + m[PROC_SETUP_BARS_SIZE_128_MB] = 0x000007ULL; + m[PROC_SETUP_BARS_SIZE_64_MB] = 0x000003ULL; + m[PROC_SETUP_BARS_SIZE_32_MB] = 0x000001ULL; + m[PROC_SETUP_BARS_SIZE_16_MB] = 0x000000ULL; + return m; + } + static const std::map<uint64_t, uint64_t> xlate_map; +}; + +// define set of PCIe MMIO BAR (BAR0/1 only) sizes +struct proc_setup_bars_pcie_bar_size +{ + static std::map<uint64_t, uint64_t> create_map() + { + std::map<uint64_t, uint64_t> m; + m[PROC_SETUP_BARS_SIZE_1_PB] = 0x000000000ULL; + m[PROC_SETUP_BARS_SIZE_512_TB] = 0x200000000ULL; + m[PROC_SETUP_BARS_SIZE_256_TB] = 0x300000000ULL; + m[PROC_SETUP_BARS_SIZE_128_TB] = 0x380000000ULL; + m[PROC_SETUP_BARS_SIZE_64_TB] = 0x3C0000000ULL; + m[PROC_SETUP_BARS_SIZE_32_TB] = 0x3E0000000ULL; + m[PROC_SETUP_BARS_SIZE_16_TB] = 0x3F0000000ULL; + m[PROC_SETUP_BARS_SIZE_8_TB] = 0x3F8000000ULL; + m[PROC_SETUP_BARS_SIZE_4_TB] = 0x3FC000000ULL; + m[PROC_SETUP_BARS_SIZE_2_TB] = 0x3FE000000ULL; + m[PROC_SETUP_BARS_SIZE_1_TB] = 0x3FF000000ULL; + m[PROC_SETUP_BARS_SIZE_512_GB] = 0x3FF800000ULL; + m[PROC_SETUP_BARS_SIZE_256_GB] = 0x3FFC00000ULL; + m[PROC_SETUP_BARS_SIZE_128_GB] = 0x3FFE00000ULL; + m[PROC_SETUP_BARS_SIZE_64_GB] = 0x3FFF00000ULL; + m[PROC_SETUP_BARS_SIZE_32_GB] = 0x3FFF80000ULL; + m[PROC_SETUP_BARS_SIZE_16_GB] = 0x3FFFC0000ULL; + m[PROC_SETUP_BARS_SIZE_8_GB] = 0x3FFFE0000ULL; + m[PROC_SETUP_BARS_SIZE_4_GB] = 0x3FFFF0000ULL; + m[PROC_SETUP_BARS_SIZE_2_GB] = 0x3FFFF8000ULL; + m[PROC_SETUP_BARS_SIZE_1_GB] = 0x3FFFFC000ULL; + m[PROC_SETUP_BARS_SIZE_512_MB] = 0x3FFFFE000ULL; + m[PROC_SETUP_BARS_SIZE_256_MB] = 0x3FFFFF000ULL; + m[PROC_SETUP_BARS_SIZE_128_MB] = 0x3FFFFF800ULL; + m[PROC_SETUP_BARS_SIZE_64_MB] = 0x3FFFFFC00ULL; + m[PROC_SETUP_BARS_SIZE_32_MB] = 0x3FFFFFE00ULL; + m[PROC_SETUP_BARS_SIZE_16_MB] = 0x3FFFFFF00ULL; + m[PROC_SETUP_BARS_SIZE_8_MB] = 0x3FFFFFF80ULL; + m[PROC_SETUP_BARS_SIZE_4_MB] = 0x3FFFFFFC0ULL; + m[PROC_SETUP_BARS_SIZE_2_MB] = 0x3FFFFFFE0ULL; + m[PROC_SETUP_BARS_SIZE_1_MB] = 0x3FFFFFFF0ULL; + m[PROC_SETUP_BARS_SIZE_512_KB] = 0x3FFFFFFF8ULL; + m[PROC_SETUP_BARS_SIZE_256_KB] = 0x3FFFFFFFCULL; + m[PROC_SETUP_BARS_SIZE_128_KB] = 0x3FFFFFFFEULL; + m[PROC_SETUP_BARS_SIZE_64_KB] = 0x3FFFFFFFFULL; + return m; + } + static const std::map<uint64_t, uint64_t> xlate_map; +}; + +// structure to represent logical HW BAR properties +struct proc_setup_bars_bar_def +{ + // mask for implemented base address bits (1 for all non implemented bits) + uint64_t base_addr_mask; + // minimum/maximum supported size values + uint64_t size_min; + uint64_t size_max; + // check that base address/size are aligned? + bool check_aligned; +}; + +// define set of supported shift operations for aligning logical +// BAR base address to physical position in HW register +enum proc_setup_bars_shift_base +{ + PROC_SETUP_BARS_SHIFT_LEFT, + PROC_SETUP_BARS_SHIFT_RIGHT, + PROC_SETUP_BARS_SHIFT_NONE +}; + +// structure to represent physical HW BAR register programming +struct proc_setup_bars_bar_reg_def +{ + // base address programming information + bool has_base; + proc_setup_bars_shift_base base_shift; + uint8_t base_shift_amount; + uint8_t base_start_bit; + uint8_t base_end_bit; + // enable programming information + bool has_enable; + uint8_t enable_bit; + // size programming information + bool has_size; + uint8_t size_start_bit; + uint8_t size_end_bit; + // translate logical size to register programming + const std::map<uint64_t, uint64_t>* xlate_map; + // static value/mask to be written along with BAR content + uint64_t static_data; + uint64_t static_data_mask; +}; + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + +const proc_setup_bars_bar_def non_mirrored_range_def = +{ + 0xFFFC0000FFFFFFFFULL, // base: RA 14:63 + PROC_SETUP_BARS_SIZE_4_GB, // size (min): 4 GB + PROC_SETUP_BARS_SIZE_4_TB, // size (max): 4 TB + false +}; + +const proc_setup_bars_bar_def mirrored_range_def = +{ + 0xFFFC0000FFFFFFFFULL, // base: RA 14:63 + PROC_SETUP_BARS_SIZE_2_GB, // size (min): 2 GB + PROC_SETUP_BARS_SIZE_2_TB, // size (max): 2 TB + false +}; + +// shared non-foreign BAR design (mirrored/non-mirrored regions) constants +const proc_setup_bars_bar_def common_nf_scope_bar_def = +{ + 0xFFFC0000FFFFFFFFULL, // base: RA 14:31 + PROC_SETUP_BARS_SIZE_4_GB, // size (min): 4 GB + PROC_SETUP_BARS_SIZE_64_TB, // size (min): 64 TB + true +}; + +const proc_setup_bars_bar_reg_def common_nf_scope_bar_reg_def = +{ + true, // base: bits 15:32 + PROC_SETUP_BARS_SHIFT_RIGHT, + 1, + 15, + 32, + true, // enable: bit 0 + 0, + true, // size: bits 1:14 + 1, + 14, + &proc_setup_bars_nf_bar_size::xlate_map, + 0x0ULL, + 0x0ULL +}; + +// shared foreign BAR design (near/far regions) constants +const proc_setup_bars_bar_def common_f_scope_bar_def = +{ + 0xFFFC000000FFFFFFULL, // base: RA 14:39 + PROC_SETUP_BARS_SIZE_16_MB, // size (min): 16 MB + PROC_SETUP_BARS_SIZE_8_TB, // size (min): 8 TB + true +}; + +const proc_setup_bars_bar_reg_def common_f_scope_bar_reg_def = +{ + true, // base: bits 20:45 + PROC_SETUP_BARS_SHIFT_RIGHT, + 6, + 20, + 45, + true, // enable: bit 0 + 0, + true, // size: bits 1:19 + 1, + 19, + &proc_setup_bars_f_bar_size::xlate_map, + 0x0ULL, + 0x0ULL +}; + +// PSI BAR constants +const proc_setup_bars_bar_def psi_bridge_bar_def = +{ + 0xFFFC0000000FFFFFULL, // base: RA 14:43 + PROC_SETUP_BARS_SIZE_1_MB, // size (min): 1 MB + PROC_SETUP_BARS_SIZE_1_MB, // size (max): 1 MB + true +}; + +const proc_setup_bars_bar_reg_def psi_bridge_bar_reg_def = +{ + true, // base: bits 14:43 + PROC_SETUP_BARS_SHIFT_NONE, + 0, + 14, + 43, + true, // enable: bit 63 + 63, + false, // size: implied + 0, + 0, + NULL, + 0x0ULL, + 0x0ULL +}; + +// FSP BAR constants +const proc_setup_bars_bar_def fsp_bar_def = +{ + 0xFFFC0000000FFFFFULL, // base: RA 14:43 + PROC_SETUP_BARS_SIZE_1_MB, // size (min): 1 MB + PROC_SETUP_BARS_SIZE_4_GB, // size (max): 4 GB + true +}; + +const proc_setup_bars_bar_reg_def fsp_bar_reg_def = +{ + true, // base: bits 14:43 + PROC_SETUP_BARS_SHIFT_NONE, + 0, + 14, + 43, + false, // enable: other reg + 0, + false, // size: other reg + 0, + 0, + NULL, + 0x0ULL, + 0x0ULL +}; + +const proc_setup_bars_bar_reg_def fsp_bar_mask_reg_def = +{ + false, // base: other reg + PROC_SETUP_BARS_SHIFT_NONE, + 0, + 0, + 0, + false, // enable: other reg + 0, + true, // size: 32:43 + 32, + 43, + &proc_setup_bars_fsp_bar_size::xlate_map, + 0x0ULL, + 0x0ULL +}; + +const proc_setup_bars_bar_reg_def fsp_bar_en_reg_def = +{ + false, // base: other reg + PROC_SETUP_BARS_SHIFT_NONE, + 0, + 0, + 0, + true, // enable: bit 1 + 1, + false, // size: other reg + 0, + 0, + NULL, + 0x0ULL, + 0x0ULL +}; + +// FSP MMIO mask constants +const proc_setup_bars_bar_def fsp_mmio_mask_def = +{ + 0xFFFFFFFFFFFFFFFFULL, // base: unused + PROC_SETUP_BARS_SIZE_256_MB, // size (min): 256 MB + PROC_SETUP_BARS_SIZE_4_GB, // size (max): 4 GB + true +}; + +const proc_setup_bars_bar_reg_def fsp_mmio_mask_reg_def = +{ + false, // base: unused + PROC_SETUP_BARS_SHIFT_NONE, + 0, + 0, + 0, + false, // enable: unused + 0, + true, // size: bits 8:11 + 8, + 11, + &proc_setup_bars_fsp_mmio_mask_size::xlate_map, + 0x0ULL, + 0x0ULL +}; + +// INTP BAR constants +const proc_setup_bars_bar_def intp_bar_def = +{ + 0xFFFC0000000FFFFFULL, // base: RA 14:43 + PROC_SETUP_BARS_SIZE_1_MB, // size (min): 1 MB + PROC_SETUP_BARS_SIZE_1_MB, // size (max): 1 MB + true +}; + +const proc_setup_bars_bar_reg_def intp_bar_reg_def = +{ + true, // base: bits 0:29 + PROC_SETUP_BARS_SHIFT_LEFT, + 14, + 0, + 29, + true, // enable: bit 30 + 30, + false, // size: implied + 0, + 0, + NULL, + 0x0ULL, + 0x0ULL +}; + +// L3 BAR constants +const uint32_t L3_BAR12_BASE_ADDR_LEFT_SHIFT_AMOUNT = 14; +const uint32_t L3_BAR12_SIZE_END_BIT = 34; +const uint32_t L3_BAR2_ENABLE_BIT = 35; + +const uint32_t L3_BAR_GROUP_MASK_RA_DIFF_START_BIT = 18; +const uint32_t L3_BAR_GROUP_MASK_RA_DIFF_END_BIT = 31; + +const uint32_t L3_BAR_GROUP_MASK_NON_MIRROR_MASK_START_BIT = 3; +const uint32_t L3_BAR_GROUP_MASK_NON_MIRROR_MASK_END_BIT = 16; + +const uint32_t L3_BAR_GROUP_MASK_MIRROR_MASK_START_BIT = 20; +const uint32_t L3_BAR_GROUP_MASK_MIRROR_MASK_END_BIT = 33; +const uint32_t L3_BAR_GROUP_MASK_MIRROR_ENABLE_BIT = 34; + +// NX MMIO BAR constants +const proc_setup_bars_bar_def nx_mmio_bar_def = +{ + 0xFFFC000000000FFFULL, // base: RA 14:51 + PROC_SETUP_BARS_SIZE_4_KB, // size (min): 4 KB + PROC_SETUP_BARS_SIZE_16_GB, // size (max): 16 GB + true +}; + +const proc_setup_bars_bar_reg_def nx_mmio_bar_reg_def = +{ + true, // base: bits 14:51 + PROC_SETUP_BARS_SHIFT_NONE, + 0, + 14, + 51, + true, // enable: bit 52 + 52, + true, // size: bits 53:55 + 53, + 55, + &proc_setup_bars_nx_mmio_bar_size::xlate_map, + 0x0ULL, + 0x0ULL +}; + +// MCD Configuration Register constants +const proc_setup_bars_bar_def mcd_bar_def = +{ + 0xFFFC000000FFFFFFULL, // base: RA 14:39 + PROC_SETUP_BARS_SIZE_16_MB, // size (min): 16 MB + PROC_SETUP_BARS_SIZE_32_TB, // size (max): 32 TB + true +}; + +const proc_setup_bars_bar_reg_def mcd_nf_bar_reg_def = +{ + true, // base: bits 30:55 + PROC_SETUP_BARS_SHIFT_RIGHT, + 16, + 30, + 55, + true, // enable: bit 0 + 0, + true, // size: bits 9:29 + 9, + 29, + &proc_setup_bars_mcd_bar_size::xlate_map, + 0x4000000000000000ULL, // 1 config/group, system scope + 0x780000000000001CULL +}; + +const proc_setup_bars_bar_reg_def mcd_f0_bar_reg_def = +{ + true, // base: bits 30:55 + PROC_SETUP_BARS_SHIFT_RIGHT, + 16, + 30, + 55, + true, // enable: bit 0 + 0, + true, // size: bits 9:29 + 9, + 29, + &proc_setup_bars_mcd_bar_size::xlate_map, + 0x4000000000000010ULL, // 1 config/group, foreign scope, f0 link + 0x780000000000001CULL +}; + +const proc_setup_bars_bar_reg_def mcd_f1_bar_reg_def = +{ + true, // base: bits 30:55 + PROC_SETUP_BARS_SHIFT_RIGHT, + 16, + 30, + 55, + true, // enable: bit 0 + 0, + true, // size: bits 9:29 + 9, + 29, + &proc_setup_bars_mcd_bar_size::xlate_map, + 0x4000000000000014ULL, // 1 config/group, foreign scope, f1 link + 0x780000000000001CULL +}; + +// PCIe BAR constants +// TODO: investigate development of PCIe chip unit support +const uint32_t PROC_SETUP_BARS_PCIE_CHIP_NON_MIRRORED_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS] = +{ + PCIE0_NODAL_BAR0_0x02012010, + PCIE1_NODAL_BAR0_0x02012410, + PCIE2_NODAL_BAR0_0x02012810 +}; + +const uint32_t PROC_SETUP_BARS_PCIE_CHIP_MIRRORED_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS] = +{ + PCIE0_NODAL_BAR1_0x02012011, + PCIE1_NODAL_BAR1_0x02012411, + PCIE2_NODAL_BAR1_0x02012811 +}; + +const uint32_t PROC_SETUP_BARS_PCIE_NODE_NON_MIRRORED_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS] = +{ + PCIE0_GROUP_BAR0_0x02012012, + PCIE1_GROUP_BAR0_0x02012412, + PCIE2_GROUP_BAR0_0x02012812 +}; + +const uint32_t PROC_SETUP_BARS_PCIE_NODE_MIRRORED_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS] = +{ + PCIE0_GROUP_BAR1_0x02012013, + PCIE1_GROUP_BAR1_0x02012413, + PCIE2_GROUP_BAR1_0x02012813 +}; + +const uint32_t PROC_SETUP_BARS_PCIE_FOREIGN_NEAR_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_FAB_SMP_NUM_F_LINKS] = +{ + { + PCIE0_NEAR_BAR_F0_0x02012014, + PCIE0_NEAR_BAR_F1_0x02012016 + }, + { + PCIE1_NEAR_BAR_F0_0x02012414, + PCIE1_NEAR_BAR_F1_0x02012416 + }, + { + PCIE2_NEAR_BAR_F0_0x02012814, + PCIE2_NEAR_BAR_F1_0x02012816 + } +}; + +const uint32_t PROC_SETUP_BARS_PCIE_FOREIGN_FAR_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_FAB_SMP_NUM_F_LINKS] = +{ + { + PCIE0_FAR_BAR_F0_0x02012015, + PCIE0_FAR_BAR_F1_0x02012017 + }, + { + PCIE1_FAR_BAR_F0_0x02012415, + PCIE1_FAR_BAR_F1_0x02012417 + }, + { + PCIE2_FAR_BAR_F0_0x02012815, + PCIE2_FAR_BAR_F1_0x02012817 + } +}; + +const uint8_t PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT_MMIO = 2; +const uint8_t PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT_PHB = 1; +const uint8_t PROC_SETUP_BARS_PCIE_REGS_PER_PHB_RANGE = 2; + +const uint8_t PROC_SETUP_BARS_PCIE_RANGE_TYPE_MMIO[PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT] = +{ + true, // BAR 0 = MMIO (primary) + true, // BAR 1 = MMIO (backup/failover) + false, // BAR 2 = PHB +}; + +const proc_setup_bars_bar_def pcie_mmio_bar_def = +{ + 0xFFFC00000000FFFFULL, // base: RA 14:47 + PROC_SETUP_BARS_SIZE_64_KB, // size (min): 64 KB + PROC_SETUP_BARS_SIZE_1_PB, // size (min): 1 PB + true +}; + +const proc_setup_bars_bar_reg_def pcie_mmio_bar_reg_def = +{ + true, // base: bits 0:33 + PROC_SETUP_BARS_SHIFT_LEFT, + 14, + 0, + 33, + false, // enable: other reg + 0, + false, // size: other reg + 0, + 0, + NULL, + 0x0ULL, + 0x0ULL +}; + +const uint32_t PROC_SETUP_BARS_PCIE_BAR_REGS_MMIO[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT_MMIO] = +{ + { + PCIE0_IO_BAR0_0x02012040, + PCIE0_IO_BAR1_0x02012041 + }, + { + PCIE1_IO_BAR0_0x02012440, + PCIE1_IO_BAR1_0x02012441 + }, + { + PCIE2_IO_BAR0_0x02012840, + PCIE2_IO_BAR1_0x02012841 + } +}; + +const proc_setup_bars_bar_reg_def pcie_mmio_bar_mask_reg_def = +{ + false, // base: other reg + PROC_SETUP_BARS_SHIFT_NONE, + 0, + 0, + 0, + false, // enable: other reg + 0, + true, // size: bits 0:33 + 0, + 33, + &proc_setup_bars_pcie_bar_size::xlate_map, + 0x0ULL, + 0x0ULL, +}; + +const uint32_t PROC_SETUP_BARS_PCIE_BAR_MASK_REGS_MMIO[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT_MMIO] = +{ + { + PCIE0_IO_MASK0_0x02012043, + PCIE0_IO_MASK1_0x02012044 + }, + { + PCIE1_IO_MASK0_0x02012443, + PCIE1_IO_MASK1_0x02012444 + }, + { + PCIE2_IO_MASK0_0x02012843, + PCIE2_IO_MASK1_0x02012844 + } +}; + +const proc_setup_bars_bar_def pcie_phb_bar_def = +{ + 0xFFFC000000000FFFULL, // base: RA 14:51 + PROC_SETUP_BARS_SIZE_4_KB, // size (min): 4 KB + PROC_SETUP_BARS_SIZE_4_KB, // size (min): 4 KB + true +}; + +const proc_setup_bars_bar_reg_def pcie_phb_bar_reg_def = +{ + true, // base: bits 0:37 + PROC_SETUP_BARS_SHIFT_LEFT, + 14, + 0, + 37, + false, // enable: other reg + 0, + false, // size: implied + 0, + 33, + NULL, + 0x0ULL, + 0x0ULL +}; + +const uint32_t PROC_SETUP_BARS_PCIE_BAR_REGS_PHB[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_SETUP_BARS_PCIE_REGS_PER_PHB_RANGE] = +{ + { + PCIE0_IO_BAR2_0x02012042, + PCIE0_ASB_BAR_0x0901200B + }, + { + PCIE1_IO_BAR2_0x02012442, + PCIE1_ASB_BAR_0x0901240B + }, + { + PCIE2_IO_BAR2_0x02012842, + PCIE2_ASB_BAR_0x0901280B + } +}; + +const uint32_t PROC_SETUP_BARS_PCIE_BAR_EN_BIT[PROC_SETUP_BARS_PCIE_NUM_UNITS] = +{ + 0x0, + 0x1, + 0x2 +}; + +const uint32_t PROC_SETUP_BARS_PCIE_BAR_EN_REGS[PROC_SETUP_BARS_PCIE_NUM_UNITS] = +{ + PCIE0_IO_BAR_EN_0x02012045, + PCIE1_IO_BAR_EN_0x02012445, + PCIE2_IO_BAR_EN_0x02012845 +}; + + +extern "C" +{ + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// function: program nest unit BAR registers, driven by attributes representing +// system memory map (including MMIO) +// parameters: i_proc_chips => vector of structures defining properties of each +// chip and links which should be considered in +// this invocation to drive initialization of BARs +// tied to remote node regions (A links) and +// foreign regions (F links) +// i_init_local_chip_local_node => boolean qualifying initilization +// of BARs tied to local chip/local +// node regions +// returns: FAPI_RC_SUCCESS if all register writes are successful, +// RC_PROC_SETUP_BARS_NON_MIRRORED_RANGE_ATTR_ERR if chip non-mirrored +// attribute content violates expected behavior, +// RC_PROC_SETUP_BARS_NON_MIRRORED_RANGE_OVERLAP_ATTR_ERR if chip +// non-mirrored range attributes specify overlapping ranges, +// RC_PROC_SETUP_BARS_NON_MIRRORED_RANGE_ERR if chip non-mirrored +// processed range content violates expected behavior, +// RC_PROC_SETUP_BARS_MIRRORED_RANGE_ATTR_ERR if individual chip +// mirrored range attribute content violates expected behavior, +// RC_PROC_SETUP_BARS_MIRRORED_RANGE_OVERLAP_ATTR_ERR if chip mirrored +// range attributes specify overlapping ranges, +// RC_PROC_SETUP_BARS_MIRRORED_RANGE_ERR if chip mirrored processed +// range content violates expected behavior, +// RC_PROC_SETUP_BARS_FOREIGN_NEAR_RANGE_ATTR_ERR if individual chip +// foriegn near range attribute content violates expected behavior, +// RC_PROC_SETUP_BARS_FOREIGN_FAR_RANGE_ATTR_ERR if individual chip +// foreign far range attribute content violates expected behavior, +// RC_PROC_SETUP_BARS_PSI_BAR_ATTR_ERR if chip PSI range +// attribute content violates expected behavior, +// RC_PROC_SETUP_BARS_FSP_BAR_ATTR_ERR if chip FSP range +// attribute content violates expected behavior, +// RC_PROC_SETUP_BARS_FSP_MMIO_MASK_ATTR_ERR if chip MMIO mask +// attribute content violates expected behavior, +// RC_PROC_SETUP_BARS_INTP_BAR_ATTR_ERR if chip INTP range +// attribute content violates expected behavior, +// RC_PROC_SETUP_BARS_NX_MMIO_BAR_ATTR_ERR if chip NX MMIO range +// attribute content violates expected behavior, +// RC_PROC_SETUP_BARS_PCIE_BAR_ATTR_ERR if individual chip PCIe IO +// range attribute content violates expected behavior, +// RC_PROC_SETUP_BARS_NODE_ADD_INTERNAL_ERR if node map insert fails, +// RC_PROC_SETUP_BARS_NODE_FIND_INTERNAL_ERR if node map lookup is +// unsuccessful, +// RC_PROC_SETUP_BARS_DUPLICATE_FABRIC_ID_ERR if chips with duplicate +// fabric node/chip IDs are detected, +// RC_PROC_SETUP_BARS_NODE_NON_MIRRORED_RANGE_OVERLAP_ERR if overlap +// is detected between existing node non-mirrored range +// and that of new chip being processed, +// RC_PROC_SETUP_BARS_NODE_MIRRORED_RANGE_OVERLAP_ERR if overlap +// is detected between existing node mirrored range +// and that of new chip being processed, +// RC_PROC_SETUP_BARS_INVALID_BAR_REG_DEF if BAR register definition +// structure is invalid, +// RC_PROC_SETUP_BARS_SIZE_XLATE_ERR if logical->physical size +// translation is unsuccessful, +// else failing return code +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_setup_bars( + std::vector<proc_setup_bars_proc_chip>& i_proc_chips, + const bool& i_init_local_chip_local_node); + +} // extern "C" + + +#endif // _PROC_SETUP_BARS_H_ diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_errors.xml b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_errors.xml new file mode 100644 index 000000000..512fa602d --- /dev/null +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_errors.xml @@ -0,0 +1,146 @@ +<!-- IBM_PROLOG_BEGIN_TAG + This is an automatically generated prolog. + + $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_errors.xml $ + + IBM CONFIDENTIAL + + COPYRIGHT International Business Machines Corp. 2012 + + p1 + + Object Code Only (OCO) source materials + Licensed Internal Code Source Materials + IBM HostBoot Licensed Internal Code + + The source code for this program is not published or other- + wise divested of its trade secrets, irrespective of what has + been deposited with the U.S. Copyright Office. + + Origin: 30 + + IBM_PROLOG_END_TAG --> +<!-- Error definitions for proc_setup_bars --> +<hwpErrors> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_SETUP_BARS_NON_MIRRORED_RANGE_ATTR_ERR</rc> + <description>Invalid definition for non-mirrored address range (from platform attributes).</description> + <ffdc>BASE_ADDR</ffdc> + <ffdc>SIZE</ffdc> + </hwpError> + <hwpError> + <rc>RC_PROC_SETUP_BARS_NON_MIRRORED_RANGE_OVERLAP_ATTR_ERR</rc> + <description>Invalid definition for non-mirrored address ranges (from platform attributes), two or more ranges on this chip overlap.</description> + </hwpError> + <hwpError> + <rc>RC_PROC_SETUP_BARS_NON_MIRRORED_RANGE_ERR</rc> + <description>Invalid definition for non-mirrored address range.</description> + <ffdc>BASE_ADDR</ffdc> + <ffdc>SIZE</ffdc> + </hwpError> + <hwpError> + <rc>RC_PROC_SETUP_BARS_MIRRORED_RANGE_ATTR_ERR</rc> + <description>Invalid definition for mirrored address range (from platform attributes).</description> + <ffdc>BASE_ADDR</ffdc> + <ffdc>SIZE</ffdc> + </hwpError> + <hwpError> + <rc>RC_PROC_SETUP_BARS_MIRRORED_RANGE_OVERLAP_ATTR_ERR</rc> + <description>Invalid definition for mirrored address ranges (from platform attributes), two or more ranges on this chip overlap.</description> + </hwpError> + <hwpError> + <rc>RC_PROC_SETUP_BARS_MIRRORED_RANGE_ERR</rc> + <description>Invalid definition for mirrored address range.</description> + <ffdc>BASE_ADDR</ffdc> + <ffdc>SIZE</ffdc> + </hwpError> + <hwpError> + <rc>RC_PROC_SETUP_BARS_FOREIGN_NEAR_RANGE_ATTR_ERR</rc> + <description>Invalid definition for foreign near address range (from platform attributes).</description> + <ffdc>BASE_ADDR</ffdc> + <ffdc>SIZE</ffdc> + </hwpError> + <hwpError> + <rc>RC_PROC_SETUP_BARS_FOREIGN_FAR_RANGE_ATTR_ERR</rc> + <description>Invalid definition for foreign far address range (from platform attributes).</description> + <ffdc>BASE_ADDR</ffdc> + <ffdc>SIZE</ffdc> + </hwpError> + <hwpError> + <rc>RC_PROC_SETUP_BARS_PSI_BAR_ATTR_ERR</rc> + <description>Invalid definition for PSI Bridge BAR address range (from platform attributes).</description> + <ffdc>BASE_ADDR</ffdc> + <ffdc>SIZE</ffdc> + </hwpError> + <hwpError> + <rc>RC_PROC_SETUP_BARS_FSP_BAR_ATTR_ERR</rc> + <description>Invalid definition for FSP BAR address range (from platform attributes).</description> + <ffdc>BASE_ADDR</ffdc> + <ffdc>SIZE</ffdc> + </hwpError> + <hwpError> + <rc>RC_PROC_SETUP_BARS_FSP_MMIO_MASK_ATTR_ERR</rc> + <description>Invalid definition for FSP MMIO Mask address range (from platform attributes).</description> + <ffdc>SIZE</ffdc> + </hwpError> + <hwpError> + <rc>RC_PROC_SETUP_BARS_INTP_BAR_ATTR_ERR</rc> + <description>Invalid definition for INTP BAR address range (from platform attributes).</description> + <ffdc>BASE_ADDR</ffdc> + <ffdc>SIZE</ffdc> + </hwpError> + <hwpError> + <rc>RC_PROC_SETUP_BARS_NX_MMIO_BAR_ATTR_ERR</rc> + <description>Invalid definition for NX MMIO BAR address range (from platform attributes).</description> + <ffdc>BASE_ADDR</ffdc> + <ffdc>SIZE</ffdc> + </hwpError> + <hwpError> + <rc>RC_PROC_SETUP_BARS_PCIE_BAR_ATTR_ERR</rc> + <description>Invalid definition for PCIe BAR address range (from platform attributes).</description> + <ffdc>UNIT</ffdc> + <ffdc>RANGE</ffdc> + <ffdc>BASE_ADDR</ffdc> + <ffdc>SIZE</ffdc> + </hwpError> + <hwpError> + <rc>RC_PROC_SETUP_BARS_NODE_ADD_INTERNAL_ERR</rc> + <description>Internal Error. Error encountered adding node to SMP structure.</description> + </hwpError> + <hwpError> + <rc>RC_PROC_SETUP_BARS_NODE_FIND_INTERNAL_ERR</rc> + <description>Internal Error. Error encountered attempting to find node in SMP structure.</description> + </hwpError> + <hwpError> + <rc>RC_PROC_SETUP_BARS_DUPLICATE_FABRIC_ID_ERR</rc> + <description>Multiple chips found with identifcal fabric node/chip ID attribute values.</description> + <ffdc>NODE_ID</ffdc> + <ffdc>CHIP_ID</ffdc> + </hwpError> + <hwpError> + <rc>RC_PROC_SETUP_BARS_NODE_NON_MIRRORED_RANGE_OVERLAP_ERR</rc> + <description>Existing node non-mirrored range overlaps chip non-mirrored range.</description> + <ffdc>NODE_BASE_ADDR</ffdc> + <ffdc>NODE_SIZE</ffdc> + <ffdc>CHIP_BASE_ADDR</ffdc> + <ffdc>CHIP_SIZE</ffdc> + </hwpError> + <hwpError> + <rc>RC_PROC_SETUP_BARS_NODE_MIRRORED_RANGE_OVERLAP_ERR</rc> + <description>Existing node mirrored range overlaps chip mirrored range.</description> + <ffdc>NODE_BASE_ADDR</ffdc> + <ffdc>NODE_SIZE</ffdc> + <ffdc>CHIP_BASE_ADDR</ffdc> + <ffdc>CHIP_SIZE</ffdc> + </hwpError> + <hwpError> + <rc>RC_PROC_SETUP_BARS_INVALID_BAR_REG_DEF</rc> + <description>Internal error. Invalid proc_setup_bars_bar_reg_def structure content.</description> + </hwpError> + <hwpError> + <rc>RC_PROC_SETUP_BARS_SIZE_XLATE_ERR</rc> + <description>Internal error. Unsupported size translation for proc_setup_bars_bar_reg_def structure.</description> + <ffdc>SIZE</ffdc> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_l3_attributes.xml b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_l3_attributes.xml new file mode 100644 index 000000000..7d72575db --- /dev/null +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_l3_attributes.xml @@ -0,0 +1,71 @@ +<!-- IBM_PROLOG_BEGIN_TAG + This is an automatically generated prolog. + + $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_l3_attributes.xml $ + + IBM CONFIDENTIAL + + COPYRIGHT International Business Machines Corp. 2012 + + p1 + + Object Code Only (OCO) source materials + Licensed Internal Code Source Materials + IBM HostBoot Licensed Internal Code + + The source code for this program is not published or other- + wise divested of its trade secrets, irrespective of what has + been deposited with the U.S. Copyright Office. + + Origin: 30 + + IBM_PROLOG_END_TAG --> +<!-- proc_setup_bars_l3_attributes.xml --> +<attributes> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_L3_BAR1_REG</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>L3 BAR1 register value + creator: proc_setup_bars + consumer: winkle image setup procedures + notes: + 64-bit register value + SCOM address: 0x1001080B + </description> + <valueType>uint64</valueType> + <writeable/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_L3_BAR2_REG</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>L3 BAR2 register value + creator: proc_setup_bars + consumer: winkle image setup procedures + notes: + 64-bit register value + SCOM address: 0x10010813 + </description> + <valueType>uint64</valueType> + <writeable/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_L3_BAR_GROUP_MASK_REG</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>L3 BAR Group Mask register value + creator: proc_setup_bars + consumer: winkle image setup procedures + notes: + 64-bit register value + SCOM address: 0x10010816 + </description> + <valueType>uint64</valueType> + <writeable/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> +</attributes>
\ No newline at end of file diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml new file mode 100644 index 000000000..aa4cf90f9 --- /dev/null +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml @@ -0,0 +1,224 @@ +<!-- IBM_PROLOG_BEGIN_TAG + This is an automatically generated prolog. + + $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml $ + + IBM CONFIDENTIAL + + COPYRIGHT International Business Machines Corp. 2012 + + p1 + + Object Code Only (OCO) source materials + Licensed Internal Code Source Materials + IBM HostBoot Licensed Internal Code + + The source code for this program is not published or other- + wise divested of its trade secrets, irrespective of what has + been deposited with the U.S. Copyright Office. + + Origin: 30 + + IBM_PROLOG_END_TAG --> +<!-- proc_setup_bars_memory_attributes.xml --> +<attributes> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_MEM_BASE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Base address for non-mirrored memory regions + creator: platform (proc_config_base_addr) + consumer: mss_setup_bars + firmware notes: + 64-bit RA + </description> + <valueType>uint64</valueType> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_MEM_BASES</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Non-mirrored memory base addresses + creator: mss_setup_bars + consumer: proc_setup_bars, platform + firmware notes: + 64-bit RA + eight independent non-mirrored segments are supported + (max number based on Venice design) + </description> + <valueType>uint64</valueType> + <array>8</array> + <writeable/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_MEM_SIZES</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Size of non-mirrored memory regions + creator: mss_setup_bars + consumer: proc_setup_bars, platform + firmware notes: + for given index value, address space assumed to be contiguous + from ATTR_PROC_MEM_BASES value at matching index + eight independent non-mirrored segments are supported + (max number based on Venice design) + </description> + <valueType>uint64</valueType> + <array>8</array> + <writeable/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_MIRROR_BASE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Base address for mirrored memory regions + creator: platform (proc_config_base_addr) + consumer: mss_setup_bars + firmware notes: + 64-bit RA + </description> + <valueType>uint64</valueType> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_MIRROR_BASES</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Mirrored memory base addresses + creator: mss_setup_bars + consumer: proc_setup_bars, platform + firmware notes: + 64-bit RA + four independent mirrored segments are supported + (max number based on Venice design) + </description> + <valueType>uint64</valueType> + <array>4</array> + <writeable/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_MIRROR_SIZES</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Size of mirrored memory region + creator: mss_setup_bars + consumer: proc_setup_bars, platform + firmware notes: + for given index value, address space assumed to be contiguous + from ATTR_PROC_MIRROR_BASES value at matching index + four independent mirrored segments are supported + (max number based on Venice design) + </description> + <valueType>uint64</valueType> + <array>4</array> + <writeable/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_FOREIGN_NEAR_BASE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Foreign (near) address region base address + creator: platform + consumer: proc_setup_bars + firmware notes: + 64-bit RA + two independent regions are supported + (one per foreign link) + </description> + <valueType>uint64</valueType> + <array>2</array> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_FOREIGN_NEAR_SIZE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Size of foreign (near) region + creator: platform + consumer: proc_setup_bars + firmware notes: + address space assumed to be contiguous from associated + ATTR_PROC_FOREIGN_NEAR_BASE for given index value + two independent regions are supported + (one per foreign link) + </description> + <valueType>uint64</valueType> + <array>2</array> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_FOREIGN_FAR_BASE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Foreign (far) address region base address + creator: platform + consumer: proc_setup_bars + firmware notes: + 64-bit RA + two independent regions are supported + (one per foreign link) + </description> + <valueType>uint64</valueType> + <array>2</array> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_FOREIGN_FAR_SIZE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Size of foreign (far) region + creator: platform + consumer: proc_setup_bars + firmware notes: + address space assumed to be contiguous from associated + ATTR_PROC_FOREIGN_FAR_BASE for given index value + two independent regions are supported + (one per foreign link) + </description> + <valueType>uint64</valueType> + <array>2</array> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_HA_BASE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>HA logging base address + firmware notes: + 64-bit RA + eight independent segments are supported + (max number based on Venice design) + </description> + <valueType>uint64</valueType> + <array>8</array> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_HA_SIZE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Size of HA memory region + firmware notes: + address space assumed to be contiguous from associated + ATTR_PROC_HA_BASE for given index value + eight independent segments are supported + (max number based on Venice design) + </description> + <valueType>uint64</valueType> + <array>8</array> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> +</attributes> diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml new file mode 100644 index 000000000..efede3a78 --- /dev/null +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml @@ -0,0 +1,306 @@ +<!-- IBM_PROLOG_BEGIN_TAG + This is an automatically generated prolog. + + $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml $ + + IBM CONFIDENTIAL + + COPYRIGHT International Business Machines Corp. 2012 + + p1 + + Object Code Only (OCO) source materials + Licensed Internal Code Source Materials + IBM HostBoot Licensed Internal Code + + The source code for this program is not published or other- + wise divested of its trade secrets, irrespective of what has + been deposited with the U.S. Copyright Office. + + Origin: 30 + + IBM_PROLOG_END_TAG --> +<!-- proc_setup_bars_mmio_attributes.xml --> +<attributes> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_PSI_BRIDGE_BAR_ENABLE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>PSI Bridge BAR enable + creator: platform + consumer: proc_setup_bars + firmware notes: none + </description> + <valueType>uint8</valueType> + <enum>DISABLE = 0x0, ENABLE = 0x1</enum> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>PSI Bridge BAR base address value + creator: platform + consumer: proc_setup_bars + firmware notes: + 64-bit address representing BAR RA + NOTE: BAR register covers RA 14:43 + NOTE: Implied size of 1MB + </description> + <valueType>uint64</valueType> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_FSP_BAR_ENABLE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>FSP BAR enable + creator: platform + consumer: proc_setup_bars + firmware notes: none + </description> + <valueType>uint8</valueType> + <enum>DISABLE = 0x0, ENABLE = 0x1</enum> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_FSP_BAR_BASE_ADDR</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>FSP BAR base address value + creator: platform + consumer: proc_setup_bars + firmware notes: + 64-bit address representing BAR RA + NOTE: BAR register covers RA 14:43 + </description> + <valueType>uint64</valueType> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_FSP_BAR_SIZE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>FSP BAR size value + creator: platform + consumer: proc_setup_bars + firmware notes: none + </description> + <valueType>uint64</valueType> + <enum> + 4_GB = 0x0000000100000000, + 2_GB = 0x0000000080000000, + 1_GB = 0x0000000040000000, + 512_MB = 0x0000000020000000, + 256_MB = 0x0000000010000000, + 128_MB = 0x0000000008000000, + 64_MB = 0x0000000004000000, + 32_MB = 0x0000000002000000, + 16_MB = 0x0000000001000000, + 8_MB = 0x0000000000800000, + 4_MB = 0x0000000000400000, + 2_MB = 0x0000000000200000, + 1_MB = 0x0000000000100000 + </enum> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_FSP_MMIO_MASK_SIZE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>FSP MMIO mask size value + creator: platform + consumer: proc_setup_bars + firmware notes: + AND mask applied to RA 32:35 when transmitting address to FSP + NOTE: RA 14:31 are always replaced with zero + </description> + <valueType>uint64</valueType> + <enum> + 4_GB = 0x0000000100000000, + 2_GB = 0x0000000080000000, + 1_GB = 0x0000000040000000, + 512_MB = 0x0000000020000000, + 256_MB = 0x0000000010000000 + </enum> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_INTP_BAR_ENABLE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>INTP BAR enable + creator: platform + consumer: proc_setup_bars + firmware notes: none + </description> + <valueType>uint8</valueType> + <enum>DISABLE = 0x0, ENABLE = 0x1</enum> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_INTP_BAR_BASE_ADDR</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>INTP BAR base address value + creator: platform + consumer: proc_setup_bars + firmware notes: + 64-bit address representing BAR RA + NOTE: BAR register covers RA 14:43 + NOTE: Implied size of 1MB + </description> + <valueType>uint64</valueType> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_NX_MMIO_BAR_ENABLE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>NX MMIO BAR enable + creator: platform + consumer: proc_setup_bars + firmware notes: none + </description> + <valueType>uint8</valueType> + <enum>DISABLE = 0x0, ENABLE = 0x1</enum> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_NX_MMIO_BAR_BASE_ADDR</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>NX MMIO BAR base address value + creator: platform + consumer: proc_setup_bars + firmware notes: + 64-bit address representing BAR RA + NOTE: BAR register covers RA 14:51 + </description> + <valueType>uint64</valueType> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_NX_MMIO_BAR_SIZE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>NX MMIO BAR size value + creator: platform + consumer: proc_setup_bars + firmware notes: none + </description> + <valueType>uint64</valueType> + <enum> + 16_GB = 0x0000000400000000, + 16_MB = 0x0000000001000000, + 1_MB = 0x0000000000100000, + 64_KB = 0x0000000000010000, + 4_KB = 0x0000000000001000 + </enum> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_PCIE_BAR_ENABLE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>PCIE BAR enable + creator: platform + consumer: proc_setup_bars + firmware notes: + first dimension: PCIE unit number (0:2) + second dimension: BAR number (0:2) + </description> + <valueType>uint8</valueType> + <enum>DISABLE = 0x0, ENABLE = 0x1</enum> + <array>3,3</array> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_PCIE_BAR_BASE_ADDR</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>PCIE BAR base address value + creator: platform + consumer: proc_setup_bars + firmware notes: + 64-bit address representing BAR RA + first dimension: PCIE unit number (0:2) + second dimension: BAR number (0:2) + NOTE: BAR0/1 registers cover RA 14:47 + NOTE: BAR2 registers covers RA 14:51 + </description> + <valueType>uint64</valueType> + <array>3,3</array> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_PCIE_BAR_SIZE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>PCIE BAR size value + creator: platform + consumer: proc_setup_bars + firmware notes: + first dimension: PCIE unit number (0:2) + second dimension: BAR number (0:2) + NOTE: supported BAR0/1 sizes are from 64KB-1PB + NOTE: only supported BAR2 size is 4KB + </description> + <valueType>uint64</valueType> + <enum> + 1_PB = 0x0004000000000000, + 512_TB = 0x0002000000000000, + 256_TB = 0x0001000000000000, + 128_TB = 0x0000800000000000, + 64_TB = 0x0000400000000000, + 32_TB = 0x0000200000000000, + 16_TB = 0x0000100000000000, + 8_TB = 0x0000080000000000, + 4_TB = 0x0000040000000000, + 2_TB = 0x0000020000000000, + 1_TB = 0x0000010000000000, + 512_GB = 0x0000008000000000, + 256_GB = 0x0000004000000000, + 128_GB = 0x0000002000000000, + 64_GB = 0x0000001000000000, + 32_GB = 0x0000000800000000, + 16_GB = 0x0000000400000000, + 8_GB = 0x0000000200000000, + 4_GB = 0x0000000100000000, + 2_GB = 0x0000000080000000, + 1_GB = 0x0000000040000000, + 512_MB = 0x0000000020000000, + 256_MB = 0x0000000010000000, + 128_MB = 0x0000000008000000, + 64_MB = 0x0000000004000000, + 32_MB = 0x0000000002000000, + 16_MB = 0x0000000001000000, + 8_MB = 0x0000000000800000, + 4_MB = 0x0000000000400000, + 2_MB = 0x0000000000200000, + 1_MB = 0x0000000000100000, + 512_KB = 0x0000000000080000, + 256_KB = 0x0000000000040000, + 128_KB = 0x0000000000020000, + 64_KB = 0x0000000000010000, + 4_KB = 0x0000000000001000 + </enum> + <array>3,3</array> + <platInit/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> +</attributes>
\ No newline at end of file diff --git a/src/usr/hwpf/hwp/memory_attributes.xml b/src/usr/hwpf/hwp/memory_attributes.xml index 7b13b1d67..8e8499941 100644 --- a/src/usr/hwpf/hwp/memory_attributes.xml +++ b/src/usr/hwpf/hwp/memory_attributes.xml @@ -1,25 +1,25 @@ <!-- IBM_PROLOG_BEGIN_TAG This is an automatically generated prolog. - + $Source: src/usr/hwpf/hwp/memory_attributes.xml $ - + IBM CONFIDENTIAL - + COPYRIGHT International Business Machines Corp. 2012 - + p1 - + Object Code Only (OCO) source materials Licensed Internal Code Source Materials IBM HostBoot Licensed Internal Code - + The source code for this program is not published or other- wise divested of its trade secrets, irrespective of what has been deposited with the U.S. Copyright Office. - + Origin: 30 - IBM_PROLOG_END_TAG --> + <attributes> <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB --> <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP --> |
