PON - HW procedures update - Set #1

Change-Id: Ibe998c8cfd6ad39f63e9ab91f836a1d9aa428431
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2661
Tested-by: Jenkins Server
Reviewed-by: Van H. Lee <vanlee@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

12 files changed, 327 insertions, 310 deletions

diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pmc_deconfig_setup.C b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pmc_deconfig_setup.C
index 0a9c1fd7f..619ff0b08 100755
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pmc_deconfig_setup.C
+++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pmc_deconfig_setup.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pmc_deconfig_setup.C,v 1.4 2012/09/20 12:22:42 stillgs Exp $
+// $Id: p8_pmc_deconfig_setup.C,v 1.6 2012/09/28 15:24:33 stillgs Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pmc_deconfig_setup.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -60,10 +60,7 @@
 #include "p8_scom_addresses.H"
 #include "p8_pmc_deconfig_setup.H"
 
-#ifdef FAPIECMD
 extern "C" {
-#endif
-
 
 using namespace fapi;
 
@@ -100,7 +97,6 @@ p8_pmc_deconfig_setup(const Target& i_target)
     ecmdDataBufferBase              data(64);
     ecmdDataBufferBase              config_data(64);
     std::vector<fapi::Target>       l_exChiplets;
-//    std::vector<Target>::iterator   l_itr;
     uint8_t                         l_functional = 0;
     uint8_t                         l_ex_number = 0;
     bool                            core_flag = false;
@@ -116,23 +112,23 @@ p8_pmc_deconfig_setup(const Target& i_target)
 	}
 
 	FAPI_DBG("\tChiplet vector size  => %u ", l_exChiplets.size());
-    
+
     // Set the buffer to assume that all chiplets are deconfigured.  Validly configured
     // chiplets will then turn off this deconfiguration.
     FAPI_INF("\tAssuming all cores are non-functional");
     e_rc |= config_data.flushTo0();
-    e_rc |= config_data.setBit(0, 16);   
+    e_rc |= config_data.setBit(0, 16);
     if (e_rc)
     {
         FAPI_ERR("Error (0x%x) flushing ecmdDataBufferBase", e_rc);
         l_rc.setEcmdError(e_rc);
         return l_rc;
     }
-    
+
     // Iterate through the returned chiplets
 	for (uint8_t j=0; j < l_exChiplets.size(); j++)
 	{
-       
+
         // Determine if it's functional
         l_rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_exChiplets[j], l_functional);
         if (l_rc)
@@ -141,8 +137,8 @@ p8_pmc_deconfig_setup(const Target& i_target)
             break;
         }
         else
-        {               
-            if ( l_functional ) 
+        {
+            if ( l_functional )
             {
                 // Get the core number
                 l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[j], l_ex_number);
@@ -153,19 +149,19 @@ p8_pmc_deconfig_setup(const Target& i_target)
                 }
 
                 l_rc=fapiGetScom(i_target, (EX_GP3_0x100F0012+(l_ex_number*0x01000000)), data);
-                if(l_rc) 
+                if(l_rc)
                 {
-                    FAPI_ERR("GetScom error"); 
+                    FAPI_ERR("GetScom error");
                     break;
                 }
 
-                FAPI_DBG("\tGP0(0) from core %x (@ %08llx) => 0x%16llx", 
-                                l_ex_number, 
+                FAPI_DBG("\tGP0(0) from core %x (@ %08llx) => 0x%16llx",
+                                l_ex_number,
                                 (EX_GP3_0x100F0012+(l_ex_number*0x01000000)),
                                 data.getDoubleWord(0));
 
-                // Check if chiplet enable bit is set (configured);  If so, 
-                // clear the chiplet bit in PMC Core Deconfig Register (0:15) 
+                // Check if chiplet enable bit is set (configured);  If so,
+                // clear the chiplet bit in PMC Core Deconfig Register (0:15)
                 // indexed by ex number
                 if ( data.isBitSet(0) )
                 {
@@ -177,25 +173,25 @@ p8_pmc_deconfig_setup(const Target& i_target)
                         l_rc.setEcmdError(e_rc);
                         break;
                     }
+                    core_flag =  true;
                 }
-	            core_flag =  true;
-                }
+            }
             else  // Not Functional so skip it
             {
                 // Do nothing
             }
         }
 	}
-    
+
     // If no errors, write the deconfig register
     if (!l_rc)
-    {    
+    {
 	    if ( core_flag )
         {
             l_rc=fapiPutScom(i_target, PMC_CORE_DECONFIG_REG_0x0006200D , config_data);
-            if(l_rc) 
+            if(l_rc)
             {
-                FAPI_ERR("PutScom error"); 
+                FAPI_ERR("PutScom error");
             }
             else
             {
@@ -212,7 +208,5 @@ p8_pmc_deconfig_setup(const Target& i_target)
 }
 
 
-
-#ifdef FAPIECMD
 } //end extern C
-#endif
+
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar.C b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar.C
index ef587eef0..38687022f 100644
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar.C
+++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar.C
@@ -21,7 +21,7 @@
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
 
-// $Id: p8_set_pore_bar.C,v 1.3 2012/10/23 20:52:31 stillgs Exp $
+// $Id: p8_set_pore_bar.C,v 1.4 2012/12/07 20:43:07 stillgs Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_set_pore_bar.C,v $
 //-------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -38,18 +38,18 @@
 /// \verbatim
 ///
 ///     Address and size of SLW image for the target (chip) is passed based on
-///     where the caller has placed the image for this target in the platform
-///     memory.
+///     where the caller has placed the image for this target in the platform 
+///     memory.  
 ///
 ///     The Base Address (BAR) and a mask for the region in which the SLW
 ///     image is placed is passed.  This is used to establish the PBA BAR and
 ///     mask hardware to set the legal bounds for SLW accesses.
 ///
-///     The BAR defines address bits 14:43 in natural bit alignment (eg no
+///     The BAR defines address bits 14:43 in natural bit alignment (eg no 
 ///     shifting)
 ///
 ///     The Size (in MB) of the region where image is located.
-///         If not a power of two value, the value will be rounded up to the
+///         If not a power of two value, the value will be rounded up to the 
 ///         next power of 2 for setting the hardware mask
 ///
 ///         If 0 is defined and the BAR is also defined as 0, then the BAR
@@ -94,7 +94,6 @@
 #include "p8_pm.H"
 #include "p8_pba_init.H"
 #include "p8_pba_bar_config.H"
-//#include "pba_firmware_registers.h"
 #include "pgp_pba.h"
 #include "sbe_xip_image.h"
 
@@ -131,9 +130,9 @@ fapi::ReturnCode pba_slave_reset(   const fapi::Target& i_target,
 ///                         located
 /// \param[in] i_mem_bar    Base address of the region where image is located
 /// \param[in] i_mem_size   Size (in MB) of the region where image is located
-///                         if not a power of two value, the value will be
-///                         rounded up to the next power of 2 for setting the
-///                         hardware mask.  The value of 0 is only legal if
+///                         if not a power of two value, the value will be 
+///                         rounded up to the next power of 2 for setting the 
+///                         hardware mask.  The value of 0 is only legal if 
 ///                         i_mem_bar is also 0;  else an error is indicated.
 /// \param[in] i_mem_type   Defines where the SLW image was loaded.  See
 ///                         p8_set_pore_bar.H enum for valid values.
@@ -164,7 +163,7 @@ p8_set_pore_bar(      const fapi::Target& i_target,
 //    uint64_t            computed_last_image_address;
 
     uint64_t            slw_branch_table_address;
-
+    
     pba_slvctln_t       ps;                         // PBA Slave
 
     // Hardcoded use of PBA BAR and Slave
@@ -181,14 +180,14 @@ p8_set_pore_bar(      const fapi::Target& i_target,
         FAPI_INF("Executing p8_set_pore_bar...");
         image_address = (uint64_t) i_image;
         FAPI_DBG("Passed address 0x%16llX ", image_address);
-
-        // Check if this is a BAR reset case.
+        
+        // Check if this is a BAR reset case. 
         if (i_mem_size == 0)
         {
             if(i_mem_bar != 0)
             {
-                FAPI_ERR("SLW Size is 0 but BAR is non-zero:  0x%16llx", i_mem_bar );
-                FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_SIZE0_ERROR);
+                FAPI_ERR("SLW Size is 0 but BAR is non-zero:  0x%16llx", i_mem_bar );               
+                FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_SIZE0_ERROR);  
                 break;
             }
             else
@@ -202,16 +201,16 @@ p8_set_pore_bar(      const fapi::Target& i_target,
                                                        i_mem_bar,
                                                        i_mem_size,
                                                        slw_pba_cmd_scope);
-
+                                                       
                 // No rc check is made as we're exiting anyway.
-
+                
                 // Exit the procedure as we don't want to access the image nor
                 // touch the SLW TBA or MRR settings.
                 break;
-            }
+            }      
         }
-
-
+        
+  
         // Get the Table Base Address from the image
         l_ecmdRc = sbe_xip_get_scalar((void*)   i_image,
                                                 "slw_branch_table",
@@ -361,12 +360,12 @@ p8_set_pore_bar(      const fapi::Target& i_target,
             // Check that the bar address passed is 1MB aligned (eg bits 44:63 are zero)
             //
             region_masked_address = i_mem_bar & 0x00000000000FFFFF;
-            if (region_masked_address != 0 )
-            {
-                FAPI_ERR("SLW BAR address is not 1MB aligned:  0x%16llx", i_mem_bar );
-                FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_PBABAR_ERROR);
+            if (region_masked_address != 0 )                        
+            {                                                                
+                FAPI_ERR("SLW BAR address is not 1MB aligned:  0x%16llx", i_mem_bar );               
+                FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_PBABAR_ERROR);  
                 break;
-            }
+            }                                                                
 
 
             // The PBA Mask indicates which bits from 23:43 (1MB grandularity) are
@@ -448,121 +447,92 @@ p8_set_pore_bar(      const fapi::Target& i_target,
             break;
         }
 
-        FAPI_DBG("Calling pba_bar_config to BAR %x Addr: 0x%16llX  Size: 0x%16llX",
-                        pba_bar, i_mem_bar, i_mem_size);
-
-        // Set the PBA BAR for the SLW region
-        FAPI_EXEC_HWP(rc, p8_pba_bar_config, i_target,
-                                               pba_bar,
-                                               i_mem_bar,
-                                               i_mem_size,
-                                               slw_pba_cmd_scope);
-        if(rc)
+        if (i_mem_type == SLW_MEMORY || i_mem_type == SLW_L3)
         {
-            break;
-        }
 
-        // Set the PBA Slave to use the above BAR
-        // \todo Does not yet comprehend the 24x7 setting to allow writing!!
-        //
-        // enable = 1;                 // Enable the slave
-        // mid_match_value=0x4;        // PORE-SLW engine
-        // mid_care_mask=0x7;          // Only the PORE-SLW
-        // write_ttype=0;              // DMA - though NA
-        // read_ttype=0;               // CL_RD_NC
-        // read_prefetch_ctl=0;        // Auto Early
-        // buf_invalidate_ctl=0;       // Disabled
-        // buf_alloc_w=0;              // SLW does not write.  24x7 will
-        // buf_alloc_a=1;              // SLW uses Buf A
-        // buf_alloc_b=0;              // SLW does not use buffer B
-        // buf_alloc_c=0;              // SLW does not use buffer C
-        // dis_write_gather=0;         // SLW does not write.  \todo 24x7
-        // wr_gather_timeout=0;        // SLW does not write   \todo 24x7
-        // write_tsize=0;              // SLW does not write   \todo 24x7
-        // extaddr=0;                  // Bits 23:36.  NA for SLW
-        //
+            FAPI_DBG("Calling pba_bar_config to BAR %x Addr: 0x%16llX  Size: 0x%16llX",
+                            pba_bar, i_mem_bar, i_mem_size);
+
+            // Set the PBA BAR for the SLW region
+            FAPI_EXEC_HWP(rc, p8_pba_bar_config, i_target,
+                                                   pba_bar,
+                                                   i_mem_bar,
+                                                   i_mem_size,
+                                                   slw_pba_cmd_scope);
+            if(rc) 
+            { 
+                break;
+            }
 
-    /*
-        // Clear the data buffer (for cleanliness)
-        l_ecmdRc |= data.flushTo0();
+            // Set the PBA Slave to use the above BAR
+            // \todo Does not yet comprehend the 24x7 setting to allow writing!!
+            //
+            // enable = 1;                 // Enable the slave
+            // mid_match_value=0x4;        // PORE-SLW engine
+            // mid_care_mask=0x7;          // Only the PORE-SLW
+            // write_ttype=0;              // DMA - though NA
+            // read_ttype=0;               // CL_RD_NC
+            // read_prefetch_ctl=0;        // Auto Early
+            // buf_invalidate_ctl=0;       // Disabled
+            // buf_alloc_w=0;              // SLW does not write.  24x7 will
+            // buf_alloc_a=1;              // SLW uses Buf A
+            // buf_alloc_b=0;              // SLW does not use buffer B
+            // buf_alloc_c=0;              // SLW does not use buffer C
+            // dis_write_gather=0;         // SLW does not write.  \todo 24x7
+            // wr_gather_timeout=0;        // SLW does not write   \todo 24x7
+            // write_tsize=0;              // SLW does not write   \todo 24x7
+            // extaddr=0;                  // Bits 23:36.  NA for SLW
+            //
 
+            // Slave 2 (PORE-SLW).  This is a read/write slave. Write gathering is
+            // allowed, but with the shortest possible timeout.  The slave is set up
+            // to allow normal reads and writes at initialization.  The 24x7 code may
+            // reprogram this slave for IMA writes using special code sequences that
+            // restore normal DMA writes after each IMA sequence.
 
-    ps.value = 0;
-    ps.fields.enable = 1;
-    ps.fields.mid_match_value = OCI_MASTER_ID_PORE_SLW;
-    ps.fields.mid_care_mask = 0x7;
-    ps.fields.read_ttype = PBA_READ_TTYPE_CL_RD_NC;
-    ps.fields.read_prefetch_ctl = PBA_READ_PREFETCH_NONE;
-    ps.fields.write_ttype = PBA_WRITE_TTYPE_DMA_PR_WR;
-    ps.fields.wr_gather_timeout = PBA_WRITE_GATHER_TIMEOUT_2_PULSES;
-    ps.fields.buf_alloc_a = 1;
-    ps.fields.buf_alloc_b = 1;
-    ps.fields.buf_alloc_c = 1;
-    ps.fields.buf_alloc_w = 1;
-
-    l_ecmdRc |=  data.setDoubleWord(0, ps.value);
-    if(l_ecmdRc)
-    {
-        FAPI_ERR("Error (0x%x) manipulating ecmdDataBufferBase for PBASLVCTL", l_ecmdRc);
-        rc.setEcmdError(l_ecmdRc);
-        return rc;
-    }
-        // set the PBASLVCTL reg
-        l_ecmdRc |= data.setBit(0);     // Enable the slave
-        l_ecmdRc |= data.setBit(1);     // PORE-SLW engine - 0b100
-        l_ecmdRc |= data.setBit(5,3);   // Care mask-only PORE-SLW
-        l_ecmdRc |= data.setBit(5,3);   // Allocate read buffer
-        l_ecmdRc |= data.setBit(5,3);   // Care mask-only PORE-SLW
-    */
-
-        // Slave 2 (PORE-SLW).  This is a read/write slave. Write gathering is
-        // allowed, but with the shortest possible timeout.  The slave is set up
-        // to allow normal reads and writes at initialization.  The 24x7 code may
-        // reprogram this slave for IMA writes using special code sequences that
-        // restore normal DMA writes after each IMA sequence.
-
-        rc = pba_slave_reset(i_target, SLW_PBA_SLAVE);
-        if (rc)
-        {
-            FAPI_ERR("PBA Slave Reset failed");
-            // \todo add FFDC
-             break;
-        }
+            rc = pba_slave_reset(i_target, SLW_PBA_SLAVE);
+            if (rc)
+            {
+                FAPI_ERR("PBA Slave Reset failed");
+                // \todo add FFDC
+                 break;
+            }
 
 
-        ps.value = 0;
-        ps.fields.enable = 1;
-        ps.fields.mid_match_value = OCI_MASTER_ID_PORE_SLW;
-        ps.fields.mid_care_mask = 0x7;
-        ps.fields.read_ttype = PBA_READ_TTYPE_CL_RD_NC;
-        ps.fields.read_prefetch_ctl = PBA_READ_PREFETCH_NONE;
-        ps.fields.write_ttype = PBA_WRITE_TTYPE_DMA_PR_WR;
-        ps.fields.wr_gather_timeout = PBA_WRITE_GATHER_TIMEOUT_2_PULSES;
-        ps.fields.buf_alloc_a = 1;
-        ps.fields.buf_alloc_b = 1;
-        ps.fields.buf_alloc_c = 1;
-        ps.fields.buf_alloc_w = 1;
-
-        l_ecmdRc |=  data.setDoubleWord(0, ps.value);
-        if(l_ecmdRc)
-        {
-            FAPI_ERR("Error (0x%x) manipulating ecmdDataBufferBase for PBASLVCTL", l_ecmdRc);
-            rc.setEcmdError(l_ecmdRc);
-            return rc;
-        }
+            ps.value = 0;
+            ps.fields.enable = 1;
+            ps.fields.mid_match_value = OCI_MASTER_ID_PORE_SLW;
+            ps.fields.mid_care_mask = 0x7;
+            ps.fields.read_ttype = PBA_READ_TTYPE_CL_RD_NC;
+            ps.fields.read_prefetch_ctl = PBA_READ_PREFETCH_NONE;
+            ps.fields.write_ttype = PBA_WRITE_TTYPE_DMA_PR_WR;
+            ps.fields.wr_gather_timeout = PBA_WRITE_GATHER_TIMEOUT_2_PULSES;
+            ps.fields.buf_alloc_a = 1;
+            ps.fields.buf_alloc_b = 1;
+            ps.fields.buf_alloc_c = 1;
+            ps.fields.buf_alloc_w = 1;
+
+            l_ecmdRc |=  data.setDoubleWord(0, ps.value);
+            if(l_ecmdRc)
+            {
+                FAPI_ERR("Error (0x%x) manipulating ecmdDataBufferBase for PBASLVCTL", l_ecmdRc);
+                rc.setEcmdError(l_ecmdRc);
+                return rc;
+            }
 
-        FAPI_DBG("  PBA_SLVCTL%x: 0x%16llx", pba_slave, data.getDoubleWord(0));
-        rc = fapiPutScom(i_target, PBA_SLVCTLs[pba_slave], data);
-        if (rc)
-        {
-            FAPI_ERR("Put SCOM error for PBA Slave Control");
-            return rc;
-        }
+            FAPI_DBG("  PBA_SLVCTL%x: 0x%16llx", pba_slave, data.getDoubleWord(0));
+            rc = fapiPutScom(i_target, PBA_SLVCTLs[pba_slave], data);
+            if (rc)
+            {
+                FAPI_ERR("Put SCOM error for PBA Slave Control");
+                return rc;
+            }
+        } // PBA setup for Memory or L3
     } while (0);
     return rc;
 }
 
-/// Reset a PBA slave with explicit timeout.
+/// Reset a PBA slave with explicit timeout.  
 ///
 /// \param id A PBA slave id in the range 0..3
 ///
@@ -580,23 +550,23 @@ p8_set_pore_bar(      const fapi::Target& i_target,
 fapi::ReturnCode
 pba_slave_reset(const fapi::Target& i_target, uint32_t id)
 {
-
+    
     uint32_t            poll_count = 0;
     pba_slvrst_t        psr;
     fapi::ReturnCode    rc;
     uint32_t            l_ecmdRc = 0;
     ecmdDataBufferBase  data(64);
 
-
+    
     // Tell PBA to reset the slave, then poll for completion with timeout.
     // The PBA is always polled at least twice to guarantee that we always
     // poll once after a timeout.
 
     psr.value = 0;
     psr.fields.set = PBA_SLVRST_SET(id);
-
+    
     FAPI_DBG("  PBA_SLVRST%x: 0x%16llx", id, psr.value);
-
+    
     l_ecmdRc |= data.setDoubleWord(0, psr.value);
     if(l_ecmdRc)
     {
@@ -604,7 +574,7 @@ pba_slave_reset(const fapi::Target& i_target, uint32_t id)
         rc.setEcmdError(l_ecmdRc);
         return rc;
     }
-
+        
     rc = fapiPutScom(i_target, PBA_SLVRST_0x00064001, data);
     if (rc)
     {
@@ -612,7 +582,7 @@ pba_slave_reset(const fapi::Target& i_target, uint32_t id)
     }
     else
     {
-        do
+        do 
         {
             rc = fapiGetScom(i_target, PBA_SLVRST_0x00064001, data);
             if (rc)
@@ -630,13 +600,13 @@ pba_slave_reset(const fapi::Target& i_target, uint32_t id)
             }
 
 
-            if (!(psr.fields.in_prog & PBA_SLVRST_IN_PROG(id)))
+            if (!(psr.fields.in_prog & PBA_SLVRST_IN_PROG(id))) 
             {
 	            break;
 	        }
 
             poll_count++;
-	        if (poll_count == PBA_SLAVE_RESET_TIMEOUT)
+	        if (poll_count == PBA_SLAVE_RESET_TIMEOUT) 
             {
 	            FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PBA_SLVRST_TIMED_OUT);
                 break;
diff --git a/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.C b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.C
index 2ef60754d..453c13493 100644
--- a/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.C
+++ b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.C
@@ -21,7 +21,7 @@
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
 // -*- mode: C++; c-file-style: "linux";  -*-
-// $Id: proc_prep_master_winkle.C,v 1.9 2012/09/11 14:06:21 jeshua Exp $
+// $Id: proc_prep_master_winkle.C,v 1.11 2012/10/24 22:22:23 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_prep_master_winkle.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -57,7 +57,6 @@
 //------------------------------------------------------------------------------
 #include "proc_prep_master_winkle.H"
 #include "p8_scom_addresses.H"
-#include "proc_sbe_ffdc.H"
 #include "p8_istep_num.H"
 #include "proc_sbe_trigger_winkle.H"
 
@@ -84,7 +83,7 @@ extern "C"
 // returns: FAPI_RC_SUCCESS if operation was successful, else error
 //------------------------------------------------------------------------------
     fapi::ReturnCode proc_prep_master_winkle(const fapi::Target & i_target, 
-                                             bool i_useRealSBE = true)
+                                             const bool & i_useRealSBE = true)
     {
         // data buffer to hold register values
         ecmdDataBufferBase data(64);
@@ -137,6 +136,7 @@ extern "C"
             if(rc_ecmd)
             {
                 FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd);
+
                 rc.setEcmdError(rc_ecmd);
                 break;
             }
diff --git a/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.H b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.H
index 0a384b567..39aeabf14 100644
--- a/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.H
+++ b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_prep_master_winkle.H,v 1.5 2012/08/24 18:32:51 jeshua Exp $
+// $Id: proc_prep_master_winkle.H,v 1.6 2012/10/24 22:22:43 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_prep_master_winkle.H,v $
 //------------------------------------------------------------------------------
 // *|
@@ -76,7 +76,7 @@ extern "C"
  * @return ReturnCode
  */
   fapi::ReturnCode proc_prep_master_winkle(const fapi::Target & i_target,
-                                           const bool i_useRealSBE);
+                                           const bool & i_useRealSBE);
 
 } // extern "C"
 
diff --git a/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle_errors.xml b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle_errors.xml
index 400d9e700..b1ee724c7 100644
--- a/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle_errors.xml
+++ b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle_errors.xml
@@ -1,46 +1,55 @@
-<!--  IBM_PROLOG_BEGIN_TAG
-     This is an automatically generated prolog.
-
-     $Source: src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle_errors.xml $
-
-     IBM CONFIDENTIAL
-
-     COPYRIGHT International Business Machines Corp. 2012
-
-     p1
-
-     Object Code Only (OCO) source materials
-     Licensed Internal Code Source Materials
-     IBM HostBoot Licensed Internal Code
-
-     The source code for this program is not published or other-
-     wise divested of its trade secrets, irrespective of what has
-     been deposited with the U.S. Copyright Office.
-
-     Origin: 30
-
-     IBM_PROLOG_END_TAG -->
-<!-- Error definitions for proc_prep_master_winkle procedure  -->
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle_errors.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2012                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Error definitions for proc_prep_master_winkle procedure -->
 <hwpErrors>
   <!-- *********************************************************************** -->
   <hwpError>
     <rc>RC_PROC_PREP_MASTER_WINKLE_SBE_NOT_RUNNING</rc>
     <description>The SBE is stopped and so will never wake up the master core</description>
-    <collectFfdc>proc_sbe_ffdc, CHIP_IN_ERROR</collectFfdc>
+    <collectRegisterFfdc>
+        <id>REG_FFDC_PROC_SBE_REGISTERS</id>
+        <target>CHIP_IN_ERROR</target>
+    </collectRegisterFfdc>
     <ffdc>SBE_STATUS</ffdc>
   </hwpError>
   <!-- *********************************************************************** -->
   <hwpError>
     <rc>RC_PROC_PREP_MASTER_WINKLE_BAD_ISTEP_NUM</rc>
     <description>The SBE is not at the correct istep number</description>
-    <collectFfdc>proc_sbe_ffdc, CHIP_IN_ERROR</collectFfdc>
+    <collectRegisterFfdc>
+        <id>REG_FFDC_PROC_SBE_REGISTERS</id>
+        <target>CHIP_IN_ERROR</target>
+    </collectRegisterFfdc>
     <ffdc>SBE_VITAL</ffdc>
   </hwpError>
   <!-- *********************************************************************** -->
   <hwpError>
     <rc>RC_PROC_PREP_MASTER_WINKLE_BAD_SUBSTEP_NUM</rc>
     <description>The SBE is not at the correct substep number</description>
-    <collectFfdc>proc_sbe_ffdc, CHIP_IN_ERROR</collectFfdc>
+    <collectRegisterFfdc>
+        <id>REG_FFDC_PROC_SBE_REGISTERS</id>
+        <target>CHIP_IN_ERROR</target>
+    </collectRegisterFfdc>
     <ffdc>SBE_VITAL</ffdc>
   </hwpError>
 </hwpErrors>
diff --git a/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.C b/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.C
index a8d992d1c..fda8bcc98 100644
--- a/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.C
+++ b/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.C
@@ -21,7 +21,7 @@
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
 // -*- mode: C++; c-file-style: "linux";  -*-
-// $Id: proc_stop_deadman_timer.C,v 1.6 2012/09/21 19:35:08 stillgs Exp $
+// $Id: proc_stop_deadman_timer.C,v 1.7 2012/10/24 22:23:37 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_stop_deadman_timer.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -54,7 +54,6 @@
 //------------------------------------------------------------------------------
 #include "proc_stop_deadman_timer.H"
 #include "p8_scom_addresses.H"
-#include "proc_sbe_ffdc.H"
 #include "p8_istep_num.H"
 #include "proc_sbe_trigger_winkle.H"
 
diff --git a/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer_errors.xml b/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer_errors.xml
index b54043d2f..fa2a94533 100644
--- a/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer_errors.xml
+++ b/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer_errors.xml
@@ -1,39 +1,45 @@
-<!--  IBM_PROLOG_BEGIN_TAG
-     This is an automatically generated prolog.
-
-     $Source: src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer_errors.xml $
-
-     IBM CONFIDENTIAL
-
-     COPYRIGHT International Business Machines Corp. 2012
-
-     p1
-
-     Object Code Only (OCO) source materials
-     Licensed Internal Code Source Materials
-     IBM HostBoot Licensed Internal Code
-
-     The source code for this program is not published or other-
-     wise divested of its trade secrets, irrespective of what has
-     been deposited with the U.S. Copyright Office.
-
-     Origin: 30
-
-     IBM_PROLOG_END_TAG -->
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer_errors.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2012                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
 <!-- Error definitions for proc_stop_deadman_timer procedure -->
 <hwpErrors>
   <!-- *********************************************************************** -->
   <hwpError>
     <rc>RC_PROC_STOP_DEADMAN_TIMER_BAD_ISTEP_NUM</rc>
     <description>The SBE is not at the correct istep number</description>
-    <collectFfdc>proc_sbe_ffdc, CHIP_IN_ERROR</collectFfdc>
+    <collectRegisterFfdc>
+        <id>REG_FFDC_PROC_SBE_REGISTERS</id>
+        <target>CHIP_IN_ERROR</target>
+    </collectRegisterFfdc>
     <ffdc>SBE_VITAL</ffdc>
   </hwpError>
   <!-- *********************************************************************** -->
   <hwpError>
     <rc>RC_PROC_STOP_DEADMAN_TIMER_BAD_SUBSTEP_NUM</rc>
     <description>The SBE is not at the correct substep number</description>
-    <collectFfdc>proc_sbe_ffdc, CHIP_IN_ERROR</collectFfdc>
+    <collectRegisterFfdc>
+        <id>REG_FFDC_PROC_SBE_REGISTERS</id>
+        <target>CHIP_IN_ERROR</target>
+    </collectRegisterFfdc>
     <ffdc>SBE_VITAL</ffdc>
   </hwpError>
 </hwpErrors>
diff --git a/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile b/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile
index dbcd537e5..4321f9b58 100644
--- a/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile
@@ -1,8 +1,9 @@
-#-- $Id: cen.dmi.scom.initfile,v 1.3 2012/06/19 23:16:29 jmcgill Exp $
+#-- $Id: cen.dmi.scom.initfile,v 1.6 2012/10/08 20:12:49 bwieman Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--     1.4 |thomsen |07/13/12|Updated non-mirrored PRBS_TAP_ID's to have abcdefgabcdefgabc... pattern
 #--     1.3 |jmcgill |06/19/12|Update non-mirrored mode PRBS TX/RX values to make DMI.SETUP_ID = DMI_BUS, setup RX FENCE
 #--     1.2 |thomsen |06/19/12|Updated PRBS_TAP_ID's to match processor
 #--     1.1 |thomsen |06/11/12|Created initial version
@@ -211,7 +212,7 @@ scom 0x800.0b(rx_dyn_rpr_err_tallying2_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr){
 # /_/   /_/ |_/_____/____/    /_/  \__,_/ .___/   /____/\___/_/\___/\___/\__/____/  banner2 -fslant
 #                                      /_/                                      
 #-------------------------------------------------------------------------------------
-# PER-LANE (RX)
+# PER-LANE (RX: 17 lanes)
 #-------------------------------------------------------------------------------------
 scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_0).0x(cn_gcr_addr){
         bits,           scom_data,                       expr;
@@ -261,17 +262,17 @@ scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_8).0x(cn_gcr_addr){
 scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_9).0x(cn_gcr_addr){
         bits,           scom_data,                       expr;
         rx_prbs_tap_id, rx_prbs_tap_id_pattern_h,        (def_rx_mirrored_mode);
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_h,        (def_rx_non_mirrored_mode);
+        rx_prbs_tap_id, rx_prbs_tap_id_pattern_b,        (def_rx_non_mirrored_mode);
 }
 scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_10).0x(cn_gcr_addr){
         bits,           scom_data,                       expr;
         rx_prbs_tap_id, rx_prbs_tap_id_pattern_g,        (def_rx_mirrored_mode);
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_g,        (def_rx_non_mirrored_mode);
+        rx_prbs_tap_id, rx_prbs_tap_id_pattern_c,        (def_rx_non_mirrored_mode);
 }
 scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_11).0x(cn_gcr_addr){
         bits,           scom_data,                       expr;
         rx_prbs_tap_id, rx_prbs_tap_id_pattern_f,        (def_rx_mirrored_mode);
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_f,        (def_rx_non_mirrored_mode);
+        rx_prbs_tap_id, rx_prbs_tap_id_pattern_d,        (def_rx_non_mirrored_mode);
 }
 scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_12).0x(cn_gcr_addr){
         bits,           scom_data,                       expr;
@@ -281,17 +282,17 @@ scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_12).0x(cn_gcr_addr){
 scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_13).0x(cn_gcr_addr){
         bits,           scom_data,                       expr;
         rx_prbs_tap_id, rx_prbs_tap_id_pattern_d,        (def_rx_mirrored_mode);
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_d,        (def_rx_non_mirrored_mode);
+        rx_prbs_tap_id, rx_prbs_tap_id_pattern_f,        (def_rx_non_mirrored_mode);
 }
 scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_14).0x(cn_gcr_addr){
         bits,           scom_data,                       expr;
         rx_prbs_tap_id, rx_prbs_tap_id_pattern_c,        (def_rx_mirrored_mode);
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_c,        (def_rx_non_mirrored_mode);
+        rx_prbs_tap_id, rx_prbs_tap_id_pattern_g,        (def_rx_non_mirrored_mode);
 }
 scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_15).0x(cn_gcr_addr){
         bits,           scom_data,                       expr;
         rx_prbs_tap_id, rx_prbs_tap_id_pattern_b,        (def_rx_mirrored_mode);
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_b,        (def_rx_non_mirrored_mode);
+        rx_prbs_tap_id, rx_prbs_tap_id_pattern_h,        (def_rx_non_mirrored_mode);
 }
 scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_16).0x(cn_gcr_addr){
         bits,           scom_data,                       expr;
@@ -299,7 +300,7 @@ scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_16).0x(cn_gcr_addr){
         rx_prbs_tap_id, rx_prbs_tap_id_pattern_a,        (def_rx_non_mirrored_mode);
 }
 #-------------------------------------------------------------------------------------
-# PER-LANE (TX)
+# PER-LANE (TX: 24 lanes)
 #-------------------------------------------------------------------------------------
 # GCR Lane = 0
 scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_0).0x(cn_gcr_addr){
@@ -377,73 +378,73 @@ scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_11).0x(cn_gcr_addr){
 scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_12).0x(cn_gcr_addr){
         bits,           scom_data,                       expr;
         tx_prbs_tap_id, tx_prbs_tap_id_pattern_d,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_d,        (def_tx_non_mirrored_mode);
+        tx_prbs_tap_id, tx_prbs_tap_id_pattern_e,        (def_tx_non_mirrored_mode);
 }
 # GCR Lane = 13
 scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_13).0x(cn_gcr_addr){
         bits,           scom_data,                       expr;
         tx_prbs_tap_id, tx_prbs_tap_id_pattern_c,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_c,        (def_tx_non_mirrored_mode);
+        tx_prbs_tap_id, tx_prbs_tap_id_pattern_f,        (def_tx_non_mirrored_mode);
 }
 # GCR Lane = 14
 scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_14).0x(cn_gcr_addr){
         bits,           scom_data,                       expr;
         tx_prbs_tap_id, tx_prbs_tap_id_pattern_b,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_b,        (def_tx_non_mirrored_mode);
+        tx_prbs_tap_id, tx_prbs_tap_id_pattern_g,        (def_tx_non_mirrored_mode);
 }
 # GCR Lane = 15
 scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_15).0x(cn_gcr_addr){
         bits,           scom_data,                       expr;
         tx_prbs_tap_id, tx_prbs_tap_id_pattern_a,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_a,        (def_tx_non_mirrored_mode);
+        tx_prbs_tap_id, tx_prbs_tap_id_pattern_h,        (def_tx_non_mirrored_mode);
 }
 # GCR Lane = 16
 scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_16).0x(cn_gcr_addr){
         bits,           scom_data,                       expr;
         tx_prbs_tap_id, tx_prbs_tap_id_pattern_h,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_h,        (def_tx_non_mirrored_mode);
+        tx_prbs_tap_id, tx_prbs_tap_id_pattern_a,        (def_tx_non_mirrored_mode);
 }
 # GCR Lane = 17
 scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_17).0x(cn_gcr_addr){
         bits,           scom_data,                       expr;
         tx_prbs_tap_id, tx_prbs_tap_id_pattern_g,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_g,        (def_tx_non_mirrored_mode);
+        tx_prbs_tap_id, tx_prbs_tap_id_pattern_b,        (def_tx_non_mirrored_mode);
 }
 # GCR Lane = 18
 scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_18).0x(cn_gcr_addr){
         bits,           scom_data,                       expr;
         tx_prbs_tap_id, tx_prbs_tap_id_pattern_f,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_f,        (def_tx_non_mirrored_mode);
+        tx_prbs_tap_id, tx_prbs_tap_id_pattern_c,        (def_tx_non_mirrored_mode);
 }
 # GCR Lane = 19
 scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_19).0x(cn_gcr_addr){
         bits,           scom_data,                       expr;
         tx_prbs_tap_id, tx_prbs_tap_id_pattern_e,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_e,        (def_tx_non_mirrored_mode);
+        tx_prbs_tap_id, tx_prbs_tap_id_pattern_d,        (def_tx_non_mirrored_mode);
 }
 # GCR Lane = 20
 scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_20).0x(cn_gcr_addr){
         bits,           scom_data,                       expr;
         tx_prbs_tap_id, tx_prbs_tap_id_pattern_d,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_d,        (def_tx_non_mirrored_mode);
+        tx_prbs_tap_id, tx_prbs_tap_id_pattern_e,        (def_tx_non_mirrored_mode);
 }
 # GCR Lane = 21
 scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_21).0x(cn_gcr_addr){
         bits,           scom_data,                       expr;
         tx_prbs_tap_id, tx_prbs_tap_id_pattern_c,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_c,        (def_tx_non_mirrored_mode);
+        tx_prbs_tap_id, tx_prbs_tap_id_pattern_f,        (def_tx_non_mirrored_mode);
 }
 # GCR Lane = 22
 scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_22).0x(cn_gcr_addr){
         bits,           scom_data,                       expr;
         tx_prbs_tap_id, tx_prbs_tap_id_pattern_b,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_b,        (def_tx_non_mirrored_mode);
+        tx_prbs_tap_id, tx_prbs_tap_id_pattern_g,        (def_tx_non_mirrored_mode);
 }
 # GCR Lane = 23
 scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_23).0x(cn_gcr_addr){
         bits,           scom_data,                       expr;
         tx_prbs_tap_id, tx_prbs_tap_id_pattern_a,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_a,        (def_tx_non_mirrored_mode);
+        tx_prbs_tap_id, tx_prbs_tap_id_pattern_h,        (def_tx_non_mirrored_mode);
 }
 
 
diff --git a/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile
index 92deef365..2fa3865f4 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile
@@ -1,8 +1,12 @@
-#-- $Id: p8.dmi.scom.initfile,v 1.7 2012/06/21 15:56:28 jmcgill Exp $
+#-- $Id: p8.dmi.scom.initfile,v 1.10 2012/10/02 15:58:53 ttnguyen Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--     2.0 |pmegan  |10/02/12|Removed rx_sls_extend_sel entry since its needed for slave chip only (Processor is always master on DMI)
+#--     1.9 |pmegan  |09/27/12|Set rx_sls_timeout_sel entry to 0b001 per defect HW220752
+#--                           |Set rx_sls_extend_sel entry to 0b100 per defect HW220806
+#--     1.8 |thomsen |07/13/12|Updated non-mirrored PRBS_TAP_ID's to have abcdefgabcdefgabc... pattern
 #--     1.7 |jmcgill |06/21/12|Update tx_clk_cntl_gcrmsg_pg to use def_tx_base_grp instead of def_rx_base_grp
 #--     1.6 |jmcgill |06/21/12|Updates to match dials
 #--     1.5 |thomsen |06/19/12|Changed name of rx_grp3 to be def_rx_base_grp in order to be more generic
@@ -243,7 +247,7 @@ scom 0x800.0b(rx_mode_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){
 # /_/   /_/ |_/_____/____/    /_/  \__,_/ .___/   /____/\___/_/\___/\___/\__/____/  banner2 -fslant
 #                                      /_/
 #-------------------------------------------------------------------------------------
-# PER-LANE (RX)
+# PER-LANE (RX: 24 lanes)
 #-------------------------------------------------------------------------------------
 #--*********************************************************************************************
 #-- rx_prbs_mode_pl: rx_prbs_tap_id
@@ -311,65 +315,65 @@ scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_11).0x(dmi0_gcr_addr){
 scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_12).0x(dmi0_gcr_addr){
         bits,                  scom_data,                 expr;
         rx_prbs_tap_id,        rx_prbs_tap_id_pattern_d,  (def_rx_mirrored_mode);    
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_d,  (def_rx_non_mirrored_mode);    
+        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_e,  (def_rx_non_mirrored_mode);    
 }
 scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_13).0x(dmi0_gcr_addr){
         bits,                  scom_data,                 expr;
         rx_prbs_tap_id,        rx_prbs_tap_id_pattern_c,  (def_rx_mirrored_mode);    
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_c,  (def_rx_non_mirrored_mode);    
+        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_f,  (def_rx_non_mirrored_mode);    
 }
 scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_14).0x(dmi0_gcr_addr){
         bits,                  scom_data,                 expr;
         rx_prbs_tap_id,        rx_prbs_tap_id_pattern_b,  (def_rx_mirrored_mode);    
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_b,  (def_rx_non_mirrored_mode);    
+        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_g,  (def_rx_non_mirrored_mode);    
 }
 scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_15).0x(dmi0_gcr_addr){
         bits,                  scom_data,                 expr;
         rx_prbs_tap_id,        rx_prbs_tap_id_pattern_a,  (def_rx_mirrored_mode);    
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_a,  (def_rx_non_mirrored_mode);    
+        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_h,  (def_rx_non_mirrored_mode);    
 }
 scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_16).0x(dmi0_gcr_addr){
         bits,                  scom_data,                 expr;
         rx_prbs_tap_id,        rx_prbs_tap_id_pattern_h,  (def_rx_mirrored_mode);    
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_h,  (def_rx_non_mirrored_mode);    
+        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_a,  (def_rx_non_mirrored_mode);    
 }
 scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_17).0x(dmi0_gcr_addr){
         bits,                  scom_data,                 expr;
         rx_prbs_tap_id,        rx_prbs_tap_id_pattern_g,  (def_rx_mirrored_mode);    
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_g,  (def_rx_non_mirrored_mode);    
+        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_b,  (def_rx_non_mirrored_mode);    
 }
 scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_18).0x(dmi0_gcr_addr){
         bits,                  scom_data,                 expr;
         rx_prbs_tap_id,        rx_prbs_tap_id_pattern_f,  (def_rx_mirrored_mode);    
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_f,  (def_rx_non_mirrored_mode);    
+        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_c,  (def_rx_non_mirrored_mode);    
 }
 scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_19).0x(dmi0_gcr_addr){
         bits,                  scom_data,                 expr;
         rx_prbs_tap_id,        rx_prbs_tap_id_pattern_e,  (def_rx_mirrored_mode);    
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_e,  (def_rx_non_mirrored_mode);    
+        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_d,  (def_rx_non_mirrored_mode);    
 }
 scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_20).0x(dmi0_gcr_addr){
         bits,                  scom_data,                 expr;
         rx_prbs_tap_id,        rx_prbs_tap_id_pattern_d,  (def_rx_mirrored_mode);    
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_d,  (def_rx_non_mirrored_mode);    
+        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_e,  (def_rx_non_mirrored_mode);    
 }
 scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_21).0x(dmi0_gcr_addr){
         bits,                  scom_data,                 expr;
         rx_prbs_tap_id,        rx_prbs_tap_id_pattern_c,  (def_rx_mirrored_mode);    
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_c,  (def_rx_non_mirrored_mode);    
+        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_f,  (def_rx_non_mirrored_mode);    
 }
 scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_22).0x(dmi0_gcr_addr){
         bits,                  scom_data,                 expr;
         rx_prbs_tap_id,        rx_prbs_tap_id_pattern_b,  (def_rx_mirrored_mode);    
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_b,  (def_rx_non_mirrored_mode);    
+        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_g,  (def_rx_non_mirrored_mode);    
 }
 scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_23).0x(dmi0_gcr_addr){
         bits,                  scom_data,                 expr;
         rx_prbs_tap_id,        rx_prbs_tap_id_pattern_a,  (def_rx_mirrored_mode);    
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_a,  (def_rx_non_mirrored_mode);    
+        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_h,  (def_rx_non_mirrored_mode);    
 }
 #-------------------------------------------------------------------------------------
-# PER-LANE (TX)
+# PER-LANE (TX: 17 lanes)
 #-------------------------------------------------------------------------------------
 #--*********************************************************************************************
 #-- tx_prbs_mode_pl: tx_prbs_tap_id
@@ -422,17 +426,17 @@ scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_8).0x(dmi0_gcr_addr){
 scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_9).0x(dmi0_gcr_addr){
         bits,                  scom_data,                 expr;
         tx_prbs_tap_id,        tx_prbs_tap_id_pattern_h,  (def_tx_mirrored_mode);    
-        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_h,  (def_tx_non_mirrored_mode);
+        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_b,  (def_tx_non_mirrored_mode);
 }
 scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_10).0x(dmi0_gcr_addr){
         bits,                  scom_data,                 expr;
         tx_prbs_tap_id,        tx_prbs_tap_id_pattern_g,  (def_tx_mirrored_mode);    
-        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_g,  (def_tx_non_mirrored_mode);
+        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_c,  (def_tx_non_mirrored_mode);
 }
 scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_11).0x(dmi0_gcr_addr){
         bits,                  scom_data,                 expr;
         tx_prbs_tap_id,        tx_prbs_tap_id_pattern_f,  (def_tx_mirrored_mode);    
-        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_f,  (def_tx_non_mirrored_mode);
+        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_d,  (def_tx_non_mirrored_mode);
 }
 scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_12).0x(dmi0_gcr_addr){
         bits,                  scom_data,                 expr;
@@ -442,17 +446,17 @@ scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_12).0x(dmi0_gcr_addr){
 scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_13).0x(dmi0_gcr_addr){
         bits,                  scom_data,                 expr;
         tx_prbs_tap_id,        tx_prbs_tap_id_pattern_d,  (def_tx_mirrored_mode);    
-        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_d,  (def_tx_non_mirrored_mode);
+        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_f,  (def_tx_non_mirrored_mode);
 }
 scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_14).0x(dmi0_gcr_addr){
         bits,                  scom_data,                 expr;
         tx_prbs_tap_id,        tx_prbs_tap_id_pattern_c,  (def_tx_mirrored_mode);    
-        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_c,  (def_tx_non_mirrored_mode);
+        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_g,  (def_tx_non_mirrored_mode);
 }
 scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_15).0x(dmi0_gcr_addr){
         bits,                  scom_data,                 expr;
         tx_prbs_tap_id,        tx_prbs_tap_id_pattern_b,  (def_tx_mirrored_mode);    
-        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_b,  (def_tx_non_mirrored_mode);
+        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_h,  (def_tx_non_mirrored_mode);
 }
 scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_16).0x(dmi0_gcr_addr){
         bits,                  scom_data,                 expr;
@@ -488,6 +492,35 @@ scom 0x800.0b(tx_clk_cntl_gcrmsg_pg)(def_tx_base_grp)(lane_na).0x(dmi0_gcr_addr)
         bits,                         scom_data;
         tx_drv_clk_pattern_gcrmsg,    0b00;    # Drive 0's to start out
 }
+#-------------------------------------------------------------------------------------
+#    ____ _  __    _______                        _____      __
+#   / __ \ |/ /   /_  __(_)___ ___  ___  _____   / ___/___  / /
+#  / /_/ /   /     / / / / __ `__ \/ _ \/ ___/   \__ \/ _ \/ / 
+# / _, _/   |     / / / / / / / / /  __/ /      ___/ /  __/ /  
+#/_/ |_/_/|_|    /_/ /_/_/ /_/ /_/\___/_/      /____/\___/_/   
+#-------------------------------------------------------------------------------------
+#--*********************************************************************************************
+#-- rx_timeout_sel_pg: rx_sls_timeout_sel        
+#--*********************************************************************************************
+scom 0x800.0b(rx_timeout_sel_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){
+        bits,                   scom_data;
+        rx_sls_timeout_sel,     0b001;    # Set this entry to 0b001 per defect HW220752
+}
+                                                              
+#-------------------------------------------------------------------------------------
+#    ____ _  __    _____ __   _____    ______     __                 __   _____      __
+#   / __ \ |/ /   / ___// /  / ___/   / ____/  __/ /____  ____  ____/ /  / ___/___  / /
+#  / /_/ /   /    \__ \/ /   \__ \   / __/ | |/_/ __/ _ \/ __ \/ __  /   \__ \/ _ \/ / 
+# / _, _/   |    ___/ / /______/ /  / /____>  </ /_/  __/ / / / /_/ /   ___/ /  __/ /  
+#/_/ |_/_/|_|   /____/_____/____/  /_____/_/|_|\__/\___/_/ /_/\__,_/   /____/\___/_/   
+#-------------------------------------------------------------------------------------
+#--*********************************************************************************************
+#-- rx_spare_mode_pg: rx_sls_extend_sel                      
+#--*********************************************************************************************
+#scom 0x800.0b(rx_spare_mode_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){
+#        bits,                   scom_data;
+#        rx_sls_extend_sel,     0b100;    # Set this entry to 0b100 per defect HW220806
+#}
 
 ############################################################################################
 # END OF FILE
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_scomoverride_chiplets/proc_scomoverride_chiplets.C b/src/usr/hwpf/hwp/nest_chiplets/proc_scomoverride_chiplets/proc_scomoverride_chiplets.C
index df397f9f7..9806d720b 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_scomoverride_chiplets/proc_scomoverride_chiplets.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_scomoverride_chiplets/proc_scomoverride_chiplets.C
@@ -1,27 +1,26 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/nest_chiplets/proc_scomoverride_chiplets/proc_scomoverride_chiplets.C $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
-// $Id: proc_scomoverride_chiplets.C,v 1.1 2012/03/13 06:02:36 venton Exp $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_scomoverride_chiplets/proc_scomoverride_chiplets.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_scomoverride_chiplets.C,v 1.2 2012/10/07 18:25:47 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_scomoverride_chiplets.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -30,10 +29,10 @@
 // *! *** IBM Confidential ***
 // *|
 // *! TITLE       : proc_scomoverride_chiplets.C
-// *! DESCRIPTION : 
+// *! DESCRIPTION :
 // *!
 // *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
-// *! OWNER NAME  : Jeshua Smith  i         Email: jeshua@us.ibm.com
+// *! OWNER NAME  : Jeshua Smith            Email: jeshua@us.ibm.com
 // *!
 //------------------------------------------------------------------------------
 
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets_errors.xml b/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets_errors.xml
index 07b028902..2fd2d6925 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets_errors.xml
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets_errors.xml
@@ -1,25 +1,25 @@
-<!--  IBM_PROLOG_BEGIN_TAG
-     This is an automatically generated prolog.
-   
-     $Source: src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets_errors.xml $
-   
-     IBM CONFIDENTIAL
-   
-     COPYRIGHT International Business Machines Corp. 2012
-   
-     p1
-   
-     Object Code Only (OCO) source materials
-     Licensed Internal Code Source Materials
-     IBM HostBoot Licensed Internal Code
-   
-     The source code for this program is not published or other-
-     wise divested of its trade secrets, irrespective of what has
-     been deposited with the U.S. Copyright Office.
-   
-     Origin: 30
-   
-     IBM_PROLOG_END_TAG -->
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets_errors.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2012                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
 <!-- Error definitions for proc_start_clocks_chiplets procedure -->
 <hwpErrors>
   <!-- *********************************************************************** -->
@@ -36,4 +36,10 @@
     <ffdc>FIR_REG</ffdc>
     <ffdc>CHIPLET_BASE_SCOM_ADDR</ffdc>
   </hwpError>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_START_CLOCKS_CHIPLETS_PARTIAL_GOOD_ERR</rc>
+    <description>Unexpected chiplet selection when reading the partial good vector.</description>
+    <ffdc>CHIPLET_BASE_SCOM_ADDR</ffdc>
+  </hwpError>
 </hwpErrors>
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_check_slave_sbe_seeprom_complete.C b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_check_slave_sbe_seeprom_complete.C
index 611f5f1f6..af5863924 100644
--- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_check_slave_sbe_seeprom_complete.C
+++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_check_slave_sbe_seeprom_complete.C
@@ -21,7 +21,7 @@
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
 // -*- mode: C++; c-file-style: "linux";  -*-
-// $Id: proc_check_slave_sbe_seeprom_complete.C,v 1.4 2012/10/29 22:05:38 jeshua Exp $
+// $Id: proc_check_slave_sbe_seeprom_complete.C,v 1.5 2012/11/13 21:00:34 jeshua Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_check_slave_sbe_seeprom_complete.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -302,7 +302,7 @@ extern "C"
                     istep_num,
                     substep_num);
                 //Get the error code from the SBE code
-                FAPI_PLAT_EXEC_HWP(rc, proc_extract_sbe_rc, i_target);
+                FAPI_EXEC_HWP(rc, proc_extract_sbe_rc, i_target);
                 break;
             }
             //Halt code was success