Add support for EI_BUS_TX_LANE_INVERT attribute

Change-Id: I1b48acb122a99e172aa00340c875ec9fbad8dd12
RTC:59275
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2667
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

1 files changed, 45 insertions, 0 deletions

diff --git a/src/usr/hwpf/hwp/common_attributes.xml b/src/usr/hwpf/hwp/common_attributes.xml
index b7954e201..d975f730e 100644
--- a/src/usr/hwpf/hwp/common_attributes.xml
+++ b/src/usr/hwpf/hwp/common_attributes.xml
@@ -75,4 +75,49 @@
     <valueType>uint32</valueType>
     <platInit/>
   </attribute>
+  <attribute>
+    <id>ATTR_EI_BUS_TX_LANE_INVERT</id>
+    <targetType>
+        TARGET_TYPE_MCS_CHIPLET,TARGET_TYPE_MEMBUF_CHIP,TARGET_TYPE_ABUS_ENDPOINT
+    </targetType>
+    <description>
+      Source: MRW: Downstream N/P Lane Swap Mask and Upstream N/P Lane Swap Mask
+         Usage:  TX_LANE_INVERT initfile setting for DMI and A buses
+            This attribute represents the polarity of a differential wire pair 
+            on the DMI and A buses. Normally differential pair wires are connected 
+            between the two positive phases of the pair and the two negative phases 
+            between two chips. In the DMI and Abus designs it's allowable for the 
+            board designer to wire the positive phase of a lane from one chip to 
+            the negative phase of the other chip on that same lane and vice versa 
+            in order to simplify wiring on the board and reduce the number of 
+            board layers.  This attribute is set up as a 32 bit uint value 
+            interpreted as a 32 bit binary vector where the left-most bit position 
+            (msb/bit0) corresponds to the polarity of lane 0 and the right-most bit 
+            position (lsb/bit31) corresponds to lane 31.  A binary 1 in any 
+            position in the attribute means that the board designer has done a 
+            polarity swap within the differential pair and the initfile must set 
+            the tx_lane_invert bit in the driving chip for that wire pair (called a lane).
+            The Downstream N/P Lane Swap Mask from the MRW represents the polarity 
+            of the bus wiring as it goes from the master chip to the slave chip 
+            (master chip is defined as the chip with a lower value of 
+            (node*100 + chip position) and Upstream N/P Lane Swap Mask represents 
+            the polarity of the bus wiring as it goes from the slave chip back to 
+            the master chip.
+            Examples:
+                  - Port A2 on Chip Target n0p0 connects to Port A2 on chip target 
+                    n0p2. This connection has a Downstream N/P Lane Swap Mask and
+                    an Upstream N/P Lane Swap Mask. Setting the Downstream N/P 
+                    Lane Swap Mask to a value of 0x80000000 means lane 0 is polarity
+                    swapped and the initfile should set lane 0's tx_lane_invert bit 
+                    on the n0p0 targeted chip (the so-called master chip). 
+                    If the Upstream N/P Lane Swap Mask is 0x20000000 this means lane
+                     2 is polarity swapped and the initfile should set lane 2's
+                    tx_lane_invert bit on the n0p2 targeted chip (the so-called slave chip).
+            It is up to the platform code to set up each ATTR_EI_BUS_TX_LANE_INVERT 
+            value for the correct target endpoints, ie. 0x80000000 for n0p0 and 
+            0x20000000 for n0p2.
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+  </attribute>
 </attributes>