diff options
| -rw-r--r-- | src/usr/hwpf/hwp/common_attributes.xml | 45 | ||||
| -rw-r--r-- | src/usr/targeting/common/xmltohb/attribute_types.xml | 20 | ||||
| -rw-r--r-- | src/usr/targeting/common/xmltohb/common.mk | 3 | ||||
| -rw-r--r-- | src/usr/targeting/common/xmltohb/target_types.xml | 3 | ||||
| -rwxr-xr-x | src/usr/targeting/xmltohb/genHwsvMrwXml.pl | 114 |
5 files changed, 178 insertions, 7 deletions
diff --git a/src/usr/hwpf/hwp/common_attributes.xml b/src/usr/hwpf/hwp/common_attributes.xml index b7954e201..d975f730e 100644 --- a/src/usr/hwpf/hwp/common_attributes.xml +++ b/src/usr/hwpf/hwp/common_attributes.xml @@ -75,4 +75,49 @@ <valueType>uint32</valueType> <platInit/> </attribute> + <attribute> + <id>ATTR_EI_BUS_TX_LANE_INVERT</id> + <targetType> + TARGET_TYPE_MCS_CHIPLET,TARGET_TYPE_MEMBUF_CHIP,TARGET_TYPE_ABUS_ENDPOINT + </targetType> + <description> + Source: MRW: Downstream N/P Lane Swap Mask and Upstream N/P Lane Swap Mask + Usage: TX_LANE_INVERT initfile setting for DMI and A buses + This attribute represents the polarity of a differential wire pair + on the DMI and A buses. Normally differential pair wires are connected + between the two positive phases of the pair and the two negative phases + between two chips. In the DMI and Abus designs it's allowable for the + board designer to wire the positive phase of a lane from one chip to + the negative phase of the other chip on that same lane and vice versa + in order to simplify wiring on the board and reduce the number of + board layers. This attribute is set up as a 32 bit uint value + interpreted as a 32 bit binary vector where the left-most bit position + (msb/bit0) corresponds to the polarity of lane 0 and the right-most bit + position (lsb/bit31) corresponds to lane 31. A binary 1 in any + position in the attribute means that the board designer has done a + polarity swap within the differential pair and the initfile must set + the tx_lane_invert bit in the driving chip for that wire pair (called a lane). + The Downstream N/P Lane Swap Mask from the MRW represents the polarity + of the bus wiring as it goes from the master chip to the slave chip + (master chip is defined as the chip with a lower value of + (node*100 + chip position) and Upstream N/P Lane Swap Mask represents + the polarity of the bus wiring as it goes from the slave chip back to + the master chip. + Examples: + - Port A2 on Chip Target n0p0 connects to Port A2 on chip target + n0p2. This connection has a Downstream N/P Lane Swap Mask and + an Upstream N/P Lane Swap Mask. Setting the Downstream N/P + Lane Swap Mask to a value of 0x80000000 means lane 0 is polarity + swapped and the initfile should set lane 0's tx_lane_invert bit + on the n0p0 targeted chip (the so-called master chip). + If the Upstream N/P Lane Swap Mask is 0x20000000 this means lane + 2 is polarity swapped and the initfile should set lane 2's + tx_lane_invert bit on the n0p2 targeted chip (the so-called slave chip). + It is up to the platform code to set up each ATTR_EI_BUS_TX_LANE_INVERT + value for the correct target endpoints, ie. 0x80000000 for n0p0 and + 0x20000000 for n0p2. + </description> + <valueType>uint32</valueType> + <platInit/> + </attribute> </attributes> diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index 626adf617..2ab2a7131 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -9271,4 +9271,24 @@ Measured in GB</description> <!-- ===== End Attributes supporting memory_attributes.xml HWPF Attributes ===== --> +<attribute> + <id>EI_BUS_TX_LANE_INVERT</id> + <description> + This attribute represents the polarity of a differential wire pair on the DMI and A buses. + creator: platform (generated based on MRW data) + See defintion in common_attributes.xml for more information. + </description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_EI_BUS_TX_LANE_INVERT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + </attributes> diff --git a/src/usr/targeting/common/xmltohb/common.mk b/src/usr/targeting/common/xmltohb/common.mk index 22b9e1c6c..c729804cf 100644 --- a/src/usr/targeting/common/xmltohb/common.mk +++ b/src/usr/targeting/common/xmltohb/common.mk @@ -73,7 +73,8 @@ FAPI_ATTR_SOURCES = \ runtime_attributes/pm_attributes_all_hwp.xml \ runtime_attributes/pm_attributes_all_plat.xml \ nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml \ - dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr_attributes.xml + dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr_attributes.xml \ + common_attributes.xml XMLTOHB_GENERIC_XML = generic.xml diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index 59bbe49ff..a3754bc49 100644 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -571,6 +571,7 @@ <attribute><id>EI_BUS_RX_MSB_LSB_SWAP</id></attribute> <attribute><id>EI_BUS_TX_MSB_LSB_SWAP</id></attribute> <attribute><id>PEER_TARGET</id></attribute> + <attribute><id>EI_BUS_TX_LANE_INVERT</id></attribute> </targetType> <targetType> @@ -834,6 +835,7 @@ <attribute><id>EI_BUS_RX_MSB_LSB_SWAP</id></attribute> <attribute><id>EI_BUS_TX_MSB_LSB_SWAP</id></attribute> <attribute><id>IBSCOM_MCS_BASE_ADDR</id></attribute> + <attribute><id>EI_BUS_TX_LANE_INVERT</id></attribute> </targetType> <targetType> @@ -945,6 +947,7 @@ </attribute> <attribute><id>MSS_CACHE_ENABLE</id></attribute> <attribute><id>VMEM_ID</id></attribute> + <attribute><id>EI_BUS_TX_LANE_INVERT</id></attribute> </targetType> <!-- Centaur MBS --> diff --git a/src/usr/targeting/xmltohb/genHwsvMrwXml.pl b/src/usr/targeting/xmltohb/genHwsvMrwXml.pl index 4c92b7437..f5a2c3683 100755 --- a/src/usr/targeting/xmltohb/genHwsvMrwXml.pl +++ b/src/usr/targeting/xmltohb/genHwsvMrwXml.pl @@ -111,16 +111,63 @@ close (FH); my $powerbus = XMLin("$mrwdir/${sysname}-power-busses.xml"); my @pbus; +use constant PBUS_FIRST_END_POINT_INDEX => 0; +use constant PBUS_SECOND_END_POINT_INDEX => 1; +use constant PBUS_DOWNSTREAM_INDEX => 2; +use constant PBUS_UPSTREAM_INDEX => 3; foreach my $i (@{$powerbus->{'power-bus'}}) { + # Pull out the connection information from the description + # example: n0:p0:A2 to n0:p2:A2 my $endp1 = $i->{'description'}; my $endp2 = $endp1; $endp1 =~ s/^(.*) to.*/$1/; $endp2 =~ s/.* to (.*)\s*$/$1/; - push @pbus, [ lc($endp1), lc($endp2) ]; - push @pbus, [ lc($endp2), lc($endp1) ]; + # Grab the lane swap information + my $dwnstrm_swap = $i->{'downstream-n-p-lane-swap-mask'}; + my $upstrm_swap = $i->{'upstream-n-p-lane-swap-mask'}; + #print STDOUT "powerbus: $endp1, $endp2, $dwnstrm_swap, $upstrm_swap\n"; + push @pbus, [ lc($endp1), lc($endp2), $dwnstrm_swap, $upstrm_swap ]; + push @pbus, [ lc($endp2), lc($endp1), $dwnstrm_swap, $upstrm_swap ]; } +open (FH, "<$mrwdir/${sysname}-dmi-busses.xml") || + die "ERROR: unable to open $mrwdir/${sysname}-dmi-busses.xml\n"; +close (FH); + +my $dmibus = XMLin("$mrwdir/${sysname}-dmi-busses.xml"); + +my @dbus_mcs; +use constant DBUS_MCS_NODE_INDEX => 0; +use constant DBUS_MCS_PROC_INDEX => 1; +use constant DBUS_MCS_UNIT_INDEX => 2; +use constant DBUS_MCS_DOWNSTREAM_INDEX => 3; + +my @dbus_centaur; +use constant DBUS_CENTAUR_NODE_INDEX => 0; +use constant DBUS_CENTAUR_MEMBUF_INDEX => 1; +use constant DBUS_CENTAUR_UPSTREAM_INDEX => 2; +foreach my $dmi (@{$dmibus->{'dmi-bus'}}) +{ + # First grab the MCS information + # MCS is always master so it gets downstream + my $node = $dmi->{'mcs'}->{'target'}->{'node'}; + my $proc = $dmi->{'mcs'}->{'target'}->{'position'}; + my $mcs = $dmi->{'mcs'}->{'target'}->{'chipUnit'}; + my $swap = $dmi->{'downstream-n-p-lane-swap-mask'}; + #print STDOUT "dbus_mcs: n$node:p$proc:mcs:$mcs swap:$swap\n"; + push @dbus_mcs, [ $node, $proc, $mcs, $swap ]; + + # Now grab the centuar chip information + # Centaur is always slave so it gets upstream + my $node = $dmi->{'centaur'}->{'target'}->{'node'}; + my $membuf = $dmi->{'centaur'}->{'target'}->{'position'}; + my $swap = $dmi->{'upstream-n-p-lane-swap-mask'}; + #print STDOUT "dbus_centaur: n$node:cen$membuf swap:$swap\n"; + push @dbus_centaur, [ $node, $membuf, $swap ]; +} + + open (FH, "<$mrwdir/${sysname}-cent-vrds.xml") || die "ERROR: unable to open $mrwdir/${sysname}-cent-vrds.xml\n"; close (FH); @@ -2069,6 +2116,18 @@ sub generate_mcs my $mcsOffset = $nodeOffset + $procOffset + $mcs*2; my $mscStr = sprintf("0x0003E%02X00000000", $mcsOffset); + my $lane_swap = 0; + foreach my $dmi ( @dbus_mcs ) + { + if (($dmi->[DBUS_MCS_NODE_INDEX], + $dmi->[DBUS_MCS_PROC_INDEX], + $dmi->[DBUS_MCS_UNIT_INDEX]) eq (${node},$proc,$mcs)) + { + $lane_swap = $dmi->[DBUS_MCS_DOWNSTREAM_INDEX]; + last; + } + } + print " <targetInstance> <id>sys${sys}node${node}proc${proc}mcs$mcs</id> @@ -2100,7 +2159,11 @@ sub generate_mcs <id>EI_BUS_TX_MSB_LSB_SWAP</id> <default>X</default> </attribute> - -->"; + --> + <attribute> + <id>EI_BUS_TX_LANE_INVERT</id> + <default>$lane_swap</default> + </attribute>"; if($build eq "fsp") { @@ -2185,15 +2248,31 @@ sub generate_ax_buses my $peer = 0; my $p_proc = 0; my $p_port = 0; - foreach my $j ( @pbus ) + my $lane_swap = 0; + foreach my $pbus ( @pbus ) { - if ($j->[0] eq "n${node}:p${proc}:${type}${i}") + if ($pbus->[PBUS_FIRST_END_POINT_INDEX] eq "n${node}:p${proc}:${type}${i}") { $peer = 1; - $p_proc = $j->[1]; + $p_proc = $pbus->[PBUS_SECOND_END_POINT_INDEX]; $p_port = $p_proc; + my $p_node = $pbus->[PBUS_SECOND_END_POINT_INDEX]; + $p_node =~ s/^n(.*):p.*:.*$/$1/; $p_proc =~ s/^.*:p(.*):.*$/$1/; $p_port =~ s/.*:p.*:.(.*)$/$1/; + # Calculation from Pete Thomsen for 'master' chip + if(((${node}*100) + $proc) < (($p_node*100) + $p_proc)) + { + # This chip is lower so it's master so it gets + # the downstream data. + $lane_swap = $pbus->[PBUS_DOWNSTREAM_INDEX]; + } + else + { + # This chip is higher so it's the slave chip + # and gets the upstream + $lane_swap = $pbus->[PBUS_UPSTREAM_INDEX]; + } last; } } @@ -2232,6 +2311,14 @@ sub generate_ax_buses <default>$ordinalId</default> </attribute>"; } + if($type eq "a") + { + print " + <attribute> + <id>EI_BUS_TX_LANE_INVERT</id> + <default>$lane_swap</default> + </attribute>"; + } print "\n</targetInstance>\n"; } @@ -2251,6 +2338,17 @@ sub generate_centaur my $uidstr = sprintf("0x%02X04%04X",${node},$mcs+$proc*8+${node}*8*8); + my $lane_swap = 0; + foreach my $dmi ( @dbus_centaur ) + { + if (($dmi->[DBUS_CENTAUR_NODE_INDEX], + $dmi->[DBUS_CENTAUR_MEMBUF_INDEX]) eq (${node},$ctaur)) + { + $lane_swap = $dmi->[DBUS_CENTAUR_UPSTREAM_INDEX]; + last; + } + } + print " <!-- $SYSNAME Centaur n${node}p${ctaur} : start --> @@ -2304,6 +2402,10 @@ sub generate_centaur <attribute> <id>FSI_OPTION_FLAGS</id> <default>0</default> + </attribute> + <attribute> + <id>EI_BUS_TX_LANE_INVERT</id> + <default>$lane_swap</default> </attribute>"; if ($build eq "fsp") |
