INITPROC: Hostboot SW252649 proc_extract_sbe_rc updates

Change-Id: I02068439c473c78eb7b0b7f04bd2ef703d8ae695
CQ:SW252649
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9812
Tested-by: Jenkins Server
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

3 files changed, 1121 insertions, 373 deletions

diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C
index 89dfd8d8f..86b8ffb0f 100644
--- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C
+++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C
@@ -21,7 +21,7 @@
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
 // -*- mode: C++; c-file-style: "linux";  -*-
-// $Id: proc_extract_sbe_rc.C,v 1.12 2014/02/19 02:31:45 jmcgill Exp $
+// $Id: proc_extract_sbe_rc.C,v 1.16 2014/03/18 14:09:27 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_sbe_rc.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -30,20 +30,19 @@
 // *! *** IBM Confidential ***
 // *|
 // *! TITLE       : proc_extract_sbe_rc.C
-// *! DESCRIPTION : Create a return code for an SBE error
+// *! DESCRIPTION : Create a return code for an SBE/SLW error
 // *!
 // *! OWNER NAME  : Johannes Koesters       Email: koesters@de.ibm.com
 // *!
 // *! Overview:
-// *!    - Check that it was a halt at magic instruction
-// *!    - Get the failing PC
-// *!    - If secure, look up PC in image pointer
-// *!    - If not secure, look the PC up in the SBE (SEEPROM/PIBMEM/OTPROM)
-// *!    - Extract the error code at that PC
-// *!    - Return the RC for that error
-// *!    
-// *! Assumption: The SBE is stopped at a "invalid instruction" error
-// *!             and the instruction was 'halt'
+// *!   - Analyze error state of SBE/SLW engine
+// *!     - Examine SBE/SLW engine state to determine if a HW error occurred.
+// *!       Return RC for HW error if present
+// *!     - For 'halt' due to SBE/SLW code generated failure:
+// *!         - Determine PC at point for failure
+// *!         - Lookup PC in appropriate code space (SEEPROM/PIBMEM/OTPROM),
+// *!           extract & return RC for its associated error
+// *!
 //------------------------------------------------------------------------------
 
 
@@ -56,25 +55,41 @@
 
 
 //------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+enum soft_error_t
+{
+    eNO_ERROR = 0,
+    eSOFT_ERR_I2CM=1, 
+    eSOFT_ERR_PNOR=2,
+    eSOFT_ERR_BOTH=3
+};
+
+//------------------------------------------------------------------------------
 // Constant definitions
 //------------------------------------------------------------------------------
-//Address masks
-const uint64_t SBE_ADDR_MASK               = 0x0000FFFFFFFFFFFFull;
-const uint64_t FOURBYTE_ALIGNMENT_MASK     = 0x0000000000000003ull;
-const uint64_t INTERNAL_ADDR_MASK          = 0x000000007FFFFFFFull;
-const uint64_t ADDR_TYPE_MASK              = 0x0000FFFF80000000ull;
-const uint64_t OTPROM_ADDR_TYPE            = 0x0000000100000000ull;
-const uint64_t PIBMEM_ADDR_TYPE            = 0x0000000800000000ull;
-const uint64_t SEEPROM_ADDR_TYPE           = 0x0000800C80000000ull;
+
+// address space/alignment masks
+const uint64_t SBE_ADDR_MASK               = 0x0000FFFFFFFFFFFFULL;
+const uint64_t FOURBYTE_ALIGNMENT_MASK     = 0x0000000000000003ULL;
+const uint64_t INTERNAL_ADDR_MASK          = 0x000000007FFFFFFFULL;
+const uint64_t ADDR_TYPE_MASK              = 0x0000FFFF80000000ULL;
+const uint64_t OTPROM_ADDR_TYPE            = 0x0000000100000000ULL;
+const uint64_t PIBMEM_ADDR_TYPE            = 0x0000000800000000ULL;
+const uint64_t SEEPROM_ADDR_TYPE           = 0x0000800C80000000ULL;
 const uint32_t ALIGN_FOUR_BYTE             = 0xFFFFFFFC;
-//Scom register offsets
+
+// common SCOM register offsets for SBE/SLW engines
 const uint32_t STATUS_OFFSET_0x00          = 0x00000000;
 const uint32_t IBUF_OFFSET_0x0D            = 0x0000000D;
 const uint32_t DEBUG0_OFFSET_0x0F          = 0x0000000F;
 const uint32_t DEBUG1_OFFSET_0x10          = 0x00000010;
-//Halt types
+
+// illegal instruction encoding for SW detected halt
 const uint32_t HALT_WITH_ERROR_INSTRUCTION = (('h' << 24) | ('a' << 16) | ('l' << 8) | ('t'));
 
+
 //------------------------------------------------------------------------------
 // Function definitions
 //------------------------------------------------------------------------------
@@ -84,485 +99,730 @@ extern "C"
 
 //------------------------------------------------------------------------------
 // subroutine:
-//      Reads the word at the given address in SEEPROM pointer
+//      reads the word at the given address in SEEPROM pointer
 //
-// parameters: i_target   => Target of chip with failed SBE
+// parameters: i_target   => target of chip with failed SBE/SLW engine
 //             i_pSEEPROM => pointer to a memory-mapped SEEPROM image
-//             i_address  => The SEEPROM address to read
-//             o_data     => A uint32_t to put the data into 
+//             i_address  => SEEPROM address to read
+//             i_engine   => type of engine that failed (SBE/SLW)
+//             i_soft_err => engine soft error status, for FFDC
+//             o_data     => return data
 //
 // returns: fapi::ReturnCode with the error, or fapi::FAPI_RC_SUCCESS
 //------------------------------------------------------------------------------
-    fapi::ReturnCode proc_extract_sbe_rc_read_SEEPROM(const fapi::Target & i_target,
-                                                      const void         * i_pSEEPROM,
-                                                      const uint32_t       i_address,
-                                                      uint32_t           & o_data)
-    {
-        // return codes
-        fapi::ReturnCode rc;
+fapi::ReturnCode proc_extract_sbe_rc_read_SEEPROM(const fapi::Target & i_target,
+                                                  const void         * i_pSEEPROM,
+                                                  const uint32_t       i_address,
+                                                  const por_engine_t   i_engine,
+                                                  const soft_error_t   i_soft_err,
+                                                  uint32_t           & o_data)
+{
+    // return codes
+    fapi::ReturnCode rc;
 
-        do
+    do
+    {
+        if (i_pSEEPROM == NULL)
         {
-            if (i_pSEEPROM==NULL)
+            FAPI_ERR("Need to extract SEEPROM address 0x%08X, but pointer to SEEPROM image content is NULL", i_address);
+            const fapi::Target & CHIP_IN_ERROR = i_target;
+            const uint32_t & PC = i_address;
+            if (i_engine == SBE)
             {
-                FAPI_ERR("Need to extract SEEPROM address 0x%08X but pointer to SEEPROM is NULL", i_address);
-                const fapi::Target & CHIP_IN_ERROR = i_target;
-                const uint32_t & ADDRESS = i_address;
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL);
-                break;
+                const soft_error_t & SOFT_ERR_STATUS = i_soft_err;
+                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL_SBE);
+            }
+            else
+            {
+                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL_SLW);
             }
-            uint8_t * p_errorCode = (uint8_t *)i_pSEEPROM + (i_address & ALIGN_FOUR_BYTE);
+            break;
+        }
+
+        // copy the data out of the image pointer
+        uint8_t * p_errorCode = (uint8_t *)i_pSEEPROM + (i_address & ALIGN_FOUR_BYTE);
+        o_data =
+            (p_errorCode[0] << 3*8) |
+            (p_errorCode[1] << 2*8) |
+            (p_errorCode[2] << 1*8) |
+            (p_errorCode[3]);
+    } while(0);
+
+    return rc;
+}
 
-            //Copy the data out of the image pointer
-            o_data =
-                (p_errorCode[0] << 3*8) |
-                (p_errorCode[1] << 2*8) |
-                (p_errorCode[2] << 1*8) |
-                (p_errorCode[3]);
-        } while(0);
-        return rc;
-    }
 
 //------------------------------------------------------------------------------
 // subroutine:
 //      Returns the PC of the given engine
 //
-// parameters: i_target   => Target of chip with failed SBE
-//             i_engine   => The type of engine that failed (SBE/SLW)
-//             o_pc       => Referenece to the uint64_t containing the PC
+// parameters: i_target   => target of chip with failed SBE/SLW engine
+//             i_engine   => type of engine that failed (SBE/SLW)
+//             i_soft_err => engine soft error status, for FFDC
+//             o_pc       => referenee to the uint64_t containing the PC
 //
 // returns: fapi::ReturnCode with the error, or fapi::FAPI_RC_SUCCESS
 //------------------------------------------------------------------------------
-    fapi::ReturnCode proc_extract_sbe_rc_get_pc(const fapi::Target & i_target,
-                                                por_engine_t         i_engine,
-                                                uint64_t           & o_pc)
+fapi::ReturnCode proc_extract_sbe_rc_get_pc(const fapi::Target & i_target,
+                                            const por_engine_t   i_engine,
+                                            const soft_error_t   i_soft_err,
+                                            uint64_t           & o_pc)
+{
+    // return codes
+    fapi::ReturnCode rc;
+
+    // data buffer to hold register values
+    ecmdDataBufferBase data(64);
+
+    do
     {
-        // return codes
-        fapi::ReturnCode rc;
+        // read PC from the Status Register
+        rc = fapiGetScom(i_target, i_engine + STATUS_OFFSET_0x00, data);
+        if (rc)
+        {
+            FAPI_ERR("Error from fapiGetScom (STATUS_REG_0x%08X)", i_engine + STATUS_OFFSET_0x00);
+            break;
+        }
 
-        // data buffer to hold register values
-        ecmdDataBufferBase data(64);
+        o_pc = (data.getDoubleWord(0) & SBE_ADDR_MASK);
 
-        do
+        if (o_pc & FOURBYTE_ALIGNMENT_MASK)
         {
-            //////////////////////////////////////////
-            //Get the PC from the status register
-            //////////////////////////////////////////
-            rc = fapiGetScom(i_target, i_engine + STATUS_OFFSET_0x00, data);
-            if (rc)
+            FAPI_ERR("Address isn't 4-byte aligned");
+            const fapi::Target & CHIP_IN_ERROR = i_target;
+            const uint64_t & PC = o_pc;
+            if (i_engine == SBE)
             {
-                FAPI_ERR("Error reading SBE status reg (0x%08X)", i_engine + STATUS_OFFSET_0x00);
-                break;
+                const soft_error_t & SOFT_ERR_STATUS = i_soft_err;
+                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SBE);
             }
-            o_pc = (data.getDoubleWord(0) & SBE_ADDR_MASK);
-
-            if (o_pc & FOURBYTE_ALIGNMENT_MASK)
+            else
             {
-                FAPI_ERR("Address isn't 4-byte aligned");
-                const fapi::Target & CHIP_IN_ERROR = i_target;
-                uint64_t & SBE_ADDRESS = o_pc;
-                if (i_engine == SBE)
-                {
-                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SBE);
-                }
-                else
-                {
-                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SLW);
-                }
-                break;
+                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SLW);
             }
-        } while(0);
-        return rc;
-    }
+            break;
+        }
+    } while(0);
+
+    return rc;
+}
+
 
 //------------------------------------------------------------------------------
 // subroutine:
 //      Returns the return code indicated by the PC of the engine
 //
-// parameters: i_target   => Target of chip with failed SBE
+// parameters: i_target   => target of chip with failed SBE/SLW engine
 //             i_pSEEPROM => pointer to a memory-mapped SEEPROM image
-//             i_engine   => The type of engine that failed (SBE/SLW)
+//             i_engine   => type of engine that failed (SBE/SLW)
+//             i_soft_err => engine soft error status, for FFDC
 //
 // returns: fapi::ReturnCode with the error
 //          This procedure will NEVER return SUCCESS
 //------------------------------------------------------------------------------
-    fapi::ReturnCode proc_extract_sbe_rc_from_address(const fapi::Target & i_target,
-                                                      const void         * i_pSEEPROM,
-                                                      por_engine_t         i_engine)
+fapi::ReturnCode proc_extract_sbe_rc_from_address(const fapi::Target & i_target,
+                                                  const void         * i_pSEEPROM,
+                                                  const por_engine_t   i_engine,
+                                                  const soft_error_t   i_soft_err)
+{
+    // return codes
+    fapi::ReturnCode rc;
+
+    // data buffer to hold register values
+    ecmdDataBufferBase data(64);
+    uint64_t address_64;
+
+    do
     {
-        // return codes
-        fapi::ReturnCode rc;
+        // read PC
+        rc = proc_extract_sbe_rc_get_pc(i_target, i_engine, i_soft_err, address_64);
+        if (rc)
+        {
+            FAPI_ERR("Error from proc_extract_sbe_rc_get_pc");
+            break;
+        }
 
-        // data buffer to hold register values
-        ecmdDataBufferBase data(64);
-        uint64_t address_64;
+        // add 4 because address_64 is pointing at the halt instruction
+        uint32_t internal_address = (uint32_t)(address_64 & INTERNAL_ADDR_MASK) + 4;
+        // error code to emit
+        uint32_t error_code = 0;
 
-        do
+        if ((address_64 & ADDR_TYPE_MASK) == SEEPROM_ADDR_TYPE)
         {
-            rc = proc_extract_sbe_rc_get_pc(i_target,i_engine,address_64);
+            // get the error code from that location in the SEEPROM image
+            FAPI_INF("Extracting the error code from address "
+                     "0x%X in the SEEPROM", internal_address);
+
+            rc = proc_extract_sbe_rc_read_SEEPROM(i_target, i_pSEEPROM, internal_address, i_engine, i_soft_err, error_code);
             if (rc)
             {
+                FAPI_ERR("Error from proc_extract_sbe_rc_read_SEEPROM (address = 0x%08X)", internal_address);
                 break;
             }
+        }
+        else if ((address_64 & ADDR_TYPE_MASK) == PIBMEM_ADDR_TYPE)
+        {
+            // get the error code from that location in the PIBMEM
+            FAPI_INF("Extracting the error code from address "
+                     "0x%X in the PIBMEM", internal_address);
 
-            uint32_t error_code = 0;
-            //Add 4 because address_64 is pointing at the halt instruction
-            uint32_t internal_address = (uint32_t)(address_64 & INTERNAL_ADDR_MASK) + 4;
-
-            if ((address_64 & ADDR_TYPE_MASK) == SEEPROM_ADDR_TYPE)
+            rc = fapiGetScom(i_target, PIBMEM0_0x00080000 + (internal_address >>3), data);
+            if (rc)
             {
-                //////////////////////////////////////////
-                //Get the error code from that location in the SEEPROM
-                //////////////////////////////////////////
-                FAPI_DBG("Extracting the error code from address "
-                         "0x%X in the SEEPROM", internal_address);
-
-                rc = proc_extract_sbe_rc_read_SEEPROM(i_target, i_pSEEPROM, internal_address, error_code);
-                if (rc)
-                {
-                    FAPI_ERR("Error reading SEEPROM address 0x%08X", internal_address);
-                    break;
-                }
+                FAPI_ERR("Error from fapiGetScom (PIBMEM address 0x%08X)", (uint32_t)PIBMEM0_0x00080000 + (internal_address >>3));
+                break;
             }
-            else
-            if ((address_64 & ADDR_TYPE_MASK) == PIBMEM_ADDR_TYPE)
-            {
-                //////////////////////////////////////////
-                //Get the error code from that location in the PIBMEM
-                //////////////////////////////////////////
-                FAPI_DBG("Extracting the error code from address "
-                         "0x%X in the PIBMEM", internal_address);
 
-                rc = fapiGetScom(i_target, PIBMEM0_0x00080000 + (internal_address >>3), data);
-                if (rc)
-                {
-                    FAPI_ERR("Error reading PIBMEM (scom address 0x%08X)", (uint32_t)PIBMEM0_0x00080000 + (internal_address >>3));
-                    break;
-                }
-                error_code = data.getWord((internal_address & 0x04)?1:0);
+            error_code = data.getWord((internal_address & 0x04)?1:0);
+        }
+        else
+        {
+            FAPI_ERR("Address (0x%012llX) isn't in a known memory address space", address_64);
+            const fapi::Target & CHIP_IN_ERROR = i_target;
+            const uint64_t & PC = address_64;
+            if (i_engine == SBE)
+            {
+                const soft_error_t & SOFT_ERR_STATUS = i_soft_err;
+                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SBE);
             }
             else
             {
-                FAPI_ERR("Address (0x%012llX) isn't in a known memory", address_64);
-                const fapi::Target & CHIP_IN_ERROR = i_target;
-                uint64_t & SBE_ADDRESS = address_64;
-                if (i_engine == SBE)
-                {
-                    FAPI_SET_HWP_ERROR(rc,
-                                       RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SBE);
-                }
-                else
-                {
-                    FAPI_SET_HWP_ERROR(rc,
-                                       RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SLW);
-                }
-                break;
+                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SLW);
             }
+            break;
+        }
 
-            //////////////////////////////////////////
-            //Look up that error code
-            //////////////////////////////////////////
-            FAPI_ERR("SBE got error code 0x%06X", error_code);
-            const fapi::Target CHIP_IN_ERROR = i_target;
-            const fapi::Target CHIP = i_target;
-            FAPI_SET_SBE_ERROR(rc, error_code);
-        } while(0);
+        // look up specified error code
+        FAPI_ERR("SBE got error code 0x%06X", error_code);
+        const fapi::Target CHIP_IN_ERROR = i_target;
+        const fapi::Target CHIP = i_target;
+        FAPI_SET_SBE_ERROR(rc, error_code);
+    } while(0);
 
-        //Make sure the code doesn't return SUCCESS
-        if (rc.ok())
+    //Make sure the code doesn't return SUCCESS
+    if (rc.ok())
+    {
+        FAPI_ERR("proc_extract_sbe_rc_from_addr tried to return SUCCESS,"
+            " which should be impossible. Must be a code bug.");
+        const fapi::Target & CHIP_IN_ERROR = i_target;
+        const uint64_t & PC = address_64;
+        if (i_engine == SBE)
         {
-            FAPI_ERR("proc_extract_sbe_rc_from_addr tried to return SUCCESS,"
-                " which should be impossible. Must be a code bug.");
-            const fapi::Target & CHIP_IN_ERROR = i_target;
-            uint64_t & SBE_ADDRESS = address_64;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG);
+            const soft_error_t & SOFT_ERR_STATUS = i_soft_err;
+            FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG_SBE);
+        }
+        else
+        {
+            FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG_SLW);
         }
-        return rc;
     }
+    return rc;
+}
+
 
 //------------------------------------------------------------------------------
 // function:
-//      Return an RC indicating the SBE error
+//      Return an RC indicating the SBE/SLW error
 //
-// parameters: i_target   => Target of chip with failed SBE
+// parameters: i_target   => Target of chip with failed SBE/SLW
 //             i_pSEEPROM => pointer to a memory-mapped SEEPROM image
 //             i_engine   => The type of engine that failed (SBE/SLW)
 //
 // returns: fapi::ReturnCode with the error
 //          This procedure will NEVER return SUCCESS
 //------------------------------------------------------------------------------
-    fapi::ReturnCode proc_extract_sbe_rc(const fapi::Target & i_target,
-                                         const void         * i_pSEEPROM,
-                                         const por_engine_t   i_engine)
-    {
-        // return codes
-        fapi::ReturnCode rc;
+fapi::ReturnCode proc_extract_sbe_rc(const fapi::Target & i_target,
+                                     const void         * i_pSEEPROM,
+                                     const por_engine_t   i_engine)
+{
+    // return codes
+    fapi::ReturnCode rc;
+
+    // data buffer to hold register values
+    ecmdDataBufferBase data(64);
+    ecmdDataBufferBase pnor_eccb_status(64);
+    ecmdDataBufferBase i2cm_eccb_status(64);
+    ecmdDataBufferBase fsi_data(32);
+    ecmdDataBufferBase sbe_data0(64);
+    ecmdDataBufferBase sbe_data1(64);
+
+    // PC value
+    uint64_t pc = 0x0ULL;
 
-        // data buffer to hold register values
-        ecmdDataBufferBase data(64);
+    // SBE PNOR/SEEPROM soft error status
+    soft_error_t soft_err = eNO_ERROR;
 
-        FAPI_INF("Processing SBE error");
+    // SBE attn status
+    bool sbe_reported_attn = false;
 
-        do
+    do
+    {
+        // check engine type
+        if ((i_engine != SBE) &&
+            (i_engine != SLW))
+        {
+            FAPI_ERR("Unknown engine type %i", i_engine);
+            const fapi::Target & CHIP_IN_ERROR = i_target;
+            const por_engine_t ENGINE = i_engine;
+            FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNKNOWN_ENGINE);
+            break;
+        }
+
+        FAPI_INF("Processing %s error", ((i_engine == SBE)?("SBE"):("SLW")));
+
+        // if analyzing SBE engine failure
+        // - make sure I2C master bus fence is released before proceeding
+        // - check ECCB engines (I2C/LPC) for UE/CE conditions (SLW does not use
+        //   these engines, so no need to check)
+        if (i_engine == SBE)
         {
-            //JDS TODO - print out the istep name based on SBE_VITAL
+            FAPI_EXEC_HWP(rc, proc_reset_i2cm_bus_fence, i_target);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from proc_reset_i2cm_bus_fence");
+                break;
+            }
+
+            // check on FSI 1007 for any PIB Access Error
+            rc = fapiGetCfamRegister(i_target, CFAM_FSI_STATUS_0x00001007, fsi_data);
+            if (rc)
+            {
+                FAPI_ERR("Error from fapiGetCfamRegister (CFAM_FSI_STATUS_0x00001007)");
+                break;
+            }
 
-            if ((i_engine != SBE) &&
-                (i_engine != SLW))
+            if (fsi_data.getNumBitsSet(17,3) != 0)
             {
-                FAPI_ERR("Unknown engine type %i", i_engine);
-                const por_engine_t ENGINE = i_engine;
+                FAPI_ERR("Error during PIB Access");
                 const fapi::Target & CHIP_IN_ERROR = i_target;
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNKNOWN_ENGINE);
+                const ecmdDataBufferBase & FSI_STATUS = fsi_data;
+                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_PIB_ERROR_SBE);
                 break;
             }
 
-            // if analyzing SBE engine failure, make sure I2C master bus fence is
-            // released before proceeding
-            if (i_engine == SBE)
+            if (fsi_data.isBitSet(30))
             {
-                FAPI_EXEC_HWP(rc, proc_reset_i2cm_bus_fence, i_target);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error from proc_reset_i2cm_bus_fence");
-                    break;
-                }
+                FAPI_ERR("SELFBOOT_ENGINE_ATTENTION - SBE reported attention to FSI2PIB status register");
+                sbe_reported_attn = true;
             }
 
-            //JDS TODO - split out the generic error into more granular errors?
-            bool generic_hw_error = false;
-            //////////////////////////////////////////
-            // Check for SBE error bits
-            //////////////////////////////////////////
-            rc = fapiGetScom(i_target, i_engine + DEBUG1_OFFSET_0x10, data);
+            // check on ECCB Error for I2C engine
+            rc = fapiGetScom(i_target, PORE_ECCB_STATUS_REGISTER_READ_0x000C0002, i2cm_eccb_status);
             if (rc)
             {
-                FAPI_ERR("Error reading SBE debug1 reg (0x%08X)", i_engine + DEBUG1_OFFSET_0x10);
+                FAPI_ERR("Error from fapiGetScom (PORE_ECCB_STATUS_REGISTER_READ_0x000C00002)");
                 break;
             }
-            if (data.isBitSet(48))
+
+            // check on ECCB Engine for PNOR Access	
+            rc = fapiGetScom(i_target, LPC_STATUS_0x000B0002, pnor_eccb_status);
+            if (rc)
             {
-                FAPI_ERR("OCI_DATA_READ_P_ERR - Parity error in read data from OCI");
-                generic_hw_error=true;
+                FAPI_ERR("Error from fapiGetScom (LPC_STATUS_0x000B0002)");
+                break;
             }
-            if (data.isBitSet(52))
+
+            // determine if either engine has reached threshold of > 128 CEs
+            if (i2cm_eccb_status.isBitSet(57))
             {
-                FAPI_ERR("BAD_PAR - bad instruction parity");
-                generic_hw_error=true;
+                soft_err = eSOFT_ERR_I2CM;
             }
-            if (data.isBitSet(53))
+
+            if (pnor_eccb_status.isBitSet(57))
             {
-                //////////////////////////////////////////
-                //Check if the SBE stopped at a code detected error
-                // (a 'halt' instruction, which is an invalid instruction)
-                //////////////////////////////////////////
-                rc = fapiGetScom(i_target, i_engine + IBUF_OFFSET_0x0D, data);
-                if (rc)
+                if (soft_err == eSOFT_ERR_I2CM)
                 {
-                    FAPI_ERR("SBE reported an invalid instruction error, but got a scom error reading SBE instruction buffer reg (0x%08X) to determine if it was a code-detected error or not", i_engine + IBUF_OFFSET_0x0D);
-                    break;
-                }
-
-                const uint32_t instruction = data.getWord(0);
-                if (instruction == HALT_WITH_ERROR_INSTRUCTION)
-                {
-                    rc = proc_extract_sbe_rc_from_address(i_target, i_pSEEPROM, i_engine);
-                    break;
+                    soft_err = eSOFT_ERR_BOTH;
                 }
                 else
                 {
-                    FAPI_ERR("BAD_INSTRUCTION - invalid instruction");
-                    generic_hw_error=true;
+                    soft_err = eSOFT_ERR_PNOR;
                 }
             }
-            if (data.isBitSet(54))
+        }
+
+        // read engine PC value
+        rc = proc_extract_sbe_rc_get_pc(i_target, i_engine, soft_err, pc);
+        if (rc)
+        {
+            FAPI_ERR("Error from proc_extract_sbe_rc_get_pc");
+            break;
+        }
+
+        if (i_engine == SBE)
+        {
+            // return error if either engine reports an unrecoverable ECC error
+            if (i2cm_eccb_status.isBitClear(41,2) && i2cm_eccb_status.isBitSet(43))
+            {
+                FAPI_ERR("Unrecoverable ECC error on I2C Access");
+                const fapi::Target & CHIP_IN_ERROR = i_target;
+                const uint64_t & PC = pc;
+                const ecmdDataBufferBase & ECCB_STATUS = i2cm_eccb_status;
+                const soft_error_t & SOFT_ERR_STATUS = soft_err;
+                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_I2C_SBE);
+                break;
+            }
+
+            if (pnor_eccb_status.isBitClear(41,2) && pnor_eccb_status.isBitSet(43))
+            {
+                FAPI_ERR("Unrecoverable ECC error on PNOR Access");
+                const fapi::Target & CHIP_IN_ERROR = i_target;
+                const uint64_t & PC = pc;
+                const ecmdDataBufferBase & ECCB_STATUS = pnor_eccb_status;
+                const soft_error_t & SOFT_ERR_STATUS = soft_err;
+                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_PNOR_SBE);
+                break;
+            }
+        } // if (i_engine == SBE)
+
+
+        // read Debug1 register state, check for any HW error
+        rc = fapiGetScom(i_target, i_engine + DEBUG1_OFFSET_0x10, sbe_data1);
+        if (rc)
+        {
+            FAPI_ERR("Error from fapiGetScom (DEBUG1_REG_0x%08X)", i_engine + DEBUG1_OFFSET_0x10);
+            break;
+        }
+
+        if (sbe_data1.isBitSet(63))  // SBE ANYERROR
+        {
+            FAPI_ERR("PIBMS_DBG_LOCK - error set");
+
+            // read Debug0 register state
+            rc = fapiGetScom(i_target, i_engine + DEBUG0_OFFSET_0x0F, sbe_data0);
+            if (rc)
+            {
+                FAPI_ERR("Error from fapiGetScom (DEBUG0_REG_0x%08X)", i_engine + DEBUG0_OFFSET_0x0F);
+                break;
+            }
+
+            // print bitwise messages for error log, unique errors will be grouped/combined into callouts below
+            // grouping is done per guideance provided by Andreas Koenig
+            if (sbe_data1.isBitSet(48))
+            {
+                FAPI_ERR("OCI_DATA_READ_P_ERR - Parity error in read data from OCI");
+            }
+            uint8_t oci_rc = (sbe_data0.getByte(7) >> 5) & 0x7;
+            if (oci_rc)
+            {
+                FAPI_ERR("Last return code from OCI SBE got return code %i", oci_rc);
+            }
+            if (sbe_data1.isBitSet(52))
+            {
+                FAPI_ERR("BAD_PAR - bad instruction parity");
+            }
+            if (sbe_data1.isBitSet(53))
+            {
+                FAPI_ERR("BAD_INSTRUCTION - invalid instruction");
+            }
+            if (sbe_data1.isBitSet(54))
             {
                 FAPI_ERR("BAD_PC - PC overflow/underflow");
-                generic_hw_error=true;
             }
-            if (data.isBitSet(55))
+            if (sbe_data1.isBitSet(55))
             {
                 FAPI_ERR("SCAN_DATA_CRC - Scan data CRC error");
-                generic_hw_error=true;
             }
-            if (data.isBitSet(56))
+            if (sbe_data1.isBitSet(56))
             {
                 FAPI_ERR("PC_STACK_ERR - PC stack PUSH error or POP error");
-                generic_hw_error=true;
             }
-            if (data.isBitSet(57))
+            if (sbe_data1.isBitSet(57))
             {
-                FAPI_ERR("INSTR_FETCH_ERROR - Non-zero return code or read data parity error was received when during fetch  - phase");
-                generic_hw_error=true;
+                FAPI_ERR("INSTR_FETCH_ERROR - Non-zero return code or read sbe_data1 parity error was received when during fetch  - phase");
             }
-            if (data.isBitSet(58))
+            if (sbe_data1.isBitSet(58))
             {
                 FAPI_ERR("BAD_OPERAND - Invalid Instruction Operand");
-                generic_hw_error=true;
             }
-            if (data.isBitSet(59))
+            if (sbe_data1.isBitSet(59))
             {
                 FAPI_ERR("BAD_INSTRUCTION_PATH - Invalid Instruction Path (e.g. FI2C parameter miss)");
-                generic_hw_error=true;
             }
-            if (data.isBitSet(60))
+            if (sbe_data1.isBitSet(60))
             {
                 FAPI_ERR("BAD_START_VECTOR_TRIGGER - Invalid Start Vector triggered");
-                generic_hw_error=true;
             }
-            if (data.isBitSet(61))
+            if (sbe_data1.isBitSet(61))
             {
                 FAPI_ERR("FI2C_PROTOCOL_HANG - Fast I2C protocol hang detected - exceeded poll limit for FI2C engine");
-                generic_hw_error=true;
             }
-            rc = fapiGetScom(i_target, i_engine + DEBUG0_OFFSET_0x0F, data);
-            if (rc)
+            if (sbe_data1.isBitSet(62))
             {
-                FAPI_ERR("Error reading SBE debug0 reg (0x%08X)", i_engine + DEBUG0_OFFSET_0x0F);
-                break;
+                FAPI_ERR("ROL_INVALID - rotate invalid");
+            }
+
+            if (sbe_data0.isBitSet(32))
+            {
+                FAPI_ERR("PIB_DATA_READ_P_ERR - Parity error in read data from PRV PIB");
             }
-            uint8_t pcb_error = data.getByte(4) >> 4;
+            uint8_t pcb_error = (sbe_data0.getByte(4) >> 4) & 0x7;
+            uint32_t scom_address = sbe_data0.getWord(0);
             if (pcb_error)
             {
-                uint32_t scom_address = data.getWord(0);
                 FAPI_ERR("SBE got PCB error %i accessing scom address 0x%08X", pcb_error, scom_address);
-                generic_hw_error=true;
             }
-            if (data.isBitSet(36))
+            if (sbe_data0.isBitSet(36))
             {
                 FAPI_ERR("I2C_BAD_STATUS_0 - I2CM internal errors including parity errors");
-                generic_hw_error=true;
             }
-            if (data.isBitSet(37))
+            if (sbe_data0.isBitSet(37))
             {
                 FAPI_ERR("I2C_BAD_STATUS_1 - bad PIB response code error for ECCAX to I2CM communication");
-                generic_hw_error=true;
             }
-            if (data.isBitSet(38))
+            if (sbe_data0.isBitSet(38))
             {
                 FAPI_ERR("I2C_BAD_STATUS_2 - ECCAX internal errors (UCE or PIB master resets)");
-                generic_hw_error=true;
             }
-            if (data.isBitSet(39))
+            if (sbe_data0.isBitSet(39))
             {
                 FAPI_ERR("I2C_BAD_STATUS_3 - I2C bus issues (I2C bus busy, NACK, stop bit error)");
-                generic_hw_error=true;
             }
-            if (data.isBitSet(40))
+            if (sbe_data0.isBitSet(40))
             {
                 FAPI_ERR("GROUP_PARITY_ERROR_0 - parity error from debug or status or error mask or pc stack regs");
-                generic_hw_error=true;
             }
-            if (data.isBitSet(41))
+            if (sbe_data0.isBitSet(41))
             {
                 FAPI_ERR("GROUP_PARITY_ERROR_1 - parity error from control or exe trigger or exe t_mask or i2c param regs");
-                generic_hw_error=true;
             }
-            if (data.isBitSet(42))
+            if (sbe_data0.isBitSet(42))
             {
                 FAPI_ERR("GROUP_PARITY_ERROR_2 - parity error from perv/oci base addr or table base addr or memory reloc");
-                generic_hw_error=true;
             }
-            if (data.isBitSet(43))
+            if (sbe_data0.isBitSet(43))
             {
-                FAPI_ERR("GROUP_PARITY_ERROR_3 - parity error from scr0 or scr1 or scr2 or data scr0 reg");
-                generic_hw_error=true;
+                FAPI_ERR("GROUP_PARITY_ERROR_3 - parity error from scr0 or scr1 or scr2 or sbe_data0 scr0 reg");
             }
-            if (data.isBitSet(44))
+            if (sbe_data0.isBitSet(44))
             {
                 FAPI_ERR("GROUP_PARITY_ERROR_4 - parity error from ibuf regs");
-                generic_hw_error=true;
             }
-            if (generic_hw_error)
+
+            //
+            // Bucketize callouts based on combination of error bits
+            //
+
+            // "Internal Error" bucket (Error Event 3)
+            if ((sbe_data0.getNumBitsSet(40,5) != 0) || sbe_data1.isBitSet(55))
             {
+                FAPI_ERR("Internal %s Error", ((i_engine == SBE)?("SBE"):("SLW")));
                 const fapi::Target & CHIP_IN_ERROR = i_target;
-                if(i_engine == SBE)
+                const uint64_t & PC = pc;
+                const uint8_t & GROUP_PARITY_ERROR_0_4 = (sbe_data0.getByte(5) >> 3) & 0x1F;
+                const bool & SCAN_DATA_CRC_ERROR = sbe_data1.isBitSet(55);
+                if (i_engine == SBE)
                 {
-                    FAPI_SET_HWP_ERROR(rc,RC_PROC_EXTRACT_SBE_RC_GENERIC_SBE_HW_ERROR);
-                    break;
+                    const soft_error_t & SOFT_ERR_STATUS = soft_err;
+                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_INTERNAL_ERROR_SBE);
                 }
                 else
                 {
-                    FAPI_SET_HWP_ERROR(rc,RC_PROC_EXTRACT_SBE_RC_GENERIC_SLW_HW_ERROR);
-                    break;
+                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_INTERNAL_ERROR_SLW);
                 }
+                break;
             }
-                    
 
-            //No error bits are set, so perhaps it was a real halt (ie. wait 0) instruction in OTPROM
-            uint64_t pc = 0;
-            rc = proc_extract_sbe_rc_get_pc(i_target, i_engine, pc);
-            if (rc)
+            // "I2C Error" bucket (Error Event 0)
+            if ((sbe_data0.getNumBitsSet(36,4) != 0) || (sbe_data1.isBitSet(61)))
+            {
+                FAPI_ERR("%s failed I2C Master operation", ((i_engine == SBE)?("SBE"):("SLW")));
+                const fapi::Target & CHIP_IN_ERROR = i_target;
+                const uint64_t & PC = pc;
+                const uint8_t & I2C_BAD_STATUS_0_3 = sbe_data0.getHalfWord(10);
+                const bool & FI2C_HANG = sbe_data1.isBitSet(61);
+
+                if (i_engine == SBE)
+                {
+                    const soft_error_t & SOFT_ERR_STATUS = soft_err;
+                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_I2C_ERROR_SBE);
+                }
+                else
+                {
+                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_I2C_ERROR_SLW);
+                }
+                break;
+            }
+
+            // "SCOM Error" bucket (Error Event 0), raise in presence of no instruction execution error
+            if ((sbe_data0.getNumBitsSet(32,4) != 0) && (sbe_data1.getNumBitsSet(52,9) == 0) && (sbe_data1.isBitClear(62)))
             {
+                FAPI_ERR("%s failed SCOM operation", ((i_engine == SBE)?("SBE"):("SLW")));
+                const fapi::Target & CHIP_IN_ERROR = i_target;
+                const uint64_t & PC = pc;
+                const uint32_t & SCOM_ADDRESS = scom_address;
+                const uint8_t & PIB_ERROR_CODE = pcb_error;
+                const bool & PIB_DATA_READ_PARITY_ERROR = sbe_data0.isBitSet(32);
+                if (i_engine == SBE)
+                {
+                    const soft_error_t & SOFT_ERR_STATUS = soft_err;
+                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SCOM_ERROR_SBE);
+                }
+                else
+                {
+                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SCOM_ERROR_SLW);
+                }
                 break;
             }
 
-            if ((pc & ADDR_TYPE_MASK) == OTPROM_ADDR_TYPE)
+            // "OCI Error" bucket (Error Event 1)
+            if ((i_engine == SLW) && (sbe_data1.getNumBitsSet(48,4) != 0))
             {
-                //Note: OTPROM halts are actual halt instructions, which means the
-                // SBE updated the PC before the halt.
-                // Thus we have to subtract 4 to get back to the address of the halt
-                uint32_t internal_address = (uint32_t)(pc & INTERNAL_ADDR_MASK) - 4;
+                FAPI_ERR("%s failed OCI Master operation", ((i_engine == SBE)?("SBE"):("SLW")));
+                const fapi::Target & CHIP_IN_ERROR = i_target;
+                const uint64_t & PC = pc;
+                const uint8_t & OCI_ERROR_CODE = oci_rc;
+                const bool & OCI_DATA_READ_PARITY_ERROR = sbe_data1.isBitSet(48);
+                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_OCI_ERROR_SLW);
+                break;
+            }
 
-                //////////////////////////////////////////
-                //Map the OTPROM address to the known error at that location
-                //The OTPROM is write-once at mfg, so addresses should remain fixed
-                //////////////////////////////////////////
-                FAPI_DBG("Determining the OTPROM error based on the address "
-                         "0x%X", internal_address);
+            // check for the execution of an invalid instruction
+            // if present, check if the SBE stopped at a code detected error (instruction = 'halt')
+            if (sbe_data1.isBitSet(53) || sbe_data1.isBitSet(62))
+            {
+                rc = fapiGetScom(i_target, i_engine + IBUF_OFFSET_0x0D, data);
+                if (rc)
+                {
+                    // fail through to "Instruction Execution Error" bucket below
+                    FAPI_ERR("Error from fapiGetScom(IBUF_REG_0x%08X)", i_engine + IBUF_OFFSET_0x0D);
+                    FAPI_ERR("SBE reported an invalid instruction error, but unable to determine if it was a code-detected error or not");
+                }
+                else
+                {
+                    // lookup return code identifying halt from image, based on PC value
+                    const uint32_t instruction = data.getWord(0);
+                    if (instruction == HALT_WITH_ERROR_INSTRUCTION)
+                    {
+                        rc = proc_extract_sbe_rc_from_address(i_target, i_pSEEPROM, i_engine, soft_err);
+                        break;
+                    }
+                }
+            }
+
+            // "Instruction Execution Error" bucket (Error Event 2)
+            if ((sbe_data1.getNumBitsSet(52,9) != 0) || (sbe_data1.isBitSet(62)))
+            {
+                FAPI_ERR("SBE encountered instruction execution error");
                 const fapi::Target & CHIP_IN_ERROR = i_target;
-                switch(internal_address)
+                const uint64_t & PC = pc;
+                const bool & INSTRUCTION_PARITY_ERROR = sbe_data1.isBitSet(52);
+                const bool & INVALID_INSTRUCTION_NON_ROTATE = sbe_data1.isBitSet(53);
+                const bool & PC_OVERFLOW_UNDERFLOW = sbe_data1.isBitSet(54);
+                // bit 55 covered by Internal Error check
+                const bool & PC_STACK_ERROR = sbe_data1.isBitSet(56);
+                const bool & INSTRUCTION_FETCH_ERROR = sbe_data1.isBitSet(57);
+                const bool & INVALID_OPERAND = sbe_data1.isBitSet(58);
+                const bool & I2C_ENGINE_MISS = sbe_data1.isBitSet(59);
+                const bool & INVALID_START_VECTOR = sbe_data1.isBitSet(60);
+                const bool & INVALID_INSTRUCTION_ROTATE = sbe_data1.isBitSet(62);
+
+                if (i_engine == SBE)
                 {
-                case (0x400fc): //Original OTPROM
-                case (0x40118): //Updated OTPROM
+                    const soft_error_t & SOFT_ERR_STATUS = soft_err;
+                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_INSTRUCTION_ERROR_SBE);
+                }
+                else
+                {
+                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_INSTRUCTION_ERROR_SLW);
+                }
+                break;
+            }
+        } // SBE ANYERROR debug(63)
+
+        // no error bits are set, check PC to check execution progress
+        // check for real halt (wait 0) instruction in OTPROM
+        if ((i_engine == SBE) && ((pc & ADDR_TYPE_MASK) == OTPROM_ADDR_TYPE))
+        {
+            // Note: OTPROM halts are actual halt instructions, which means the
+            //       SBE updated the PC before the halt.
+            //       Thus we have to subtract 4 to get back to the address of the halt
+            uint32_t internal_address = (uint32_t)(pc & INTERNAL_ADDR_MASK) - 4;
+
+            // map the OTPROM address to the known error at that location
+            // the OTPROM is write-once at mfg test, so addresses should remain fixed in this code
+            FAPI_INF("Determining the OTPROM error based on the address "
+                     "0x%X", internal_address);
+            const fapi::Target & CHIP_IN_ERROR = i_target;
+            const uint64_t & PC = internal_address;
+
+            switch (internal_address)
+            {
+                case (0x400fc): // original OTPROM version
+                case (0x40118): // updated OTPROM version
                     FAPI_ERR("Chip not identified as Murano or Venice");
-                    FAPI_SET_HWP_ERROR(rc,RC_PROC_EXTRACT_SBE_RC_BAD_CHIP_TYPE);
+                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_BAD_CHIP_TYPE_SBE);
                     break;
                 case (0x401c0):
                     FAPI_ERR("SEEPROM magic number didn't match \"XIP SEPM\"");
-                    FAPI_SET_HWP_ERROR(rc,RC_PROC_EXTRACT_SBE_RC_SEEPROM_MAGIC_NUMBER_MISMATCH);
+                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SEEPROM_MAGIC_NUMBER_MISMATCH_SBE);
                     break;
                 case (0x401ec):
                     FAPI_ERR("Branch to SEEPROM didn't happen");
-                    FAPI_SET_HWP_ERROR(rc,RC_PROC_EXTRACT_SBE_RC_BRANCH_TO_SEEPROM_FAIL);
+                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_BRANCH_TO_SEEPROM_FAIL_SBE);
                     break;
                 default:
                     FAPI_ERR("Halted in OTPROM, but not at an expected halt location");
-                    FAPI_SET_HWP_ERROR(rc,RC_PROC_EXTRACT_SBE_RC_UNEXPECTED_OTPROM_HALT);
+                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNEXPECTED_OTPROM_HALT_SBE);
                     break;
-                }                    
+            }
+            break;
+        }
+
+        // check to see if engine was never started
+        if (((pc & SBE_ADDR_MASK) == 0x0000800000000000ULL) ||
+            ((pc & SBE_ADDR_MASK) == 0x0000000000000000ULL))
+        {
+            FAPI_ERR("PC is all zeros, which means %s was probably never started", ((i_engine == SBE)?("SBE"):("SLW")));
+            const fapi::Target & CHIP_IN_ERROR = i_target;
+            const uint64_t & PC = pc;
+
+            if (i_engine == SBE)
+            {
+                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_NEVER_STARTED_SBE);
                 break;
             }
-            else if (((pc & SBE_ADDR_MASK) == 0x0000800000000000ull) ||
-                     ((pc & SBE_ADDR_MASK) == 0x0000000000000000ull))
+            else
             {
-                //PC is all zeros, which means SBE was probably never started
-                FAPI_ERR("PC is all zeros, which means SBE was probably never started");
-                const fapi::Target & CHIP_IN_ERROR = i_target;
-                if(i_engine == SBE)
-                {
-                    FAPI_SET_HWP_ERROR(rc,RC_PROC_EXTRACT_SBE_RC_SBE_NEVER_STARTED);
-                    break;
-                }
-                else
-                {
-                    FAPI_SET_HWP_ERROR(rc,RC_PROC_EXTRACT_SBE_RC_SLW_NEVER_STARTED);
-                    break;
-                }
+                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_NEVER_STARTED_SLW);
+                break;
             }
+        }
 
-        } while(0);
-
-        //Make sure the code doesn't return SUCCESS
-        if (rc.ok())
+        // return soft error with lowest priority
+        if ((i_engine == SBE) && (soft_err != eNO_ERROR))
         {
-            FAPI_ERR("proc_extract_sbe_rc tried to return SUCCESS,"
-                " which should be impossible. Must be a code bug.");
+            if ((soft_err == eSOFT_ERR_PNOR) || (soft_err == eSOFT_ERR_BOTH))
+            {
+                FAPI_ERR("Recoverable ECC Error on PNOR Access");
+            }
+            if ((soft_err == eSOFT_ERR_I2CM) || (soft_err == eSOFT_ERR_BOTH))
+            {
+                FAPI_ERR("Recoverable ECC Error on I2C Access");
+            }
             const fapi::Target & CHIP_IN_ERROR = i_target;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_CODE_BUG);
+            const soft_error_t & SOFT_ERR_STATUS = soft_err;
+            const ecmdDataBufferBase & PNOR_ECCB_STATUS = pnor_eccb_status;
+            const ecmdDataBufferBase & I2C_ECCB_STATUS = i2cm_eccb_status;
+            FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_SBE);
+            break;
         }
-        return rc;
+
+    } while(0);
+
+    // if SBE, make sure that the code doesn't return FAPI_RC_SUCCESS
+    // if the engine reported an attn to the FSI2PIB status register
+    if (rc.ok() && (i_engine == SBE) && (sbe_reported_attn))
+    {
+        FAPI_ERR("SBE reported attention, but proc_extract_sbe_rc tried to return SUCCESS,"
+            " which should be impossible. Must be a code bug.");
+        const fapi::Target & CHIP_IN_ERROR = i_target;
+        const uint64_t & PC = pc;  
+        FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_CODE_BUG_SBE);
     }
+    return rc;
+}
+
 
 } // extern "C"
 /* Local Variables: */
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.H b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.H
index b332c6e94..009429e4b 100644
--- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.H
+++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_extract_sbe_rc.H,v 1.5 2014/02/10 02:57:57 stillgs Exp $
+// $Id: proc_extract_sbe_rc.H,v 1.7 2014/03/18 14:09:28 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_sbe_rc.H,v $
 //------------------------------------------------------------------------------
 // *|
@@ -29,8 +29,7 @@
 // *! *** IBM Confidential ***
 // *|
 // *! TITLE       : proc_extract_sbe_rc.H
-// *! DESCRIPTION : Create a return code for an SBE error. Will NEVER return
-// *!               with SUCCESS.
+// *! DESCRIPTION : Create a return code for an SBE/SLW error.
 // *!
 // *! OWNER NAME  : Johannes Koesters       Email: koesters@de.ibm.com
 // *!
@@ -42,17 +41,12 @@
 //------------------------------------------------------------------------------
 // Includes
 //------------------------------------------------------------------------------
-
 #include <fapi.H>
-#include "p8_scom_addresses.H"
+#include <p8_scom_addresses.H>
 
 //------------------------------------------------------------------------------
 // Structure definitions
 //------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Enum definitions
-//------------------------------------------------------------------------------
 enum por_engine_t {
   SBE = PORE_SBE_0x000E0000,
   SLW = PORE_SLW_0x00068000
@@ -72,14 +66,11 @@ extern "C"
 {
 
 /**
- * @brief Create a return code based off the current SBE RC.
- *
- * @param[in] i_target         Reference to processor target containing the SBE
+ * @brief Create a return code based off the current SBE/SLW RC.
  *
+ * @param[in] i_target         Reference to processor target containing the SBE/SLW engine
  * @param[in] i_pSEEPROM       Pointer to a memory-mapped SEEPROM image (or NULL) 
- *
  * @param[in] i_engine         The POR engine type (SBE/SLW)
- *
  * @return ReturnCode          The error code the SBE hit, or the error hit
  *                             while trying to get the error code
  */
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc_errors.xml b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc_errors.xml
index a754f87ad..1700a2a29 100644
--- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc_errors.xml
+++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc_errors.xml
@@ -20,23 +20,61 @@
 <!-- Origin: 30                                                             -->
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
-<!-- $Id: proc_extract_sbe_rc_errors.xml,v 1.8 2014/02/10 02:55:29 stillgs Exp $ -->
+<!-- $Id: proc_extract_sbe_rc_errors.xml,v 1.12 2014/03/18 14:11:37 jmcgill Exp $ -->
 <!-- Error definitions for proc_extract_sbe_rc procedure -->
 <hwpErrors>
   <!-- *********************************************************************** -->
   <hwpError>
-    <rc>RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL</rc>
+    <rc>RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL_SBE</rc>
     <description>
       Procedure: proc_extract_sbe_rc
-      Can't extract an error from a NULL SEEPROM image
+      NULL image pointer prevented extraction of SBE error code
     </description>
-    <ffdc>ADDRESS</ffdc>
     <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
+    <ffdc>SOFT_ERR_STATUS</ffdc>
     <collectRegisterFfdc>
       <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
       <id>REG_FFDC_PROC_SBE_REGISTERS</id>
+      <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
       <target>CHIP_IN_ERROR</target>
     </collectRegisterFfdc>
+    <callout>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>LOW</priority>
+    </callout>
+    <deconfigure>
+      <target>CHIP_IN_ERROR</target>
+    </deconfigure>
+    <gard>
+      <target>CHIP_IN_ERROR</target>
+    </gard>
+  </hwpError>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL_SLW</rc>
+    <description>
+      Procedure: proc_extract_sbe_rc
+      NULL image pointer prevented extraction of SLW error code
+    </description>
+    <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
+    <collectRegisterFfdc>
+      <id>REG_FFDC_PROC_SLW_REGISTERS</id>
+      <target>CHIP_IN_ERROR</target>
+    </collectRegisterFfdc>
+    <callout>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>LOW</priority>
+    </callout>
     <deconfigure>
       <target>CHIP_IN_ERROR</target>
     </deconfigure>
@@ -46,35 +84,76 @@
   </hwpError>
   <!-- *********************************************************************** -->
   <hwpError>
-    <rc>RC_PROC_EXTRACT_SBE_RC_BAD_CHIP_TYPE</rc>
+    <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SBE</rc>
     <description>
       Procedure: proc_extract_sbe_rc
-      OTPROM code didn't recognize this chip as a Murano or Venice chip
+      The SBE stop address isn't properly aligned
     </description>
     <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
+    <ffdc>SOFT_ERR_STATUS</ffdc>
     <collectRegisterFfdc>
       <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
       <id>REG_FFDC_PROC_SBE_REGISTERS</id>
+      <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
+      <target>CHIP_IN_ERROR</target>
+    </collectRegisterFfdc>
+    <callout>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>CHIP_IN_ERROR</target>
+    </deconfigure>
+    <gard>
+      <target>CHIP_IN_ERROR</target>
+    </gard>
+  </hwpError>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SLW</rc>
+    <description>
+      Procedure: proc_extract_sbe_rc
+      The SLW stop address isn't properly aligned
+    </description>
+    <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
+    <collectRegisterFfdc>
+      <id>REG_FFDC_PROC_SLW_REGISTERS</id>
       <target>CHIP_IN_ERROR</target>
     </collectRegisterFfdc>
+    <callout>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
     <deconfigure>
       <target>CHIP_IN_ERROR</target>
     </deconfigure>
+    <gard>
+      <target>CHIP_IN_ERROR</target>
+    </gard>
   </hwpError>
   <!-- *********************************************************************** -->
   <hwpError>
-    <rc>RC_PROC_EXTRACT_SBE_RC_SEEPROM_MAGIC_NUMBER_MISMATCH</rc>
+    <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SBE</rc>
     <description>
       Procedure: proc_extract_sbe_rc
-      The magic number read out of the SEEPROM doesn't match SBE SEPM
+      The SBE stop address isn't in a recognized address space
     </description>
     <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
+    <ffdc>SOFT_ERR_STATUS</ffdc>
     <collectRegisterFfdc>
       <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
       <id>REG_FFDC_PROC_SBE_REGISTERS</id>
+      <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
       <target>CHIP_IN_ERROR</target>
     </collectRegisterFfdc>
     <callout>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
+    <callout>
       <procedure>CODE</procedure>
       <priority>LOW</priority>
     </callout>
@@ -87,17 +166,25 @@
   </hwpError>
   <!-- *********************************************************************** -->
   <hwpError>
-    <rc>RC_PROC_EXTRACT_SBE_RC_BRANCH_TO_SEEPROM_FAIL</rc>
+    <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SLW</rc>
     <description>
       Procedure: proc_extract_sbe_rc
-      The branch into the SEEPROM didn't happen
+      The SLW stop address isn't in a reognized address space
     </description>
     <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
     <collectRegisterFfdc>
-      <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
-      <id>REG_FFDC_PROC_SBE_REGISTERS</id>
+      <id>REG_FFDC_PROC_SLW_REGISTERS</id>
       <target>CHIP_IN_ERROR</target>
     </collectRegisterFfdc>
+    <callout>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>LOW</priority>
+    </callout>
     <deconfigure>
       <target>CHIP_IN_ERROR</target>
     </deconfigure>
@@ -107,17 +194,55 @@
   </hwpError>
   <!-- *********************************************************************** -->
   <hwpError>
-    <rc>RC_PROC_EXTRACT_SBE_RC_UNEXPECTED_OTPROM_HALT</rc>
+    <rc>RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG_SBE</rc>
     <description>
       Procedure: proc_extract_sbe_rc
-      The OTPROM code halted at an unexpected location
+      Extract RC from address subroutine tried to return SUCCESS for SBE, which isn't allowed
     </description>
     <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
+    <ffdc>SOFT_ERR_STATUS</ffdc>
     <collectRegisterFfdc>
       <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
       <id>REG_FFDC_PROC_SBE_REGISTERS</id>
       <target>CHIP_IN_ERROR</target>
     </collectRegisterFfdc>
+    <callout>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>LOW</priority>
+    </callout>
+    <deconfigure>
+      <target>CHIP_IN_ERROR</target>
+    </deconfigure>
+    <gard>
+      <target>CHIP_IN_ERROR</target>
+    </gard>
+  </hwpError>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG_SLW</rc>
+    <description>
+      Procedure: proc_extract_sbe_rc
+      Extract RC from address subroutine tried to return SUCCESS for SLW, which isn't allowed
+    </description>
+    <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
+    <collectRegisterFfdc>
+      <id>REG_FFDC_PROC_SLW_REGISTERS</id>
+      <target>CHIP_IN_ERROR</target>
+    </collectRegisterFfdc>
+    <callout>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>LOW</priority>
+    </callout>
     <deconfigure>
       <target>CHIP_IN_ERROR</target>
     </deconfigure>
@@ -147,17 +272,23 @@
   </hwpError>
   <!-- *********************************************************************** -->
   <hwpError>
-    <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SBE</rc>
+    <rc>RC_PROC_EXTRACT_SBE_RC_PIB_ERROR_SBE</rc>
     <description>
       Procedure: proc_extract_sbe_rc
-      The SBE stop address isn't properly aligned
+      Error during PIB access for SBE
     </description>
-    <ffdc>SBE_ADDRESS</ffdc>
+    <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>FSI_STATUS</ffdc>
     <collectRegisterFfdc>
       <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
       <id>REG_FFDC_PROC_SBE_REGISTERS</id>
+      <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
       <target>CHIP_IN_ERROR</target>
     </collectRegisterFfdc>
+    <callout>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
     <deconfigure>
       <target>CHIP_IN_ERROR</target>
     </deconfigure>
@@ -167,53 +298,185 @@
   </hwpError>
   <!-- *********************************************************************** -->
   <hwpError>
-    <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SLW</rc>
+    <rc>RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_I2C_SBE</rc>
     <description>
       Procedure: proc_extract_sbe_rc
-      The SLW stop address isn't properly aligned
+      ECCB indicates unrecoverable ECC error from I2C during SBE execution
+      Reload/update of SEEPROM required
+    </description>
+    <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
+    <ffdc>ECCB_STATUS</ffdc>
+    <ffdc>SOFT_ERR_STATUS</ffdc>
+    <collectRegisterFfdc>
+      <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
+      <id>REG_FFDC_PROC_SBE_REGISTERS</id>
+      <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
+      <target>CHIP_IN_ERROR</target>
+    </collectRegisterFfdc>
+    <callout>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>CHIP_IN_ERROR</target>
+    </deconfigure>
+    <gard>
+      <target>CHIP_IN_ERROR</target>
+    </gard>
+  </hwpError>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_PNOR_SBE</rc>
+    <description>
+      Procedure: proc_extract_sbe_rc
+      ECCB indicates unrecoverable ECC error from PNOR during SBE execution
+      Reload/Update of PNOR required
     </description>
-    <ffdc>SBE_ADDRESS</ffdc>
+    <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
+    <ffdc>ECCB_STATUS</ffdc>
+    <ffdc>SOFT_ERR_STATUS</ffdc>
+    <collectRegisterFfdc>
+      <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
+      <id>REG_FFDC_PROC_SBE_REGISTERS</id>
+      <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
+      <target>CHIP_IN_ERROR</target>
+    </collectRegisterFfdc>
+    <callout>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>CHIP_IN_ERROR</target>
+    </deconfigure>
+    <gard>
+      <target>CHIP_IN_ERROR</target>
+    </gard>
+  </hwpError>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_EXTRACT_SBE_RC_INTERNAL_ERROR_SBE</rc>
+    <description>
+      Procedure: proc_extract_sbe_rc
+      SBE engine encountered an internal error
+    </description>
+    <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
+    <ffdc>GROUP_PARITY_ERROR_0_4</ffdc>
+    <ffdc>SCAN_DATA_CRC_ERROR</ffdc>
+    <ffdc>SOFT_ERR_STATUS</ffdc>
+    <collectRegisterFfdc>
+      <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
+      <id>REG_FFDC_PROC_SBE_REGISTERS</id>
+      <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
+      <target>CHIP_IN_ERROR</target>
+    </collectRegisterFfdc>
+    <callout>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>CHIP_IN_ERROR</target>
+    </deconfigure>
+    <gard>
+      <target>CHIP_IN_ERROR</target>
+    </gard>
+  </hwpError>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_EXTRACT_SBE_RC_INTERNAL_ERROR_SLW</rc>
+    <description>
+      Procedure: proc_extract_sbe_rc
+      SLW engine encountered an internal error
+    </description>
+    <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
+    <ffdc>GROUP_PARITY_ERROR_0_4</ffdc>
+    <ffdc>SCAN_DATA_CRC_ERROR</ffdc>
     <collectRegisterFfdc>
       <id>REG_FFDC_PROC_SLW_REGISTERS</id>
       <target>CHIP_IN_ERROR</target>
     </collectRegisterFfdc>
+    <callout>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>CHIP_IN_ERROR</target>
+    </deconfigure>
     <gard>
       <target>CHIP_IN_ERROR</target>
     </gard>
   </hwpError>
   <!-- *********************************************************************** -->
   <hwpError>
-    <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SBE</rc>
+    <rc>RC_PROC_EXTRACT_SBE_RC_SCOM_ERROR_SBE</rc>
     <description>
       Procedure: proc_extract_sbe_rc
-      The SBE stop address isn't in a memory we know how to read
+      SBE engine encountered a SCOM error
     </description>
-    <ffdc>SBE_ADDRESS</ffdc>
+    <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
+    <ffdc>SCOM_ADDRESS</ffdc>
+    <ffdc>PIB_ERROR_CODE</ffdc>
+    <ffdc>PIB_DATA_READ_PARITY_ERROR</ffdc>
+    <ffdc>SOFT_ERR_STATUS</ffdc>
     <collectRegisterFfdc>
       <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
       <id>REG_FFDC_PROC_SBE_REGISTERS</id>
+      <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
       <target>CHIP_IN_ERROR</target>
     </collectRegisterFfdc>
     <callout>
       <target>CHIP_IN_ERROR</target>
       <priority>HIGH</priority>
     </callout>
+    <deconfigure>
+      <target>CHIP_IN_ERROR</target>
+    </deconfigure>
+    <gard>
+      <target>CHIP_IN_ERROR</target>
+    </gard>
+  </hwpError>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_EXTRACT_SBE_RC_SCOM_ERROR_SLW</rc>
+    <description>
+      Procedure: proc_extract_sbe_rc
+      SLW engine encountered a SCOM error
+    </description>
+    <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
+    <ffdc>SCOM_ADDRESS</ffdc>
+    <ffdc>PIB_ERROR_CODE</ffdc>
+    <ffdc>PIB_DATA_READ_PARITY_ERROR</ffdc>
+    <collectRegisterFfdc>
+      <id>REG_FFDC_PROC_SLW_REGISTERS</id>
+      <target>CHIP_IN_ERROR</target>
+    </collectRegisterFfdc>
     <callout>
-      <procedure>CODE</procedure>
-      <priority>LOW</priority>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
     </callout>
     <deconfigure>
       <target>CHIP_IN_ERROR</target>
     </deconfigure>
+    <gard>
+      <target>CHIP_IN_ERROR</target>
+    </gard>
   </hwpError>
   <!-- *********************************************************************** -->
   <hwpError>
-    <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SLW</rc>
+    <rc>RC_PROC_EXTRACT_SBE_RC_OCI_ERROR_SLW</rc>
     <description>
       Procedure: proc_extract_sbe_rc
-      The SLW stop address isn't in a memory we know how to read
+      SLW engine encountered error on OCI interface
     </description>
-    <ffdc>SBE_ADDRESS</ffdc>
+    <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
+    <ffdc>OCI_ERROR_CODE</ffdc>
+    <ffdc>OCI_DATA_READ_PARITY_ERROR</ffdc>
     <collectRegisterFfdc>
       <id>REG_FFDC_PROC_SLW_REGISTERS</id>
       <target>CHIP_IN_ERROR</target>
@@ -222,120 +485,354 @@
       <target>CHIP_IN_ERROR</target>
       <priority>HIGH</priority>
     </callout>
+    <deconfigure>
+      <target>CHIP_IN_ERROR</target>
+    </deconfigure>
+    <gard>
+      <target>CHIP_IN_ERROR</target>
+    </gard>
+  </hwpError>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_EXTRACT_SBE_RC_I2C_ERROR_SBE</rc>
+    <description>
+      Procedure: proc_extract_sbe_rc
+      SBE engine encountered a I2C interface/setup error
+    </description>
+    <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
+    <ffdc>I2C_BAD_STATUS_0_3</ffdc>
+    <ffdc>FI2C_HANG</ffdc>
+    <ffdc>SOFT_ERR_STATUS</ffdc>
+    <collectRegisterFfdc>
+      <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
+      <id>REG_FFDC_PROC_SBE_REGISTERS</id>
+      <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
+      <target>CHIP_IN_ERROR</target>
+    </collectRegisterFfdc>
     <callout>
-      <procedure>CODE</procedure>
-      <priority>LOW</priority>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
     </callout>
+    <deconfigure>
+      <target>CHIP_IN_ERROR</target>
+    </deconfigure>
+    <gard>
+      <target>CHIP_IN_ERROR</target>
+    </gard>
   </hwpError>
   <!-- *********************************************************************** -->
   <hwpError>
-    <rc>RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG</rc>
+    <rc>RC_PROC_EXTRACT_SBE_RC_I2C_ERROR_SLW</rc>
     <description>
       Procedure: proc_extract_sbe_rc
-      Extract RC from address subroutine tried to return SUCCESS, which isn't allowed
+      SLW engine encountered a I2C interface/setup error
     </description>
-    <ffdc>SBE_ADDRESS</ffdc>
+    <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
+    <ffdc>I2C_BAD_STATUS_0_3</ffdc>
+    <ffdc>FI2C_HANG</ffdc>
+    <collectRegisterFfdc>
+      <id>REG_FFDC_PROC_SLW_REGISTERS</id>
+      <target>CHIP_IN_ERROR</target>
+    </collectRegisterFfdc>
+    <callout>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>CHIP_IN_ERROR</target>
+    </deconfigure>
+    <gard>
+      <target>CHIP_IN_ERROR</target>
+    </gard>
+  </hwpError>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_EXTRACT_SBE_RC_INSTRUCTION_ERROR_SBE</rc>
+    <description>
+      Procedure: proc_extract_sbe_rc
+      SBE engine encountered an instruction fetch/decode/execution error
+    </description>
+    <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
+    <ffdc>INSTRUCTION_PARITY_ERROR</ffdc>
+    <ffdc>INVALID_INSTRUCTION_NON_ROTATE</ffdc>
+    <ffdc>PC_OVERFLOW_UNDERFLOW</ffdc>
+    <ffdc>PC_STACK_ERROR</ffdc>
+    <ffdc>INSTRUCTION_FETCH_ERROR</ffdc>
+    <ffdc>INVALID_OPERAND</ffdc>
+    <ffdc>I2C_ENGINE_MISS</ffdc>
+    <ffdc>INVALID_START_VECTOR</ffdc>
+    <ffdc>INVALID_INSTRUCTION_ROTATE</ffdc>
+    <ffdc>SOFT_ERR_STATUS</ffdc>
     <collectRegisterFfdc>
       <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
       <id>REG_FFDC_PROC_SBE_REGISTERS</id>
+      <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
       <target>CHIP_IN_ERROR</target>
     </collectRegisterFfdc>
     <callout>
       <target>CHIP_IN_ERROR</target>
       <priority>HIGH</priority>
     </callout>
+    <deconfigure>
+      <target>CHIP_IN_ERROR</target>
+    </deconfigure>
+    <gard>
+      <target>CHIP_IN_ERROR</target>
+    </gard>
+  </hwpError>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_EXTRACT_SBE_RC_INSTRUCTION_ERROR_SLW</rc>
+    <description>
+      Procedure: proc_extract_sbe_rc
+      SLW engine encountered an instruction fetch/decode/execution error
+    </description>
+    <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
+    <ffdc>INSTRUCTION_PARITY_ERROR</ffdc>
+    <ffdc>INVALID_INSTRUCTION_NON_ROTATE</ffdc>
+    <ffdc>PC_OVERFLOW_UNDERFLOW</ffdc>
+    <ffdc>PC_STACK_ERROR</ffdc>
+    <ffdc>INSTRUCTION_FETCH_ERROR</ffdc>
+    <ffdc>INVALID_OPERAND</ffdc>
+    <ffdc>I2C_ENGINE_MISS</ffdc>
+    <ffdc>INVALID_START_VECTOR</ffdc>
+    <ffdc>INVALID_INSTRUCTION_ROTATE</ffdc>
+    <collectRegisterFfdc>
+      <id>REG_FFDC_PROC_SLW_REGISTERS</id>
+      <target>CHIP_IN_ERROR</target>
+    </collectRegisterFfdc>
     <callout>
-      <procedure>CODE</procedure>
-      <priority>LOW</priority>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>CHIP_IN_ERROR</target>
+    </deconfigure>
+    <gard>
+      <target>CHIP_IN_ERROR</target>
+    </gard>
+  </hwpError>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_EXTRACT_SBE_RC_BAD_CHIP_TYPE_SBE</rc>
+    <description>
+      Procedure: proc_extract_sbe_rc
+      SBE execution of OTPROM code failed chip type (Murano/Venice) check
+    </description>
+    <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
+    <collectRegisterFfdc>
+      <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
+      <id>REG_FFDC_PROC_SBE_REGISTERS</id>
+      <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
+      <id>REG_FFDC_PROC_FIRST_OTPROM_INSTRUCTIONS</id>
+      <target>CHIP_IN_ERROR</target>
+    </collectRegisterFfdc>
+    <callout>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
     </callout>
     <deconfigure>
       <target>CHIP_IN_ERROR</target>
     </deconfigure>
+    <gard>
+      <target>CHIP_IN_ERROR</target>
+    </gard>
   </hwpError>
   <!-- *********************************************************************** -->
   <hwpError>
-    <rc>RC_PROC_EXTRACT_SBE_RC_GENERIC_SBE_HW_ERROR</rc>
+    <rc>RC_PROC_EXTRACT_SBE_RC_SEEPROM_MAGIC_NUMBER_MISMATCH_SBE</rc>
     <description>
       Procedure: proc_extract_sbe_rc
-      An error bit is set in the SBE debug registers.
+      SBE execution of OTPROM code failed SEEPROM magic number check
     </description>
+    <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
     <collectRegisterFfdc>
       <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
       <id>REG_FFDC_PROC_SBE_REGISTERS</id>
+      <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
+      <id>REG_FFDC_PROC_FIRST_OTPROM_INSTRUCTIONS</id>
       <target>CHIP_IN_ERROR</target>
     </collectRegisterFfdc>
+    <callout>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
     <deconfigure>
       <target>CHIP_IN_ERROR</target>
     </deconfigure>
+    <gard>
+      <target>CHIP_IN_ERROR</target>
+    </gard>
   </hwpError>
   <!-- *********************************************************************** -->
   <hwpError>
-    <rc>RC_PROC_EXTRACT_SBE_RC_GENERIC_SLW_HW_ERROR</rc>
+    <rc>RC_PROC_EXTRACT_SBE_RC_BRANCH_TO_SEEPROM_FAIL_SBE</rc>
     <description>
       Procedure: proc_extract_sbe_rc
-      An error bit is set in the SLW debug registers.
+      SBE execution of OTPROM code failed to branch to SEEPROM
     </description>
+    <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
     <collectRegisterFfdc>
       <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
-      <id>REG_FFDC_PROC_SLW_REGISTERS</id>
+      <id>REG_FFDC_PROC_SBE_REGISTERS</id>
+      <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
+      <id>REG_FFDC_PROC_FIRST_OTPROM_INSTRUCTIONS</id>
       <target>CHIP_IN_ERROR</target>
     </collectRegisterFfdc>
+    <callout>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>CHIP_IN_ERROR</target>
+    </deconfigure>
     <gard>
       <target>CHIP_IN_ERROR</target>
     </gard>
   </hwpError>
   <!-- *********************************************************************** -->
   <hwpError>
-    <rc>RC_PROC_EXTRACT_SBE_RC_CODE_BUG</rc>
+    <rc>RC_PROC_EXTRACT_SBE_RC_UNEXPECTED_OTPROM_HALT_SBE</rc>
     <description>
       Procedure: proc_extract_sbe_rc
-      SBE rc extract code tried to return SUCCESS, which isn't allowed
+      SBE execution of OTPROM code halted at an unexpected location
     </description>
+    <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
     <collectRegisterFfdc>
       <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
       <id>REG_FFDC_PROC_SBE_REGISTERS</id>
+      <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
+      <id>REG_FFDC_PROC_FIRST_OTPROM_INSTRUCTIONS</id>
       <target>CHIP_IN_ERROR</target>
     </collectRegisterFfdc>
     <callout>
-      <procedure>CODE</procedure>
-      <priority>LOW</priority>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
     </callout>
     <deconfigure>
       <target>CHIP_IN_ERROR</target>
     </deconfigure>
+    <gard>
+      <target>CHIP_IN_ERROR</target>
+    </gard>
   </hwpError>
   <!-- *********************************************************************** -->
   <hwpError>
-    <rc>RC_PROC_EXTRACT_SBE_RC_SBE_NEVER_STARTED</rc>
+    <rc>RC_PROC_EXTRACT_SBE_RC_NEVER_STARTED_SBE</rc>
     <description>
       Procedure: proc_extract_sbe_rc
       Procedure was called when no error bits were set and PC is all zeros. SBE
       was probably never started.
     </description>
+    <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
     <collectRegisterFfdc>
       <id>REG_FFDC_PROC_CFAM_REGISTERS</id>
+      <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
       <id>REG_FFDC_PROC_SBE_REGISTERS</id>
+      <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
       <id>REG_FFDC_PROC_FIRST_OTPROM_INSTRUCTIONS</id>
       <target>CHIP_IN_ERROR</target>
     </collectRegisterFfdc>
+    <callout>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>LOW</priority>
+    </callout>
     <deconfigure>
       <target>CHIP_IN_ERROR</target>
     </deconfigure>
+    <gard>
+      <target>CHIP_IN_ERROR</target>
+    </gard>
   </hwpError>
   <!-- *********************************************************************** -->
   <hwpError>
-    <rc>RC_PROC_EXTRACT_SBE_RC_SLW_NEVER_STARTED</rc>
+    <rc>RC_PROC_EXTRACT_SBE_RC_NEVER_STARTED_SLW</rc>
     <description>
       Procedure: proc_extract_sbe_rc
       Procedure was called when no error bits were set and PC is all zeros. SLW
       was probably never started.
     </description>
+    <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
     <collectRegisterFfdc>
       <id>REG_FFDC_PROC_SLW_REGISTERS</id>
       <target>CHIP_IN_ERROR</target>
     </collectRegisterFfdc>
+    <callout>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>LOW</priority>
+    </callout>
+    <deconfigure>
+      <target>CHIP_IN_ERROR</target>
+    </deconfigure>
     <gard>
       <target>CHIP_IN_ERROR</target>
     </gard>
   </hwpError>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_SBE</rc>
+    <description>
+      Procedure: proc_extract_sbe_rc
+      ECCB indicates correctable ECC error threshold from I2C/PNOR was exceeded during SBE execution
+      Reload/update of SEEPROM/PNOR required
+    </description>
+    <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>SOFT_ERR_STATUS</ffdc>
+    <ffdc>I2C_ECCB_STATUS</ffdc>
+    <ffdc>PNOR_ECCB_STATUS</ffdc>
+    <collectRegisterFfdc>
+      <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
+      <id>REG_FFDC_PROC_SBE_REGISTERS</id>
+      <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
+      <target>CHIP_IN_ERROR</target>
+    </collectRegisterFfdc>
+    <callout>
+      <target>CHIP_IN_ERROR</target>
+      <priority>LOW</priority>
+    </callout>
+  </hwpError>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_EXTRACT_SBE_RC_CODE_BUG_SBE</rc>
+    <description>
+      Procedure: proc_extract_sbe_rc
+      SBE reported attention, but procedure attempted to return SUCCESS
+    </description>
+    <ffdc>CHIP_IN_ERROR</ffdc>
+    <ffdc>PC</ffdc>
+    <collectRegisterFfdc>
+      <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
+      <id>REG_FFDC_PROC_SBE_REGISTERS</id>
+      <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
+      <target>CHIP_IN_ERROR</target>
+    </collectRegisterFfdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>LOW</priority>
+    </callout>
+    <deconfigure>
+      <target>CHIP_IN_ERROR</target>
+    </deconfigure>
+  </hwpError>
+  <!-- *********************************************************************** -->
 </hwpErrors>
+
+