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author | Thi Tran <thi@us.ibm.com> | 2014-03-22 09:34:07 -0500 |
---|---|---|
committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2014-03-24 08:56:02 -0500 |
commit | 78e08bb7f3f0ba62edcba7efc8e0d5aa2d694bd6 (patch) | |
tree | 35d56cc4743c8229b8b70317742014b83c224837 /src/usr/hwpf | |
parent | c1b2c3d4d0030b063b06cc553c016351ce096cc3 (diff) | |
download | talos-hostboot-78e08bb7f3f0ba62edcba7efc8e0d5aa2d694bd6.tar.gz talos-hostboot-78e08bb7f3f0ba62edcba7efc8e0d5aa2d694bd6.zip |
INITPROC: Hostboot SW252649 proc_extract_sbe_rc updates
Change-Id: I02068439c473c78eb7b0b7f04bd2ef703d8ae695
CQ:SW252649
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9812
Tested-by: Jenkins Server
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf')
5 files changed, 1328 insertions, 579 deletions
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_control.C b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_control.C index 7383526e2..6d103cb03 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_control.C +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_control.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_pfet_control.C,v 1.12 2014/02/06 21:58:40 stillgs Exp $ +// $Id: p8_pfet_control.C,v 1.14 2014/03/13 20:48:21 stillgs Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pfet_control.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -35,25 +35,6 @@ /// High-level procedure flow: /// \verbatim /// -/** - Check for valid parms - Check if PMGP0(0) has the PM function enabled. If not, enable it. - - - - - - - - - - - - - - - */ -/// /// Procedure Prereq: /// - System clocks are running /// \endverbatim @@ -86,9 +67,9 @@ /// 46:49 - not relevant /// 50:53 - eco_vcs_pfet_state (50: Idle; 51: Increment; 52: Decrement; 53: Wait) /// 54:57 - not relevant - - - +/// +/// buildfapiprcd -e "../../xml/error_info/p8_pfet_errors.xml" -C p8_pm_utils.C p8_pfet_control.C +/// //------------------------------------------------------------------------------ @@ -154,6 +135,7 @@ fapi::ReturnCode p8_pfet_off_override( const fapi::Target& i_target, pfet_dom_t i_domain); fapi::ReturnCode p8_pfet_poll(const fapi::Target& i_target, + uint8_t i_ex_number, uint64_t i_address, pfet_dom_t i_domain); @@ -174,7 +156,7 @@ fapi::ReturnCode p8_pfet_ivrm_fsm_fix(const fapi::Target& i_target, /// \param[in] i_target Chip target /// \param[in] i_ex_number EX number /// \param[in] i_domain Domain: BOTH, ECO, CORE -/// \param[in] i_op Operation: VON, VOFF, NONE +/// \param[in] i_op Operation: VON, VOFF, VOFF_OVERRIDE /// /// \retval FAPI_RC_SUCCESS if something good happens, /// \retval BAD_RETURN_CODE otherwise @@ -190,7 +172,7 @@ p8_pfet_control( const fapi::Target& i_target, ecmdDataBufferBase data(64); ecmdDataBufferBase pmgp0(64); ecmdDataBufferBase gp3(64); - uint64_t address; + uint64_t address = 0; bool restore_pmgp0 = false; bool restore_gp3 = false; @@ -204,27 +186,27 @@ p8_pfet_control( const fapi::Target& i_target, do { - + uint8_t ipl_mode = 0; l_rc = FAPI_ATTR_GET(ATTR_IS_MPIPL, NULL, ipl_mode); if (!l_rc.ok()) { FAPI_ERR("fapiGetAttribute of ATTR_IS_MPIPL rc = 0x%x", (uint32_t)l_rc); break; - } - FAPI_INF("IPL mode = %s", ipl_mode ? "MPIPL" : "NORMAL"); - - l_rc = p8_pm_pcbs_fsm_trace (i_target, i_ex_number, + } + FAPI_INF("IPL mode = %s", ipl_mode ? "MPIPL" : "NORMAL"); + + l_rc = p8_pm_pcbs_fsm_trace (i_target, i_ex_number, "start of p8_pfet_control"); if (!l_rc.ok()) { break; } - + // Check for valid operation parameter - if ((i_op != VON) && (i_op != VOFF) && (i_op != VOFF_OVERRIDE) && (i_op != NONE)) + if ((i_op != VON) && (i_op != VOFF) && (i_op != VOFF_OVERRIDE)) { FAPI_ERR("\tInvalid operation parm 0x%x", i_op); - const uint64_t& EX = i_ex_number; - const uint64_t& DOMAIN = i_domain; - const uint64_t& OPERATION = i_op; + const uint8_t & EX = i_ex_number; + const pfet_dom_t & DOMAIN = i_domain; + const pfet_force_t & OPERATION = i_op; FAPI_SET_HWP_ERROR(l_rc, RC_PMPROC_PFETLIB_BAD_OP); break; } @@ -233,8 +215,8 @@ p8_pfet_control( const fapi::Target& i_target, if ((i_domain != CORE) && (i_domain != ECO) && (i_domain != BOTH)) { FAPI_ERR("\tInvalid domain parm 0x%x", i_domain); - const uint64_t& EX = i_ex_number; - const uint64_t& DOMAIN = i_domain; + const uint8_t & EX = i_ex_number; + const pfet_dom_t & DOMAIN = i_domain; FAPI_SET_HWP_ERROR(l_rc, RC_PMPROC_PFETLIB_BAD_DOMAIN); break; } @@ -275,7 +257,7 @@ p8_pfet_control( const fapi::Target& i_target, break; } - l_rc = p8_pm_pcbs_fsm_trace (i_target, i_ex_number, + l_rc = p8_pm_pcbs_fsm_trace (i_target, i_ex_number, "after of PM enablement"); if (!l_rc.ok()) { break; } @@ -417,25 +399,6 @@ p8_pfet_control( const fapi::Target& i_target, break; } - // --- Align f and f/2 (done only to mimic proc_sbe_chiplet_init.S) -// address = EX_GP0_AND_0x10000004 + (0x01000000 * i_ex_number); -// e_rc |= data.flushTo1(); -// e_rc |= data.clearBit(62); // Edge delayed -// -// if (e_rc) -// { -// FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", e_rc); -// l_rc.setEcmdError(e_rc); -// break; -// } -// -// l_rc=fapiPutScom( i_target, address, data ); -// if(!l_rc.ok()) -// { -// FAPI_ERR("PutScom error 0x%08llX", address); -// break; -// } - FAPI_DBG("\tSetting DPLL, PERV THOLD and Perv ECO Fence in PMGP0"); address = EX_PMGP0_OR_0x100F0102 + (0x01000000 * i_ex_number); e_rc |= data.flushTo0(); @@ -495,8 +458,8 @@ p8_pfet_control( const fapi::Target& i_target, FAPI_ERR("PutScom error 0x%08llX", address); break; } - - l_rc = p8_pm_pcbs_fsm_trace (i_target, i_ex_number, + + l_rc = p8_pm_pcbs_fsm_trace (i_target, i_ex_number, "after of GP3(0) handling"); if (!l_rc.ok()) { break; } } @@ -518,8 +481,8 @@ p8_pfet_control( const fapi::Target& i_target, FAPI_ERR("GetScom error 0x%08llX", address); break; } - - l_rc = p8_pm_pcbs_fsm_trace (i_target, i_ex_number, + + l_rc = p8_pm_pcbs_fsm_trace (i_target, i_ex_number, "before transition choice"); if (!l_rc.ok()) { break; } @@ -540,7 +503,7 @@ p8_pfet_control( const fapi::Target& i_target, if(!l_rc.ok()) { FAPI_ERR("\tPFET turn off of %s domains failed", - pfet_dom_names[i_domain]); + pfet_dom_names[i_domain]); break; } } @@ -554,23 +517,12 @@ p8_pfet_control( const fapi::Target& i_target, pfet_dom_names[i_domain]); break; } - - l_rc = p8_pm_pcbs_fsm_trace (i_target, i_ex_number, + + l_rc = p8_pm_pcbs_fsm_trace (i_target, i_ex_number, "after VON handling"); if (!l_rc.ok()) { break; } - - } - // Error - else - { - FAPI_ERR("\tUnreachable core op point 0x%x", i_op); - const uint64_t& EX = i_ex_number; - const uint64_t& DOMAIN = i_domain; - const uint64_t& OPERATION = i_op; - FAPI_SET_HWP_ERROR(l_rc, RC_PMPROC_PFETLIB_CODE_FAULT); - break; - } + } // Restore GP3 except for reinit_endp as this will force power on if (restore_gp3) @@ -648,7 +600,7 @@ p8_pfet_on( const fapi::Target& i_target, b_eco = true; } - uint8_t chipHasPFETPoweroffBug = 0; + uint8_t chipHasPFETPoweroffBug = 0; l_rc = FAPI_ATTR_GET(ATTR_CHIP_EC_PFET_POWEROFF_BUG, &i_target, chipHasPFETPoweroffBug); @@ -692,7 +644,7 @@ p8_pfet_on( const fapi::Target& i_target, FAPI_DBG("\tEnabling turn on of Core VDD"); e_rc |= data.clearBit(CORE_OVERRIDE_STATE, CORE_OVERRIDE_LENGTH); e_rc |= data.clearBit(CORE_FORCE_STATE, CORE_FORCE_LENGTH); - e_rc |= data.insert((uint32_t)VON, CORE_FORCE_STATE, CORE_FORCE_LENGTH, 30); + e_rc |= data.insert((uint32_t)VON, CORE_FORCE_STATE, CORE_FORCE_LENGTH, 30); } if (b_eco) @@ -723,11 +675,10 @@ p8_pfet_on( const fapi::Target& i_target, } // Poll for completion - l_rc=p8_pfet_poll(i_target, address, i_domain); + l_rc=p8_pfet_poll(i_target, i_ex_number, address, i_domain); if(!l_rc.ok()) { FAPI_ERR("PFET poll timeout turning on VCS"); - // l_rc is set timeout xml based code in p8_pfet_poll break; } @@ -798,11 +749,10 @@ p8_pfet_on( const fapi::Target& i_target, } // Poll for completion - l_rc=p8_pfet_poll(i_target, address, i_domain); + l_rc=p8_pfet_poll(i_target, i_ex_number, address, i_domain); if(!l_rc.ok()) { FAPI_ERR("PFET poll timeout turning on VDD"); - // l_rc is set timeout xml based code in p8_pfet_poll break; } @@ -848,7 +798,7 @@ p8_pfet_off( const fapi::Target& i_target, uint64_t address; bool b_core = false; bool b_eco = false; - + uint8_t core_vret_voff_value; uint8_t eco_vret_voff_value; @@ -862,8 +812,8 @@ p8_pfet_off( const fapi::Target& i_target, { b_eco = true; } - - uint8_t chipHasPFETPoweroffBug = 0; + + uint8_t chipHasPFETPoweroffBug = 0; l_rc = FAPI_ATTR_GET(ATTR_CHIP_EC_PFET_POWEROFF_BUG, &i_target, chipHasPFETPoweroffBug); @@ -926,11 +876,11 @@ p8_pfet_off( const fapi::Target& i_target, data.getDoubleWord(0)); - // As we need to turn the PFETs off, ensure the stage pointers to the + // As we need to turn the PFETs off, ensure the stage pointers to the // OFF value are in place (and not assumed). core_vret_voff_value = 0xBB; eco_vret_voff_value = 0xBB; - + // ------------------------------------------------------------- FAPI_DBG("\tSetting Core Voff Settings"); e_rc |= data.insertFromRight(core_vret_voff_value, 0, 8); @@ -967,11 +917,41 @@ p8_pfet_off( const fapi::Target& i_target, break; } + // Ensure that the chiplet is electrically fenced before shutting down + // the power + FAPI_INF("Force EX electrical fence ON before turning off power"); + e_rc |= data.flushTo0(); + e_rc |= data.setBit(27); + if (e_rc) + { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", e_rc); + l_rc.setEcmdError(e_rc); + break; + } + + address = EX_GP3_OR_0x100F0014 + (0x01000000 * i_ex_number); + l_rc=fapiPutScom( i_target, address, data); + if(!l_rc.ok()) + { + FAPI_ERR("PutScom error 0x%08llX", address); + break; + } + + address = EX_GP3_0x100F0012 + (0x01000000 * i_ex_number); + l_rc=fapiGetScom( i_target, address, data); + if(!l_rc.ok()) + { + FAPI_ERR("GetScom error 0x%08llX", address); + break; + } + FAPI_DBG("\tEX_GP3_0x%08llX with electrical fence set 0x%16llX", + address, + data.getDoubleWord(0)); // VDD --------------------- FAPI_INF("Turning off VDD"); - + address = EX_PFET_CTL_REG_0x100F0106 + (0x01000000 * i_ex_number); l_rc=fapiGetScom( i_target, address, data ); if(!l_rc.ok()) @@ -1019,18 +999,16 @@ p8_pfet_off( const fapi::Target& i_target, } // Poll for completion - l_rc=p8_pfet_poll(i_target, address, i_domain); + l_rc=p8_pfet_poll(i_target, i_ex_number, address, i_domain); if(!l_rc.ok()) { FAPI_ERR("PFET poll timeout turning off VDD"); - // l_rc is set timeout xml based code in p8_pfet_poll break; } FAPI_DBG("Put the controls back to a Nop state"); e_rc |= data.clearBit(CORE_FORCE_STATE, CORE_FORCE_LENGTH); e_rc |= data.clearBit(ECO_FORCE_STATE, ECO_FORCE_LENGTH); -// e_rc |= data.insert((uint32_t)NONE, CORE_FORCE_STATE, CORE_FORCE_LENGTH, 30); if (e_rc) { FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", e_rc); @@ -1104,18 +1082,16 @@ p8_pfet_off( const fapi::Target& i_target, } // Poll for completion - l_rc=p8_pfet_poll(i_target, address, i_domain); + l_rc=p8_pfet_poll(i_target, i_ex_number, address, i_domain); if(!l_rc.ok()) { FAPI_ERR("PFET poll timeout turning on VCS"); - // l_rc is set timeout xml based code in p8_pfet_poll break; } FAPI_DBG("\tPut the controls back to a Nop state"); e_rc |= data.clearBit(CORE_FORCE_STATE, CORE_FORCE_LENGTH); e_rc |= data.clearBit(ECO_FORCE_STATE, ECO_FORCE_LENGTH); - // e_rc |= data.insert((uint32_t)NONE, ECO_FORCE_STATE, ECO_FORCE_LENGTH, 30); if (e_rc) { FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", e_rc); @@ -1178,7 +1154,7 @@ p8_pfet_off_override( const fapi::Target& i_target, b_eco = true; } - uint8_t chipHasPFETPoweroffBug = 0; + uint8_t chipHasPFETPoweroffBug = 0; l_rc = FAPI_ATTR_GET(ATTR_CHIP_EC_PFET_POWEROFF_BUG, &i_target, chipHasPFETPoweroffBug); @@ -1302,10 +1278,6 @@ p8_pfet_off_override( const fapi::Target& i_target, { FAPI_DBG("\tClearing Core VDD regulation finger %d", core_regulation_finger); e_rc |= data.clearBit(core_regulation_finger); - -// FAPI_DBG("\tSetting the select value to indicate OFF for ECO VDD"); -// e_rc |= data.setBit(5); -// e_rc |= data.insert((uint32_t)0xB, CORE_OVERRIDE_SEL, CORE_OVERRIDE_SEL_LENGTH, 28); } if (e_rc) @@ -1315,25 +1287,10 @@ p8_pfet_off_override( const fapi::Target& i_target, break; } -// FAPI_DBG("\tEX_PFET_CTL_REG_0x%08llX after 0x%16llX", -// address, -// data.getDoubleWord(0)); -// -// l_rc=fapiPutScom( i_target, address, data ); -// if(!l_rc.ok()) -// { -// FAPI_ERR("PutScom error 0x%08llX", address); -// break; -// } -// if (b_eco) { FAPI_DBG("\tClearing ECO regulation VDD finger %d", eco_regulation_finger); e_rc |= data.clearBit(eco_regulation_finger); - -// FAPI_DBG("\tSetting the select value to indicate OFF for ECO VDD"); -// e_rc |= data.setBit(7); -// e_rc |= data.insert((uint32_t)0xB, ECO_OVERRIDE_SEL, ECO_OVERRIDE_SEL_LENGTH, 28); } if (e_rc) @@ -1407,10 +1364,6 @@ p8_pfet_off_override( const fapi::Target& i_target, { FAPI_DBG("\tClearing Core VCS regulation finger %d", core_regulation_finger); e_rc |= data.clearBit(core_regulation_finger); - -// FAPI_DBG("\tSetting the select value to indicate OFF for ECO VCS"); -// e_rc |= data.setBit(5); -// e_rc |= data.insert((uint32_t)0xB, CORE_OVERRIDE_SEL, CORE_OVERRIDE_SEL_LENGTH, 28); } if (e_rc) @@ -1420,25 +1373,10 @@ p8_pfet_off_override( const fapi::Target& i_target, break; } -// FAPI_DBG("\tEX_PFET_CTL_REG_0x%08llX after 0x%16llX", -// address, -// data.getDoubleWord(0)); -// -// l_rc=fapiPutScom( i_target, address, data ); -// if(!l_rc.ok()) -// { -// FAPI_ERR("PutScom error 0x%08llX", address); -// break; -// } - if (b_eco) { FAPI_DBG("\tClearing ECO regulation VCS finger %d", eco_regulation_finger); e_rc |= data.clearBit(eco_regulation_finger); - -// FAPI_DBG("\tSetting the select value to indicate OFF for ECO VCS"); -// e_rc |= data.setBit(7); -// e_rc |= data.insert((uint32_t)0xB, ECO_OVERRIDE_SEL, ECO_OVERRIDE_SEL_LENGTH, 28); } if (e_rc) @@ -1486,12 +1424,13 @@ p8_pfet_off_override( const fapi::Target& i_target, /// \retval RC_PROCPM_PFET_TIMEOUT otherwise fapi::ReturnCode p8_pfet_poll( const fapi::Target& i_target, + uint8_t i_ex_number, uint64_t i_address, pfet_dom_t i_domain) { fapi::ReturnCode l_rc; ecmdDataBufferBase data(64); - uint32_t i; + uint32_t i = 0; bool b_core_idle = false; bool b_eco_idle = false; char core_state_buffer[32]; @@ -1505,15 +1444,6 @@ p8_pfet_poll( const fapi::Target& i_target, FAPI_DBG("\tPoll for FSM to go back to idle"); for (i=0; i<=PFET_MAX_IDLE_POLLS; i++) { - - // Delay between polls - l_rc=fapiDelay( PFET_POLL_WAIT, PFET_POLL_WAIT_SIM ); - if(!l_rc.ok()) - { - FAPI_ERR("fapiDelay error"); - break; - } - l_rc=fapiGetScom(i_target, i_address, data ); if(!l_rc.ok()) { @@ -1538,8 +1468,10 @@ p8_pfet_poll( const fapi::Target& i_target, } } - // Exit the polling loop if both are idle - if (b_core_idle && b_eco_idle) + // Exit the polling loop if selected are idle + if ( ((i_domain == BOTH) && b_core_idle && b_eco_idle) || + ((i_domain == CORE) && b_core_idle) || + ((i_domain == ECO) && b_eco_idle) ) { FAPI_DBG("\tPoll complete"); @@ -1566,31 +1498,42 @@ p8_pfet_poll( const fapi::Target& i_target, } FAPI_DBG("\tCore State: %s; ECO State: %s", core_state_buffer, eco_state_buffer); - break; } + // Delay between polls + l_rc=fapiDelay( PFET_POLL_WAIT, PFET_POLL_WAIT_SIM ); + if(!l_rc.ok()) + { + FAPI_ERR("fapiDelay error"); + break; + } + } + if (l_rc) + { + // Error in for loop + break; } - // If both rails are not idle, error out - if (!(b_core_idle && b_eco_idle)) + + if (i >= PFET_MAX_IDLE_POLLS) { + // Poll timeout FAPI_ERR("\tERROR: Polling timeout "); const uint64_t& ADDRESS = i_address; const uint64_t& PFETCONTROLVALUE = data.getDoubleWord(0); const uint64_t& DOMAIN = i_domain; + const fapi::Target & PROC_CHIP_IN_ERROR = i_target; + const uint8_t & EX_NUMBER_IN_ERROR = i_ex_number; FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFETLIB_TIMEOUT); break; } - - - } while(0); return l_rc; } //------------------------------------------------------------------------------ -/// pfet_read_state_delay +/// p8_pfet_read_state /// /// \param[in] i_target Chip target /// \param[in] i_address Address to poll for PFET State @@ -1676,6 +1619,7 @@ p8_pfet_ivrm_fsm_fix(const fapi::Target& i_target, ecmdDataBufferBase pmgp0(64); const uint32_t PM_DISABLE_BIT = 0; + const uint32_t PFET_WORKAROUND_MARK_PMGP0_BIT = 47; ecmdDataBufferBase pcbspm_mode(64); const uint32_t TIMER_MODE_BIT = 7; @@ -1696,16 +1640,16 @@ p8_pfet_ivrm_fsm_fix(const fapi::Target& i_target, ecmdDataBufferBase core_voff_vret(64); ecmdDataBufferBase eco_voff_vret(64); - - - + + + FAPI_INF("Beginning FET work-around for IVRM FSM"); do { - // --------------------------------------------------------------------- - + // --------------------------------------------------------------------- + // Determine if Pstates have been previously enabled. If so, the // work-around was previously run and cannot be run again. address = EX_PCBSPM_MODE_REG_0x100F0156 + 0x01000000*i_ex_number; @@ -1721,8 +1665,55 @@ p8_pfet_ivrm_fsm_fix(const fapi::Target& i_target, { FAPI_INF("Skipping PFET work-around as Pstate have already been enabled"); break; - } - + } + + // Adding another layer of protection. + // Set PMGP0(47) [a spare bit in chips that have this bug] + // to indicated that this work-around has already been run + // to avoid contaminating the PState mechanism in the event + // that it was not first disabled. + + address = EX_PMGP0_0x100F0100 + (0x01000000 * i_ex_number); + l_rc=fapiGetScom( i_target, address, data ); + if(!l_rc.ok()) + { + FAPI_ERR("GetScom error 0x%08llX", address); + break; + } + if (data.isBitSet(PFET_WORKAROUND_MARK_PMGP0_BIT)) + { + FAPI_INF("Skipping PFET work-around as iVRM/FFET work-around has previously run on %s EX:%d", + i_target.toEcmdString(), + i_ex_number); + break; + + } + else + { + e_rc |= data.flushTo0(); + e_rc |= data.setBit(PFET_WORKAROUND_MARK_PMGP0_BIT); + if (e_rc) + { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", e_rc); + l_rc.setEcmdError(e_rc); + break; + } + + address = EX_PMGP0_OR_0x100F0102 + (0x01000000 * i_ex_number); + l_rc=fapiPutScom( i_target, address, data ); + if(!l_rc.ok()) + { + FAPI_ERR("PutScom error 0x%08llX", address); + break; + } + + FAPI_INF("Setting flag that PFET work-around cannot be run again on %s EX:%d", + i_target.toEcmdString(), + i_ex_number); + // This can set the PMGP0 snitch bit (PMErr(12)). It is cleared, + // though, in p8_pfet_init.C (the caller) + } + address = EX_GP3_0x100F0012 + 0x01000000*i_ex_number; // Save the setting for later restoration @@ -1766,9 +1757,9 @@ p8_pfet_ivrm_fsm_fix(const fapi::Target& i_target, FAPI_ERR("PutScom error 0x%08llX", address); break; } - + // ---------------------- - // Read back for debug + // Read back for debug address = EX_GP3_0x100F0012 + 0x01000000*i_ex_number; l_rc=fapiGetScom( i_target, address, data ); if(!l_rc.ok()) @@ -1777,7 +1768,7 @@ p8_pfet_ivrm_fsm_fix(const fapi::Target& i_target, break; } FAPI_DBG("\tGP3 value: 0x%016llX", data.getDoubleWord(0)); - + // ---------------------- FAPI_INF("Set Slave Winkle fence"); e_rc |= data.flushTo0(); @@ -1788,7 +1779,7 @@ p8_pfet_ivrm_fsm_fix(const fapi::Target& i_target, l_rc.setEcmdError(e_rc); break; } - + // Set the bit address = EX_PMGP0_OR_0x100F0102 + 0x01000000*i_ex_number; l_rc=fapiPutScom( i_target, address, data ); @@ -1799,7 +1790,7 @@ p8_pfet_ivrm_fsm_fix(const fapi::Target& i_target, } // ---------------------- - // Read back for debug + // Read back for debug address = EX_PMGP0_0x100F0100 + 0x01000000*i_ex_number; l_rc=fapiGetScom( i_target, address, data ); if(!l_rc.ok()) @@ -1808,7 +1799,7 @@ p8_pfet_ivrm_fsm_fix(const fapi::Target& i_target, break; } FAPI_DBG("\tPMGP0 value: 0x%016llX", data.getDoubleWord(0)); - + FAPI_INF("Temporarily enable the chiplet"); e_rc |= data.flushTo0(); e_rc |= data.setBit(0); @@ -1827,7 +1818,7 @@ p8_pfet_ivrm_fsm_fix(const fapi::Target& i_target, FAPI_ERR("PutScom error 0x%08llX", address); break; } - + // ---------------------- // Read back for debug address = EX_GP3_OR_0x100F0014 + 0x01000000*i_ex_number; @@ -1838,7 +1829,7 @@ p8_pfet_ivrm_fsm_fix(const fapi::Target& i_target, break; } FAPI_DBG("\tGP3 value: 0x%016llX", data.getDoubleWord(0)); - + address = EX_PMGP0_0x100F0100 + 0x01000000*i_ex_number; l_rc=fapiGetScom( i_target, address, data ); if(!l_rc.ok()) @@ -1847,7 +1838,7 @@ p8_pfet_ivrm_fsm_fix(const fapi::Target& i_target, break; } FAPI_DBG("\tPMGP0 value: 0x%016llX", data.getDoubleWord(0)); - // ---------------------- + // ---------------------- } // --------------------------------------------------------------------- @@ -2177,11 +2168,10 @@ p8_pfet_ivrm_fsm_fix(const fapi::Target& i_target, break; } - e_rc |= fapiDelay(10000, 1000); - if (e_rc) + l_rc = fapiDelay(10000, 1000); + if (l_rc) { - FAPI_ERR("Error (0x%x) from fapiDelay", e_rc); - l_rc.setEcmdError(e_rc); + FAPI_ERR("Error from fapiDelay"); break; } @@ -2191,11 +2181,9 @@ p8_pfet_ivrm_fsm_fix(const fapi::Target& i_target, if (i >= BABYSTEPPER_WINKLE_TIMEOUT) { - FAPI_DBG("\tBaby Stepper Timeout %d", i_ex_number); - //const uint64_t& EX = i_ex_number; - //FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFETLIB_BABYSTEPPER_TIMEOUT); - //break; - + // This is a workaround for early chip EC levels, just trace and do + // not return error + FAPI_ERR("\tBaby Stepper Timeout %d", i_ex_number); } // --------------------------------------------------------------------- @@ -2235,14 +2223,15 @@ p8_pfet_ivrm_fsm_fix(const fapi::Target& i_target, i++; + // No delay needed, hardware reacton should be nearly immediate and + // this is a workaround for early chip EC levels + } while (data.isBitSet(GOTO_WAKEUP_BIT) && i < BABYSTEPPER_WAKEUP_TIMEOUT); if (i >= BABYSTEPPER_WAKEUP_TIMEOUT) { - FAPI_DBG("\tBaby Stepper Timeout on Wakeup %d", i_ex_number); - //const uint64_t& EX = i_ex_number; - //FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFETLIB_BABYSTEPPER_WAKEUP_TIMEOUT); - //break; - + // This is a workaround for early chip EC levels, just trace and do + // not return error + FAPI_ERR("\tBaby Stepper Timeout on Wakeup %d", i_ex_number); } @@ -2379,4 +2368,3 @@ p8_pfet_ivrm_fsm_fix(const fapi::Target& i_target, } } //end extern - diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_errors.xml b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_errors.xml index 5bc6eafe8..397939d20 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_errors.xml +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- COPYRIGHT International Business Machines Corp. 2013,2014 --> <!-- --> <!-- p1 --> <!-- --> @@ -20,7 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: p8_pfet_errors.xml,v 1.4 2013/05/23 18:44:19 stillgs Exp $ --> +<!-- $Id: p8_pfet_errors.xml,v 1.5 2014/02/25 04:07:23 stillgs Exp $ --> <!-- Error definitions for p8_pfet_init and p8_pfet_lib procedures --> <hwpErrors> <!-- *********************************************************************** --> @@ -29,6 +29,10 @@ <description>Invalid domain value passed to p8_pfet_control.</description> <ffdc>EX</ffdc> <ffdc>DOMAIN</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- *********************************************************************** --> <hwpError> @@ -37,6 +41,10 @@ <ffdc>EX</ffdc> <ffdc>DOMAIN</ffdc> <ffdc>OPERATION</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- *********************************************************************** --> <hwpError> @@ -56,30 +64,35 @@ </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PMPROC_PFETLIB_CODE_FAULT</rc> - <ffdc>EX</ffdc> - <ffdc>DOMAIN</ffdc> - <ffdc>OPERATION</ffdc> - <description>Unreachable code point in p8_pfet_control.</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> <rc>RC_PROCPM_PFETLIB_TIMEOUT</rc> - <description>PFET sequencer timed out in p8_pfet_control.</description> + <description> + PFET sequencer timed out in p8_pfet_control. + Bad EX Chiplet + </description> <ffdc>ADDRESS</ffdc> <ffdc>PFETCONTROLVALUE</ffdc> <ffdc>DOMAIN</ffdc> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROCPM_PFETLIB_BABYSTEPPER_TIMEOUT</rc> - <description>IVRM babystepper timed out in p8_pfet_control.</description> - <ffdc>EX</ffdc> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROCPM_PFETLIB_BABYSTEPPER_WAKEUP_TIMEOUT</rc> - <description>IVRM babystepper timed out waking up in p8_pfet_control.</description> - <ffdc>EX</ffdc> + <callout> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_EX_CHIPLET</childType> + <childNumber>EX_NUMBER_IN_ERROR</childNumber> + </childTargets> + <priority>HIGH</priority> + </callout> + <deconfigure> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_EX_CHIPLET</childType> + <childNumber>EX_NUMBER_IN_ERROR</childNumber> + </childTargets> + </deconfigure> + <gard> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_EX_CHIPLET</childType> + <childNumber>EX_NUMBER_IN_ERROR</childNumber> + </childTargets> + </gard> </hwpError> </hwpErrors> diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C index 89dfd8d8f..86b8ffb0f 100644 --- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C +++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C @@ -21,7 +21,7 @@ /* */ /* IBM_PROLOG_END_TAG */ // -*- mode: C++; c-file-style: "linux"; -*- -// $Id: proc_extract_sbe_rc.C,v 1.12 2014/02/19 02:31:45 jmcgill Exp $ +// $Id: proc_extract_sbe_rc.C,v 1.16 2014/03/18 14:09:27 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_sbe_rc.C,v $ //------------------------------------------------------------------------------ // *| @@ -30,20 +30,19 @@ // *! *** IBM Confidential *** // *| // *! TITLE : proc_extract_sbe_rc.C -// *! DESCRIPTION : Create a return code for an SBE error +// *! DESCRIPTION : Create a return code for an SBE/SLW error // *! // *! OWNER NAME : Johannes Koesters Email: koesters@de.ibm.com // *! // *! Overview: -// *! - Check that it was a halt at magic instruction -// *! - Get the failing PC -// *! - If secure, look up PC in image pointer -// *! - If not secure, look the PC up in the SBE (SEEPROM/PIBMEM/OTPROM) -// *! - Extract the error code at that PC -// *! - Return the RC for that error -// *! -// *! Assumption: The SBE is stopped at a "invalid instruction" error -// *! and the instruction was 'halt' +// *! - Analyze error state of SBE/SLW engine +// *! - Examine SBE/SLW engine state to determine if a HW error occurred. +// *! Return RC for HW error if present +// *! - For 'halt' due to SBE/SLW code generated failure: +// *! - Determine PC at point for failure +// *! - Lookup PC in appropriate code space (SEEPROM/PIBMEM/OTPROM), +// *! extract & return RC for its associated error +// *! //------------------------------------------------------------------------------ @@ -56,25 +55,41 @@ //------------------------------------------------------------------------------ +// Structure definitions +//------------------------------------------------------------------------------ + +enum soft_error_t +{ + eNO_ERROR = 0, + eSOFT_ERR_I2CM=1, + eSOFT_ERR_PNOR=2, + eSOFT_ERR_BOTH=3 +}; + +//------------------------------------------------------------------------------ // Constant definitions //------------------------------------------------------------------------------ -//Address masks -const uint64_t SBE_ADDR_MASK = 0x0000FFFFFFFFFFFFull; -const uint64_t FOURBYTE_ALIGNMENT_MASK = 0x0000000000000003ull; -const uint64_t INTERNAL_ADDR_MASK = 0x000000007FFFFFFFull; -const uint64_t ADDR_TYPE_MASK = 0x0000FFFF80000000ull; -const uint64_t OTPROM_ADDR_TYPE = 0x0000000100000000ull; -const uint64_t PIBMEM_ADDR_TYPE = 0x0000000800000000ull; -const uint64_t SEEPROM_ADDR_TYPE = 0x0000800C80000000ull; + +// address space/alignment masks +const uint64_t SBE_ADDR_MASK = 0x0000FFFFFFFFFFFFULL; +const uint64_t FOURBYTE_ALIGNMENT_MASK = 0x0000000000000003ULL; +const uint64_t INTERNAL_ADDR_MASK = 0x000000007FFFFFFFULL; +const uint64_t ADDR_TYPE_MASK = 0x0000FFFF80000000ULL; +const uint64_t OTPROM_ADDR_TYPE = 0x0000000100000000ULL; +const uint64_t PIBMEM_ADDR_TYPE = 0x0000000800000000ULL; +const uint64_t SEEPROM_ADDR_TYPE = 0x0000800C80000000ULL; const uint32_t ALIGN_FOUR_BYTE = 0xFFFFFFFC; -//Scom register offsets + +// common SCOM register offsets for SBE/SLW engines const uint32_t STATUS_OFFSET_0x00 = 0x00000000; const uint32_t IBUF_OFFSET_0x0D = 0x0000000D; const uint32_t DEBUG0_OFFSET_0x0F = 0x0000000F; const uint32_t DEBUG1_OFFSET_0x10 = 0x00000010; -//Halt types + +// illegal instruction encoding for SW detected halt const uint32_t HALT_WITH_ERROR_INSTRUCTION = (('h' << 24) | ('a' << 16) | ('l' << 8) | ('t')); + //------------------------------------------------------------------------------ // Function definitions //------------------------------------------------------------------------------ @@ -84,485 +99,730 @@ extern "C" //------------------------------------------------------------------------------ // subroutine: -// Reads the word at the given address in SEEPROM pointer +// reads the word at the given address in SEEPROM pointer // -// parameters: i_target => Target of chip with failed SBE +// parameters: i_target => target of chip with failed SBE/SLW engine // i_pSEEPROM => pointer to a memory-mapped SEEPROM image -// i_address => The SEEPROM address to read -// o_data => A uint32_t to put the data into +// i_address => SEEPROM address to read +// i_engine => type of engine that failed (SBE/SLW) +// i_soft_err => engine soft error status, for FFDC +// o_data => return data // // returns: fapi::ReturnCode with the error, or fapi::FAPI_RC_SUCCESS //------------------------------------------------------------------------------ - fapi::ReturnCode proc_extract_sbe_rc_read_SEEPROM(const fapi::Target & i_target, - const void * i_pSEEPROM, - const uint32_t i_address, - uint32_t & o_data) - { - // return codes - fapi::ReturnCode rc; +fapi::ReturnCode proc_extract_sbe_rc_read_SEEPROM(const fapi::Target & i_target, + const void * i_pSEEPROM, + const uint32_t i_address, + const por_engine_t i_engine, + const soft_error_t i_soft_err, + uint32_t & o_data) +{ + // return codes + fapi::ReturnCode rc; - do + do + { + if (i_pSEEPROM == NULL) { - if (i_pSEEPROM==NULL) + FAPI_ERR("Need to extract SEEPROM address 0x%08X, but pointer to SEEPROM image content is NULL", i_address); + const fapi::Target & CHIP_IN_ERROR = i_target; + const uint32_t & PC = i_address; + if (i_engine == SBE) { - FAPI_ERR("Need to extract SEEPROM address 0x%08X but pointer to SEEPROM is NULL", i_address); - const fapi::Target & CHIP_IN_ERROR = i_target; - const uint32_t & ADDRESS = i_address; - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL); - break; + const soft_error_t & SOFT_ERR_STATUS = i_soft_err; + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL_SBE); + } + else + { + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL_SLW); } - uint8_t * p_errorCode = (uint8_t *)i_pSEEPROM + (i_address & ALIGN_FOUR_BYTE); + break; + } + + // copy the data out of the image pointer + uint8_t * p_errorCode = (uint8_t *)i_pSEEPROM + (i_address & ALIGN_FOUR_BYTE); + o_data = + (p_errorCode[0] << 3*8) | + (p_errorCode[1] << 2*8) | + (p_errorCode[2] << 1*8) | + (p_errorCode[3]); + } while(0); + + return rc; +} - //Copy the data out of the image pointer - o_data = - (p_errorCode[0] << 3*8) | - (p_errorCode[1] << 2*8) | - (p_errorCode[2] << 1*8) | - (p_errorCode[3]); - } while(0); - return rc; - } //------------------------------------------------------------------------------ // subroutine: // Returns the PC of the given engine // -// parameters: i_target => Target of chip with failed SBE -// i_engine => The type of engine that failed (SBE/SLW) -// o_pc => Referenece to the uint64_t containing the PC +// parameters: i_target => target of chip with failed SBE/SLW engine +// i_engine => type of engine that failed (SBE/SLW) +// i_soft_err => engine soft error status, for FFDC +// o_pc => referenee to the uint64_t containing the PC // // returns: fapi::ReturnCode with the error, or fapi::FAPI_RC_SUCCESS //------------------------------------------------------------------------------ - fapi::ReturnCode proc_extract_sbe_rc_get_pc(const fapi::Target & i_target, - por_engine_t i_engine, - uint64_t & o_pc) +fapi::ReturnCode proc_extract_sbe_rc_get_pc(const fapi::Target & i_target, + const por_engine_t i_engine, + const soft_error_t i_soft_err, + uint64_t & o_pc) +{ + // return codes + fapi::ReturnCode rc; + + // data buffer to hold register values + ecmdDataBufferBase data(64); + + do { - // return codes - fapi::ReturnCode rc; + // read PC from the Status Register + rc = fapiGetScom(i_target, i_engine + STATUS_OFFSET_0x00, data); + if (rc) + { + FAPI_ERR("Error from fapiGetScom (STATUS_REG_0x%08X)", i_engine + STATUS_OFFSET_0x00); + break; + } - // data buffer to hold register values - ecmdDataBufferBase data(64); + o_pc = (data.getDoubleWord(0) & SBE_ADDR_MASK); - do + if (o_pc & FOURBYTE_ALIGNMENT_MASK) { - ////////////////////////////////////////// - //Get the PC from the status register - ////////////////////////////////////////// - rc = fapiGetScom(i_target, i_engine + STATUS_OFFSET_0x00, data); - if (rc) + FAPI_ERR("Address isn't 4-byte aligned"); + const fapi::Target & CHIP_IN_ERROR = i_target; + const uint64_t & PC = o_pc; + if (i_engine == SBE) { - FAPI_ERR("Error reading SBE status reg (0x%08X)", i_engine + STATUS_OFFSET_0x00); - break; + const soft_error_t & SOFT_ERR_STATUS = i_soft_err; + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SBE); } - o_pc = (data.getDoubleWord(0) & SBE_ADDR_MASK); - - if (o_pc & FOURBYTE_ALIGNMENT_MASK) + else { - FAPI_ERR("Address isn't 4-byte aligned"); - const fapi::Target & CHIP_IN_ERROR = i_target; - uint64_t & SBE_ADDRESS = o_pc; - if (i_engine == SBE) - { - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SBE); - } - else - { - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SLW); - } - break; + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SLW); } - } while(0); - return rc; - } + break; + } + } while(0); + + return rc; +} + //------------------------------------------------------------------------------ // subroutine: // Returns the return code indicated by the PC of the engine // -// parameters: i_target => Target of chip with failed SBE +// parameters: i_target => target of chip with failed SBE/SLW engine // i_pSEEPROM => pointer to a memory-mapped SEEPROM image -// i_engine => The type of engine that failed (SBE/SLW) +// i_engine => type of engine that failed (SBE/SLW) +// i_soft_err => engine soft error status, for FFDC // // returns: fapi::ReturnCode with the error // This procedure will NEVER return SUCCESS //------------------------------------------------------------------------------ - fapi::ReturnCode proc_extract_sbe_rc_from_address(const fapi::Target & i_target, - const void * i_pSEEPROM, - por_engine_t i_engine) +fapi::ReturnCode proc_extract_sbe_rc_from_address(const fapi::Target & i_target, + const void * i_pSEEPROM, + const por_engine_t i_engine, + const soft_error_t i_soft_err) +{ + // return codes + fapi::ReturnCode rc; + + // data buffer to hold register values + ecmdDataBufferBase data(64); + uint64_t address_64; + + do { - // return codes - fapi::ReturnCode rc; + // read PC + rc = proc_extract_sbe_rc_get_pc(i_target, i_engine, i_soft_err, address_64); + if (rc) + { + FAPI_ERR("Error from proc_extract_sbe_rc_get_pc"); + break; + } - // data buffer to hold register values - ecmdDataBufferBase data(64); - uint64_t address_64; + // add 4 because address_64 is pointing at the halt instruction + uint32_t internal_address = (uint32_t)(address_64 & INTERNAL_ADDR_MASK) + 4; + // error code to emit + uint32_t error_code = 0; - do + if ((address_64 & ADDR_TYPE_MASK) == SEEPROM_ADDR_TYPE) { - rc = proc_extract_sbe_rc_get_pc(i_target,i_engine,address_64); + // get the error code from that location in the SEEPROM image + FAPI_INF("Extracting the error code from address " + "0x%X in the SEEPROM", internal_address); + + rc = proc_extract_sbe_rc_read_SEEPROM(i_target, i_pSEEPROM, internal_address, i_engine, i_soft_err, error_code); if (rc) { + FAPI_ERR("Error from proc_extract_sbe_rc_read_SEEPROM (address = 0x%08X)", internal_address); break; } + } + else if ((address_64 & ADDR_TYPE_MASK) == PIBMEM_ADDR_TYPE) + { + // get the error code from that location in the PIBMEM + FAPI_INF("Extracting the error code from address " + "0x%X in the PIBMEM", internal_address); - uint32_t error_code = 0; - //Add 4 because address_64 is pointing at the halt instruction - uint32_t internal_address = (uint32_t)(address_64 & INTERNAL_ADDR_MASK) + 4; - - if ((address_64 & ADDR_TYPE_MASK) == SEEPROM_ADDR_TYPE) + rc = fapiGetScom(i_target, PIBMEM0_0x00080000 + (internal_address >>3), data); + if (rc) { - ////////////////////////////////////////// - //Get the error code from that location in the SEEPROM - ////////////////////////////////////////// - FAPI_DBG("Extracting the error code from address " - "0x%X in the SEEPROM", internal_address); - - rc = proc_extract_sbe_rc_read_SEEPROM(i_target, i_pSEEPROM, internal_address, error_code); - if (rc) - { - FAPI_ERR("Error reading SEEPROM address 0x%08X", internal_address); - break; - } + FAPI_ERR("Error from fapiGetScom (PIBMEM address 0x%08X)", (uint32_t)PIBMEM0_0x00080000 + (internal_address >>3)); + break; } - else - if ((address_64 & ADDR_TYPE_MASK) == PIBMEM_ADDR_TYPE) - { - ////////////////////////////////////////// - //Get the error code from that location in the PIBMEM - ////////////////////////////////////////// - FAPI_DBG("Extracting the error code from address " - "0x%X in the PIBMEM", internal_address); - rc = fapiGetScom(i_target, PIBMEM0_0x00080000 + (internal_address >>3), data); - if (rc) - { - FAPI_ERR("Error reading PIBMEM (scom address 0x%08X)", (uint32_t)PIBMEM0_0x00080000 + (internal_address >>3)); - break; - } - error_code = data.getWord((internal_address & 0x04)?1:0); + error_code = data.getWord((internal_address & 0x04)?1:0); + } + else + { + FAPI_ERR("Address (0x%012llX) isn't in a known memory address space", address_64); + const fapi::Target & CHIP_IN_ERROR = i_target; + const uint64_t & PC = address_64; + if (i_engine == SBE) + { + const soft_error_t & SOFT_ERR_STATUS = i_soft_err; + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SBE); } else { - FAPI_ERR("Address (0x%012llX) isn't in a known memory", address_64); - const fapi::Target & CHIP_IN_ERROR = i_target; - uint64_t & SBE_ADDRESS = address_64; - if (i_engine == SBE) - { - FAPI_SET_HWP_ERROR(rc, - RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SBE); - } - else - { - FAPI_SET_HWP_ERROR(rc, - RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SLW); - } - break; + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SLW); } + break; + } - ////////////////////////////////////////// - //Look up that error code - ////////////////////////////////////////// - FAPI_ERR("SBE got error code 0x%06X", error_code); - const fapi::Target CHIP_IN_ERROR = i_target; - const fapi::Target CHIP = i_target; - FAPI_SET_SBE_ERROR(rc, error_code); - } while(0); + // look up specified error code + FAPI_ERR("SBE got error code 0x%06X", error_code); + const fapi::Target CHIP_IN_ERROR = i_target; + const fapi::Target CHIP = i_target; + FAPI_SET_SBE_ERROR(rc, error_code); + } while(0); - //Make sure the code doesn't return SUCCESS - if (rc.ok()) + //Make sure the code doesn't return SUCCESS + if (rc.ok()) + { + FAPI_ERR("proc_extract_sbe_rc_from_addr tried to return SUCCESS," + " which should be impossible. Must be a code bug."); + const fapi::Target & CHIP_IN_ERROR = i_target; + const uint64_t & PC = address_64; + if (i_engine == SBE) { - FAPI_ERR("proc_extract_sbe_rc_from_addr tried to return SUCCESS," - " which should be impossible. Must be a code bug."); - const fapi::Target & CHIP_IN_ERROR = i_target; - uint64_t & SBE_ADDRESS = address_64; - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG); + const soft_error_t & SOFT_ERR_STATUS = i_soft_err; + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG_SBE); + } + else + { + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG_SLW); } - return rc; } + return rc; +} + //------------------------------------------------------------------------------ // function: -// Return an RC indicating the SBE error +// Return an RC indicating the SBE/SLW error // -// parameters: i_target => Target of chip with failed SBE +// parameters: i_target => Target of chip with failed SBE/SLW // i_pSEEPROM => pointer to a memory-mapped SEEPROM image // i_engine => The type of engine that failed (SBE/SLW) // // returns: fapi::ReturnCode with the error // This procedure will NEVER return SUCCESS //------------------------------------------------------------------------------ - fapi::ReturnCode proc_extract_sbe_rc(const fapi::Target & i_target, - const void * i_pSEEPROM, - const por_engine_t i_engine) - { - // return codes - fapi::ReturnCode rc; +fapi::ReturnCode proc_extract_sbe_rc(const fapi::Target & i_target, + const void * i_pSEEPROM, + const por_engine_t i_engine) +{ + // return codes + fapi::ReturnCode rc; + + // data buffer to hold register values + ecmdDataBufferBase data(64); + ecmdDataBufferBase pnor_eccb_status(64); + ecmdDataBufferBase i2cm_eccb_status(64); + ecmdDataBufferBase fsi_data(32); + ecmdDataBufferBase sbe_data0(64); + ecmdDataBufferBase sbe_data1(64); + + // PC value + uint64_t pc = 0x0ULL; - // data buffer to hold register values - ecmdDataBufferBase data(64); + // SBE PNOR/SEEPROM soft error status + soft_error_t soft_err = eNO_ERROR; - FAPI_INF("Processing SBE error"); + // SBE attn status + bool sbe_reported_attn = false; - do + do + { + // check engine type + if ((i_engine != SBE) && + (i_engine != SLW)) + { + FAPI_ERR("Unknown engine type %i", i_engine); + const fapi::Target & CHIP_IN_ERROR = i_target; + const por_engine_t ENGINE = i_engine; + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNKNOWN_ENGINE); + break; + } + + FAPI_INF("Processing %s error", ((i_engine == SBE)?("SBE"):("SLW"))); + + // if analyzing SBE engine failure + // - make sure I2C master bus fence is released before proceeding + // - check ECCB engines (I2C/LPC) for UE/CE conditions (SLW does not use + // these engines, so no need to check) + if (i_engine == SBE) { - //JDS TODO - print out the istep name based on SBE_VITAL + FAPI_EXEC_HWP(rc, proc_reset_i2cm_bus_fence, i_target); + if (!rc.ok()) + { + FAPI_ERR("Error from proc_reset_i2cm_bus_fence"); + break; + } + + // check on FSI 1007 for any PIB Access Error + rc = fapiGetCfamRegister(i_target, CFAM_FSI_STATUS_0x00001007, fsi_data); + if (rc) + { + FAPI_ERR("Error from fapiGetCfamRegister (CFAM_FSI_STATUS_0x00001007)"); + break; + } - if ((i_engine != SBE) && - (i_engine != SLW)) + if (fsi_data.getNumBitsSet(17,3) != 0) { - FAPI_ERR("Unknown engine type %i", i_engine); - const por_engine_t ENGINE = i_engine; + FAPI_ERR("Error during PIB Access"); const fapi::Target & CHIP_IN_ERROR = i_target; - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNKNOWN_ENGINE); + const ecmdDataBufferBase & FSI_STATUS = fsi_data; + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_PIB_ERROR_SBE); break; } - // if analyzing SBE engine failure, make sure I2C master bus fence is - // released before proceeding - if (i_engine == SBE) + if (fsi_data.isBitSet(30)) { - FAPI_EXEC_HWP(rc, proc_reset_i2cm_bus_fence, i_target); - if (!rc.ok()) - { - FAPI_ERR("Error from proc_reset_i2cm_bus_fence"); - break; - } + FAPI_ERR("SELFBOOT_ENGINE_ATTENTION - SBE reported attention to FSI2PIB status register"); + sbe_reported_attn = true; } - //JDS TODO - split out the generic error into more granular errors? - bool generic_hw_error = false; - ////////////////////////////////////////// - // Check for SBE error bits - ////////////////////////////////////////// - rc = fapiGetScom(i_target, i_engine + DEBUG1_OFFSET_0x10, data); + // check on ECCB Error for I2C engine + rc = fapiGetScom(i_target, PORE_ECCB_STATUS_REGISTER_READ_0x000C0002, i2cm_eccb_status); if (rc) { - FAPI_ERR("Error reading SBE debug1 reg (0x%08X)", i_engine + DEBUG1_OFFSET_0x10); + FAPI_ERR("Error from fapiGetScom (PORE_ECCB_STATUS_REGISTER_READ_0x000C00002)"); break; } - if (data.isBitSet(48)) + + // check on ECCB Engine for PNOR Access + rc = fapiGetScom(i_target, LPC_STATUS_0x000B0002, pnor_eccb_status); + if (rc) { - FAPI_ERR("OCI_DATA_READ_P_ERR - Parity error in read data from OCI"); - generic_hw_error=true; + FAPI_ERR("Error from fapiGetScom (LPC_STATUS_0x000B0002)"); + break; } - if (data.isBitSet(52)) + + // determine if either engine has reached threshold of > 128 CEs + if (i2cm_eccb_status.isBitSet(57)) { - FAPI_ERR("BAD_PAR - bad instruction parity"); - generic_hw_error=true; + soft_err = eSOFT_ERR_I2CM; } - if (data.isBitSet(53)) + + if (pnor_eccb_status.isBitSet(57)) { - ////////////////////////////////////////// - //Check if the SBE stopped at a code detected error - // (a 'halt' instruction, which is an invalid instruction) - ////////////////////////////////////////// - rc = fapiGetScom(i_target, i_engine + IBUF_OFFSET_0x0D, data); - if (rc) + if (soft_err == eSOFT_ERR_I2CM) { - FAPI_ERR("SBE reported an invalid instruction error, but got a scom error reading SBE instruction buffer reg (0x%08X) to determine if it was a code-detected error or not", i_engine + IBUF_OFFSET_0x0D); - break; - } - - const uint32_t instruction = data.getWord(0); - if (instruction == HALT_WITH_ERROR_INSTRUCTION) - { - rc = proc_extract_sbe_rc_from_address(i_target, i_pSEEPROM, i_engine); - break; + soft_err = eSOFT_ERR_BOTH; } else { - FAPI_ERR("BAD_INSTRUCTION - invalid instruction"); - generic_hw_error=true; + soft_err = eSOFT_ERR_PNOR; } } - if (data.isBitSet(54)) + } + + // read engine PC value + rc = proc_extract_sbe_rc_get_pc(i_target, i_engine, soft_err, pc); + if (rc) + { + FAPI_ERR("Error from proc_extract_sbe_rc_get_pc"); + break; + } + + if (i_engine == SBE) + { + // return error if either engine reports an unrecoverable ECC error + if (i2cm_eccb_status.isBitClear(41,2) && i2cm_eccb_status.isBitSet(43)) + { + FAPI_ERR("Unrecoverable ECC error on I2C Access"); + const fapi::Target & CHIP_IN_ERROR = i_target; + const uint64_t & PC = pc; + const ecmdDataBufferBase & ECCB_STATUS = i2cm_eccb_status; + const soft_error_t & SOFT_ERR_STATUS = soft_err; + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_I2C_SBE); + break; + } + + if (pnor_eccb_status.isBitClear(41,2) && pnor_eccb_status.isBitSet(43)) + { + FAPI_ERR("Unrecoverable ECC error on PNOR Access"); + const fapi::Target & CHIP_IN_ERROR = i_target; + const uint64_t & PC = pc; + const ecmdDataBufferBase & ECCB_STATUS = pnor_eccb_status; + const soft_error_t & SOFT_ERR_STATUS = soft_err; + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_PNOR_SBE); + break; + } + } // if (i_engine == SBE) + + + // read Debug1 register state, check for any HW error + rc = fapiGetScom(i_target, i_engine + DEBUG1_OFFSET_0x10, sbe_data1); + if (rc) + { + FAPI_ERR("Error from fapiGetScom (DEBUG1_REG_0x%08X)", i_engine + DEBUG1_OFFSET_0x10); + break; + } + + if (sbe_data1.isBitSet(63)) // SBE ANYERROR + { + FAPI_ERR("PIBMS_DBG_LOCK - error set"); + + // read Debug0 register state + rc = fapiGetScom(i_target, i_engine + DEBUG0_OFFSET_0x0F, sbe_data0); + if (rc) + { + FAPI_ERR("Error from fapiGetScom (DEBUG0_REG_0x%08X)", i_engine + DEBUG0_OFFSET_0x0F); + break; + } + + // print bitwise messages for error log, unique errors will be grouped/combined into callouts below + // grouping is done per guideance provided by Andreas Koenig + if (sbe_data1.isBitSet(48)) + { + FAPI_ERR("OCI_DATA_READ_P_ERR - Parity error in read data from OCI"); + } + uint8_t oci_rc = (sbe_data0.getByte(7) >> 5) & 0x7; + if (oci_rc) + { + FAPI_ERR("Last return code from OCI SBE got return code %i", oci_rc); + } + if (sbe_data1.isBitSet(52)) + { + FAPI_ERR("BAD_PAR - bad instruction parity"); + } + if (sbe_data1.isBitSet(53)) + { + FAPI_ERR("BAD_INSTRUCTION - invalid instruction"); + } + if (sbe_data1.isBitSet(54)) { FAPI_ERR("BAD_PC - PC overflow/underflow"); - generic_hw_error=true; } - if (data.isBitSet(55)) + if (sbe_data1.isBitSet(55)) { FAPI_ERR("SCAN_DATA_CRC - Scan data CRC error"); - generic_hw_error=true; } - if (data.isBitSet(56)) + if (sbe_data1.isBitSet(56)) { FAPI_ERR("PC_STACK_ERR - PC stack PUSH error or POP error"); - generic_hw_error=true; } - if (data.isBitSet(57)) + if (sbe_data1.isBitSet(57)) { - FAPI_ERR("INSTR_FETCH_ERROR - Non-zero return code or read data parity error was received when during fetch - phase"); - generic_hw_error=true; + FAPI_ERR("INSTR_FETCH_ERROR - Non-zero return code or read sbe_data1 parity error was received when during fetch - phase"); } - if (data.isBitSet(58)) + if (sbe_data1.isBitSet(58)) { FAPI_ERR("BAD_OPERAND - Invalid Instruction Operand"); - generic_hw_error=true; } - if (data.isBitSet(59)) + if (sbe_data1.isBitSet(59)) { FAPI_ERR("BAD_INSTRUCTION_PATH - Invalid Instruction Path (e.g. FI2C parameter miss)"); - generic_hw_error=true; } - if (data.isBitSet(60)) + if (sbe_data1.isBitSet(60)) { FAPI_ERR("BAD_START_VECTOR_TRIGGER - Invalid Start Vector triggered"); - generic_hw_error=true; } - if (data.isBitSet(61)) + if (sbe_data1.isBitSet(61)) { FAPI_ERR("FI2C_PROTOCOL_HANG - Fast I2C protocol hang detected - exceeded poll limit for FI2C engine"); - generic_hw_error=true; } - rc = fapiGetScom(i_target, i_engine + DEBUG0_OFFSET_0x0F, data); - if (rc) + if (sbe_data1.isBitSet(62)) { - FAPI_ERR("Error reading SBE debug0 reg (0x%08X)", i_engine + DEBUG0_OFFSET_0x0F); - break; + FAPI_ERR("ROL_INVALID - rotate invalid"); + } + + if (sbe_data0.isBitSet(32)) + { + FAPI_ERR("PIB_DATA_READ_P_ERR - Parity error in read data from PRV PIB"); } - uint8_t pcb_error = data.getByte(4) >> 4; + uint8_t pcb_error = (sbe_data0.getByte(4) >> 4) & 0x7; + uint32_t scom_address = sbe_data0.getWord(0); if (pcb_error) { - uint32_t scom_address = data.getWord(0); FAPI_ERR("SBE got PCB error %i accessing scom address 0x%08X", pcb_error, scom_address); - generic_hw_error=true; } - if (data.isBitSet(36)) + if (sbe_data0.isBitSet(36)) { FAPI_ERR("I2C_BAD_STATUS_0 - I2CM internal errors including parity errors"); - generic_hw_error=true; } - if (data.isBitSet(37)) + if (sbe_data0.isBitSet(37)) { FAPI_ERR("I2C_BAD_STATUS_1 - bad PIB response code error for ECCAX to I2CM communication"); - generic_hw_error=true; } - if (data.isBitSet(38)) + if (sbe_data0.isBitSet(38)) { FAPI_ERR("I2C_BAD_STATUS_2 - ECCAX internal errors (UCE or PIB master resets)"); - generic_hw_error=true; } - if (data.isBitSet(39)) + if (sbe_data0.isBitSet(39)) { FAPI_ERR("I2C_BAD_STATUS_3 - I2C bus issues (I2C bus busy, NACK, stop bit error)"); - generic_hw_error=true; } - if (data.isBitSet(40)) + if (sbe_data0.isBitSet(40)) { FAPI_ERR("GROUP_PARITY_ERROR_0 - parity error from debug or status or error mask or pc stack regs"); - generic_hw_error=true; } - if (data.isBitSet(41)) + if (sbe_data0.isBitSet(41)) { FAPI_ERR("GROUP_PARITY_ERROR_1 - parity error from control or exe trigger or exe t_mask or i2c param regs"); - generic_hw_error=true; } - if (data.isBitSet(42)) + if (sbe_data0.isBitSet(42)) { FAPI_ERR("GROUP_PARITY_ERROR_2 - parity error from perv/oci base addr or table base addr or memory reloc"); - generic_hw_error=true; } - if (data.isBitSet(43)) + if (sbe_data0.isBitSet(43)) { - FAPI_ERR("GROUP_PARITY_ERROR_3 - parity error from scr0 or scr1 or scr2 or data scr0 reg"); - generic_hw_error=true; + FAPI_ERR("GROUP_PARITY_ERROR_3 - parity error from scr0 or scr1 or scr2 or sbe_data0 scr0 reg"); } - if (data.isBitSet(44)) + if (sbe_data0.isBitSet(44)) { FAPI_ERR("GROUP_PARITY_ERROR_4 - parity error from ibuf regs"); - generic_hw_error=true; } - if (generic_hw_error) + + // + // Bucketize callouts based on combination of error bits + // + + // "Internal Error" bucket (Error Event 3) + if ((sbe_data0.getNumBitsSet(40,5) != 0) || sbe_data1.isBitSet(55)) { + FAPI_ERR("Internal %s Error", ((i_engine == SBE)?("SBE"):("SLW"))); const fapi::Target & CHIP_IN_ERROR = i_target; - if(i_engine == SBE) + const uint64_t & PC = pc; + const uint8_t & GROUP_PARITY_ERROR_0_4 = (sbe_data0.getByte(5) >> 3) & 0x1F; + const bool & SCAN_DATA_CRC_ERROR = sbe_data1.isBitSet(55); + if (i_engine == SBE) { - FAPI_SET_HWP_ERROR(rc,RC_PROC_EXTRACT_SBE_RC_GENERIC_SBE_HW_ERROR); - break; + const soft_error_t & SOFT_ERR_STATUS = soft_err; + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_INTERNAL_ERROR_SBE); } else { - FAPI_SET_HWP_ERROR(rc,RC_PROC_EXTRACT_SBE_RC_GENERIC_SLW_HW_ERROR); - break; + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_INTERNAL_ERROR_SLW); } + break; } - - //No error bits are set, so perhaps it was a real halt (ie. wait 0) instruction in OTPROM - uint64_t pc = 0; - rc = proc_extract_sbe_rc_get_pc(i_target, i_engine, pc); - if (rc) + // "I2C Error" bucket (Error Event 0) + if ((sbe_data0.getNumBitsSet(36,4) != 0) || (sbe_data1.isBitSet(61))) + { + FAPI_ERR("%s failed I2C Master operation", ((i_engine == SBE)?("SBE"):("SLW"))); + const fapi::Target & CHIP_IN_ERROR = i_target; + const uint64_t & PC = pc; + const uint8_t & I2C_BAD_STATUS_0_3 = sbe_data0.getHalfWord(10); + const bool & FI2C_HANG = sbe_data1.isBitSet(61); + + if (i_engine == SBE) + { + const soft_error_t & SOFT_ERR_STATUS = soft_err; + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_I2C_ERROR_SBE); + } + else + { + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_I2C_ERROR_SLW); + } + break; + } + + // "SCOM Error" bucket (Error Event 0), raise in presence of no instruction execution error + if ((sbe_data0.getNumBitsSet(32,4) != 0) && (sbe_data1.getNumBitsSet(52,9) == 0) && (sbe_data1.isBitClear(62))) { + FAPI_ERR("%s failed SCOM operation", ((i_engine == SBE)?("SBE"):("SLW"))); + const fapi::Target & CHIP_IN_ERROR = i_target; + const uint64_t & PC = pc; + const uint32_t & SCOM_ADDRESS = scom_address; + const uint8_t & PIB_ERROR_CODE = pcb_error; + const bool & PIB_DATA_READ_PARITY_ERROR = sbe_data0.isBitSet(32); + if (i_engine == SBE) + { + const soft_error_t & SOFT_ERR_STATUS = soft_err; + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SCOM_ERROR_SBE); + } + else + { + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SCOM_ERROR_SLW); + } break; } - if ((pc & ADDR_TYPE_MASK) == OTPROM_ADDR_TYPE) + // "OCI Error" bucket (Error Event 1) + if ((i_engine == SLW) && (sbe_data1.getNumBitsSet(48,4) != 0)) { - //Note: OTPROM halts are actual halt instructions, which means the - // SBE updated the PC before the halt. - // Thus we have to subtract 4 to get back to the address of the halt - uint32_t internal_address = (uint32_t)(pc & INTERNAL_ADDR_MASK) - 4; + FAPI_ERR("%s failed OCI Master operation", ((i_engine == SBE)?("SBE"):("SLW"))); + const fapi::Target & CHIP_IN_ERROR = i_target; + const uint64_t & PC = pc; + const uint8_t & OCI_ERROR_CODE = oci_rc; + const bool & OCI_DATA_READ_PARITY_ERROR = sbe_data1.isBitSet(48); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_OCI_ERROR_SLW); + break; + } - ////////////////////////////////////////// - //Map the OTPROM address to the known error at that location - //The OTPROM is write-once at mfg, so addresses should remain fixed - ////////////////////////////////////////// - FAPI_DBG("Determining the OTPROM error based on the address " - "0x%X", internal_address); + // check for the execution of an invalid instruction + // if present, check if the SBE stopped at a code detected error (instruction = 'halt') + if (sbe_data1.isBitSet(53) || sbe_data1.isBitSet(62)) + { + rc = fapiGetScom(i_target, i_engine + IBUF_OFFSET_0x0D, data); + if (rc) + { + // fail through to "Instruction Execution Error" bucket below + FAPI_ERR("Error from fapiGetScom(IBUF_REG_0x%08X)", i_engine + IBUF_OFFSET_0x0D); + FAPI_ERR("SBE reported an invalid instruction error, but unable to determine if it was a code-detected error or not"); + } + else + { + // lookup return code identifying halt from image, based on PC value + const uint32_t instruction = data.getWord(0); + if (instruction == HALT_WITH_ERROR_INSTRUCTION) + { + rc = proc_extract_sbe_rc_from_address(i_target, i_pSEEPROM, i_engine, soft_err); + break; + } + } + } + + // "Instruction Execution Error" bucket (Error Event 2) + if ((sbe_data1.getNumBitsSet(52,9) != 0) || (sbe_data1.isBitSet(62))) + { + FAPI_ERR("SBE encountered instruction execution error"); const fapi::Target & CHIP_IN_ERROR = i_target; - switch(internal_address) + const uint64_t & PC = pc; + const bool & INSTRUCTION_PARITY_ERROR = sbe_data1.isBitSet(52); + const bool & INVALID_INSTRUCTION_NON_ROTATE = sbe_data1.isBitSet(53); + const bool & PC_OVERFLOW_UNDERFLOW = sbe_data1.isBitSet(54); + // bit 55 covered by Internal Error check + const bool & PC_STACK_ERROR = sbe_data1.isBitSet(56); + const bool & INSTRUCTION_FETCH_ERROR = sbe_data1.isBitSet(57); + const bool & INVALID_OPERAND = sbe_data1.isBitSet(58); + const bool & I2C_ENGINE_MISS = sbe_data1.isBitSet(59); + const bool & INVALID_START_VECTOR = sbe_data1.isBitSet(60); + const bool & INVALID_INSTRUCTION_ROTATE = sbe_data1.isBitSet(62); + + if (i_engine == SBE) { - case (0x400fc): //Original OTPROM - case (0x40118): //Updated OTPROM + const soft_error_t & SOFT_ERR_STATUS = soft_err; + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_INSTRUCTION_ERROR_SBE); + } + else + { + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_INSTRUCTION_ERROR_SLW); + } + break; + } + } // SBE ANYERROR debug(63) + + // no error bits are set, check PC to check execution progress + // check for real halt (wait 0) instruction in OTPROM + if ((i_engine == SBE) && ((pc & ADDR_TYPE_MASK) == OTPROM_ADDR_TYPE)) + { + // Note: OTPROM halts are actual halt instructions, which means the + // SBE updated the PC before the halt. + // Thus we have to subtract 4 to get back to the address of the halt + uint32_t internal_address = (uint32_t)(pc & INTERNAL_ADDR_MASK) - 4; + + // map the OTPROM address to the known error at that location + // the OTPROM is write-once at mfg test, so addresses should remain fixed in this code + FAPI_INF("Determining the OTPROM error based on the address " + "0x%X", internal_address); + const fapi::Target & CHIP_IN_ERROR = i_target; + const uint64_t & PC = internal_address; + + switch (internal_address) + { + case (0x400fc): // original OTPROM version + case (0x40118): // updated OTPROM version FAPI_ERR("Chip not identified as Murano or Venice"); - FAPI_SET_HWP_ERROR(rc,RC_PROC_EXTRACT_SBE_RC_BAD_CHIP_TYPE); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_BAD_CHIP_TYPE_SBE); break; case (0x401c0): FAPI_ERR("SEEPROM magic number didn't match \"XIP SEPM\""); - FAPI_SET_HWP_ERROR(rc,RC_PROC_EXTRACT_SBE_RC_SEEPROM_MAGIC_NUMBER_MISMATCH); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SEEPROM_MAGIC_NUMBER_MISMATCH_SBE); break; case (0x401ec): FAPI_ERR("Branch to SEEPROM didn't happen"); - FAPI_SET_HWP_ERROR(rc,RC_PROC_EXTRACT_SBE_RC_BRANCH_TO_SEEPROM_FAIL); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_BRANCH_TO_SEEPROM_FAIL_SBE); break; default: FAPI_ERR("Halted in OTPROM, but not at an expected halt location"); - FAPI_SET_HWP_ERROR(rc,RC_PROC_EXTRACT_SBE_RC_UNEXPECTED_OTPROM_HALT); + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNEXPECTED_OTPROM_HALT_SBE); break; - } + } + break; + } + + // check to see if engine was never started + if (((pc & SBE_ADDR_MASK) == 0x0000800000000000ULL) || + ((pc & SBE_ADDR_MASK) == 0x0000000000000000ULL)) + { + FAPI_ERR("PC is all zeros, which means %s was probably never started", ((i_engine == SBE)?("SBE"):("SLW"))); + const fapi::Target & CHIP_IN_ERROR = i_target; + const uint64_t & PC = pc; + + if (i_engine == SBE) + { + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_NEVER_STARTED_SBE); break; } - else if (((pc & SBE_ADDR_MASK) == 0x0000800000000000ull) || - ((pc & SBE_ADDR_MASK) == 0x0000000000000000ull)) + else { - //PC is all zeros, which means SBE was probably never started - FAPI_ERR("PC is all zeros, which means SBE was probably never started"); - const fapi::Target & CHIP_IN_ERROR = i_target; - if(i_engine == SBE) - { - FAPI_SET_HWP_ERROR(rc,RC_PROC_EXTRACT_SBE_RC_SBE_NEVER_STARTED); - break; - } - else - { - FAPI_SET_HWP_ERROR(rc,RC_PROC_EXTRACT_SBE_RC_SLW_NEVER_STARTED); - break; - } + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_NEVER_STARTED_SLW); + break; } + } - } while(0); - - //Make sure the code doesn't return SUCCESS - if (rc.ok()) + // return soft error with lowest priority + if ((i_engine == SBE) && (soft_err != eNO_ERROR)) { - FAPI_ERR("proc_extract_sbe_rc tried to return SUCCESS," - " which should be impossible. Must be a code bug."); + if ((soft_err == eSOFT_ERR_PNOR) || (soft_err == eSOFT_ERR_BOTH)) + { + FAPI_ERR("Recoverable ECC Error on PNOR Access"); + } + if ((soft_err == eSOFT_ERR_I2CM) || (soft_err == eSOFT_ERR_BOTH)) + { + FAPI_ERR("Recoverable ECC Error on I2C Access"); + } const fapi::Target & CHIP_IN_ERROR = i_target; - FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_CODE_BUG); + const soft_error_t & SOFT_ERR_STATUS = soft_err; + const ecmdDataBufferBase & PNOR_ECCB_STATUS = pnor_eccb_status; + const ecmdDataBufferBase & I2C_ECCB_STATUS = i2cm_eccb_status; + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_SBE); + break; } - return rc; + + } while(0); + + // if SBE, make sure that the code doesn't return FAPI_RC_SUCCESS + // if the engine reported an attn to the FSI2PIB status register + if (rc.ok() && (i_engine == SBE) && (sbe_reported_attn)) + { + FAPI_ERR("SBE reported attention, but proc_extract_sbe_rc tried to return SUCCESS," + " which should be impossible. Must be a code bug."); + const fapi::Target & CHIP_IN_ERROR = i_target; + const uint64_t & PC = pc; + FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_CODE_BUG_SBE); } + return rc; +} + } // extern "C" /* Local Variables: */ diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.H b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.H index b332c6e94..009429e4b 100644 --- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.H +++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_extract_sbe_rc.H,v 1.5 2014/02/10 02:57:57 stillgs Exp $ +// $Id: proc_extract_sbe_rc.H,v 1.7 2014/03/18 14:09:28 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_sbe_rc.H,v $ //------------------------------------------------------------------------------ // *| @@ -29,8 +29,7 @@ // *! *** IBM Confidential *** // *| // *! TITLE : proc_extract_sbe_rc.H -// *! DESCRIPTION : Create a return code for an SBE error. Will NEVER return -// *! with SUCCESS. +// *! DESCRIPTION : Create a return code for an SBE/SLW error. // *! // *! OWNER NAME : Johannes Koesters Email: koesters@de.ibm.com // *! @@ -42,17 +41,12 @@ //------------------------------------------------------------------------------ // Includes //------------------------------------------------------------------------------ - #include <fapi.H> -#include "p8_scom_addresses.H" +#include <p8_scom_addresses.H> //------------------------------------------------------------------------------ // Structure definitions //------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Enum definitions -//------------------------------------------------------------------------------ enum por_engine_t { SBE = PORE_SBE_0x000E0000, SLW = PORE_SLW_0x00068000 @@ -72,14 +66,11 @@ extern "C" { /** - * @brief Create a return code based off the current SBE RC. - * - * @param[in] i_target Reference to processor target containing the SBE + * @brief Create a return code based off the current SBE/SLW RC. * + * @param[in] i_target Reference to processor target containing the SBE/SLW engine * @param[in] i_pSEEPROM Pointer to a memory-mapped SEEPROM image (or NULL) - * * @param[in] i_engine The POR engine type (SBE/SLW) - * * @return ReturnCode The error code the SBE hit, or the error hit * while trying to get the error code */ diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc_errors.xml b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc_errors.xml index a754f87ad..1700a2a29 100644 --- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc_errors.xml +++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc_errors.xml @@ -20,23 +20,61 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_extract_sbe_rc_errors.xml,v 1.8 2014/02/10 02:55:29 stillgs Exp $ --> +<!-- $Id: proc_extract_sbe_rc_errors.xml,v 1.12 2014/03/18 14:11:37 jmcgill Exp $ --> <!-- Error definitions for proc_extract_sbe_rc procedure --> <hwpErrors> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL_SBE</rc> <description> Procedure: proc_extract_sbe_rc - Can't extract an error from a NULL SEEPROM image + NULL image pointer prevented extraction of SBE error code </description> - <ffdc>ADDRESS</ffdc> <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> + <ffdc>SOFT_ERR_STATUS</ffdc> <collectRegisterFfdc> <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_MBOX_REGISTERS</id> <target>CHIP_IN_ERROR</target> </collectRegisterFfdc> + <callout> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>CHIP_IN_ERROR</target> + </deconfigure> + <gard> + <target>CHIP_IN_ERROR</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL_SLW</rc> + <description> + Procedure: proc_extract_sbe_rc + NULL image pointer prevented extraction of SLW error code + </description> + <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <callout> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> <deconfigure> <target>CHIP_IN_ERROR</target> </deconfigure> @@ -46,35 +84,76 @@ </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_BAD_CHIP_TYPE</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SBE</rc> <description> Procedure: proc_extract_sbe_rc - OTPROM code didn't recognize this chip as a Murano or Venice chip + The SBE stop address isn't properly aligned </description> <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> + <ffdc>SOFT_ERR_STATUS</ffdc> <collectRegisterFfdc> <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_MBOX_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <callout> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP_IN_ERROR</target> + </deconfigure> + <gard> + <target>CHIP_IN_ERROR</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SLW</rc> + <description> + Procedure: proc_extract_sbe_rc + The SLW stop address isn't properly aligned + </description> + <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> <target>CHIP_IN_ERROR</target> </collectRegisterFfdc> + <callout> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> + </callout> <deconfigure> <target>CHIP_IN_ERROR</target> </deconfigure> + <gard> + <target>CHIP_IN_ERROR</target> + </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_SEEPROM_MAGIC_NUMBER_MISMATCH</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SBE</rc> <description> Procedure: proc_extract_sbe_rc - The magic number read out of the SEEPROM doesn't match SBE SEPM + The SBE stop address isn't in a recognized address space </description> <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> + <ffdc>SOFT_ERR_STATUS</ffdc> <collectRegisterFfdc> <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_MBOX_REGISTERS</id> <target>CHIP_IN_ERROR</target> </collectRegisterFfdc> <callout> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> + </callout> + <callout> <procedure>CODE</procedure> <priority>LOW</priority> </callout> @@ -87,17 +166,25 @@ </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_BRANCH_TO_SEEPROM_FAIL</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SLW</rc> <description> Procedure: proc_extract_sbe_rc - The branch into the SEEPROM didn't happen + The SLW stop address isn't in a reognized address space </description> <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> <collectRegisterFfdc> - <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> <target>CHIP_IN_ERROR</target> </collectRegisterFfdc> + <callout> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> <deconfigure> <target>CHIP_IN_ERROR</target> </deconfigure> @@ -107,17 +194,55 @@ </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_UNEXPECTED_OTPROM_HALT</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG_SBE</rc> <description> Procedure: proc_extract_sbe_rc - The OTPROM code halted at an unexpected location + Extract RC from address subroutine tried to return SUCCESS for SBE, which isn't allowed </description> <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> + <ffdc>SOFT_ERR_STATUS</ffdc> <collectRegisterFfdc> <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> <id>REG_FFDC_PROC_SBE_REGISTERS</id> <target>CHIP_IN_ERROR</target> </collectRegisterFfdc> + <callout> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>CHIP_IN_ERROR</target> + </deconfigure> + <gard> + <target>CHIP_IN_ERROR</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG_SLW</rc> + <description> + Procedure: proc_extract_sbe_rc + Extract RC from address subroutine tried to return SUCCESS for SLW, which isn't allowed + </description> + <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <callout> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> <deconfigure> <target>CHIP_IN_ERROR</target> </deconfigure> @@ -147,17 +272,23 @@ </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SBE</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_PIB_ERROR_SBE</rc> <description> Procedure: proc_extract_sbe_rc - The SBE stop address isn't properly aligned + Error during PIB access for SBE </description> - <ffdc>SBE_ADDRESS</ffdc> + <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>FSI_STATUS</ffdc> <collectRegisterFfdc> <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_MBOX_REGISTERS</id> <target>CHIP_IN_ERROR</target> </collectRegisterFfdc> + <callout> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> + </callout> <deconfigure> <target>CHIP_IN_ERROR</target> </deconfigure> @@ -167,53 +298,185 @@ </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SLW</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_I2C_SBE</rc> <description> Procedure: proc_extract_sbe_rc - The SLW stop address isn't properly aligned + ECCB indicates unrecoverable ECC error from I2C during SBE execution + Reload/update of SEEPROM required + </description> + <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> + <ffdc>ECCB_STATUS</ffdc> + <ffdc>SOFT_ERR_STATUS</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_MBOX_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <callout> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP_IN_ERROR</target> + </deconfigure> + <gard> + <target>CHIP_IN_ERROR</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_PNOR_SBE</rc> + <description> + Procedure: proc_extract_sbe_rc + ECCB indicates unrecoverable ECC error from PNOR during SBE execution + Reload/Update of PNOR required </description> - <ffdc>SBE_ADDRESS</ffdc> + <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> + <ffdc>ECCB_STATUS</ffdc> + <ffdc>SOFT_ERR_STATUS</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_MBOX_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <callout> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP_IN_ERROR</target> + </deconfigure> + <gard> + <target>CHIP_IN_ERROR</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_EXTRACT_SBE_RC_INTERNAL_ERROR_SBE</rc> + <description> + Procedure: proc_extract_sbe_rc + SBE engine encountered an internal error + </description> + <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> + <ffdc>GROUP_PARITY_ERROR_0_4</ffdc> + <ffdc>SCAN_DATA_CRC_ERROR</ffdc> + <ffdc>SOFT_ERR_STATUS</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_MBOX_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <callout> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP_IN_ERROR</target> + </deconfigure> + <gard> + <target>CHIP_IN_ERROR</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_EXTRACT_SBE_RC_INTERNAL_ERROR_SLW</rc> + <description> + Procedure: proc_extract_sbe_rc + SLW engine encountered an internal error + </description> + <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> + <ffdc>GROUP_PARITY_ERROR_0_4</ffdc> + <ffdc>SCAN_DATA_CRC_ERROR</ffdc> <collectRegisterFfdc> <id>REG_FFDC_PROC_SLW_REGISTERS</id> <target>CHIP_IN_ERROR</target> </collectRegisterFfdc> + <callout> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP_IN_ERROR</target> + </deconfigure> <gard> <target>CHIP_IN_ERROR</target> </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SBE</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_SCOM_ERROR_SBE</rc> <description> Procedure: proc_extract_sbe_rc - The SBE stop address isn't in a memory we know how to read + SBE engine encountered a SCOM error </description> - <ffdc>SBE_ADDRESS</ffdc> + <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> + <ffdc>SCOM_ADDRESS</ffdc> + <ffdc>PIB_ERROR_CODE</ffdc> + <ffdc>PIB_DATA_READ_PARITY_ERROR</ffdc> + <ffdc>SOFT_ERR_STATUS</ffdc> <collectRegisterFfdc> <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_MBOX_REGISTERS</id> <target>CHIP_IN_ERROR</target> </collectRegisterFfdc> <callout> <target>CHIP_IN_ERROR</target> <priority>HIGH</priority> </callout> + <deconfigure> + <target>CHIP_IN_ERROR</target> + </deconfigure> + <gard> + <target>CHIP_IN_ERROR</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_EXTRACT_SBE_RC_SCOM_ERROR_SLW</rc> + <description> + Procedure: proc_extract_sbe_rc + SLW engine encountered a SCOM error + </description> + <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> + <ffdc>SCOM_ADDRESS</ffdc> + <ffdc>PIB_ERROR_CODE</ffdc> + <ffdc>PIB_DATA_READ_PARITY_ERROR</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> </callout> <deconfigure> <target>CHIP_IN_ERROR</target> </deconfigure> + <gard> + <target>CHIP_IN_ERROR</target> + </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SLW</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_OCI_ERROR_SLW</rc> <description> Procedure: proc_extract_sbe_rc - The SLW stop address isn't in a memory we know how to read + SLW engine encountered error on OCI interface </description> - <ffdc>SBE_ADDRESS</ffdc> + <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> + <ffdc>OCI_ERROR_CODE</ffdc> + <ffdc>OCI_DATA_READ_PARITY_ERROR</ffdc> <collectRegisterFfdc> <id>REG_FFDC_PROC_SLW_REGISTERS</id> <target>CHIP_IN_ERROR</target> @@ -222,120 +485,354 @@ <target>CHIP_IN_ERROR</target> <priority>HIGH</priority> </callout> + <deconfigure> + <target>CHIP_IN_ERROR</target> + </deconfigure> + <gard> + <target>CHIP_IN_ERROR</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_EXTRACT_SBE_RC_I2C_ERROR_SBE</rc> + <description> + Procedure: proc_extract_sbe_rc + SBE engine encountered a I2C interface/setup error + </description> + <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> + <ffdc>I2C_BAD_STATUS_0_3</ffdc> + <ffdc>FI2C_HANG</ffdc> + <ffdc>SOFT_ERR_STATUS</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_MBOX_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> </callout> + <deconfigure> + <target>CHIP_IN_ERROR</target> + </deconfigure> + <gard> + <target>CHIP_IN_ERROR</target> + </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_I2C_ERROR_SLW</rc> <description> Procedure: proc_extract_sbe_rc - Extract RC from address subroutine tried to return SUCCESS, which isn't allowed + SLW engine encountered a I2C interface/setup error </description> - <ffdc>SBE_ADDRESS</ffdc> + <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> + <ffdc>I2C_BAD_STATUS_0_3</ffdc> + <ffdc>FI2C_HANG</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <callout> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP_IN_ERROR</target> + </deconfigure> + <gard> + <target>CHIP_IN_ERROR</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_EXTRACT_SBE_RC_INSTRUCTION_ERROR_SBE</rc> + <description> + Procedure: proc_extract_sbe_rc + SBE engine encountered an instruction fetch/decode/execution error + </description> + <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> + <ffdc>INSTRUCTION_PARITY_ERROR</ffdc> + <ffdc>INVALID_INSTRUCTION_NON_ROTATE</ffdc> + <ffdc>PC_OVERFLOW_UNDERFLOW</ffdc> + <ffdc>PC_STACK_ERROR</ffdc> + <ffdc>INSTRUCTION_FETCH_ERROR</ffdc> + <ffdc>INVALID_OPERAND</ffdc> + <ffdc>I2C_ENGINE_MISS</ffdc> + <ffdc>INVALID_START_VECTOR</ffdc> + <ffdc>INVALID_INSTRUCTION_ROTATE</ffdc> + <ffdc>SOFT_ERR_STATUS</ffdc> <collectRegisterFfdc> <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_MBOX_REGISTERS</id> <target>CHIP_IN_ERROR</target> </collectRegisterFfdc> <callout> <target>CHIP_IN_ERROR</target> <priority>HIGH</priority> </callout> + <deconfigure> + <target>CHIP_IN_ERROR</target> + </deconfigure> + <gard> + <target>CHIP_IN_ERROR</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_EXTRACT_SBE_RC_INSTRUCTION_ERROR_SLW</rc> + <description> + Procedure: proc_extract_sbe_rc + SLW engine encountered an instruction fetch/decode/execution error + </description> + <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> + <ffdc>INSTRUCTION_PARITY_ERROR</ffdc> + <ffdc>INVALID_INSTRUCTION_NON_ROTATE</ffdc> + <ffdc>PC_OVERFLOW_UNDERFLOW</ffdc> + <ffdc>PC_STACK_ERROR</ffdc> + <ffdc>INSTRUCTION_FETCH_ERROR</ffdc> + <ffdc>INVALID_OPERAND</ffdc> + <ffdc>I2C_ENGINE_MISS</ffdc> + <ffdc>INVALID_START_VECTOR</ffdc> + <ffdc>INVALID_INSTRUCTION_ROTATE</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP_IN_ERROR</target> + </deconfigure> + <gard> + <target>CHIP_IN_ERROR</target> + </gard> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_EXTRACT_SBE_RC_BAD_CHIP_TYPE_SBE</rc> + <description> + Procedure: proc_extract_sbe_rc + SBE execution of OTPROM code failed chip type (Murano/Venice) check + </description> + <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_MBOX_REGISTERS</id> + <id>REG_FFDC_PROC_FIRST_OTPROM_INSTRUCTIONS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <callout> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> </callout> <deconfigure> <target>CHIP_IN_ERROR</target> </deconfigure> + <gard> + <target>CHIP_IN_ERROR</target> + </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_GENERIC_SBE_HW_ERROR</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_SEEPROM_MAGIC_NUMBER_MISMATCH_SBE</rc> <description> Procedure: proc_extract_sbe_rc - An error bit is set in the SBE debug registers. + SBE execution of OTPROM code failed SEEPROM magic number check </description> + <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> <collectRegisterFfdc> <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_MBOX_REGISTERS</id> + <id>REG_FFDC_PROC_FIRST_OTPROM_INSTRUCTIONS</id> <target>CHIP_IN_ERROR</target> </collectRegisterFfdc> + <callout> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> + </callout> <deconfigure> <target>CHIP_IN_ERROR</target> </deconfigure> + <gard> + <target>CHIP_IN_ERROR</target> + </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_GENERIC_SLW_HW_ERROR</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_BRANCH_TO_SEEPROM_FAIL_SBE</rc> <description> Procedure: proc_extract_sbe_rc - An error bit is set in the SLW debug registers. + SBE execution of OTPROM code failed to branch to SEEPROM </description> + <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> <collectRegisterFfdc> <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> - <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_MBOX_REGISTERS</id> + <id>REG_FFDC_PROC_FIRST_OTPROM_INSTRUCTIONS</id> <target>CHIP_IN_ERROR</target> </collectRegisterFfdc> + <callout> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP_IN_ERROR</target> + </deconfigure> <gard> <target>CHIP_IN_ERROR</target> </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_CODE_BUG</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_UNEXPECTED_OTPROM_HALT_SBE</rc> <description> Procedure: proc_extract_sbe_rc - SBE rc extract code tried to return SUCCESS, which isn't allowed + SBE execution of OTPROM code halted at an unexpected location </description> + <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> <collectRegisterFfdc> <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_MBOX_REGISTERS</id> + <id>REG_FFDC_PROC_FIRST_OTPROM_INSTRUCTIONS</id> <target>CHIP_IN_ERROR</target> </collectRegisterFfdc> <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> </callout> <deconfigure> <target>CHIP_IN_ERROR</target> </deconfigure> + <gard> + <target>CHIP_IN_ERROR</target> + </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_SBE_NEVER_STARTED</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_NEVER_STARTED_SBE</rc> <description> Procedure: proc_extract_sbe_rc Procedure was called when no error bits were set and PC is all zeros. SBE was probably never started. </description> + <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> <collectRegisterFfdc> <id>REG_FFDC_PROC_CFAM_REGISTERS</id> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_MBOX_REGISTERS</id> <id>REG_FFDC_PROC_FIRST_OTPROM_INSTRUCTIONS</id> <target>CHIP_IN_ERROR</target> </collectRegisterFfdc> + <callout> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> <deconfigure> <target>CHIP_IN_ERROR</target> </deconfigure> + <gard> + <target>CHIP_IN_ERROR</target> + </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_EXTRACT_SBE_RC_SLW_NEVER_STARTED</rc> + <rc>RC_PROC_EXTRACT_SBE_RC_NEVER_STARTED_SLW</rc> <description> Procedure: proc_extract_sbe_rc Procedure was called when no error bits were set and PC is all zeros. SLW was probably never started. </description> + <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> <collectRegisterFfdc> <id>REG_FFDC_PROC_SLW_REGISTERS</id> <target>CHIP_IN_ERROR</target> </collectRegisterFfdc> + <callout> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>CHIP_IN_ERROR</target> + </deconfigure> <gard> <target>CHIP_IN_ERROR</target> </gard> </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_SBE</rc> + <description> + Procedure: proc_extract_sbe_rc + ECCB indicates correctable ECC error threshold from I2C/PNOR was exceeded during SBE execution + Reload/update of SEEPROM/PNOR required + </description> + <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>SOFT_ERR_STATUS</ffdc> + <ffdc>I2C_ECCB_STATUS</ffdc> + <ffdc>PNOR_ECCB_STATUS</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_MBOX_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <callout> + <target>CHIP_IN_ERROR</target> + <priority>LOW</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_EXTRACT_SBE_RC_CODE_BUG_SBE</rc> + <description> + Procedure: proc_extract_sbe_rc + SBE reported attention, but procedure attempted to return SUCCESS + </description> + <ffdc>CHIP_IN_ERROR</ffdc> + <ffdc>PC</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_MBOX_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>CHIP_IN_ERROR</target> + </deconfigure> + </hwpError> + <!-- *********************************************************************** --> </hwpErrors> + + |