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author | Thi Tran <thi@us.ibm.com> | 2014-04-17 11:04:37 -0500 |
---|---|---|
committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2014-04-17 14:13:13 -0500 |
commit | f2ebdd59c50c32c09c9c4c557fb403417c7d7d9d (patch) | |
tree | 369b7861fcc88bb75af1e3c706189924fefa518f /src/usr/hwpf/hwp/pstates/pstates/pstate_tables.c | |
parent | 3e70c6a9efd70ff393c21bd35fdac85bc06a3cf1 (diff) | |
download | talos-hostboot-f2ebdd59c50c32c09c9c4c557fb403417c7d7d9d.tar.gz talos-hostboot-f2ebdd59c50c32c09c9c4c557fb403417c7d7d9d.zip |
SW256954: Tuleta: OCC held in reset after Pstate bias
Change-Id: I5e5d7ef5be5f6f269ea344599e8ae466272e04a3
CQ:SW256954
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/10611
Tested-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/10613
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf/hwp/pstates/pstates/pstate_tables.c')
-rwxr-xr-x | src/usr/hwpf/hwp/pstates/pstates/pstate_tables.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/usr/hwpf/hwp/pstates/pstates/pstate_tables.c b/src/usr/hwpf/hwp/pstates/pstates/pstate_tables.c index f1c899dd0..8be742714 100755 --- a/src/usr/hwpf/hwp/pstates/pstates/pstate_tables.c +++ b/src/usr/hwpf/hwp/pstates/pstates/pstate_tables.c @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: pstate_tables.c,v 1.18 2014/04/11 19:15:17 stillgs Exp $ +// $Id: pstate_tables.c,v 1.20 2014/04/16 17:56:30 cmolsen Exp $ /// \file pstate_tables.c /// \brief This file contains code used to generate Pstate tables from real or @@ -578,8 +578,9 @@ gpst_create(GlobalPstateTable *gpst, // Hardcode the vrm delay settings for GA1 // This should be set by gpst_stepping_setup() in the future. gpst->pstate_stepsize = pstate_stepsize; - gpst->vrm_stepdelay_range = 0xF; - gpst->vrm_stepdelay_value = 0xFF; + // SW256954: Updated following two values + gpst->vrm_stepdelay_range = 0x8; + gpst->vrm_stepdelay_value = 0x9; } while (0); |