diff options
| author | Thi Tran <thi@us.ibm.com> | 2013-08-15 07:47:40 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-08-19 09:07:30 -0500 |
| commit | c458b54157b6cb417db2f2cf158b7379f00b7557 (patch) | |
| tree | 8935dd7e5bca2366ec8b23758014bfa5330e6dda /src/usr/hwpf/hwp/occ | |
| parent | 6f2f3aa49961f017af6de723c28cf004ca8fbc36 (diff) | |
| download | talos-hostboot-c458b54157b6cb417db2f2cf158b7379f00b7557.tar.gz talos-hostboot-c458b54157b6cb417db2f2cf158b7379f00b7557.zip | |
NITPROC: Hostboot - Updated HWPs from defects SW213666/SW214730/SW214731
SW213666 SW214730 SW214731
Change-Id: I5301c3df79b54f50f227c0625be847bd21ca9b75
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5801
Tested-by: Jenkins Server
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf/hwp/occ')
4 files changed, 970 insertions, 643 deletions
diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.C index 239541921..c049b8b5d 100644 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_cpu_special_wakeup.C,v 1.7 2013/04/16 12:14:14 pchatnah Exp $ +// $Id: p8_cpu_special_wakeup.C,v 1.13 2013/08/02 18:59:13 stillgs Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_cpu_special_wakeup.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -79,10 +79,7 @@ #include "p8_pm.H" #include "p8_cpu_special_wakeup.H" -#include <ecmdDataBufferBase.H> -//#include <ecmdClientCapi.H> -#include <fapi.H> - +#include "p8_pcb_scom_errors.H" extern "C" { @@ -101,33 +98,32 @@ p8_cpu_special_wakeup( const fapi::Target& i_target, PROC_SPCWKUP_ENTITY i_entity ) { - fapi::ReturnCode l_rc; + fapi::ReturnCode rc; + fapi::ReturnCode oha_rc; uint32_t e_rc = 0; ecmdDataBufferBase data(64); + ecmdDataBufferBase fsi_data(64); ecmdDataBufferBase polldata(64); - //TODO RTC: 71328 - hack to indicate unused - bool __attribute__((unused)) error_flag = false; - //TODO RTC: 71328 - needs to be const - const char* PROC_SPCWKUP_ENTITY_NAMES[] = - { - "HOST", - "FSP", - "OCC", - "PHYP", - "SPW_ALL" - }; - - - - //TODO RTC: 71328 - needs to be const + + fapi::Target l_parentTarget; + uint8_t attr_chip_unit_pos = 0; + + const char* PROC_SPCWKUP_ENTITY_NAMES[] = + { + "HOST", + "FSP", + "OCC", + "PHYP", + "SPW_ALL" + }; + const char* PROC_SPCWKUP_OPS_NAMES[] = - { - "DISABLE", - "ENABLE", - "INIT" - }; - - + { + "DISABLE", + "ENABLE", + "INIT" + }; + uint32_t special_wakeup_max_polls; /// Time (binary in milliseconds) for the first poll check (running/nap @@ -136,8 +132,9 @@ p8_cpu_special_wakeup( const fapi::Target& i_target, /// Get an attribute that defines the maximum special wake-up polling /// timing (binary in milliseconds). + /// Increased timeout to 200ms - 6/10/13 - uint32_t special_wakeup_timeout = 25; + uint32_t special_wakeup_timeout = 200; /// Get an attribute that defines the special wake-up polling interval /// (binary in milliseconds). @@ -149,49 +146,70 @@ p8_cpu_special_wakeup( const fapi::Target& i_target, std::vector<fapi::Target> l_chiplets; std::vector<Target>::iterator itr; - uint64_t SP_WKUP_REG_ADDRS; + uint8_t oha_spwkup_flag = 0; + uint8_t ignore_xstop_flag = 0; //-------------------------------------------------------------------------- // Read the counts of different ENTITY (FSP,OCC,PHYP) from the Attributes //-------------------------------------------------------------------------- - uint32_t PHYP_SPWKUP_COUNT = 0; - uint32_t FSP_SPWKUP_COUNT = 0; - uint32_t OCC_SPWKUP_COUNT = 0; + uint32_t phyp_spwkup_count = 0; + uint32_t fsp_spwkup_count = 0; + uint32_t occ_spwkup_count = 0; + + uint64_t spwkup_address = 0; do { - + FAPI_INF("Executing p8_cpu_special_wakeup %s for %s ...", PROC_SPCWKUP_OPS_NAMES[i_operation], PROC_SPCWKUP_ENTITY_NAMES[i_entity]); - + // Initialize the attributes to 0. if (i_operation == SPCWKUP_INIT) { + FAPI_INF("Processing target %s", i_target.toEcmdString()); FAPI_INF("Initializing ATTR_PM_SPWUP_FSP"); - l_rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_FSP, &i_target, FSP_SPWKUP_COUNT); - if (l_rc) + rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_FSP, &i_target, fsp_spwkup_count); + if (rc) { - FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_FSP with l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_FSP with rc = 0x%x", (uint32_t)rc); + break ; } FAPI_INF("Initializing ATTR_PM_SPWUP_OCC"); - l_rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OCC, &i_target, OCC_SPWKUP_COUNT); - if (l_rc) + rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OCC, &i_target, occ_spwkup_count); + if (rc) { - FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_OCC with l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_OCC with rc = 0x%x", (uint32_t)rc); break; } FAPI_INF("Initializing ATTR_PM_SPWUP_PHYP"); - l_rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_PHYP, &i_target, PHYP_SPWKUP_COUNT); - if (l_rc) + rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_PHYP, &i_target, phyp_spwkup_count); + if (rc) { - FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_PHYP with l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_PHYP with rc = 0x%x", (uint32_t)rc); break; } + FAPI_INF("Initializing ATTR_PM_SPWUP_OHA_FLAG"); + rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OHA_FLAG, &i_target, oha_spwkup_flag); + if (rc) + { + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)rc); + break; + } + + FAPI_INF("Initializing ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG"); + rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG, &i_target, ignore_xstop_flag); + if (rc) + { + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG with rc = 0x%x", (uint32_t)rc); + break ; + } + // Leave the procedure break; } @@ -200,55 +218,43 @@ p8_cpu_special_wakeup( const fapi::Target& i_target, // Checking the ENTITY who raised this OPERATION //-------------------------------------------------------------------------- - fapi::Target l_parentTarget; - uint8_t attr_chip_unit_pos = 0; - // Get the parent chip to target the registers - l_rc = fapiGetParentChip(i_target, l_parentTarget); - if (l_rc) + rc = fapiGetParentChip(i_target, l_parentTarget); + if (rc) { break; // throw error } - // Check whether system is checkstopped - l_rc=fapiGetScom(l_parentTarget, PCBMS_INTERRUPT_TYPE_REG_0x000F001A, data); - if( data.isBitSet( 2 ) ) - { - FAPI_ERR( "This chip is xstopped, so ignoring the special wakeup request\n" ); - FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_CHKSTOP); - break; - } - // Get the core number - l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, attr_chip_unit_pos); - if (l_rc) + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, attr_chip_unit_pos); + if (rc) { - FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)rc); break; } - // CORE_NUM = attr_chip_unit_pos; + FAPI_DBG("Core number = %d", attr_chip_unit_pos); - // Read the Attributes to know the Special_wake counts form each entities . + // Read the Attributes to know the Special_wake counts from each entity // This should be different for different EX chiplets. - l_rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_FSP, &i_target, FSP_SPWKUP_COUNT); - if (l_rc) + rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_FSP, &i_target, fsp_spwkup_count); + if (rc) { - FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_FSP with l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_FSP with rc = 0x%x", (uint32_t)rc); break; } - l_rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_OCC, &i_target, OCC_SPWKUP_COUNT ); - if (l_rc) + rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_OCC, &i_target, occ_spwkup_count ); + if (rc) { - FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_FSP with l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_OCC with rc = 0x%x", (uint32_t)rc); break; } - l_rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_PHYP,&i_target , PHYP_SPWKUP_COUNT ); - if (l_rc) + rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_PHYP,&i_target , phyp_spwkup_count ); + if (rc) { - FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_FSP with l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_PHYP with rc = 0x%x", (uint32_t)rc); break; } @@ -261,23 +267,23 @@ p8_cpu_special_wakeup( const fapi::Target& i_target, // Process counts based on the calling entity if (i_entity == OCC) { - count = OCC_SPWKUP_COUNT ; + count = occ_spwkup_count ; FAPI_INF("OCC count before = %d" , count); - SP_WKUP_REG_ADDRS = PM_SPECIAL_WKUP_OCC_0x100F010C + + spwkup_address = PM_SPECIAL_WKUP_OCC_0x100F010C + (attr_chip_unit_pos * 0x01000000) ; } else if (i_entity == FSP) { - count = FSP_SPWKUP_COUNT ; + count = fsp_spwkup_count ; FAPI_INF("FSP count before = %d" , count); - SP_WKUP_REG_ADDRS = PM_SPECIAL_WKUP_FSP_0x100F010B + + spwkup_address = PM_SPECIAL_WKUP_FSP_0x100F010B + (attr_chip_unit_pos * 0x01000000); } else if (i_entity == PHYP) { - count = PHYP_SPWKUP_COUNT ; + count = phyp_spwkup_count ; FAPI_INF("PHYP count before = %d" , count); - SP_WKUP_REG_ADDRS = PM_SPECIAL_WKUP_PHYP_0x100F010D + + spwkup_address = PM_SPECIAL_WKUP_PHYP_0x100F010D + (attr_chip_unit_pos * 0x01000000); } else @@ -285,7 +291,7 @@ p8_cpu_special_wakeup( const fapi::Target& i_target, FAPI_ERR("Unknown entity passed to proc_special_wakeup. Entity %x ....", i_entity); // I_ENTITY = i_entity; PROC_SPCWKUP_ENTITY & I_ENTITY = i_entity ; - FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_SPCWKUP_CODE_BAD_ENTITY); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_SPCWKUP_CODE_BAD_ENTITY); break; } @@ -293,106 +299,313 @@ p8_cpu_special_wakeup( const fapi::Target& i_target, // Checking the type of OPERATION and process the request ///////////////////////////////////////////////////////////////////////////// - l_rc=fapiGetScom(l_parentTarget, EX_PMGP0_0x1X0F0100, data); - if(l_rc) + rc=fapiGetScom(l_parentTarget, EX_PMGP0_0x1X0F0100, data); + if(rc) { break; } if (i_operation == SPCWKUP_ENABLE) { + + // If the OHA flag is set, then any subsequent calls to the this + // procedure must return a "good" response or else an infinite + // loop results for any calling algorithm that first sets + // special wake-up, does a SCOM, and then clears special + // wake-up. + rc = FAPI_ATTR_GET( ATTR_PM_SPWUP_OHA_FLAG, + &i_target, + oha_spwkup_flag); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)rc); + break; + } + + if (oha_spwkup_flag) + { + FAPI_INF("OHA special wakeup flag is set so returning with good response to break recursion. Counts are NOT updated."); + // This is a purposeful mid-procedure return + return rc; + } + + // Determine if xstop checking should be ignored base on a caller + // set attribute. + // + // This is used during MPIPL clean-up to a core to clear FIRs that + // will eventually clear the xstop condition. However, to do so + // needs the xstop check to not keep the special wake-up operation + // from happening. + rc = FAPI_ATTR_GET( ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG, + &i_target, + ignore_xstop_flag); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG with rc = 0x%x", (uint32_t)rc); + break ; + } + + if (!ignore_xstop_flag) + { + // Check whether system is checkstopped.. + rc=fapiGetScom(l_parentTarget, PCBMS_INTERRUPT_TYPE_REG_0x000F001A, data); + if(rc) + { + break; + } + + if( data.isBitSet( 2 ) ) + { + FAPI_ERR( "This chip is xstopped, so ignoring the special wakeup request\n" ); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_CHKSTOP); + break; + } + } + else + { + FAPI_INF("Ignore checkstop flag is set so checkstop checking is NOT being performed"); + } + FAPI_INF("Setting Special Wake-up ...") ; - // FAPI_INF("Count value after the increment is %x ...", count); if (count == 0) { - GETSCOM(i_target, SP_WKUP_REG_ADDRS, data); + GETSCOM(rc, i_target, spwkup_address, data); e_rc = data.flushTo0(); e_rc |= data.setBit(0); - E_RC_CHECK(e_rc, l_rc); + E_RC_CHECK(e_rc, rc); - PUTSCOM(i_target, SP_WKUP_REG_ADDRS, data); + PUTSCOM(rc, i_target, spwkup_address, data); // poll for the set completion pollcount = 0; e_rc=data.flushTo0(); - E_RC_CHECK(e_rc, l_rc); + E_RC_CHECK(e_rc, rc); while (data.isBitClear(31) && pollcount < special_wakeup_max_polls) { - GETSCOM(l_parentTarget, EX_PMGP0_0x1X0F0100, data); - FAPI_DBG(" Loop get for PMGP0(31) to goto 1 => 0x%16llx", data.getDoubleWord(0)); - - fapiDelay(special_wakeup_poll_interval*1000, 1000000); + GETSCOM(rc, l_parentTarget, EX_PMGP0_0x1X0F0100, data); + FAPI_DBG(" Loop get for PMGP0(31) to goto 1 => 0x%016llx", data.getDoubleWord(0)); + + rc = fapiDelay(special_wakeup_poll_interval*1000, 1000000); + if (rc) + { + break; + } pollcount ++ ; + } + if (!rc.ok()) + { + break; + } + + // Workaround for HW255321 start here + // at timeout time: + // - check for existing external interrupts or malf alerts pending : PMGP0 bit52 + // AND if OHA is in the AISS-FSM-state P7_SEQ_WAIT_INT_PENDING EX_OHA_RO_STATUS_REG_0x1002000B + // If yes - then OHA hangs + // To leave this FSM state: + // - Set Bit 9 of OHA_ARCH_IDLE_STATE_REG( RESET_IDLE_STATE_SEQUENCER). EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 + // This resets the idle sequencer and force OHA into the DO_NOTHING_STATE ...should be completed in the next cycle + // + // Continue further down and check special_wakeup completion by checking bit31 of EX_PMGP0_0x1X0F0100 + // If set then is OHA awake else error + + GETSCOM(rc, l_parentTarget, EX_PMGP0_0x1X0F0100, data); + + if (data.isBitClear(31) && data.isBitSet(52) ) + { + FAPI_DBG("Timed out setting Special wakeup with regular wake-up available, the logical OR of external interrupt and malfunction alert ... "); + FAPI_DBG("Checking for Hang-Situation in AISS-FSM-State P7_SEQ_WAIT_INT_PENDING ... "); + FAPI_DBG("Special Wake-up Done NOT asserted (PMGP0(31,52)!! =>0x%016llx", data.getDoubleWord(0)); + + oha_spwkup_flag = 1; + + rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OHA_FLAG, &i_target, oha_spwkup_flag); + if (rc) + { + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)rc); + break; + } + FAPI_INF("Set OHA special wakeup flag"); + + // Check now if OHA is in the AISS-FSM-state P7_SEQ_WAIT_INT_PENDING EX_OHA_RO_STATUS_REG_0x1002000B (bit 13-19) 0b0011100 + GETSCOM(rc, i_target, EX_OHA_RO_STATUS_REG_0x1002000B, data); + + FAPI_DBG("\tCURRENT_AISS_FSM_STATE_VECTOR (OHA_RO_STATUS(13:19) => 0x%016llx", data.getDoubleWord(0)); + + if (data.isBitClear(13) && // 0 + data.isBitClear(14) && // 0 + data.isBitSet(15) && // 1 + data.isBitSet(16) && // 1 + data.isBitSet(17) && // 1 + data.isBitClear(18) && // 0 + data.isBitClear(19) ) // 0 + { + FAPI_DBG("OHA hanging in AISS-FSM-state P7_SEQ_WAIT_INT_PENDING (0b11100) (OHA_RO_STATUS_REG(13:19) => 0x%016llx", data.getDoubleWord(0)); + FAPI_DBG("Start reset of IDLE STATE SEQUENCER: Set OHA_ARCH_IDLE_STATE_REG(9)"); + + GETSCOM(rc, i_target, EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011, data); + FAPI_DBG("\tEX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 : 0x%016llx", data.getDoubleWord(0)); + + //Set RESET_IDLE_STATE_SEQUENCER ... Bit 9 of OHA_ARCH_IDLE_STATE_REG + e_rc=data.setBit(9); + E_RC_CHECK(e_rc, rc); + + PUTSCOM(rc, i_target, EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011, data); + + // This resets the idle sequencer and force OHA into the + // DO_NOTHING_STATE ... should be completed in the next + // cycle since special wakeup is still asserted, OHA should + // not leave the DO_NOTHING_STATE + + // Check again for AISS-FSM-state P7_SEQ_WAIT_INT_PENDING EX_OHA_RO_STATUS_REG_0x1002000B (bit 13-19) 0b11100 + GETSCOM(rc, i_target, EX_OHA_RO_STATUS_REG_0x1002000B, data); + FAPI_DBG("\tCURRENT_AISS_FSM_STATE_VECTOR (OHA_RO_STATUS(13:19) => 0x%016llx", data.getDoubleWord(0)); + + // We're done accessing the OHA so clear the flag + oha_spwkup_flag = 0; + rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OHA_FLAG, &i_target, oha_spwkup_flag); + if (rc) + { + FAPI_ERR("fapiSetAttribute to clear ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)rc); + // This is a purposeful mid-procedure return + return rc; + } + FAPI_INF("Cleared OHA special wakeup flag"); + } } + + // Check again if special_wakeup completed + GETSCOM(rc, l_parentTarget, EX_PMGP0_0x1X0F0100, data); + + // Workaround for HW255321 ends here + if (data.isBitClear(31)) { FAPI_ERR("Timed out in setting the CPU in Special wakeup ... "); - FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_SPCWKUP_TIMEOUT); - break; - } - GETSCOM(l_parentTarget, EX_PMGP0_0x1X0F0100, data); - FAPI_DBG(" Special Wake-up Done asserted (PMGP0(31)!! =>0x%16llx", data.getDoubleWord(0)); - GETSCOM(i_target, EX_OHA_RO_STATUS_REG_0x1002000B, data); - FAPI_DBG(" Special Wake-up complete (OHA_RO_STATUS(1)!! => 0x%16llx", data.getDoubleWord(0)); + GETSCOM(rc, l_parentTarget, EX_PMGP0_0x1X0F0100, data); + FAPI_DBG("Special Wake-up Done asserted (PMGP0(31)!! =>0x%016llx", data.getDoubleWord(0)); + const uint64_t& PMGP0 = data.getDoubleWord(0); + + // Removing per SW205177 as the following GETSCOM creates an + // infinite loop during execution on the FSP. It is not + // clear why that is so we'll address its reinstatement as + // part of the RAS review process. + + // GETSCOM(rc, i_target, EX_OHA_RO_STATUS_REG_0x1002000B, data); + // FAPI_DBG(" Special Wake-up complete (OHA_RO_STATUS(1)!! => 0x%016llx", data.getDoubleWord(0)); + // const uint64_t& OHA_RO_STATUS = data.getDoubleWord(0); - GETSCOM(l_parentTarget, SP_WKUP_REG_ADDRS , data); - FAPI_DBG(" After set of SPWKUP_REG (0x%08llx) => 0x%16llx", SP_WKUP_REG_ADDRS, data.getDoubleWord(0)); + GETSCOM(rc, l_parentTarget, spwkup_address , data); + FAPI_DBG(" After set of SPWKUP_REG (0x%08llx) => 0x%016llx", spwkup_address, data.getDoubleWord(0)); + const uint64_t& SP_WKUP_REG_ADDRESS = spwkup_address; + const uint64_t& SP_WKUP_REG_VALUE = data.getDoubleWord(0); + const uint64_t& POLLCOUNT = (uint64_t)pollcount; + const uint64_t& EX = (uint64_t)attr_chip_unit_pos; + const uint64_t& ENTITY = (uint64_t)i_entity; + PROC_SPCWKUP_OPS& I_OPERATION = i_operation ; + + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_SPCWKUP_TIMEOUT); + break; + + } + else + { + FAPI_INF("Special wakeup done is set. SUCCESS! ... "); + } } count++ ; - } else if (i_operation == SPCWKUP_DISABLE) { FAPI_INF("Clearing Special Wake-up..."); + // If the OHA flag is set, then any subsequent calls to the this + // procedure must return a "good" response or elso an infinite + // loop results for any calling algorithm that first sets + // special wake-up, does a SCOM, and then clears special + // wake-up. + + rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_OHA_FLAG, &i_target, oha_spwkup_flag); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)rc); + break; + } + + if (oha_spwkup_flag) + { + FAPI_INF("OHA special wakeup flag is set so returning with good response to break recursion. Counts are NOT updated."); + // This is a purposeful mid-procedure return + return rc; + } + + if ( count == 1 ) { - GETSCOM(l_parentTarget, SP_WKUP_REG_ADDRS , data); - FAPI_DBG(" Before clear of SPWKUP_REG (0x%08llx) => =>0x%16llx", SP_WKUP_REG_ADDRS, data.getDoubleWord(0)); + GETSCOM(rc, l_parentTarget, spwkup_address , data); + FAPI_DBG(" Before clear of SPWKUP_REG (0x%08llx) => =>0x%016llx", spwkup_address, data.getDoubleWord(0)); e_rc=data.flushTo0(); - E_RC_CHECK(e_rc, l_rc); + E_RC_CHECK(e_rc, rc); - PUTSCOM(l_parentTarget, SP_WKUP_REG_ADDRS , data); - FAPI_DBG(" After clear putscom of SPWKUP_REG (0x%08llx) => 0x%16llx", SP_WKUP_REG_ADDRS, data.getDoubleWord(0)); + PUTSCOM(rc, l_parentTarget, spwkup_address , data); + FAPI_DBG(" After clear putscom of SPWKUP_REG (0x%08llx) => 0x%016llx", spwkup_address, data.getDoubleWord(0)); // This puts an inherent delay in the propagation of the reset transition. - GETSCOM(l_parentTarget, SP_WKUP_REG_ADDRS , data); - FAPI_DBG(" After read (delay) of SPWKUP_REG (0x%08llx) 0x%16llx", SP_WKUP_REG_ADDRS, data.getDoubleWord(0)); + GETSCOM(rc, l_parentTarget, spwkup_address , data); + FAPI_DBG(" After read (delay) of SPWKUP_REG (0x%08llx) 0x%016llx", spwkup_address, data.getDoubleWord(0)); count -- ; } else if ( count > 1 ) { - FAPI_INF("Other processes having clear Special Wake-up pending. Chiplet is still in Special Wake-up state."); + FAPI_INF("Other processes have clear Special Wake-up pending. Chiplet is still in Special Wake-up state."); count -- ; } - else + else // this should never happen { - FAPI_ERR("Illegal Special wake up operation : already Disabled on this platform %x", i_entity); - FAPI_ERR (" FSP_COUNT = %d , OCC_COUNT = %d , PHYP_COUNT = %d ", FSP_SPWKUP_COUNT ,OCC_SPWKUP_COUNT ,PHYP_SPWKUP_COUNT); + FAPI_ERR("Ineffective Special wake up Disable operation as it is already disabled for this platform %x", i_entity); + FAPI_ERR (" FSP_COUNT = %d , OCC_COUNT = %d , PHYP_COUNT = %d ", fsp_spwkup_count ,occ_spwkup_count ,phyp_spwkup_count); PROC_SPCWKUP_OPS & I_OPERATION = i_operation ; - FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_SPCWKUP_CODE_BAD_OP); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_SPCWKUP_CODE_BAD_OP); break; } - GETSCOM(l_parentTarget, SP_WKUP_REG_ADDRS , data); - FAPI_DBG(" After configuring SPWKUP_REG value =>0x%16llx", data.getDoubleWord(0)); + GETSCOM(rc, l_parentTarget, spwkup_address , data); + FAPI_DBG(" After configuring SPWKUP_REG value =>0x%016llx", data.getDoubleWord(0)); + + } + else if (i_operation == SPCWKUP_FORCE_DEASSERT) + { + + GETSCOM(rc, l_parentTarget, spwkup_address , data); + FAPI_DBG(" Before clear of SPWKUP_REG (0x%08llx) => =>0x%016llx", spwkup_address, data.getDoubleWord(0)); + + e_rc=data.flushTo0(); + E_RC_CHECK(e_rc, rc); + PUTSCOM(rc, l_parentTarget, spwkup_address , data); + FAPI_DBG(" After clear putscom of SPWKUP_REG (0x%08llx) => 0x%016llx", spwkup_address, data.getDoubleWord(0)); + + // This puts an inherent delay in the propagation of the reset transition. + GETSCOM(rc, l_parentTarget, spwkup_address , data); + FAPI_DBG(" After read (delay) of SPWKUP_REG (0x%08llx) 0x%016llx", spwkup_address, data.getDoubleWord(0)); + + count = 0; } else { - FAPI_ERR("Please specify operation either ENABLE or DISABLE. Operation %x", i_operation ); + FAPI_ERR("ENABLE, DISABLE or INIT must be specified. Operation %x", i_operation ); PROC_SPCWKUP_OPS & I_OPERATION = i_operation ; - FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_SPCWKUP_CODE_BAD_OP); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_SPCWKUP_CODE_BAD_OP); break; } @@ -402,39 +615,83 @@ p8_cpu_special_wakeup( const fapi::Target& i_target, if ( i_entity == OCC ) { - OCC_SPWKUP_COUNT = count ; - l_rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OCC, &i_target, OCC_SPWKUP_COUNT ); - if (l_rc) + occ_spwkup_count = count ; + rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OCC, &i_target, occ_spwkup_count ); + if (rc) { - FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_OCC with l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_OCC with rc = 0x%x", (uint32_t)rc); break; } } else if (i_entity == FSP) { - FSP_SPWKUP_COUNT = count ; - l_rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_FSP, &i_target, FSP_SPWKUP_COUNT ); - if (l_rc) + fsp_spwkup_count = count ; + rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_FSP, &i_target, fsp_spwkup_count ); + if (rc) { - FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_FSP with l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_FSP with rc = 0x%x", (uint32_t)rc); break; } } else if (i_entity == PHYP) { - PHYP_SPWKUP_COUNT = count; - l_rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_PHYP, &i_target, PHYP_SPWKUP_COUNT ); - if (l_rc) + phyp_spwkup_count = count; + rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_PHYP, &i_target, phyp_spwkup_count ); + if (rc) { - FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_PHYP1 with l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_PHYP with rc = 0x%x", (uint32_t)rc); break; } } - FAPI_INF (" FSP_COUNT = %d , OCC_COUNT = %d , PHYP_COUNT = %d ", FSP_SPWKUP_COUNT ,OCC_SPWKUP_COUNT ,PHYP_SPWKUP_COUNT); + FAPI_INF (" FSP_COUNT = %d , OCC_COUNT = %d , PHYP_COUNT = %d ", fsp_spwkup_count ,occ_spwkup_count ,phyp_spwkup_count); } while (0); - return l_rc ; + // Clean up the OHA flag as it should not be set out of this exit (normal + // and error) path. Note: there is ia mid-procedure return above. + oha_rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_OHA_FLAG, &i_target, oha_spwkup_flag); + if (oha_rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)oha_rc); + } + else + { + if (oha_spwkup_flag) + { + oha_spwkup_flag = 0; + + oha_rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OHA_FLAG, &i_target, oha_spwkup_flag); + if (oha_rc) + { + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)oha_rc); + } + + FAPI_ERR("Clearing OHA flag attribute upon procedure exit. This is NOT expected"); + PROC_SPCWKUP_OPS& I_OPERATION = i_operation ; + const uint64_t& EX = (uint64_t)attr_chip_unit_pos; + const uint64_t& ENTITY = (uint64_t)i_entity; + const uint64_t& PHYP_SPCWKUP_COUNT = (uint64_t)phyp_spwkup_count; + const uint64_t& FSP_SPCWKUP_COUNT = (uint64_t)fsp_spwkup_count; + const uint64_t& OCC_SPCWKUP_COUNT = (uint64_t)occ_spwkup_count; + FAPI_SET_HWP_ERROR(oha_rc, RC_PROCPM_SPCWKUP_OHA_FLAG_SET_ON_EXIT); + + } + } + + // Exit with the proper return code. rc has priority over oha_rc as it indicates + // the first failure. + if (!rc.ok()) + { + return rc ; + } + else if (!oha_rc.ok()) + { + return oha_rc ; + } + else + { + return rc; + } } diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.H index 99b3686de..616ccd119 100644 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.H +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_cpu_special_wakeup.H,v 1.5 2013/04/16 12:14:35 pchatnah Exp $ +// $Id: p8_cpu_special_wakeup.H,v 1.6 2013/08/02 18:59:22 stillgs Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_cpu_special_wakeup.H,v $ //------------------------------------------------------------------------------ // *| @@ -65,7 +65,8 @@ enum PROC_SPCWKUP_OPS { SPCWKUP_DISABLE, SPCWKUP_ENABLE, - SPCWKUP_INIT + SPCWKUP_INIT, + SPCWKUP_FORCE_DEASSERT }; diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C index c9247ee01..6059dcc57 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_pcbs_init.C,v 1.18 2013/05/23 02:18:02 stillgs Exp $ +// $Id: p8_pcbs_init.C,v 1.19 2013/08/02 19:03:12 stillgs Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pcbs_init.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -185,7 +185,7 @@ /// -- PCBS_OCC_Heartbeat_Reg[8] /// /// // IVRM Setup -/// get the mrwb attribute ivrms_enabled -- If '0' Salerno, if '1' Venice +/// get the mrwb `ibute ivrms_enabled -- If '0' Salerno, if '1' Venice /// if ivrms_enabled { /// set ivrm_fsm_enable = 0 -- PCBS_iVRM_Control_Status_Reg[0] /// -- ivrm_fsm_enable have be '0' to enable bypass_b writes @@ -346,13 +346,13 @@ using namespace fapi; if(e_rc) \ { \ FAPI_ERR("Set DoubleWord failed. With rc = 0x%x", (uint32_t)e_rc); \ - l_rc.setEcmdError(e_rc); \ + rc.setEcmdError(e_rc); \ break; \ } \ FAPI_DBG("Scan0 equivalent reset of 0x%08llx to 0x%16llX", \ _mi_address, _mi_reset_value); \ - l_rc = fapiPutScom(_mi_target, _mi_address, _mi_buffer); \ - if(!l_rc.ok()) \ + rc = fapiPutScom(_mi_target, _mi_address, _mi_buffer); \ + if(!rc.ok()) \ { \ FAPI_ERR("PutScom error to address 0x%08llx", _mi_address); \ break; \ @@ -365,13 +365,13 @@ using namespace fapi; if(e_rc) \ { \ FAPI_ERR("Set Word failed. With rc = 0x%x", (uint32_t)e_rc); \ - l_rc.setEcmdError(e_rc); \ + rc.setEcmdError(e_rc); \ break; \ } \ FAPI_DBG("Scan0 equivalent reset of 0x%08llx to 0x%08X", \ _mi_address, _mi_reset_value); \ - l_rc = fapiPutScom(_mi_target, _mi_address, _mi_buffer); \ - if(!l_rc.ok()) \ + rc = fapiPutScom(_mi_target, _mi_address, _mi_buffer); \ + if(!rc.ok()) \ { \ FAPI_ERR("PutScom error to address 0x%08llx", _mi_address); \ break; \ @@ -467,7 +467,7 @@ p8_pcbs_init_scan0(const Target &i_target, uint8_t i_ex_number); fapi::ReturnCode p8_pcbs_init( const Target& i_target, uint32_t i_mode) { - fapi::ReturnCode l_rc; + fapi::ReturnCode rc; //Declare parms struct struct_pcbs_val_init_type pcbs_val_init; @@ -479,10 +479,10 @@ p8_pcbs_init( const Target& i_target, uint32_t i_mode) if ( i_mode == PM_CONFIG ) { - l_rc=p8_pcbs_init_config(i_target); - if (l_rc) + rc=p8_pcbs_init_config(i_target); + if (rc) { - FAPI_ERR("p8_pcbs_init_config failed. With l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("p8_pcbs_init_config failed. With rc = 0x%x", (uint32_t)rc); break; } @@ -490,10 +490,10 @@ p8_pcbs_init( const Target& i_target, uint32_t i_mode) else if ( i_mode == PM_INIT ) { - l_rc=p8_pcbs_init_init(i_target); - if (l_rc) + rc=p8_pcbs_init_init(i_target); + if (rc) { - FAPI_ERR("p8_pcbs_init_init failed. With l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("p8_pcbs_init_init failed. With rc = 0x%x", (uint32_t)rc); break; } } @@ -502,8 +502,9 @@ p8_pcbs_init( const Target& i_target, uint32_t i_mode) // ---------------------------------------------------------------------- // Assign default values // ---------------------------------------------------------------------- + // These are only needed to put the hardware back to a known state from + // which the OCC can start again in enabling Pstates - /// \todo CHECK: Review those defaults pcbs_val_init.MAX_PSAFE_FSM_LOOPS = 20; // PMSR poll attempts pcbs_val_init.MAX_DELAY = 1000000; // in ns; 1ms pcbs_val_init.MAX_SIM_CYCLES = 1000; @@ -517,46 +518,46 @@ p8_pcbs_init( const Target& i_target, uint32_t i_mode) pcbs_val_init.KUV = 0; // Default pcbs_val_init.ivrms_enabled = 1 ; - // l_rc = FAPI_ATTR_GET( ATTR_PM_IVRMS_ENABLED, + // rc = FAPI_ATTR_GET( ATTR_PM_IVRMS_ENABLED, // &i_target, // pcbs_val_init.ivrms_enabled); - if (l_rc) + if (rc) { - FAPI_ERR("fapiGetAttribute of ATTR_PM_IVRMS_ENABLED with rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetAttribute of ATTR_PM_IVRMS_ENABLED with rc = 0x%x", (uint32_t)rc); break; } -// l_rc = FAPI_ATTR_GET( ATTR_PM_SAFE_PSTATE, +// rc = FAPI_ATTR_GET( ATTR_PM_SAFE_PSTATE, // &i_target, // pcbs_val_init.PSAFE); - if (l_rc) + if (rc) { - FAPI_ERR("fapiGetAttribute of ATTR_PM_SAFE_PSTATE with rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetAttribute of ATTR_PM_SAFE_PSTATE with rc = 0x%x", (uint32_t)rc); break; } -// l_rc = FAPI_ATTR_GET( ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM, +// rc = FAPI_ATTR_GET( ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM, // &i_target, // pcbs_val_init.PUV_MIN); - if (l_rc) + if (rc) { - FAPI_ERR("fapiGetAttribute of ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM with rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetAttribute of ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM with rc = 0x%x", (uint32_t)rc); break; } - // l_rc = FAPI_ATTR_GET( ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM, + // rc = FAPI_ATTR_GET( ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM, // &i_target, // pcbs_val_init.PUV_MAX); - if (l_rc) + if (rc) { - FAPI_ERR("fapiGetAttribute of ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM with rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetAttribute of ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM with rc = 0x%x", (uint32_t)rc); break; } - l_rc = p8_pcbs_init_reset( i_target, pcbs_val_init); - if (l_rc) + rc = p8_pcbs_init_reset( i_target, pcbs_val_init); + if (rc) { - FAPI_ERR("p8_pcbs_init_reset failed. With l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("p8_pcbs_init_reset failed. With rc = 0x%x", (uint32_t)rc); break; } } @@ -564,12 +565,12 @@ p8_pcbs_init( const Target& i_target, uint32_t i_mode) { FAPI_ERR("Unknown mode passed to p8_pcbs_init. Mode %x ....", i_mode); const uint64_t& MODE = (uint32_t)i_mode; - FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PCBS_CODE_BAD_MODE); + FAPI_SET_HWP_ERROR(rc, RC_PROC_PCBS_CODE_BAD_MODE); } } while(0); FAPI_INF("Exiting p8_pcbs_init ..."); - return l_rc; + return rc; } @@ -586,7 +587,7 @@ p8_pcbs_init( const Target& i_target, uint32_t i_mode) fapi::ReturnCode p8_pcbs_init_config(const Target& i_target) { - fapi::ReturnCode l_rc; + fapi::ReturnCode rc; /// Function moved in p8_pfet_int.C /// FAPI_DBG("*************************************"); @@ -594,7 +595,7 @@ p8_pcbs_init_config(const Target& i_target) /// FAPI_DBG("*************************************"); /// - return l_rc; + return rc; } //end CONFIG @@ -610,29 +611,28 @@ p8_pcbs_init_config(const Target& i_target) fapi::ReturnCode p8_pcbs_init_init(const Target& i_target) { - fapi::ReturnCode l_rc; + fapi::ReturnCode rc; uint32_t e_rc; // eCmd returncode ecmdDataBufferBase data(64); // Variables std::vector<fapi::Target> l_exChiplets; - fapi::TargetState l_state = TARGET_STATE_FUNCTIONAL; - uint8_t l_functional = 0; uint8_t l_ex_number = 0; uint64_t address; + uint64_t ex_offset; FAPI_INF("p8_pcbs_init_init beginning for target %s ...", i_target.toEcmdString()); do { - l_rc = fapiGetChildChiplets(i_target, + rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_EX_CHIPLET, l_exChiplets, - l_state); - if (l_rc) + TARGET_STATE_FUNCTIONAL); + if (rc) { - FAPI_ERR("fapiGetChildChiplets with rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetChildChiplets with rc = 0x%x", (uint32_t)rc); break; } @@ -641,60 +641,42 @@ p8_pcbs_init_init(const Target& i_target) // For each chiplet in the functional list for (uint8_t c=0; c< l_exChiplets.size(); c++) { - FAPI_DBG("\tLoop Variable %d ",c); - l_rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_exChiplets[c], l_functional); - if (l_rc) + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[c], l_ex_number); + if (rc) { - FAPI_ERR("fapiGetAttribute of ATTR_FUNCTIONAL with rc = 0x%x", (uint32_t)l_rc); - break; - } - - - if (!l_functional) - { - FAPI_DBG("Core number = %d is not functional", c); - // Iterate - continue; - } - - // The ex is functional let's build the SCOM address - l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[c], l_ex_number); - if (l_rc) - { - FAPI_ERR("No functional chiplets exist"); - FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)rc); break; } FAPI_DBG("Core number = %d", l_ex_number); + ex_offset = l_ex_number * 0x01000000; + // Set DPLL Lock Replacement value (15:23) = 2 (eg bit 22 = 1) FAPI_INF ("Set DPLL Lock Replacement value of EX_DPLL_CPM_PARM_REG_0x1*0F0152 "); - address = EX_DPLL_CPM_PARM_REG_0x100F0152 + - (l_ex_number * 0x01000000); - GETSCOM(i_target, address, data); + address = EX_DPLL_CPM_PARM_REG_0x100F0152 + ex_offset; + GETSCOM(rc, i_target, address, data); e_rc = data.setBit(22); - E_RC_CHECK(e_rc, l_rc); + E_RC_CHECK(e_rc, rc); - PUTSCOM(i_target, address, data); + PUTSCOM(rc, i_target, address, data); // ****************************************************************** // - Enable DPLL Lock Replacement mode // ****************************************************************** FAPI_INF("Set DPLL Lock Replacement mode"); - address = EX_PCBSPM_MODE_REG_0x100F0156 + - (l_ex_number * 0x01000000); + address = EX_PCBSPM_MODE_REG_0x100F0156 + ex_offset; - GETSCOM(i_target, address, data ); + GETSCOM(rc, i_target, address, data ); e_rc |= data.setBit(7); - E_RC_CHECK(e_rc, l_rc); + E_RC_CHECK(e_rc, rc); - PUTSCOM(i_target, address, data ); + PUTSCOM(rc, i_target, address, data ); // ****************************************************************** // - set PCBS_PM_PMGP1_REG_1 @@ -706,10 +688,10 @@ p8_pcbs_init_init(const Target& i_target) // Clear buffer e_rc = data.flushTo0(); e_rc |= data.setBit(11); // Force OCC SPR Mode = 1 - E_RC_CHECK(e_rc, l_rc); + E_RC_CHECK(e_rc, rc); - address = EX_PMGP1_OR_0x100F0105 + (l_ex_number * 0x01000000); - PUTSCOM(i_target, address, data ); + address = EX_PMGP1_OR_0x100F0105 + ex_offset; + PUTSCOM(rc, i_target, address, data ); FAPI_INF("Forced OCC SPR Mode"); @@ -720,11 +702,10 @@ p8_pcbs_init_init(const Target& i_target) // Clear buffer e_rc = data.flushTo0(); - E_RC_CHECK(e_rc, l_rc); + E_RC_CHECK(e_rc, rc); - address = EX_PCBS_Power_Management_Control_Reg_0x100F0159 + - (l_ex_number * 0x01000000); - PUTSCOM(i_target, address, data); + address = EX_PCBS_Power_Management_Control_Reg_0x100F0159 + ex_offset; + PUTSCOM(rc, i_target, address, data); // ****************************************************************** // - Power Management Idle Control Reg @@ -733,22 +714,21 @@ p8_pcbs_init_init(const Target& i_target) // Clear buffer e_rc = data.flushTo0(); - E_RC_CHECK(e_rc, l_rc); + E_RC_CHECK(e_rc, rc); - address = EX_PCBS_Power_Management_Idle_Control_Reg_0x100F0158 + - (l_ex_number * 0x01000000); - PUTSCOM(i_target, address, data); + address = EX_PCBS_Power_Management_Idle_Control_Reg_0x100F0158 + ex_offset; + PUTSCOM(rc, i_target, address, data); FAPI_INF ("PMCR default value adjustment (Hardware flush 0) of EX_PCBS_Power_Management_Idle_Control_Reg_0x1*0F0158 " ); } //END FOR - if (!l_rc.ok() ) + if (!rc.ok() ) { break; } } while(0); - return l_rc; + return rc; } //end INIT @@ -767,7 +747,7 @@ p8_pcbs_init_init(const Target& i_target) fapi::ReturnCode p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_init) { - fapi::ReturnCode l_rc; + fapi::ReturnCode rc; uint32_t e_rc; // ecmd returncode ecmdDataBufferBase data(64); @@ -776,22 +756,56 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i // Variables std::vector<fapi::Target> l_exChiplets; - fapi::TargetState l_state = TARGET_STATE_FUNCTIONAL; - uint8_t l_functional = 0; uint8_t l_ex_number = 0; uint64_t address; - uint32_t loopcount = 0; // number of times PCBS-PMSR has been checked + uint64_t ex_offset; + + uint32_t loopcount = 0; + // PCBSPM MODE bits + const uint32_t PCBSPMMODE_ENABLE_PSTATE_MODE_BIT = 0; + const uint32_t PCBSPMMODE_ENABLE_GLOBAL_PSTATE_REQ_BIT = 2; + + // PMGP1 bits + const uint32_t PMGP1_DPLL_FREQ_OVERRIDE_ENABLE = 10; + const uint32_t PMGP1_PM_SPR_OVERRIDE_EN_BIT = 11; + const uint32_t PMGP1_FORCE_SAFE_MODE_BIT = 12; + + // PMSR bits + const uint32_t PMSR_PSAFE_MODE_ACTIVE_BIT = 33; + const uint32_t PMSR_ALL_FSMS_IN_SAFE_STATE_BIT = 36; + + // PMCR bits + const uint32_t PMSR_AUTO_OVERRIDE0_PSTATE_LIMIT_EN_BIT = 16; + const uint32_t PMSR_AUTO_OVERRIDE1_PSTATE_LIMIT_EN_BIT = 17; + + // PMICR bits + const uint32_t PMICR_NAP_PSTATE_EN_BIT = 8; + const uint32_t PMICR_SLEEP_PSTATE_EN_BIT = 24; + const uint32_t PMICR_WINKLE_PSTATE_EN_BIT = 40; + + // GP3 bits + const uint32_t GP3_RESCLK_DIS_BIT = 22; + + // PCBS OCC Heartbeat bits + const uint32_t POHR_OCC_HEARTBEAT_EN_BIT = 8; + + // PCBS OCC Heartbeat bits + const uint32_t IVRMCS_IVRM_FSM_ENABLE_BIT = 0; + const uint32_t IVRMCS_IVRM_CORE_VDD_BYPASS_B_BIT = 4; + const uint32_t IVRMCS_IVRM_CORE_VCS_BYPASS_B_BIT = 6; + const uint32_t IVRMCS_IVRM_ECO_VDD_BYPASS_B_BIT = 8; + const uint32_t IVRMCS_IVRM_ECO_VCS_BYPASS_B_BIT = 10; FAPI_INF("p8_pcbs_init_reset beginning for target %s ...", i_target.toEcmdString()); do { - l_rc = fapiGetChildChiplets(i_target, + rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_EX_CHIPLET, l_exChiplets, - l_state); - if (l_rc) + TARGET_STATE_FUNCTIONAL); + if (rc) { - FAPI_ERR("fapiGetChildChiplets with rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetChildChiplets with rc = 0x%x", (uint32_t)rc); break; } @@ -800,43 +814,17 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i // For each chiplet for (uint8_t c=0; c< l_exChiplets.size(); c++) { - FAPI_DBG("\tLoop Variable %d ",c); - l_rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_exChiplets[c], l_functional); - if (l_rc) + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[c], l_ex_number); + if (rc) { - FAPI_ERR("fapiGetAttribute of ATTR_FUNCTIONAL with rc = 0x%x", (uint32_t)l_rc); - break; - } - - if (!l_functional) - { - FAPI_DBG("Core number = %d is not functional", c); - // Iterate - continue; - } - - // The ex is functional let's build the SCOM address - l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[c], l_ex_number); - if (l_rc) - { - FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)rc); break; } FAPI_DBG("\tCore number = %d", l_ex_number); - // ****************************************************************** - // Set the regs back to scan0 state - NO... NOT HERE! - // ****************************************************************** - - l_rc = p8_pcbs_init_scan0(i_target, l_ex_number); - if (l_rc) - { - FAPI_ERR(" p8_pcbs_init_scan0 failed. With l_rc = 0x%x", (uint32_t)l_rc); - break; - } - + ex_offset = l_ex_number * 0x01000000; // ****************************************************************** // Force safe mode if Pstates are enabled. @@ -845,12 +833,11 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i // [12] force_safe_mode = 1 // ****************************************************************** - address = EX_PCBSPM_MODE_REG_0x100F0156 + - (l_ex_number * 0x01000000); - GETSCOM(i_target, address, data); + address = EX_PCBSPM_MODE_REG_0x100F0156 + ex_offset; + GETSCOM(rc, i_target, address, data); FAPI_DBG("\tPCBS_MODE_REG value 0x%16llX", data.getDoubleWord(0)); - if (data.isBitSet(0)) // Pstates enabled + if (data.isBitSet(PCBSPMMODE_ENABLE_PSTATE_MODE_BIT)) // Pstates enabled { FAPI_INF("Pstate enabled - Force safe mode"); @@ -858,14 +845,13 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i // Using Write OR to just set bit12 // Clear buffer e_rc = data.flushTo0(); - E_RC_CHECK(e_rc, l_rc); + E_RC_CHECK(e_rc, rc); - e_rc = data.setBit(12); // force_safe_mode = 1 - E_RC_CHECK(e_rc, l_rc); + e_rc = data.setBit(PMGP1_FORCE_SAFE_MODE_BIT); // force_safe_mode = 1 + E_RC_CHECK(e_rc, rc); - address = EX_PMGP1_OR_0x100F0105 + - (l_ex_number * 0x01000000);; - PUTSCOM(i_target, address, data); + address = EX_PMGP1_OR_0x100F0105 + ex_offset; + PUTSCOM(rc, i_target, address, data); FAPI_INF("Forced Safe Mode"); @@ -875,27 +861,28 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i // ****************************************************************** // - PCBS_POWER_MANAGEMENT_STATUS_REG[33] safe_mode_active // - PCBS_POWER_MANAGEMENT_STATUS_REG[36] all_fsms_in_safe_state - // // ****************************************************************** FAPI_INF("Psafe Pstate and FSM-stable?"); loopcount = 0; - address = EX_PCBS_POWER_MANAGEMENT_STATUS_REG_0x100F0153 + - (l_ex_number * 0x01000000); - GETSCOM(i_target, address, data); - + address = EX_PCBS_POWER_MANAGEMENT_STATUS_REG_0x100F0153 + ex_offset; // loop until (safe_mode_active AND all_fsms_in_safe_state) - while( data.isBitClear( 33 ) || data.isBitClear( 36 ) ) + do { + + // Read PMSR + GETSCOM(rc, i_target, address, data); + FAPI_DBG("\t loopcount => %d ",loopcount ); // OR timeout .... set to 20 loops if( ++loopcount > pcbs_val_init.MAX_PSAFE_FSM_LOOPS ) { FAPI_ERR("Gave up waiting for Psafe Pstate and FSM-stable!" ); + const fapi::Target& PROC_CHIP = i_target; const uint64_t& LOOPCOUNT = (uint32_t)loopcount; const uint64_t& PMSR = data.getDoubleWord(0); - FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PCBS_CODE_SAFE_FSM_TIMEOUT); + FAPI_SET_HWP_ERROR(rc, RC_PROC_PCBS_CODE_SAFE_FSM_TIMEOUT); break; } @@ -906,19 +893,17 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i FAPI_DBG("\t Wait DELAY: %d ", pcbs_val_init.MAX_DELAY); FAPI_DBG("\t Wait SimCycles: %d ", pcbs_val_init.MAX_SIM_CYCLES); - l_rc = fapiDelay(pcbs_val_init.MAX_DELAY, pcbs_val_init.MAX_SIM_CYCLES); - if (l_rc) + rc = fapiDelay(pcbs_val_init.MAX_DELAY, pcbs_val_init.MAX_SIM_CYCLES); + if (rc) { - FAPI_ERR("fapiDelay(MAX_DELAY, MAX_SIM_CYCLES) failed. With rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiDelay(MAX_DELAY, MAX_SIM_CYCLES) failed. With rc = 0x%x", (uint32_t)rc); break; } - // Read PMSR again - GETSCOM(i_target, address, data); - - } + } while ( data.isBitClear(PMSR_PSAFE_MODE_ACTIVE_BIT) || + data.isBitClear(PMSR_ALL_FSMS_IN_SAFE_STATE_BIT)); // if error, break the outer loop - if (!l_rc.ok()) + if (!rc.ok()) { break; } @@ -946,26 +931,26 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i FAPI_INF("Hold the DPLL to the value that the last Pstate represents"); // Write calculated values to FREQ_CTRL_REG - address = EX_FREQCNTL_0x100F0151 + (l_ex_number * 0x01000000); - GETSCOM(i_target, address, data); + address = EX_FREQCNTL_0x100F0151 + ex_offset; + GETSCOM(rc, i_target, address, data); FAPI_DBG(" Pre write content of FREQ_CTRL_REG_0x1*0F0151 : %016llX", data.getDoubleWord(0)); // Clear the DPLL bias; did not clear other fields e_rc = data.clearBit(18, 4); - E_RC_CHECK(e_rc, l_rc); + E_RC_CHECK(e_rc, rc); - PUTSCOM(i_target, address, data); + PUTSCOM(rc, i_target, address, data); // Lock the DPLL in via the override mode. Note: this DOES // allow for continued CPM enablement e_rc |= data.flushTo0(); - e_rc |= data.setBit(10); // dpll_freq_override_enable - E_RC_CHECK(e_rc, l_rc); + e_rc |= data.setBit(PMGP1_DPLL_FREQ_OVERRIDE_ENABLE); + E_RC_CHECK(e_rc, rc); - address = EX_PMGP1_OR_0x100F0105 + (l_ex_number * 0x01000000); - PUTSCOM(i_target, address, data); + address = EX_PMGP1_OR_0x100F0105 + ex_offset; + PUTSCOM(rc, i_target, address, data); // ****************************************************************** // - Disable Pstate mode @@ -973,16 +958,15 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i // ****************************************************************** FAPI_INF("Disable Pstate mode and disable Pstate requests"); - address = EX_PCBSPM_MODE_REG_0x100F0156 + - (l_ex_number * 0x01000000); + address = EX_PCBSPM_MODE_REG_0x100F0156 + ex_offset; - GETSCOM(i_target, address, data ); + GETSCOM(rc, i_target, address, data ); - e_rc |= data.clearBit(0); //Disable Pstate mode - e_rc |= data.clearBit(2); //Disable Pstate requests - E_RC_CHECK(e_rc, l_rc); + e_rc |= data.clearBit(PCBSPMMODE_ENABLE_PSTATE_MODE_BIT); + e_rc |= data.clearBit(PCBSPMMODE_ENABLE_GLOBAL_PSTATE_REQ_BIT); + E_RC_CHECK(e_rc, rc); - PUTSCOM(i_target, address, data ); + PUTSCOM(rc, i_target, address, data ); FAPI_INF("Disabled Pstate mode"); @@ -998,11 +982,11 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i // Using Write OR to set bit11 // Clear buffer e_rc = data.flushTo0(); - e_rc |= data.setBit(11); // Force OCC SPR Mode = 1 - E_RC_CHECK(e_rc, l_rc); + e_rc |= data.setBit(PMGP1_PM_SPR_OVERRIDE_EN_BIT); + E_RC_CHECK(e_rc, rc); - address = EX_PMGP1_OR_0x100F0105 + (l_ex_number * 0x01000000); - PUTSCOM(i_target, address, data ); + address = EX_PMGP1_OR_0x100F0105 + ex_offset; + PUTSCOM(rc, i_target, address, data ); FAPI_INF("Forced OCC SPR Mode"); @@ -1014,26 +998,25 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i FAPI_INF("Disabling Global Pstate Request bits "); address = EX_PCBS_Power_Management_Idle_Control_Reg_0x100F0158 + - (l_ex_number * 0x01000000); - GETSCOM(i_target, address, data ); + ex_offset; + GETSCOM(rc, i_target, address, data ); - e_rc |= data.clearBit(8); // Disable Nap Pstate Enable - e_rc |= data.clearBit(24); // Disable Sleep Pstate Enable - e_rc |= data.clearBit(40); // Disable Winkle Pstate Enable - E_RC_CHECK(e_rc, l_rc); + e_rc |= data.clearBit(PMICR_NAP_PSTATE_EN_BIT); + e_rc |= data.clearBit(PMICR_SLEEP_PSTATE_EN_BIT); + e_rc |= data.clearBit(PMICR_WINKLE_PSTATE_EN_BIT); + E_RC_CHECK(e_rc, rc); - PUTSCOM(i_target, address, data ); + PUTSCOM(rc, i_target, address, data ); // Auto overrides - address = EX_PCBS_Power_Management_Control_Reg_0x100F0159 + - (l_ex_number * 0x01000000); - GETSCOM(i_target, address, data ); + address = EX_PCBS_Power_Management_Control_Reg_0x100F0159 + ex_offset; + GETSCOM(rc, i_target, address, data ); - e_rc |= data.clearBit(16); // Disable Auto Override 0 - e_rc |= data.clearBit(17); // Disable Auto Override 1 - E_RC_CHECK(e_rc, l_rc); + e_rc |= data.clearBit(PMSR_AUTO_OVERRIDE0_PSTATE_LIMIT_EN_BIT); + e_rc |= data.clearBit(PMSR_AUTO_OVERRIDE1_PSTATE_LIMIT_EN_BIT); + E_RC_CHECK(e_rc, rc); - PUTSCOM(i_target, address, data ); + PUTSCOM(rc, i_target, address, data ); FAPI_INF("Disabled Global Pstate Requests"); @@ -1046,11 +1029,10 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i e_rc |= data.flushTo0(); e_rc |= data.setByte(0, pcbs_val_init.PMIN_CLIP); //Pmin_clip = -128 e_rc |= data.setByte(1, pcbs_val_init.PMAX_CLIP); //Pmax_clip = 127 - E_RC_CHECK(e_rc, l_rc); + E_RC_CHECK(e_rc, rc); - address = EX_PCBS_Power_Management_Bounds_Reg_0x100F015D + - (l_ex_number * 0x01000000); - PUTSCOM(i_target, address, data ); + address = EX_PCBS_Power_Management_Bounds_Reg_0x100F015D + ex_offset; + PUTSCOM(rc, i_target, address, data ); FAPI_DBG("Pmin/Pmax written to PCBS_Power_Management_Bounds_Reg : %016llX", data.getDoubleWord(0)); @@ -1067,28 +1049,27 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i // Using Write OR to just set bit22 // Clear buffer e_rc = data.flushTo0(); - e_rc = data.setBit(22); //disable RESCLK - E_RC_CHECK(e_rc, l_rc); + e_rc = data.setBit(GP3_RESCLK_DIS_BIT); + E_RC_CHECK(e_rc, rc); - address = EX_GP3_OR_0x100F0014 + (l_ex_number * 0x01000000); - PUTSCOM(i_target, address, data); + address = EX_GP3_OR_0x100F0014 + ex_offset; + PUTSCOM(rc, i_target, address, data); FAPI_INF ("Disabled RESCLK, set bit 22 of GP3_REG_0_RWXx1*0F0012 " ); // ****************************************************************** // Disable OCC Heartbeat // ****************************************************************** - address = EX_PCBS_OCC_Heartbeat_Reg_0x100F0164 + - (l_ex_number * 0x01000000); - GETSCOM(i_target, address, data); + address = EX_PCBS_OCC_Heartbeat_Reg_0x100F0164 + ex_offset; + GETSCOM(rc, i_target, address, data); FAPI_DBG(" Pre write content of PCBS_OCC_HEARTBEAT_REG_0x1*0F0164 : %016llX", data.getDoubleWord(0)); - e_rc = data.clearBit(8); //OCC Heartbeat disable - E_RC_CHECK(e_rc, l_rc); + e_rc = data.clearBit(POHR_OCC_HEARTBEAT_EN_BIT); + E_RC_CHECK(e_rc, rc); - PUTSCOM(i_target, address, data); + PUTSCOM(rc, i_target, address, data); FAPI_INF ("OCC Heartbeat disabled, cleared bit 8 of PCBS_OCC_HEARTBEAT_REG_0x1*0F0164" ); @@ -1104,22 +1085,21 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i if (pcbs_val_init.ivrms_enabled) { - address = EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 + - (l_ex_number * 0x01000000); - GETSCOM(i_target, address, data); + address = EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 + ex_offset; + GETSCOM(rc, i_target, address, data); FAPI_DBG(" Pre write content of PCBS_iVRM_Control_Status_Reg_0x1*0F0154 : %016llX", data.getDoubleWord(0)); - e_rc = data.clearBit(0); // disable ivrms - e_rc |= data.clearBit(4); // ivrm_core_vdd_bypass_b - e_rc |= data.clearBit(6); // ivrm_core_vcs_bypass_b - e_rc |= data.clearBit(8); // ivrm_eco_vdd_bypass_b - e_rc |= data.clearBit(10); // ivrm_eco_vcs_bypass_b - E_RC_CHECK(e_rc, l_rc); + e_rc = data.clearBit(IVRMCS_IVRM_FSM_ENABLE_BIT); + e_rc |= data.clearBit(IVRMCS_IVRM_CORE_VDD_BYPASS_B_BIT); + e_rc |= data.clearBit(IVRMCS_IVRM_CORE_VCS_BYPASS_B_BIT); + e_rc |= data.clearBit(IVRMCS_IVRM_ECO_VDD_BYPASS_B_BIT); + e_rc |= data.clearBit(IVRMCS_IVRM_ECO_VCS_BYPASS_B_BIT); + E_RC_CHECK(e_rc, rc); - PUTSCOM(i_target, address, data); + PUTSCOM(rc, i_target, address, data); // Write twice since ivrm_fsm_enable have to be 0 to enable the set the bypass modes - PUTSCOM(i_target, address, data); + PUTSCOM(rc, i_target, address, data); FAPI_INF ("iVRMs disabled and in bypass-mode" ); } @@ -1127,9 +1107,8 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i // ****************************************************************** // Disable undervolting // ****************************************************************** - address = EX_PCBS_UNDERVOLTING_REG_0x100F015B + - (l_ex_number * 0x01000000); - GETSCOM(i_target, address, data); + address = EX_PCBS_UNDERVOLTING_REG_0x100F015B + ex_offset; + GETSCOM(rc, i_target, address, data); FAPI_DBG(" Pre write content of PCBS_UNDERVOLTING_REG_0x1*0F015B : %016llX", data.getDoubleWord(0)); @@ -1137,11 +1116,9 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i e_rc |= data.setByte(0, pcbs_val_init.PUV_MIN); //Puv_min = -128 e_rc |= data.setByte(1, pcbs_val_init.PUV_MAX); //Puv_max = -128 e_rc |= data.setByte(2, pcbs_val_init.KUV); //Kuv = 0 - E_RC_CHECK(e_rc, l_rc); - - PUTSCOM(i_target, address, data); - + E_RC_CHECK(e_rc, rc); + PUTSCOM(rc, i_target, address, data); FAPI_DBG("\t PUV_MIN => %d ", pcbs_val_init.PUV_MIN ); FAPI_DBG("\t PUV_MAX => %d ", pcbs_val_init.PUV_MAX ); @@ -1153,25 +1130,36 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i // Disable Local Pstate Frequency Target mechanism // ****************************************************************** address = EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168 - + (l_ex_number * 0x01000000); - GETSCOM(i_target, address, data); + + ex_offset; + GETSCOM(rc, i_target, address, data); e_rc |= data.clearBit(20); - E_RC_CHECK(e_rc, l_rc); - - PUTSCOM(i_target, address, data); + E_RC_CHECK(e_rc, rc); + PUTSCOM(rc, i_target, address, data); FAPI_INF ("Local Pstate Frequency Target mechanism disabled" ); + + // ****************************************************************** + // Set other regs back to scan0 state + // ****************************************************************** + + rc = p8_pcbs_init_scan0(i_target, l_ex_number); + if (rc) + { + FAPI_ERR(" p8_pcbs_init_scan0 failed. With rc = 0x%x", (uint32_t)rc); + break; + } + } // Chiplet loop } while(0); - if (l_rc.ok()) + if (rc.ok()) { - FAPI_INF("Reset complete ...."); + FAPI_INF("Reset complete ...\n"); } - return l_rc; + return rc; } // end RESET //------------------------------------------------------------------------------ @@ -1188,17 +1176,20 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i fapi::ReturnCode p8_pcbs_init_scan0(const Target &i_target, uint8_t i_ex_number) { - fapi::ReturnCode l_rc; + fapi::ReturnCode rc; uint32_t e_rc; // ecmd returncode ecmdDataBufferBase data(64); uint64_t address; + uint64_t ex_offset; uint64_t reset_doubleword; uint32_t reset_word; do { + ex_offset = i_ex_number * 0x01000000; + // ****************************************************************** - // initialize all pm_reg with scan-zero values upfront + // Initialize PM Regs with scan-zero values // ***************************************************************** FAPI_INF("Put selective PCBSLV_PM registers to the scan0 value that are touched by OCC firmware"); @@ -1210,7 +1201,7 @@ p8_pcbs_init_scan0(const Target &i_target, uint8_t i_ex_number) // VDD to operational chiplets. // EX_PFVddCntlStat_REG_0x100F010E not reset has this would disrupt // VCS to operational chiplets - // EX_FREQCNTL_0x100F0151not reset has this would disrupt the frequency + // EX_FREQCNTL_0x100F0151 not reset has this would disrupt the frequency // of operational chiplets // EX_DPLL_CPM_PARM_REG_0x100F0152 not reset has this has DPLL control // bits that could/would disrupt operational chiplets @@ -1225,74 +1216,64 @@ p8_pcbs_init_scan0(const Target &i_target, uint8_t i_ex_number) // by register accesses //---- - address = EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165 - + (i_ex_number * 0x01000000); + address = EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165 + ex_offset; reset_doubleword = EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165_scan0; SETDWSCAN0(i_target, address, data, reset_doubleword ); //---- - address = EX_PMErrMask_REG_0x100F010A - + (i_ex_number * 0x01000000); + address = EX_PMErrMask_REG_0x100F010A + ex_offset; reset_word = EX_PMErrMask_REG_0x100F010A_scan0; SETSCAN0(i_target, address, data, reset_word ); // OCC does not mess with the PFET delays so these are left in tact. // This can only be done IF the IVRM is previously disabled. - address = EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 - + (i_ex_number * 0x01000000); + address = EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 + ex_offset; reset_word = EX_PCBS_iVRM_Control_Status_Reg_0x100F0154_scan0; SETSCAN0(i_target, address, data, reset_word ); //---- - address = EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155 - + (i_ex_number * 0x01000000); + address = EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155 + ex_offset; reset_word = EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155_scan0; SETSCAN0(i_target, address, data, reset_word ); //---- - address = EX_PCBS_PMC_VF_CTRL_REG_0x100F015A - + (i_ex_number * 0x01000000); + address = EX_PCBS_PMC_VF_CTRL_REG_0x100F015A + ex_offset; reset_word = EX_PCBS_PMC_VF_CTRL_REG_0x100F015A_scan0; SETSCAN0(i_target, address, data, reset_word ); //---- - address = EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C - + (i_ex_number * 0x01000000); + address = EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C + ex_offset; reset_word = EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C_scan0; SETSCAN0(i_target, address, data, reset_word ); //---- - address = EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E - + (i_ex_number * 0x01000000); + address = EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E + ex_offset; reset_word = EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E_scan0; SETSCAN0(i_target, address, data, reset_word ); //---- - address = EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162 - + (i_ex_number * 0x01000000); + address = EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162 + ex_offset; reset_word = EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162_scan0; SETSCAN0(i_target, address, data, reset_word ); //---- - address = EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163 - + (i_ex_number * 0x01000000); + address = EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163 + ex_offset; reset_word = EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163_scan0; SETSCAN0(i_target, address, data, reset_word ); //---- - address = EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166 - + (i_ex_number * 0x01000000); + address = EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166 + ex_offset; reset_word = EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166_scan0; SETSCAN0(i_target, address, data, reset_word ); /// \todo Regcheck error check at latest model // address = EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168 - // + (i_ex_number * 0x01000000); + // + ex_offset; // reset_word = EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168_scan0; // SETSCAN0(i_target, address, data, reset_word ); } while(0); - return l_rc; + return rc; } } //end extern C @@ -1303,6 +1284,13 @@ This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: p8_pcbs_init.C,v $ +Revision 1.19 2013/08/02 19:03:12 stillgs + +- Fix for SW209736 (OCC Reset Procedure incorrectly sets Freq to Turbo Value) +- Removed redundant check of functional attribute (Gerrit) +- Moved reg bit definitions to literals for clarity +- General clean-up in prep for RAS reviews. Added some FFDC info. + Revision 1.18 2013/05/23 02:18:02 stillgs Fix error_flag compile issue by removing it as coming header change will do anyway diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C index faa456221..4545c8be4 100644 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_pmc_init.C,v 1.35 2013/06/07 19:17:24 stillgs Exp $ +// $Id: p8_pmc_init.C,v 1.36 2013/08/02 19:09:07 stillgs Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pmc_init.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -100,19 +100,20 @@ pmc_config_spivid_settings(const Target& l_pTarget) uint32_t attr_pm_spivid_inter_retry_delay_value; uint32_t attr_pm_spivid_inter_retry_delay; - + FAPI_INF("pmc_config_spivid start..."); do { - FAPI_INF("Entering the config function"); //---------------------------------------------------------- - GETATTR( ATTR_FREQ_PB, + GETATTR( rc, + ATTR_FREQ_PB, "ATTR_FREQ_PB", NULL, attr_proc_nest_frequency); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_FREQUENCY, + GETATTR_DEFAULT( rc, + ATTR_PM_SPIVID_FREQUENCY, "ATTR_PM_SPIVID_FREQUENCY", NULL, attr_pm_spivid_frequency, @@ -123,7 +124,8 @@ pmc_config_spivid_settings(const Target& l_pTarget) (attr_pm_spivid_frequency*8)-1 ); - SETATTR( ATTR_PM_SPIVID_CLOCK_DIVIDER, + SETATTR( rc, + ATTR_PM_SPIVID_CLOCK_DIVIDER, "ATTR_PM_SPIVID_CLOCK_DIVIDER", &l_pTarget, attr_pm_spivid_clock_divider); @@ -132,7 +134,8 @@ pmc_config_spivid_settings(const Target& l_pTarget) // Delay between command and status frames of a SPIVID WRITE operation // (binary in nanoseconds) - GETATTR_DEFAULT( ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS, + GETATTR_DEFAULT( rc, + ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS, "ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS", &l_pTarget, attr_pm_spivid_interframe_delay_write_status, @@ -144,7 +147,8 @@ pmc_config_spivid_settings(const Target& l_pTarget) attr_pm_spivid_interframe_delay_write_status_value = attr_pm_spivid_interframe_delay_write_status / 100; - SETATTR( ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE, + SETATTR( rc, + ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE, "ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE", &l_pTarget, attr_pm_spivid_interframe_delay_write_status_value); @@ -154,7 +158,8 @@ pmc_config_spivid_settings(const Target& l_pTarget) // Delay between SPIVID reture attempts when WRITE command status // indicates an error (binary in nanoseconds) - GETATTR_DEFAULT( ATTR_PM_SPIVID_INTER_RETRY_DELAY, + GETATTR_DEFAULT( rc, + ATTR_PM_SPIVID_INTER_RETRY_DELAY, "ATTR_PM_SPIVID_INTER_RETRY_DELAY", &l_pTarget, attr_pm_spivid_inter_retry_delay, @@ -169,15 +174,17 @@ pmc_config_spivid_settings(const Target& l_pTarget) attr_pm_spivid_inter_retry_delay_value = attr_pm_spivid_inter_retry_delay / 100; - SETATTR( ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE, + SETATTR( rc, + ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE, "ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE", &l_pTarget, attr_pm_spivid_inter_retry_delay_value); - FAPI_INF("Exiting the config function"); } while(0); + FAPI_INF("pmc_config_spivid end..."); + return rc ; } @@ -193,11 +200,15 @@ pmc_config_spivid_settings(const Target& l_pTarget) * @retval ERROR defined in xml */ fapi::ReturnCode -pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 ) +pmc_reset_function( const fapi::Target& i_target1 , + const fapi::Target& i_target2, + uint32_t i_mode) { fapi::ReturnCode rc; ecmdDataBufferBase data(64); + ecmdDataBufferBase pmcmode_master(64); + ecmdDataBufferBase pmcmode_slave(64); // ecmdDataBufferBase mask(64); uint32_t e_rc = 0; uint32_t count = 0 ; @@ -228,6 +239,8 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 uint8_t attr_dcm_installed_2 = 0; uint64_t any_error = 0; + FAPI_INF("pmc_reset start..."); + do { // Check for validity of passed parms @@ -246,8 +259,8 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 if (attr_dcm_installed_1 == 0) { - // target2 should be NULL - // if not NULL, exit with config error + // target2 should be NULL + // if not NULL, exit with config error if (i_target2.getType() != TARGET_TYPE_NONE ) { FAPI_ERR ("config error : target2 is not null for target1 dcm not installed case"); @@ -267,24 +280,26 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // break; //} - if (i_target2.getType() != TARGET_TYPE_NONE ) - { rc = FAPI_ATTR_GET(ATTR_PROC_DCM_INSTALLED, &i_target2, attr_dcm_installed_2); - if (rc) - { - FAPI_ERR("fapiGetAttribute of ATTR_DCM_INSTALLED with rc = 0x%x", (uint32_t)rc); - break; - } - FAPI_INF (" ATTR_DCM_INSTALLED value in reset function = 0x%x", attr_dcm_installed_2 ); + if (i_target2.getType() != TARGET_TYPE_NONE ) + { + rc = FAPI_ATTR_GET(ATTR_PROC_DCM_INSTALLED, &i_target2, attr_dcm_installed_2); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_DCM_INSTALLED with rc = 0x%x", (uint32_t)rc); + break; + } + FAPI_INF (" ATTR_DCM_INSTALLED value in reset function = 0x%x", attr_dcm_installed_2 ); - if (attr_dcm_installed_2 != 1) - { - FAPI_ERR ("config error: DCM_INSTALLED target2 does not match target1"); - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_DCM_INSTALL_ERROR); - break; - } + if (attr_dcm_installed_2 != 1) + { + FAPI_ERR ("config error: DCM_INSTALLED target2 does not match target1"); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_DCM_INSTALL_ERROR); + break; + } - dcm = true; - } + dcm = true; + + } } //////////////////////////////////////////////////////////////////////////// @@ -295,7 +310,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 //////////////////////////////////////////////////////////////////////////// - FAPI_INF("Performing STEP 1"); + FAPI_INF("Determine master chip and slave targets"); rc = FAPI_ATTR_GET( ATTR_PM_SPIVID_PORT_ENABLE, &i_target1, attr_pm_spivid_port_enable1); @@ -307,58 +322,20 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 FAPI_INF (" value read from the attribute attr_pm_spivid_port_enable in reset function = 0x%x", attr_pm_spivid_port_enable1); - // \todo Removing until as the secondary port enable attrributes are irrelevant - /* - if (dcm) - { - rc = FAPI_ATTR_GET( ATTR_PM_SPIVID_PORT_ENABLE, - &i_target2, - attr_pm_spivid_port_enable2); - if (rc) - { - FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_PORT_ENABLE with rc = 0x%x", (uint32_t)rc); - break; - } - FAPI_INF (" value read from the attribute attr_pm_spivid_port_enable in reset function = 0x%x", - attr_pm_spivid_port_enable2); - } - - if (attr_pm_spivid_port_enable2 != 0 && attr_pm_spivid_port_enable1 != 0 ) + if (attr_pm_spivid_port_enable1 != 0 ) { - FAPI_ERR("Both targets have SPIVIDs enabled: check the configuration setup."); - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_TARGET_ERROR); - break; + master_target = i_target1; + slave_target = i_target2; } - else if (attr_pm_spivid_port_enable2 == 0 && attr_pm_spivid_port_enable1 == 0 ) + else { - FAPI_ERR("Neither target has SPIVID enabled: check the configuration setup."); - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_TARGET_ERROR); + FAPI_ERR("Master target does not have SPIVID ports enabled: ATTR_PM_SPIVID_PORT_ENABLE must be non-zero."); + const fapi::Target& MASTER_TARGET = i_target1; + const uint64_t& ATTR_SPIVID_PORT_ENABLE = (uint64_t)attr_pm_spivid_port_enable1; + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_SPIVID_CONFIG_ERROR); break; } - else - { - - if (attr_pm_spivid_port_enable2 != 0 ) - { - master_target = i_target2; - slave_target = i_target1; - } - */ - if (attr_pm_spivid_port_enable1 != 0 ) - { - master_target = i_target1; - slave_target = i_target2; - } - else - { - FAPI_ERR("Master target does not have SPIVID ports enabled: check the configuration setup."); - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_TARGET_ERROR); - break; - } - //} - - //////////////////////////////////////////////////////////////////////////// // 2.0 cRQ_TD_IntMaskRQ: Mask OCC interrupts in OIMR1 @@ -383,7 +360,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // Master // ****************************************************** - FAPI_INF("Performing STEP 2.00"); + FAPI_INF("Mask OCC interrupts in OIMR0 and OIMR1 on Master"); // CHECKING PMC_FIRS @@ -405,11 +382,8 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 if (any_error) { FAPI_DBG(" PMC_FIR has error(s) active. Continuing though 0x%16llX ", data.getDoubleWord(0)); - //FAPI_SET_HWP_ERROR(rc, RC_PROCPM_FIR_ERROR); break; - //return rc ; } - e_rc = data.flushTo0(); if (e_rc) { @@ -418,12 +392,13 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 } rc = fapiGetScom(master_target, OCB_OCI_OIMR1_0x0006a014 , data ); - if (rc) { - FAPI_ERR("fapiGetScom(OCB_OCI_OIMR1_0x0006a014) failed."); break; + if (rc) + { + FAPI_ERR("fapiGetScom(OCB_OCI_OIMR1_0x0006a014) failed."); + break; } - - e_rc = data.setBit(12); + e_rc |= data.setBit(12); e_rc |= data.setBit(13); e_rc |= data.setBit(14); e_rc |= data.setBit(15); @@ -438,17 +413,20 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 } rc = fapiPutScom(master_target, OCB_OCI_OIMR1_0x0006a014 , data ); - if (rc) { - FAPI_ERR("fapiPutScom(OCB_OCI_OIMR1_0x0006a014) failed."); break; + if (rc) + { + FAPI_ERR("fapiPutScom(OCB_OCI_OIMR1_0x0006a014) failed."); + break; } rc = fapiGetScom(master_target, OCB_OCI_OIMR0_0x0006a004 , data ); - if (rc) { - FAPI_ERR("fapiGetScom(OCB_OCI_OIMR0_0x0006a004) failed."); break; + if (rc) + { + FAPI_ERR("fapiGetScom(OCB_OCI_OIMR0_0x0006a004) failed."); + break; } - - e_rc = data.setBit(9); + e_rc |= data.setBit(9); e_rc |= data.setBit(13); e_rc |= data.setBit(21); if (e_rc) @@ -458,8 +436,6 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 break; } - - rc = fapiPutScom(master_target, OCB_OCI_OIMR0_0x0006a004 , data ); if (rc) { @@ -474,7 +450,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 if (dcm) { - FAPI_INF("Performing STEP 2.01"); + FAPI_INF("Mask OCC interrupts in OIMR0 and OIMR1 on Slave"); // CHECKING PMC_FIRS @@ -487,18 +463,17 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 } rc = fapiGetScom(slave_target, PMC_LFIR_0x01010840 , data ); - if (rc) { - FAPI_ERR("fapiGetScom(PMC_LFIR_0x01010840) failed."); - break; + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_LFIR_0x01010840) failed."); + break; } any_error = data.getDoubleWord(0); if (any_error) { - FAPI_ERR(" PMC_FIR has error(s) active. 0x%16llX ", data.getDoubleWord(0)); - //FAPI_SET_HWP_ERROR(rc, RC_PROCPM_FIR_ERROR); break; - //return rc ; + FAPI_DBG(" PMC_FIR has error(s) active. Continuing though 0x%16llX ", data.getDoubleWord(0)); } e_rc = data.flushTo0(); @@ -515,7 +490,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 FAPI_ERR("fapiGetScom(OCB_OCI_OIMR1_0x0006a014) failed."); break; } - e_rc = data.setBit(12); + e_rc |= data.setBit(12); e_rc |= data.setBit(13); e_rc |= data.setBit(14); e_rc |= data.setBit(15); @@ -543,7 +518,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 break; } - e_rc = data.setBit(9); + e_rc |= data.setBit(9); e_rc |= data.setBit(13); e_rc |= data.setBit(21); if (e_rc) @@ -576,7 +551,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // ****************************************************** // Master // ****************************************************** - FAPI_INF("Performing STEP 3.00"); + FAPI_INF("Halt Pstates and Idles on Master"); rc = fapiGetScom(master_target, PMC_MODE_REG_0x00062000 , data ); if (rc) @@ -585,7 +560,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 break; } - e_rc = data.setBit(05); + e_rc |= data.setBit(05); e_rc |= data.setBit(14); if (e_rc) { @@ -606,6 +581,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 master_enable_fw_pstate_mode = data.isBitSet(2) ; master_is_enable_interchip_interface = data.isBitSet(6) ; + pmcmode_master = data; // ****************************************************** // Slave @@ -613,7 +589,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 if (dcm) { - FAPI_INF("Performing STEP 3.01"); + FAPI_INF("Halt Pstates and Idles on Slave"); rc = fapiGetScom(slave_target, PMC_MODE_REG_0x00062000 , data ); if (rc) { @@ -622,7 +598,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 } - e_rc = data.setBit(05); + e_rc |= data.setBit(05); e_rc |= data.setBit(14); if (e_rc) { @@ -643,32 +619,46 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 slave_enable_fw_pstate_mode = data.isBitSet(2) ; slave_is_enable_interchip_interface = data.isBitSet(6) ; + pmcmode_slave = data; // Check with Greg about return // TODO : if ATTR_DCM_INSTALLED = 1 chip level attribute + /* if (master_is_MasterPMC == 0) { - FAPI_ERR(" MasterPMC bit of Master PMC is not set"); - + FAPI_ERR(" MasterPMC bit of Master PMC is not set"); + const uint64_t& MASTERPMCMODE = pmcmode_master.getDoubleWord(0); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMC_MASTER_CONFIG_ERROR); + break; } if (slave_is_MasterPMC == 1) { FAPI_ERR(" MasterPMC bit of Slave PMC is set"); + const uint64_t& SLAVEPMCMODE = pmcmode_slave.getDoubleWord(0); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMC_SLAVE_CONFIG_ERROR); + break; } if ((master_is_enable_interchip_interface ==1) && (slave_is_enable_interchip_interface == 0)) { - FAPI_ERR (" Configuration Error : Master is enabled with interchip interface but slave is not "); - + FAPI_ERR (" Configuration Error : Master is enabled with interchip interface but slave is not "); + const uint64_t& MASTERPMCMODE = pmcmode_master.getDoubleWord(0); + const uint64_t& SLAVEPMCMODE = pmcmode_slave.getDoubleWord(0); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMC_INTERCHIP_CONFIG_ERROR); + break; } if ( (master_enable_fw_pstate_mode == 1) && (slave_enable_fw_pstate_mode == 0)) { FAPI_ERR (" Configuration Error : Master is enabled with FW pstate mode but slave is not "); - + const uint64_t& MASTERPMCMODE = pmcmode_master.getDoubleWord(0); + const uint64_t& SLAVEPMCMODE = pmcmode_slave.getDoubleWord(0); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMC_INTERCHIP_CONFIG_ERROR); + break; } + */ } @@ -705,7 +695,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // ****************************************************** if (dcm) { - FAPI_INF("Performing STEP 4.00"); + FAPI_INF("Halt interchip interface on Master"); if (master_is_enable_interchip_interface == 1) { @@ -818,9 +808,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // ****************************************************** // Slave // ****************************************************** - - - FAPI_INF("Performing STEP 4.01"); + FAPI_INF("Halt interchip interface on Slave"); if (slave_is_enable_interchip_interface ==1) { @@ -950,10 +938,10 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // else -->MPS_HaltWait //////////////////////////////////////////////////////////////////////////// - FAPI_INF("Performing STEP 5.00"); - if (master_enable_pstate_voltage_changes==1) { + FAPI_INF("Halt SPIVID controller on Master"); + // HaltSpivid: PMC_SPIV_COMMAND_REG.spivid_halt_fsm<-1 rc = fapiGetScom(master_target, PMC_SPIV_COMMAND_REG_0x00062047 , data ); if (rc) @@ -1003,7 +991,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // Timeout check if (count > VOLTAGE_CHANGE_POLL_COUNT) { - FAPI_ERR("Timed out in polling spiv ongoing : Reset_suspicious ... "); + FAPI_ERR("Timed out in polling SPIVID ongoing : Reset_suspicious ... "); // \todo // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); // break; @@ -1030,8 +1018,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // if (!is_stopped) then -->MPS_HaltWait (Wait limit) //////////////////////////////////////////////////////////////////////////// - FAPI_INF("Performing STEP 6.00 "); - + FAPI_INF("Check for Pstate FSM being stopped on Master"); // ****************************************************** // Master @@ -1079,7 +1066,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // ****************************************************** if (dcm) { - FAPI_INF("Performing STEP 6.01 "); + FAPI_INF("Check for Pstate FSM being stopped on Slave"); for (count = 0 , is_stopped = 0 ; count <= PSTATE_HALT_POLL_COUNT && is_stopped == 0 ; count++) { @@ -1158,7 +1145,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // Master // ****************************************************** - FAPI_INF("Performing STEP 7.00 "); + FAPI_INF("Poll for O2P bridge being complete on Master"); rc = fapiGetScom(master_target, PMC_O2S_COMMAND_REG_0x00062057 , data ); if (rc) { @@ -1244,7 +1231,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 if (dcm) { - FAPI_INF("Performing STEP 7.01 "); + FAPI_INF("Poll for O2P bridge being complete on Slave"); for (count = 0 , is_stopped = 0 ; count <= O2P_POLL_COUNT && is_stopped == 0 ; count++) { @@ -1292,7 +1279,11 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // the execution of p8_poreslw_recovery.C will have taken place. /////////////////////////////////////////////////////////////////////////////////////////////////////////// - FAPI_INF("Performing STEP 8.00 "); + // ****************************************************** + // Master + // ****************************************************** + + FAPI_INF("Poll for Idle FSM being quiesced on Master"); for (count = 0 , is_stopped = 0 ; count <= PORE_REQ_POLL_COUNT && is_stopped == 0 ; count++) { rc = fapiGetScom(master_target, PMC_PORE_REQ_REG0_0x0006208E , data ); @@ -1320,6 +1311,41 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // break; } + // ****************************************************** + // Slave + // ****************************************************** + + if (dcm) + { + FAPI_INF("Poll for Idle FSM being quiesced on Slave"); + for (count = 0 , is_stopped = 0 ; count <= PORE_REQ_POLL_COUNT && is_stopped == 0 ; count++) + { + rc = fapiGetScom(slave_target, PMC_PORE_REQ_REG0_0x0006208E , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_O2P_STATUS_REG__0x00062061) failed."); + break; + } + + is_stopped = (data.isBitClear(20)) ; + FAPI_DBG("Polling pore_busy bit ..."); + } + + // Error check + if (!rc.ok()) + { + break; + } + + // Timeout check + if (count > PORE_REQ_POLL_COUNT) + { + FAPI_ERR("Timed out in polling pore_busy bit . : Reset_suspicious .. "); + // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); + // break; + } + } + /////////////////////////////////////////////////////////////////////////////// // GREG: // Issue interchip interface reset (if enabled) on master_chiptarget @@ -1340,7 +1366,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // ****************************************************** - FAPI_INF("Performing STEP 9.00 "); + FAPI_INF("Reset interchip interface on Master"); if ( master_is_enable_interchip_interface == 1) { @@ -1389,7 +1415,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 if (dcm) { - FAPI_INF("Performing STEP 9.01 "); + FAPI_INF("Reset interchip interface on Slave"); if ( slave_is_enable_interchip_interface == 1) { @@ -1433,101 +1459,117 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 } } - /////////////////////////////////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////// // Issue reset to the PMC - // Note: this action will wipe out the Idle Pending queue so that requests for idle transitions (entry and exit) will be lost which means that PHYP notification needs to happen. + // Note: this action will wipe out the Idle Pending queue so that + // requests for idle transitions (entry and exit) will be lost which + // means that PHYP notification needs to happen. + // // Write PMC_MODE_REG.pmc_reset_all_voltage_registers = 1. // Clearing LFIRs will have been done by PRD // Note: this will remove CONFIG settings // This puts the PMC into firmware mode which halts any future Global Actual operations - /////////////////////////////////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////// // ****************************************************** // Master // ****************************************************** // RESET_ALL_PMC_REGISTERS - rc = fapiGetScom(master_target, PMC_MODE_REG_0x00062000 , data ); - if (rc) - { - FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); - break; - } - - e_rc = data.setBit(12); - if (e_rc) - { - FAPI_ERR("ecmdDataBufferBase error setting up PMC_INTCHP_COMMAND_REG_0x00062014 on Master reset"); - rc.setEcmdError(e_rc); - break; - } - if (rc) - { - FAPI_ERR("fapiPutScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); - break; - } - - rc = fapiPutScom(master_target, PMC_MODE_REG_0x00062000 , data ); - if (rc) - { - FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); - break; - } - - // ****************************************************** - // Slave - // ****************************************************** - if (dcm) + + if (i_mode == PM_RESET) { - - rc = fapiGetScom(slave_target, PMC_MODE_REG_0x00062000 , data ); + FAPI_INF("Hard reset detected"); + FAPI_INF("Reset PMC on Master"); + rc = fapiGetScom(master_target, PMC_MODE_REG_0x00062000 , data ); if (rc) { - FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); - break; - } - - e_rc = data.setBit(12); - if (e_rc) - { - FAPI_ERR("ecmdDataBufferBase error setting up PMC_MODE_REG_0x00062000 on Slave reset"); - rc.setEcmdError(e_rc); + FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); break; } - rc = fapiPutScom(slave_target, PMC_MODE_REG_0x00062000 , data ); + e_rc = data.setBit(12); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_INTCHP_COMMAND_REG_0x00062014 on Master reset"); + rc.setEcmdError(e_rc); + break; + } if (rc) { - FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); + FAPI_ERR("fapiPutScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); break; } - // \todo remove in deference to init path - // Restored only for slave - // SAFE_MODE_WITHOUT_SPIVID - rc = fapiGetScom(slave_target, PMC_MODE_REG_0x00062000 , data ); + rc = fapiPutScom(master_target, PMC_MODE_REG_0x00062000 , data ); if (rc) { - FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); - break; + FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); + break; } - e_rc = data.setBit(13); - if (e_rc) + // ****************************************************** + // Slave + // ****************************************************** + if (dcm) { - FAPI_ERR("ecmdDataBufferBase error for PMC_MODE_REG_0x00062000 on Slave reset"); - rc.setEcmdError(e_rc); - break; - } + FAPI_INF("Reset PMC on Slave"); - rc = fapiPutScom(slave_target, PMC_MODE_REG_0x00062000 , data ); - if (rc) - { - FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); - break; + rc = fapiGetScom(slave_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + + e_rc = data.setBit(12); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_MODE_REG_0x00062000 on Slave reset"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiPutScom(slave_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + + // \todo remove in deference to init path + // Restored only for slave + // SAFE_MODE_WITHOUT_SPIVID + rc = fapiGetScom(slave_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + + e_rc = data.setBit(13); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error for PMC_MODE_REG_0x00062000 on Slave reset"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiPutScom(slave_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); + break; + } } } + else + { + FAPI_INF("Soft reset detected. PMC register reset skipped."); + } } while(0); + FAPI_INF("pmc_reset end..."); + return rc; } @@ -1593,99 +1635,113 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) interchip_clock_divider = ( proc_nest_frequency /(attr_pm_interchip_frequency*8)-1 ); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_FRAME_SIZE, - "ATTR_PM_SPIVID_FRAME_SIZE", - &i_target1, - attr_pm_spivid_frame_size, - default_spivid_frame_size ); + GETATTR_DEFAULT(rc, + ATTR_PM_SPIVID_FRAME_SIZE, + "ATTR_PM_SPIVID_FRAME_SIZE", + &i_target1, + attr_pm_spivid_frame_size, + default_spivid_frame_size ); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_IN_DELAY_FRAME1, - "ATTR_PM_SPIVID_IN_DELAY_FRAME1", - &i_target1, - attr_pm_spivid_in_delay_frame1, - default_spivid_in_delay_frame1 ); + GETATTR_DEFAULT(rc, + ATTR_PM_SPIVID_IN_DELAY_FRAME1, + "ATTR_PM_SPIVID_IN_DELAY_FRAME1", + &i_target1, + attr_pm_spivid_in_delay_frame1, + default_spivid_in_delay_frame1 ); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_IN_DELAY_FRAME1, - "ATTR_PM_SPIVID_IN_DELAY_FRAME1", - &i_target1, - attr_pm_spivid_in_delay_frame2, - default_spivid_in_delay_frame2 ); + GETATTR_DEFAULT(rc, + ATTR_PM_SPIVID_IN_DELAY_FRAME1, + "ATTR_PM_SPIVID_IN_DELAY_FRAME1", + &i_target1, + attr_pm_spivid_in_delay_frame2, + default_spivid_in_delay_frame2 ); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_CLOCK_POLARITY, - "ATTR_PM_SPIVID_CLOCK_POLARITY", - &i_target1, - attr_pm_spivid_clock_polarity, - default_spivid_clock_polarity ); + GETATTR_DEFAULT(rc, + ATTR_PM_SPIVID_CLOCK_POLARITY, + "ATTR_PM_SPIVID_CLOCK_POLARITY", + &i_target1, + attr_pm_spivid_clock_polarity, + default_spivid_clock_polarity ); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_CLOCK_PHASE, - "ATTR_PM_SPIVID_CLOCK_PHASE", - &i_target1, - attr_pm_spivid_clock_phase, - default_spivid_clock_phase ); + GETATTR_DEFAULT(rc, + ATTR_PM_SPIVID_CLOCK_PHASE, + "ATTR_PM_SPIVID_CLOCK_PHASE", + &i_target1, + attr_pm_spivid_clock_phase, + default_spivid_clock_phase ); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_CRC_GEN_ENABLE, - "ATTR_PM_SPIVID_CRC_GEN_ENABLE", - &i_target1, - attr_pm_spivid_crc_gen_enable, - default_spivid_crc_gen_enable ); + GETATTR_DEFAULT(rc, + ATTR_PM_SPIVID_CRC_GEN_ENABLE, + "ATTR_PM_SPIVID_CRC_GEN_ENABLE", + &i_target1, + attr_pm_spivid_crc_gen_enable, + default_spivid_crc_gen_enable ); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_CRC_CHECK_ENABLE, - "ATTR_PM_SPIVID_CRC_CHECK_ENABLE", - &i_target1, - attr_pm_spivid_crc_check_enable, - default_spivid_crc_check_enable ); + GETATTR_DEFAULT(rc, + ATTR_PM_SPIVID_CRC_CHECK_ENABLE, + "ATTR_PM_SPIVID_CRC_CHECK_ENABLE", + &i_target1, + attr_pm_spivid_crc_check_enable, + default_spivid_crc_check_enable ); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE, - "ATTR_PM_SPIVID_CRC_CHECK_ENABLE", - &i_target1, - attr_pm_spivid_majority_vote_enable, - default_spivid_majority_vote_enable ); + GETATTR_DEFAULT(rc, + ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE, + "ATTR_PM_SPIVID_CRC_CHECK_ENABLE", + &i_target1, + attr_pm_spivid_majority_vote_enable, + default_spivid_majority_vote_enable ); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_MAX_RETRIES, - "ATTR_PM_SPIVID_MAX_RETRIES", - &i_target1, - attr_pm_spivid_max_retries, - default_spivid_max_retries ); + GETATTR_DEFAULT(rc, + ATTR_PM_SPIVID_MAX_RETRIES, + "ATTR_PM_SPIVID_MAX_RETRIES", + &i_target1, + attr_pm_spivid_max_retries, + default_spivid_max_retries ); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES, - "ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES", - &i_target1, - attr_pm_spivid_crc_polynomial_enables, - default_spivid_crc_polynomial_enables ); + GETATTR_DEFAULT(rc, + ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES, + "ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES", + &i_target1, + attr_pm_spivid_crc_polynomial_enables, + default_spivid_crc_polynomial_enables ); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_PORT_ENABLE, - "ATTR_PM_SPIVID_PORT_ENABLE", - &i_target1, - attr_pm_spivid_port_enable, - default_spivid_port_enable ); + GETATTR_DEFAULT(rc, + ATTR_PM_SPIVID_PORT_ENABLE, + "ATTR_PM_SPIVID_PORT_ENABLE", + &i_target1, + attr_pm_spivid_port_enable, + default_spivid_port_enable ); //---------------------------------------------------------- - GETATTR( ATTR_PM_SPIVID_CLOCK_DIVIDER, - "ATTR_PM_SPIVID_CLOCK_DIVIDER", - &i_target1, - attr_pm_spivid_clock_divider); + GETATTR( rc, + ATTR_PM_SPIVID_CLOCK_DIVIDER, + "ATTR_PM_SPIVID_CLOCK_DIVIDER", + &i_target1, + attr_pm_spivid_clock_divider); //---------------------------------------------------------- - GETATTR( ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE, - "ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE", - &i_target1, - attr_pm_spivid_interframe_delay_write_status_value); + GETATTR( rc, + ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE, + "ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE", + &i_target1, + attr_pm_spivid_interframe_delay_write_status_value); //---------------------------------------------------------- - GETATTR( ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE, - "ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE", - &i_target1, - attr_pm_spivid_inter_retry_delay_value); + GETATTR( rc, + ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE, + "ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE", + &i_target1, + attr_pm_spivid_inter_retry_delay_value); FAPI_INF("PMC initialization..."); @@ -1761,9 +1817,11 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) if (any_error) { - FAPI_ERR(" PMC_FIR has error(s) active. 0x%16llX ", data.getDoubleWord(0)); - //FAPI_SET_HWP_ERROR(rc, RC_PROCPM_FIR_ERROR); break; - //return rc ; + // Once clear FIRs are established, this will throw errors. + FAPI_INF("WARNING: PMC_FIR has error(s) active. 0x%016llX ", data.getDoubleWord(0)); + //FAPI_ERR(" PMC_FIR has error(s) active. 0x%16llX ", data.getDoubleWord(0)); + //FAPI_SET_HWP_ERROR(rc, RC_PROCPM_FIR_ERROR); + //break; } // ****************************************************************** @@ -2336,7 +2394,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) * * @param[in] i_target1 Primary Chip target: Murano - chip0; Venice - chip * @param[in] i_target2 Secondary Chip target: Murano - chip1; Venice - NULL - * @param[in] mode (PM_INIT , PM_CONFIG, PM_RESET) + * @param[in] mode (PM_INIT , PM_CONFIG, PM_RESET, PM_RESET_SOFT) * * @retval ECMD_SUCCESS * @retval ERROR defined in xml @@ -2398,11 +2456,26 @@ p8_pmc_init(const fapi::Target& i_target1, const fapi::Target& i_target2, uint32 } /// ------------------------------- - /// Reset: perform reset of PMC + /// Reset: perform hard reset of PMC /// ------------------------------- else if (mode == PM_RESET) { - rc = pmc_reset_function(i_target1 , i_target2); + FAPI_INF("Hard reset detected. Calling pmc_reset_function"); + rc = pmc_reset_function(i_target1 , i_target2, mode); + if (rc) + { + FAPI_ERR("Error from pmc_reset_function"); + break; + } + } + + // ------------------------------- + /// Reset: perform soft reset of PMC + /// ------------------------------- + else if (mode == PM_RESET_SOFT) + { + FAPI_INF("Soft reset detected. Calling pmc_reset_function"); + rc = pmc_reset_function(i_target1 , i_target2, mode); if (rc) { FAPI_ERR("Error from pmc_reset_function"); @@ -2410,13 +2483,14 @@ p8_pmc_init(const fapi::Target& i_target1, const fapi::Target& i_target2, uint32 } } + /// ------------------------------- /// Unsupported Mode /// ------------------------------- else { FAPI_ERR("Unknown mode passed to p8_pmc_init. Mode %x ", mode); - uint32_t & MODE = mode; + const uint64_t & MODE = (uint64_t)mode; FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMC_CODE_BAD_MODE); } @@ -2434,6 +2508,13 @@ This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: p8_pmc_init.C,v $ +Revision 1.36 2013/08/02 19:09:07 stillgs + +- Support for p8_pm.H. +- Temporarily changed the detection of set FIR bit from FAPI_ERR to FAPI_INF until fully complete with testing. +This keeps "FAPI ERR" from showing up in log for things that do not give non-zero RCs. +- Added plumbing support for "soft" rest. FUNCTION IS NOT YET SUPPORTED + Revision 1.35 2013/06/07 19:17:24 stillgs Fix swap of Pmin and PMax rail settings |
