diff options
| author | Thi Tran <thi@us.ibm.com> | 2013-08-15 07:47:40 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-08-19 09:07:30 -0500 |
| commit | c458b54157b6cb417db2f2cf158b7379f00b7557 (patch) | |
| tree | 8935dd7e5bca2366ec8b23758014bfa5330e6dda | |
| parent | 6f2f3aa49961f017af6de723c28cf004ca8fbc36 (diff) | |
| download | talos-hostboot-c458b54157b6cb417db2f2cf158b7379f00b7557.tar.gz talos-hostboot-c458b54157b6cb417db2f2cf158b7379f00b7557.zip | |
NITPROC: Hostboot - Updated HWPs from defects SW213666/SW214730/SW214731
SW213666 SW214730 SW214731
Change-Id: I5301c3df79b54f50f227c0625be847bd21ca9b75
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5801
Tested-by: Jenkins Server
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
19 files changed, 1875 insertions, 1546 deletions
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pm.H b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pm.H index b059d169a..5a26c3ce1 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pm.H +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pm.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_pm.H,v 1.6 2013/05/31 10:53:14 pchatnah Exp $ +// $Id: p8_pm.H,v 1.7 2013/08/02 19:02:43 stillgs Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm.H,v $ //------------------------------------------------------------------------------ // *| @@ -64,8 +64,10 @@ enum p8_PM_FLOW_MODE { PM_SETUP = 0x4, PM_SETUP_PIB = 0x5, PM_SETUP_ALL = 0x6, - PM_RESET_NOPMC = 0x7, - PM_INIT_SPECIAL = 0x8 + PM_RESET_SOFT = 0x7, + PM_CONFIG_SOFT = PM_CONFIG, + PM_INIT_SOFT = 0x8, + PM_INIT_SPECIAL = 0x9 }; #endif // _P8_PM_FLOW_MODE @@ -74,18 +76,18 @@ enum p8_PM_FLOW_MODE { // Assume the error path is to break out of the current loop. If nested loops // are employed, the error_flag can be used to break out of the necessary // levels. -#define PUTSCOM(_mi_target, _mi_address, _mi_buffer){ \ - l_rc = fapiPutScom(_mi_target, _mi_address, _mi_buffer); \ - if(!l_rc.ok()) \ +#define PUTSCOM(_mi_rc, _mi_target, _mi_address, _mi_buffer){ \ + _mi_rc = fapiPutScom(_mi_target, _mi_address, _mi_buffer); \ + if(!_mi_rc.ok()) \ { \ FAPI_ERR("PutScom error to address 0x%08llx", _mi_address); \ break; \ } \ } -#define GETSCOM(_mi_target, _mi_address, _mi_buffer){ \ - l_rc = fapiGetScom(_mi_target, _mi_address, _mi_buffer); \ - if(!l_rc.ok()) \ +#define GETSCOM(_mi_rc, _mi_target, _mi_address, _mi_buffer){ \ + _mi_rc = fapiGetScom(_mi_target, _mi_address, _mi_buffer); \ + if(!_mi_rc.ok()) \ { \ FAPI_ERR("GetScom error to address 0x%08llx", _mi_address); \ break; \ @@ -101,11 +103,11 @@ enum p8_PM_FLOW_MODE { } \ } -#define GETATTR_DEFAULT(_mi_attr, _mi_attr_name, _mi_target, _mi_value, _mi_default){\ - rc = FAPI_ATTR_GET(_mi_attr, _mi_target, _mi_value); \ - if (rc) \ +#define GETATTR_DEFAULT(_mi_rc, _mi_attr, _mi_attr_name, _mi_target, _mi_value, _mi_default){\ + _mi_rc = FAPI_ATTR_GET(_mi_attr, _mi_target, _mi_value); \ + if (_mi_rc) \ { \ - FAPI_ERR("fapiGetAttribute of %s with rc = 0x%x", _mi_attr_name, (uint32_t)rc); \ + FAPI_ERR("fapiGetAttribute of %s with rc = 0x%x", _mi_attr_name, (uint32_t)_mi_rc); \ break; \ } \ FAPI_INF (" value read from attribute %s = 0x%x", _mi_attr_name, _mi_value ); \ @@ -116,9 +118,9 @@ enum p8_PM_FLOW_MODE { } \ } -#define GETATTR(_mi_attr, _mi_attr_name, _mi_target, _mi_value){\ - rc = FAPI_ATTR_GET(_mi_attr, _mi_target, _mi_value); \ - if (rc) \ +#define GETATTR(_mi_rc, _mi_attr, _mi_attr_name, _mi_target, _mi_value){\ + _mi_rc = FAPI_ATTR_GET(_mi_attr, _mi_target, _mi_value); \ + if (_mi_rc) \ { \ FAPI_ERR("fapiGetAttribute of %s with rc = 0x%x", _mi_attr_name, (uint32_t)rc); \ break; \ @@ -126,11 +128,11 @@ enum p8_PM_FLOW_MODE { FAPI_INF (" value read from attribute %s = 0x%x", _mi_attr_name, _mi_value ); \ } -#define SETATTR(_mi_attr, _mi_attr_name, _mi_target, _mi_value){\ - rc = FAPI_ATTR_SET(_mi_attr, _mi_target, _mi_value); \ - if (rc) \ +#define SETATTR(_mi_rc, _mi_attr, _mi_attr_name, _mi_target, _mi_value){\ + _mi_rc = FAPI_ATTR_SET(_mi_attr, _mi_target, _mi_value); \ + if (_mi_rc) \ { \ - FAPI_ERR("fapiSetAttribute of %s with rc = 0x%x", _mi_attr_name, (uint32_t)rc); \ + FAPI_ERR("fapiSetAttribute of %s with rc = 0x%x", _mi_attr_name, (uint32_t)_mi_rc); \ break; \ } \ FAPI_INF (" value written to attribute %s = 0x%x", _mi_attr_name, _mi_value ); \ diff --git a/src/usr/hwpf/hwp/bus_training/io_run_training.C b/src/usr/hwpf/hwp/bus_training/io_run_training.C index d0ca1a529..12bde5710 100644 --- a/src/usr/hwpf/hwp/bus_training/io_run_training.C +++ b/src/usr/hwpf/hwp/bus_training/io_run_training.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: io_run_training.C,v 1.40 2013/06/20 06:16:29 varkeykv Exp $ +// $Id: io_run_training.C,v 1.42 2013/07/11 12:13:05 varkeykv Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -298,8 +298,8 @@ ReturnCode fir_workaround_post_training(const Target& master_target, io_interfa // This will continue until we run out of valid DLL reg selects or when the DLL cal passes ReturnCode check_dll_status_and_modify(const Target &master_target, io_interface_t master_interface,const Target &slave_target, - io_interface_t slave_interface,bool dll_master_array[16], - bool dll_slave_array[16],bool &dll_workaround_done,bool &dll_workaround_fail) + io_interface_t slave_interface,bool dll_master_array[], + bool dll_slave_array[],bool &dll_workaround_done,bool &dll_workaround_fail) { ReturnCode rc; uint32_t rc_ecmd=0; @@ -320,6 +320,7 @@ ReturnCode check_dll_status_and_modify(const Target &master_target, io_interface { FAPI_ERR("Failed buffer intialization in DLL workaround function \n"); rc.setEcmdError(rc_ecmd); + return(rc); } FAPI_INF("DLL WORKAROUND CODE executing"); @@ -327,11 +328,13 @@ ReturnCode check_dll_status_and_modify(const Target &master_target, io_interface for (int current_group = 0 ; current_group < 4; current_group++){ // slave side operations rc = GCR_read( slave_target, slave_interface, ei4_rx_dll_analog_tweaks_pg, current_group, 0, dll_reg); + if(rc){return rc;} rc_ecmd|=dll_reg.extract( &dll_value, 4, 3 ); if(rc_ecmd) { FAPI_ERR("Failed buffer intialization in DLL workaround function \n"); rc.setEcmdError(rc_ecmd); + return(rc); } FAPI_DBG("Extracted DLL value is %d",dll_value); @@ -344,6 +347,8 @@ ReturnCode check_dll_status_and_modify(const Target &master_target, io_interface } else{ FAPI_ERR("DLL Vreg Cal sel value out of bounds for workaround !!"); + FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_DLL_VAL_OUT_OF_BOUND_RC); + return rc; } rc = GCR_read( slave_target, slave_interface, ei4_rx_dll_cal_cntl_pg, current_group, 0, dll_reg); @@ -352,21 +357,26 @@ ReturnCode check_dll_status_and_modify(const Target &master_target, io_interface // Some DLL error is present , lets push this Clock group ref cal value to the next untried value FAPI_DBG("DLL error detected on clock group %d on slave target",current_group); - rc=GCR_write(slave_target, slave_interface, ei4_rx_dll_cal_cntl_pg, current_group,0, temp_bits, temp_bits,1,1); - rc=GCR_write(master_target, master_interface, ei4_rx_dll_cal_cntl_pg, current_group,0, temp_bits, temp_bits,1,1); + rc=GCR_write(slave_target, slave_interface, ei4_rx_dll_cal_cntl_pg, current_group,0, temp_bits, temp_bits,1,1); + if(rc){return rc;} + rc=GCR_write(master_target, master_interface, ei4_rx_dll_cal_cntl_pg, current_group,0, temp_bits, temp_bits,1,1); + if(rc){return rc;} for(int dll_valid=0;dll_valid<6;++dll_valid){ if(dll_slave_array[current_group*6 + dll_valid]==false){ // Now set the DLL vref cal sel reg value to the next valid untried value dll_value=dll_vals[dll_valid]; FAPI_DBG("DLL value to be written is %d dll_valid=%d current_group=%d",dll_value,dll_valid,current_group); rc=GCR_read(slave_target , slave_interface, ei4_rx_dll_analog_tweaks_pg, current_group,0, set_bits); + if(rc){return rc;} rc_ecmd=set_bits.insert(dll_value,4,3,13); if(rc_ecmd) { FAPI_ERR("Failed buffer insertion in DLL workaround function \n"); rc.setEcmdError(rc_ecmd); + return rc; } rc=GCR_write(slave_target, slave_interface, ei4_rx_dll_analog_tweaks_pg, current_group,0, set_bits, clear_bits); + if(rc){return rc;} found_dll_slave=true; dll_slave_array[current_group*6 + dll_valid]=true; break; @@ -377,6 +387,8 @@ ReturnCode check_dll_status_and_modify(const Target &master_target, io_interface // Now do FFDC call outs //dump_ffdc=true; dll_workaround_fail=true; + FAPI_SET_HWP_ERROR(rc,IO_RUN_TRAINING_DLL_WORKAROUND_FAIL); + return rc; } } else{ @@ -388,11 +400,13 @@ ReturnCode check_dll_status_and_modify(const Target &master_target, io_interface // Push current DLL value into the std::vector dll_reg.flushTo0(); rc = GCR_read( master_target, master_interface, ei4_rx_dll_analog_tweaks_pg, current_group, 0, dll_reg); + if(rc){return rc;} rc_ecmd|=dll_reg.extract( &dll_value, 4, 3 ); if(rc_ecmd) { FAPI_ERR("Failed buffer intialization in DLL workaround function \n"); rc.setEcmdError(rc_ecmd); + return rc; } FAPI_DBG("Extracted DLL value is %d",dll_value); @@ -404,14 +418,18 @@ ReturnCode check_dll_status_and_modify(const Target &master_target, io_interface } else{ FAPI_ERR("DLL Vreg Cal sel value out of bounds for workaround !!"); + FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_DLL_VAL_OUT_OF_BOUND_RC); + return rc; } rc = GCR_read( master_target, master_interface, ei4_rx_dll_cal_cntl_pg, current_group, 0, dll_reg); if(rc){return rc;} if(dll_reg.isBitSet(1) || dll_reg.isBitSet(2) || dll_reg.isBitSet(9) || dll_reg.isBitSet(10)){ // Some DLL error is present , lets push this Clock group to the next untried value FAPI_DBG("DLL error detected on clock group %d on master target",current_group); - rc=GCR_write(slave_target, slave_interface, ei4_rx_dll_cal_cntl_pg, current_group,0, temp_bits, temp_bits,1,1); - rc=GCR_write(master_target, master_interface, ei4_rx_dll_cal_cntl_pg, current_group,0, temp_bits, temp_bits,1,1); + rc=GCR_write(slave_target, slave_interface, ei4_rx_dll_cal_cntl_pg, current_group,0, temp_bits, temp_bits,1,1); + if(rc){return rc;} + rc=GCR_write(master_target, master_interface, ei4_rx_dll_cal_cntl_pg, current_group,0, temp_bits, temp_bits,1,1); + if(rc){return rc;} for(int dll_valid=0;dll_valid<6;++dll_valid){ if(dll_master_array[current_group*6 + dll_valid]==false){ @@ -419,13 +437,16 @@ ReturnCode check_dll_status_and_modify(const Target &master_target, io_interface dll_value=dll_vals[dll_valid]; FAPI_DBG("DLL value to be written is %d",dll_value); rc=GCR_read(master_target , master_interface, ei4_rx_dll_analog_tweaks_pg, current_group,0, set_bits); + if(rc){return rc;} rc_ecmd=set_bits.insert(dll_value,4,3,13); if(rc_ecmd) { FAPI_ERR("Failed buffer insertion in DLL workaround function \n"); rc.setEcmdError(rc_ecmd); + return rc; } rc=GCR_write(master_target, master_interface, ei4_rx_dll_analog_tweaks_pg, current_group,0, set_bits, clear_bits); + if(rc){return rc;} found_dll_master=true; dll_master_array[current_group*6 + dll_valid]=true; break; @@ -474,7 +495,7 @@ ReturnCode set_tx_drv_pattern(const Target &master_target, io_interface_t master ReturnCode rc; uint32_t rc_ecmd=0; // For DLL shmoo workaround - ecmdDataBufferBase set_bits(16),clear_bits(16); + ecmdDataBufferBase set_bits(16),clear_bits(16),clear_train_bits(16); uint16_t bits=0; FAPI_DBG("DLL workaround : Setting TX DRV pattern back to 0000 before restarting training on X bus "); @@ -485,9 +506,12 @@ ReturnCode set_tx_drv_pattern(const Target &master_target, io_interface_t master { FAPI_ERR("Failed buffer intialization in DLL workaround function \n"); rc.setEcmdError(rc_ecmd); + return rc; } rc=GCR_write(slave_target, slave_interface,ei4_tx_data_cntl_gcrmsg_pl , 15,31, set_bits, clear_bits,1,1); + if(rc){return rc;} rc=GCR_write(master_target, master_interface,ei4_tx_data_cntl_gcrmsg_pl , 15,31, set_bits, clear_bits,1,1); + if(rc){return rc;} //Clear Data pattern bits=ei4_tx_drv_clk_pattern_gcrmsg_clear; rc_ecmd=clear_bits.insert(bits,0,16); @@ -495,25 +519,44 @@ ReturnCode set_tx_drv_pattern(const Target &master_target, io_interface_t master { FAPI_ERR("Failed buffer intialization in DLL workaround function \n"); rc.setEcmdError(rc_ecmd); + return rc; } rc=GCR_write(slave_target, slave_interface, ei4_tx_clk_cntl_gcrmsg_pg , 15,0, set_bits, clear_bits,1,1); + if(rc){return rc;} rc=GCR_write(master_target, master_interface, ei4_tx_clk_cntl_gcrmsg_pg , 15,0, set_bits, clear_bits,1,1); + if(rc){return rc;} // According to John G , This reset is required as well bits= ei4_rx_wt_cu_pll_reset_clear ; rc_ecmd=clear_bits.insert(bits,0,16); + if(rc_ecmd) + { + FAPI_ERR("Failed buffer intialization in DLL workaround function \n"); + rc.setEcmdError(rc_ecmd); + return rc; + } set_bits.flushTo0(); - //Reset wt_cu_pll + //Reset wt_cu_pll & Wiretest status & Start bits for (int current_group = 0 ; current_group < 4; current_group++){ - //rc = GCR_read( slave_target, slave_interface,ei4_rx_wiretest_pll_cntl_pg , current_group, 0, set_bits); - //set_bits.clearBit(1); + //Reset training start and status bits - as per Rob + rc=GCR_write(slave_target , slave_interface, ei4_rx_training_start_pg,current_group,0, set_bits, clear_train_bits,1,1); + if(rc){return rc;} + rc=GCR_write(slave_target , slave_interface, ei4_rx_training_status_pg, current_group,0, set_bits,clear_train_bits,1,1); + if(rc){return rc;} + //Reset Wt PLL as per John G rc=GCR_write(slave_target, slave_interface, ei4_rx_wiretest_pll_cntl_pg , current_group,0, set_bits, clear_bits,1,1); - // - //rc = GCR_read( master_target, master_interface,ei4_rx_wiretest_pll_cntl_pg , current_group, 0, set_bits); - //set_bits.clearBit(1); + if(rc){return rc;} + + //Reset training start and status bits - as per Rob + rc=GCR_write(master_target , master_interface, ei4_rx_training_start_pg,current_group,0, set_bits, clear_train_bits,1,1); + if(rc){return rc;} + rc=GCR_write(master_target , master_interface, ei4_rx_training_status_pg, current_group,0, set_bits,clear_train_bits,1,1); + if(rc){return rc;} + // Reset Wt PLL as per John G rc=GCR_write(master_target, master_interface, ei4_rx_wiretest_pll_cntl_pg , current_group,0, set_bits, clear_bits,1,1); + if(rc){return rc;} } - + FAPI_DBG("Done Setting TX Drv pattern to 0000 and wt_cu_pll_reset to 0 for DLL workaround "); return rc; @@ -576,7 +619,7 @@ ReturnCode io_run_training(const Target &master_target,const Target &slave_targe // For Xbus DLL Workaround , we need Wiretest alone , then DE and RF edi_training init_w(SELECTED,NOT_RUNNING, NOT_RUNNING, NOT_RUNNING, NOT_RUNNING); // Run W for Xbus - edi_training init_de(SELECTED,SELECTED,SELECTED, NOT_RUNNING, NOT_RUNNING); // Run DE next for X bus + edi_training init_wde(SELECTED,SELECTED,SELECTED, NOT_RUNNING, NOT_RUNNING); // Run DE next for X bus // Need an object to restore object state after one wiretest run. edi_training copy_w=init_w; // DE & RF needs to be split due to HW 220654 @@ -591,23 +634,32 @@ ReturnCode io_run_training(const Target &master_target,const Target &slave_targe // This is a DMI/MC bus - if( (master_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET )&& (slave_target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP)){ + if( (master_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET )&& + (slave_target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP)) + { FAPI_DBG("This is a DMI bus using base DMI scom address"); master_interface=CP_IOMC0_P0; // base scom for MC bus slave_interface=CEN_DMI; // Centaur scom base master_group=3; // Design requires us to do this as per scom map and layout slave_group=0; - rc=fir_workaround_pre_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group, - slave_data_one_old,slave_data_two_old,master_data_one_old,master_data_two_old); + rc=fir_workaround_pre_training(master_target,master_interface,master_group, + slave_target,slave_interface,slave_group, + slave_data_one_old,slave_data_two_old, + master_data_one_old,master_data_two_old); if(rc) return rc; // Workaround - HW 220654 -- Need to split WDERF into WDE + RF due to sync problem - rc=init1.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group); + rc=init1.run_training(master_target,master_interface,master_group, + slave_target,slave_interface,slave_group); if(!rc.ok()){ return rc; } - rc=init2.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group); - rc=fir_workaround_post_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group, - slave_data_one_old,slave_data_two_old,master_data_one_old,master_data_two_old); + rc=init2.run_training(master_target,master_interface,master_group, + slave_target,slave_interface,slave_group); + rc=fir_workaround_post_training(master_target,master_interface, + master_group,slave_target, + slave_interface,slave_group, + slave_data_one_old,slave_data_two_old, + master_data_one_old,master_data_two_old); if(rc) return rc; rc=handle_max_spare(master_target,master_interface,master_group); if(rc) return rc; @@ -616,7 +668,9 @@ ReturnCode io_run_training(const Target &master_target,const Target &slave_targe } //This is an X Bus - else if( (master_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT )&& (slave_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT )){ + else if( (master_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT )&& + (slave_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT )) + { FAPI_DBG("This is a X Bus training invocation"); master_interface=CP_FABRIC_X0; // base scom for X bus slave_interface=CP_FABRIC_X0; // base scom for X bus @@ -636,27 +690,45 @@ ReturnCode io_run_training(const Target &master_target,const Target &slave_targe rc=init.isChipMaster(master_target,master_interface,master_group,is_master); if(rc.ok()){ - if(!is_master){ - //Swap slave and slave targets !! - FAPI_DBG("X Bus ..target swap performed"); - rc=fir_workaround_pre_training(slave_target,slave_interface,slave_group,slave_target,slave_interface,slave_group, - slave_data_one_old,slave_data_two_old,master_data_one_old,master_data_two_old); - if(rc) return rc; - do{ + if(!is_master) + { + //Swap slave and slave targets !! + FAPI_DBG("X Bus ..target swap performed"); + rc=fir_workaround_pre_training(slave_target,slave_interface, + slave_group,slave_target, + slave_interface,slave_group, + slave_data_one_old,slave_data_two_old, + master_data_one_old,master_data_two_old); + if(rc) return rc; + do + { trial_count++; FAPI_DBG("TRAINING TRIAL count=%d",trial_count); - rc=init_w.run_training(slave_target,slave_interface,slave_group,master_target,master_interface,master_group); + rc=init_w.run_training(slave_target,slave_interface, + slave_group,master_target, + master_interface,master_group); if(rc) { //HW249235 --For DLL workaround FAPI_DBG("Starting DLL Workaround"); - rc=check_dll_status_and_modify(slave_target,slave_interface,master_target,master_interface, - dll_slave_array,dll_master_array,dll_workaround_done,dll_workaround_fail); + rc=check_dll_status_and_modify(slave_target, + slave_interface, + master_target, + master_interface, + dll_slave_array, + dll_master_array, + dll_workaround_done, + dll_workaround_fail); if(rc) return rc; // Reset tx drive pattern to 0000 before starting Wiretest again -- As per Rob /Pete //Prep the targets for next round of WDE training -- Steps by Rob & Pete - if(!dll_workaround_done){ - rc=set_tx_drv_pattern(slave_target,slave_interface,slave_group,master_target,master_interface, - master_group); + if(!dll_workaround_done) + { + rc=set_tx_drv_pattern(slave_target, + slave_interface, + slave_group, + master_target, + master_interface, + master_group); } if(rc) return rc; } @@ -668,20 +740,47 @@ ReturnCode io_run_training(const Target &master_target,const Target &slave_targe } init_w=copy_w; }while(!dll_workaround_done); - rc=init_de.run_training(slave_target,slave_interface,slave_group,master_target,master_interface,master_group); - if(rc) return rc; - rc=init2.run_training(slave_target,slave_interface,slave_group,master_target,master_interface,master_group); - rc=fir_workaround_post_training(slave_target,slave_interface,slave_group,slave_target,slave_interface,slave_group, - slave_data_one_old,slave_data_two_old,master_data_one_old,master_data_two_old); - if(rc) return rc; - //HW Defect HW220449 , HW HW247831 - // Set rx_sls_extend_sel=001 on slave side of X bus post training - rc=do_sls_fix(master_target,master_interface); - if(rc) return rc; + if(!dll_workaround_fail){ + // We need to reset Wirtest machine so that we can do WDE again + rc=set_tx_drv_pattern(slave_target,slave_interface, + slave_group,master_target, + master_interface,master_group); + if(rc) return rc; + rc=init_wde.run_training(slave_target,slave_interface, + slave_group,master_target, + master_interface,master_group); + if(rc) return rc; + rc=init2.run_training(slave_target,slave_interface, + slave_group,master_target, + master_interface,master_group); + rc=fir_workaround_post_training(slave_target, + slave_interface, + slave_group, + slave_target, + slave_interface, + slave_group, + slave_data_one_old, + slave_data_two_old, + master_data_one_old, + master_data_two_old); + if(rc) return rc; + //HW Defect HW220449 , HW HW247831 + // Set rx_sls_extend_sel=001 on slave side of X bus post training + rc=do_sls_fix(master_target,master_interface); + if(rc) return rc; + } } else{ - rc=fir_workaround_pre_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group, - master_data_one_old,master_data_two_old,slave_data_one_old,slave_data_two_old); + rc=fir_workaround_pre_training(master_target, + master_interface, + master_group, + slave_target, + slave_interface, + slave_group, + master_data_one_old, + master_data_two_old, + slave_data_one_old, + slave_data_two_old); if(rc) return rc; do{ trial_count++; @@ -710,7 +809,11 @@ ReturnCode io_run_training(const Target &master_target,const Target &slave_targe init_w=copy_w;// Reset training object state to default }while(!dll_workaround_done); if(!dll_workaround_fail){ - rc=init_de.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group); + // We need to reset Wirtest machine so that we can do WDE again + rc=set_tx_drv_pattern(master_target,master_interface,master_group,slave_target,slave_interface, + slave_group); + if(rc) return rc; + rc=init_wde.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group); if(rc) { return rc;} @@ -719,11 +822,12 @@ ReturnCode io_run_training(const Target &master_target,const Target &slave_targe rc=fir_workaround_post_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group, master_data_one_old,master_data_two_old,slave_data_one_old,slave_data_two_old); if(rc) return rc; + + //HW Defect HW220449 , HW HW247831 + // Set rx_sls_extend_sel=001 on slave side of X bus post training + rc=do_sls_fix(slave_target,slave_interface); + if(rc) return rc; } - //HW Defect HW220449 , HW HW247831 - // Set rx_sls_extend_sel=001 on slave side of X bus post training - rc=do_sls_fix(slave_target,slave_interface); - if(rc) return rc; } for(uint32_t current_group=0;current_group<max_group;++current_group){ rc=handle_max_spare(master_target,master_interface,current_group); diff --git a/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C b/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C index 636077eba..7dffc80c6 100644 --- a/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C +++ b/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: cen_mem_startclocks.C,v 1.10 2013/03/04 17:56:29 mfred Exp $ +// $Id: cen_mem_startclocks.C,v 1.11 2013/07/08 13:38:27 mfred Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_mem_startclocks.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -277,7 +277,7 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target) if ( scom_data.getDoubleWord(0) != MEM_CLK_STATUS_REG_EXP_DATA ) { FAPI_ERR("Unexpected clock status! Clk Status Reg 0x03030008 = %16llX, but %16llX was expected.",scom_data.getDoubleWord(0),MEM_CLK_STATUS_REG_EXP_DATA); - FAPI_SET_HWP_ERROR(rc, RC_MSS_UNEXPECTED_CLOCK_STATUS); + FAPI_SET_HWP_ERROR(rc, RC_MSS_UNEXPECTED_MEM_CLK_STATUS); break; } @@ -393,6 +393,9 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target) This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: cen_mem_startclocks.C,v $ +Revision 1.11 2013/07/08 13:38:27 mfred +Change one hwp_error usage from RC_MSS_UNEXPECTED_CLOCK_STATUS to RC_MSS_UNEXPECTED_MEM_CLK_STATUS. + Revision 1.10 2013/03/04 17:56:29 mfred Add some header comments for BACKUP and SCREEN. diff --git a/src/usr/hwpf/hwp/include/common_scom_addresses.H b/src/usr/hwpf/hwp/include/common_scom_addresses.H index b3a5eddd8..7f712c0d5 100755 --- a/src/usr/hwpf/hwp/include/common_scom_addresses.H +++ b/src/usr/hwpf/hwp/include/common_scom_addresses.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: common_scom_addresses.H,v 1.46 2013/05/06 21:03:10 jeshua Exp $ +// $Id: common_scom_addresses.H,v 1.47 2013/07/10 15:30:36 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/common_scom_addresses.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -36,7 +36,7 @@ // The purpose of this header is to define scom addresses for use by procedures. // This will help catch address typos at compile time, and will make it easy // to track down which procedures use each address -// + #ifndef COMMON_SCOM_ADDRESSES #define COMMON_SCOM_ADDRESSES @@ -123,6 +123,18 @@ CONST_UINT64_T( GENERIC_GP0_AND_0x00000004 , ULL(0x00000004) ); CONST_UINT64_T( GENERIC_GP0_OR_0x00000005 , ULL(0x00000005) ); //------------------------------------------------------------------------------ +// GENERIC DEBUG +//------------------------------------------------------------------------------ +CONST_UINT64_T( GENERIC_DBG_MODE_REG_0x000107C0 , ULL(0x000107C0) ); +CONST_UINT64_T( GENERIC_DBG_INST1_COND_REG1_0x000107C1 , ULL(0x000107C1) ); +CONST_UINT64_T( GENERIC_DBG_INST1_COND_REG2_0x000107C2 , ULL(0x000107C2) ); +CONST_UINT64_T( GENERIC_DBG_INST2_COND_REG1_0x000107C3 , ULL(0x000107C3) ); +CONST_UINT64_T( GENERIC_DBG_INST2_COND_REG2_0x000107C4 , ULL(0x000107C4) ); +CONST_UINT64_T( GENERIC_DBG_TRACE_REG0_0x000107C9 , ULL(0x000107C9) ); +CONST_UINT64_T( GENERIC_DBG_TRACE_REG1_0x000107CA , ULL(0x000107CA) ); +CONST_UINT64_T( GENERIC_DBG_TRACE_REG2_0x000107CB , ULL(0x000107CB) ); + +//------------------------------------------------------------------------------ // GENERIC CLOCK CONTROL //------------------------------------------------------------------------------ CONST_UINT64_T( GENERIC_OPCG_CNTL0_0x00030002 , ULL(0x00030002) ); @@ -621,6 +633,9 @@ This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: common_scom_addresses.H,v $ +Revision 1.47 2013/07/10 15:30:36 jmcgill +add entries for SCOM debug resources + Revision 1.46 2013/05/06 21:03:10 jeshua Added GENERIC_PCB_ERR_0x000F001F diff --git a/src/usr/hwpf/hwp/initfiles/mba_def.initfile b/src/usr/hwpf/hwp/initfiles/mba_def.initfile index f69cc6400..9985b7014 100644 --- a/src/usr/hwpf/hwp/initfiles/mba_def.initfile +++ b/src/usr/hwpf/hwp/initfiles/mba_def.initfile @@ -1,9 +1,12 @@ -#-- $Id: mba_def.initfile,v 1.44 2013/05/06 15:28:35 yctschan Exp $ +#-- $Id: mba_def.initfile,v 1.46 2013/07/17 18:23:53 yctschan Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.46|tschang | 7/17/13|updated refresh interval and refresh check interval calculations +#-- 1.45|tschang | 6/04/13|using ATTR_EFF_DRAM_RRD, etc timing parms for settings +#-- setting RD ODT according to Menlo's equation #-- 1.44|tschang | 5/06/13|added 2n_mode to timing parms equations #-- 1.43|tschang | 5/01/13|def_refresh_interval optimized to avoid divide by 0 condition #-- 1.42|tschang | 5/01/13|cfg_min_domain_reduction disabled as requested by performance team @@ -1983,10 +1986,7 @@ scom 0x0301040B { 48:51 , 0b1001 + def_margin2 , 1 , (CENTAUR.ATTR_MSS_FREQ == 2400); # WWDM_dly 12 D 52:55 , 0b0100 + def_margin2 , 1 , any; # RROP_dly is 4 for all cfgs 13 D 56:59 , 0b0100 + def_margin2 , 1 , any; # WWOP_dly is 4 for all cfgs 14 D - 60:63 , 0b0100 + def_margin2 , 1 , (def_MBA_TMR0Q_Trrd_dly4 == 1); # TMR0Q_Trrd 15 - 60:63 , 0b0101 + def_margin2 , 1 , (def_MBA_TMR0Q_Trrd_dly5 == 1); # TMR0Q_Trrd 15 - 60:63 , 0b0110 + def_margin2 , 1 , (def_MBA_TMR0Q_Trrd_dly6 == 1); # TMR0Q_Trrd 15 - 60:63 , 0b0111 + def_margin2 , 1 , (def_MBA_TMR0Q_Trrd_dly7 == 1); # TMR0Q_Trrd 15 + 60:63 , ATTR_EFF_DRAM_TRRD , 1 , any; # TMR0Q_Trrd } # MBA_TMR1Q mba01 timer settings @@ -2018,6 +2018,7 @@ scom 0x0301040C { 7:13 , 0b0110001 , 1 , (def_mba_tmr1q_cfg_twap49 == 1); # cfg_twap 17 7:13 , 0b0110011 , 1 , (def_mba_tmr1q_cfg_twap51 == 1); # cfg_twap 17 7:13 , 0b0110101 , 1 , (def_mba_tmr1q_cfg_twap53 == 1); # cfg_twap 17 +# 14:19 , ATTR_EFF_DRAM_TFAW, 1 , any; # cfg_tfaw # uncomment when Anuwat has added in fix 14:19 , 0b010100 , 1 , (def_mba_tmr1q_cfg_tfaw_dly20 == 1); # cfg_tfaw 18 14:19 , 0b010110 , 1 , (def_mba_tmr1q_cfg_tfaw_dly22 == 1); # cfg_tfaw 18 14:19 , 0b010111 , 1 , (def_mba_tmr1q_cfg_tfaw_dly23 == 1); # cfg_tfaw 18 @@ -2056,6 +2057,11 @@ define def_WL_AL0 = (ATTR_EFF_DRAM_CWL - 7); define def_WL_AL_MINUS1 = (ATTR_EFF_DRAM_CWL + ATTR_EFF_DRAM_CL - 1 - 7); define def_WL_AL_MINUS2 = (ATTR_EFF_DRAM_CWL + ATTR_EFF_DRAM_CL - 2 - 7); +define def_RDODT_start_udimm = (ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_CWL + 1); +define def_RDODT_start_rdimm = (ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_CWL + 2); +define def_RDODT_start_lrdimm = (ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_CWL + 6); +define def_RDODT_duration = (5); + # MBA_DSM0Q mba01 data state machine settings #< B0.C0.M00A.CENTAUR.MBU.MBA01.MBA_SRQ.MBA_DSM0Q(0:63) = 0x0870466094038800 #> B0.C0.M00A.CENTAUR.MBU.MBA01.MBA_SRQ.MBA_DSM0Q(0:63) = 0x08704660A4838800 @@ -2063,18 +2069,14 @@ define def_WL_AL_MINUS2 = (ATTR_EFF_DRAM_CWL + ATTR_EFF_DRAM_CL - 2 - 7); scom 0x0301040A { bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:5 , 0b000000 , 1 , (def_mba_dsm0q_CFG_RODT_start_dly0 == 1); # CFG_RODT_start_dly 21 - 0:5 , 0b000001 , 1 , (def_mba_dsm0q_CFG_RODT_start_dly1 == 1); # CFG_RODT_start_dly 21 - 0:5 , 0b000010 , 1 , (def_mba_dsm0q_CFG_RODT_start_dly2 == 1); # CFG_RODT_start_dly 21 - 0:5 , 0b000011 , 1 , (def_mba_dsm0q_CFG_RODT_start_dly3 == 1); # CFG_RODT_start_dly 21 - 0:5 , 0b000100 , 1 , (def_mba_dsm0q_CFG_RODT_start_dly4 == 1); # CFG_RODT_start_dly 21 - 6:11 , 0b000101 , 1 , (def_mba_dsm0q_CFG_RODT_end_dly5 == 1); # CFG_RODT_end_dly 22 - 6:11 , 0b000110 , 1 , (def_mba_dsm0q_CFG_RODT_end_dly6 == 1); # CFG_RODT_end_dly 22 - 6:11 , 0b000111 , 1 , (def_mba_dsm0q_CFG_RODT_end_dly7 == 1); # CFG_RODT_end_dly 22 - 6:11 , 0b001000 , 1 , (def_mba_dsm0q_CFG_RODT_end_dly8 == 1); # CFG_RODT_end_dly 22 - 6:11 , 0b001001 , 1 , (def_mba_dsm0q_CFG_RODT_end_dly9 == 1); # CFG_RODT_end_dly 22 - 12:17 , 0b000000 , 1 , any; # CFG_WODT_start_dly is 1 for all cfgs 23 D - 18:23 , 0b000101 , 1 , any; # CFG_WODT_end_dly is 6 for all cfgs 24 D + 0:5 , def_RDODT_start_udimm , 1 , (ATTR_EFF_DIMM_TYPE == 0) && (ATTR_EFF_DIMM_TYPE == 2); # CFG_RODT_start_dly 21 + 0:5 , def_RDODT_start_rdimm , 1 , (ATTR_EFF_DIMM_TYPE == 1); # CFG_RODT_start_dly 21 + 0:5 , def_RDODT_start_lrdimm , 1 , (ATTR_EFF_DIMM_TYPE == 3); # CFG_RODT_start_dly 21 + 6:11 , def_RDODT_start_udimm + def_RDODT_duration , 1 , (ATTR_EFF_DIMM_TYPE == 0) && (ATTR_EFF_DIMM_TYPE == 2); # CFG_RODT_end_dly 22 + 6:11 , def_RDODT_start_rdimm + def_RDODT_duration , 1 , (ATTR_EFF_DIMM_TYPE == 1); # CFG_RODT_end_dly 22 + 6:11 , def_RDODT_start_lrdimm + def_RDODT_duration , 1 , (ATTR_EFF_DIMM_TYPE == 3); # CFG_RODT_end_dly 22 + 12:17 , 0b000000 , 1 , any; # CFG_WODT_start_dly is 0 for all cfgs 23 D + 18:23 , 0b000101 , 1 , any; # CFG_WODT_end_dly is 5 for all cfgs 24 D 24:29 , 0b011000 , 1 , any; # wrdone_dly is 24 for all cfgs 25 D 30:35 , def_WL_AL0 + 1 , 1 , (((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 3)) && (ATTR_EFF_DRAM_AL == 0)); # wrdata_dly 30:35 , def_WL_AL0 , 1 , (((ATTR_EFF_DIMM_TYPE == 0) || (ATTR_EFF_DIMM_TYPE == 2)) && (ATTR_EFF_DRAM_AL == 0)); # wrdata_dly @@ -2100,31 +2102,34 @@ scom 0x0301040A { 36:41 , 0b011011 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly27 == 1); # rdtag_dly 27 36:41 , 0b011100 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly28 == 1); # rdtag_dly 27 36:41 , 0b011101 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly29 == 1); # rdtag_dly 27 - 43:48 , 0b000101 , 1 , (def_mba_dsm0q_CFG_RODT_BC4_END_DLY5 == 1); # CFG_RODT_BC4_END_DLY 28 - 43:48 , 0b000110 , 1 , (def_mba_dsm0q_CFG_RODT_BC4_END_DLY6 == 1); # CFG_RODT_BC4_END_DLY 28 - 43:48 , 0b000111 , 1 , (def_mba_dsm0q_CFG_RODT_BC4_END_DLY7 == 1); # CFG_RODT_BC4_END_DLY 28 - 43:48 , 0b001000 , 1 , (def_mba_dsm0q_CFG_RODT_BC4_END_DLY8 == 1); # CFG_RODT_BC4_END_DLY 28 - 43:48 , 0b001001 , 1 , (def_mba_dsm0q_CFG_RODT_BC4_END_DLY9 == 1); # CFG_RODT_BC4_END_DLY 28 - 49:54 , 0b000100 , 1 , any; # CFG_WODT_BC4_END_DLY is 4 for all cfgs 29 D + 43:48 , def_RDODT_start_udimm + def_RDODT_duration - 2 , 1 , (ATTR_EFF_DIMM_TYPE == 0) && (ATTR_EFF_DIMM_TYPE == 2); # CFG_RODT_BC4_END_DLY 28 + 43:48 , def_RDODT_start_rdimm + def_RDODT_duration - 2 , 1 , (ATTR_EFF_DIMM_TYPE == 1); # CFG_RODT_BC4_END_DLY 28 + 43:48 , def_RDODT_start_lrdimm + def_RDODT_duration - 2 , 1 , (ATTR_EFF_DIMM_TYPE == 3); # CFG_RODT_BC4_END_DLY 28 + 49:54 , 0b000011 , 1 , any; # CFG_WODT_BC4_END_DLY is 3 for all cfgs 29 D } ## Refresh Interval Calculuation -## refresh_interval = ((ATTR_EFF_DRAM_TRFI/(def_num_ranks/2))/8); -define def_num_ranks = (ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[0][1] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][1]); -define def_refresh_interval = ((2*ATTR_EFF_DRAM_TRFI)/(8*def_num_ranks)); +## refresh_interval = ((ATTR_EFF_DRAM_TRFI/(def_num_ranks))/8); +#define def_num_ranks = (ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[0][1] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][1]); +define def_mba01_num_ranks = (ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[0][1]); +define def_mba23_num_ranks = (ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][1]); +define def_mba01_refresh_interval = ((ATTR_EFF_DRAM_TRFI)/(8*def_mba01_num_ranks)); +define def_mba23_refresh_interval = ((ATTR_EFF_DRAM_TRFI)/(8*def_mba23_num_ranks)); +define def_refresh_check_interval = (ATTR_EFF_DRAM_TRFI/8); # same for both mba01 and mba23 # MBAREF0Q mba01 refresh settings # scom 0x03010432 { bits , scom_data , ATTR_FUNCTIONAL, expr; 4:7 , 0b0111 , 1 , any; # MBAREF0Q_refresh priority threshold is 0x7 for all cfgs 30 ?# refresh interval = tREFI(7.8) / # ranks per port / DRAM clk(ns) / 0.008 - 8:18 , def_refresh_interval, 1 , any; # MBAREF0Q_refresh intveral set to 176 decimal 31 ? !!FIXME# reset check interval = tREFI(7.8) / DRAM clk(ns) / 0.008 + 8:18 , def_mba01_refresh_interval, 1 , ATTR_CHIP_UNIT_POS == 0; # see calculation above + 8:18 , def_mba23_refresh_interval, 1 , ATTR_CHIP_UNIT_POS == 1; # see calculation above 19:29 , 0b00011000010, 1 , any; # MBAREF0Q_refresh reset interval set to 194 decimal 32 ? !!FIXME 30:39 , ATTR_EFF_DRAM_TRFC, 1 , any; # MBAREF0Q_cfg_trfc 33 40:49 , 0b0000100000 , 1 , (def_MBAREF0Q_cfg_refr_tsv_stack_dly32 == 1); # MBAREF0Q_cfg_refr_tsv_stack 33 40:49 , 0b0000110000 , 1 , (def_MBAREF0Q_cfg_refr_tsv_stack_dly48 == 1); # MBAREF0Q_cfg_refr_tsv_stack 33 40:49 , 0b0001000000 , 1 , (def_MBAREF0Q_cfg_refr_tsv_stack_dly64 == 1); # MBAREF0Q_cfg_refr_tsv_stack 33 - 50:60 , 0b01100001100, 1 , any; # MBAREF0Q_refresh check intveral set to 780 decimal 35 + 50:60 , def_refresh_check_interval, 1 , any; # MBAREF0Q_refresh check intveral set to 780 decimal 35 } # MBAPC0Q power control settings reg 1 diff --git a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile index 73e583ae7..240245a94 100644 --- a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile +++ b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile @@ -1,9 +1,14 @@ -#-- $Id: mbs_def.initfile,v 1.31 2013/04/17 14:41:41 yctschan Exp $ +#-- $Id: mbs_def.initfile,v 1.36 2013/07/08 14:37:16 yctschan Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- -#-- 1.30 |tschang |04/17/13| hash mode updated for type 1a/1b/5b +#-- 1.36 |tschang |07/03/13| L4.ATTR_FUNCTIONAL for cache enable for some bits I missed +#-- 1.35 |tschang |07/02/13| L4.ATTR_FUNCTIONAL for cache enable +#-- 1.34 |tschang |06/11/13| removed mask out bit 8 - internal parity error - HW244827 and HW251643 +#-- 1.33 |tschang |06/06/13| mask out bit 8 - internal parity error - HW244827 and HW251643 +#-- 1.32 |tschang |04/24/13| fixed 1d cfg type +#-- 1.31 |tschang |04/17/13| hash mode updated for type 1a/1b/5b #-- 1.30 |tschang |04/16/13| updated file for new IBM_TYPE defnitions #-- 1.29 |tschang |04/08/13| added MBI cfg register initialization for Irving #-- 1.26 |tschang |03/13/13| changed cache interleave mode to have ATTR_MSS_CACHE_ENABLE as a condition @@ -78,6 +83,8 @@ define def_equal_test = (SYS.ATTR_SCRATCH_UINT32_1 == SYS.ATTR_SCRATCH_UINT define MBA0 = TGT1; define MBA1 = TGT2; +define L4 = TGT3; + # MBA0.ATTR_CHIP_UNIT_POS - that should equal 0 # MBA1.ATTR_CHIP_UNIT_POS should equal @@ -106,17 +113,19 @@ define def_mba01_1b_2socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 2 ))) ## 1C 1 and 2 sockets not supported #define def_mba01_1c_1socket = 0; #define def_mba01_1c_2socket = 0; -define def_mba01_1c_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba01_1c_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba01_1c_cdimm = ((((MBA0.ATTR_CHIP_UNIT_POS == 1 ) && (MBA0.ATTR_EFF_IBM_TYPE[1][0] == 3 )) || ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 3 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type1B 2 socket RDIMM cfg for DDR3/4 +#define def_mba01_1c_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false +#define def_mba01_1c_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false +define def_mba01_1c_1socket = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 3 ) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || def_mba01_1d_1socket; +define def_mba01_1c_2socket = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 3 ) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || def_mba01_1d_2socket; +define def_mba01_1c_cdimm = (((MBA0.ATTR_EFF_IBM_TYPE[1][0] == 3 ) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 3 )) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type1B 2 socket RDIMM cfg for DDR3/4 ## Current they is no 1D IBM type in the attribute #define def_mba01_1d_1socket = 0; #define def_mba01_1d_2socket = 0; #define def_mba01_1d_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false #define def_mba01_1d_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba01_1d_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -define def_mba01_1d_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); +define def_mba01_1d_1socket = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4 ) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); +define def_mba01_1d_2socket = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4 ) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); ## note the CDIMMs 2A-2C CDIMMs are wired just like the single slot ISDIMMs define def_mba01_2a_1socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2a_cdimm)); @@ -202,8 +211,10 @@ define def_mba23_1b_2socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2 ))) ## 1C 1 and 2 sockets not supported #define def_mba23_1c_1socket = 0; #define def_mba23_1c_2socket = 0; -define def_mba23_1c_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba23_1c_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false +#define def_mba23_1c_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false +#define def_mba23_1c_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false +define def_mba23_1c_1socket = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 3 ) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || def_mba23_1d_1socket; +define def_mba23_1c_2socket = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 3 ) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || def_mba23_1d_2socket; define def_mba23_1c_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 3 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type1B 2 socket RDIMM cfg for DDR3/4 ## Current they is no 1D IBM type in the attribute @@ -211,8 +222,8 @@ define def_mba23_1c_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 3 ))) & #define def_mba23_1d_2socket = 0; #define def_mba23_1d_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false #define def_mba23_1d_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -#efine def_mba23_1d_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -#efine def_mba23_1d_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); +define def_mba23_1d_1socket = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4 ) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); +define def_mba23_1d_2socket = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4 ) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); ## note the CDIMMs 2A-2C CDIMMs are wired just like the single slot ISDIMMs define def_mba23_2a_1socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2a_cdimm)); @@ -394,6 +405,16 @@ define def_mba23_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated = (def_mb #define def_01ATTR_EFF_MBA_POS = 0; # -MW not needed? #define def_23ATTR_EFF_MBA_POS = 1; # -MW not needed? +#--****************************************************************************** +#-- MBS FIR MASK Register +#--****************************************************************************** +# scom 0x02011403 { +# bits , scom_data ; +# 8 , 0b1 ; # int_parity_error - HW244827 and HW251643 +# +# } + + # YCT added for Irving #--****************************************************************************** #-- MBI Configuration Register @@ -470,12 +491,11 @@ scom 0x02011411 { # MBCCFGQ MBC Configuration Register scom 0x0201140F { bits, scom_data , expr; - 0 , 0b0 , (ATTR_MSS_CACHE_ENABLE == 0); # MBCCFGQ_cache_enable - 0 , 0b1 , (ATTR_MSS_CACHE_ENABLE != 0); # MBCCFGQ_cache_enable -# 1 , 0b0 , any ; # -MW match dials + 0 , 0b0 , (L4.ATTR_FUNCTIONAL == 0) || (ATTR_MSS_CACHE_ENABLE == 0); # MBCCFGQ_cache_enable + 0 , 0b1 , (L4.ATTR_FUNCTIONAL == 1) && (ATTR_MSS_CACHE_ENABLE != 0); # MBCCFGQ_cache_enable 1 , 0b0 , any ; # MBCCFGQ_cfg_dyn_whap_en - 2 , 0b0 , ((SYS.ATTR_MSS_CLEANER_ENABLE == 0) || (ATTR_MSS_CACHE_ENABLE != 1)); # MBCCFGQ_cleaner_enable - 2 , 0b1 , ((SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (ATTR_MSS_CACHE_ENABLE == 1)); # MBCCFGQ_cleaner_enable + 2 , 0b0 , ((SYS.ATTR_MSS_CLEANER_ENABLE == 0) || ((L4.ATTR_FUNCTIONAL == 0) || (ATTR_MSS_CACHE_ENABLE == 0))); # MBCCFGQ_cleaner_enable + 2 , 0b1 , ((SYS.ATTR_MSS_CLEANER_ENABLE == 1) && ((L4.ATTR_FUNCTIONAL == 1) && (ATTR_MSS_CACHE_ENABLE != 0))); # MBCCFGQ_cleaner_enable 3 , 0b0 , any ; # MBCCFGQ_cache_only_enable 4 , 0b0 , any ; # MBCCFGQ_lru_dmap_en 5 , 0b0 , any ; # MBCCFGQ_lru_random_en @@ -610,8 +630,8 @@ scom 0x0201140B { # 10:11 , 0b00 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 0); # MBAXCR01Q_MBA01_Hash_Mode # 10:11 , 0b01 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 1); # MBAXCR01Q_MBA01_Hash_Mode # 10:11 , 0b10 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 2); # MBAXCR01Q_MBA01_Hash_Mode - 12 , 0b0 , 1 , ((SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 0) || (ATTR_MSS_CACHE_ENABLE != 1)); # MBAXCR01Q_MBA01_Interleave_Mode - 12 , 0b1 , 1 , ((SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 1) && (ATTR_MSS_CACHE_ENABLE == 1)); # MBAXCR01Q_MBA01_Interleave_Mod + 12 , 0b0 , 1 , ((SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 0) || ((L4.ATTR_FUNCTIONAL == 0) || (ATTR_MSS_CACHE_ENABLE == 0))); # MBAXCR01Q_MBA01_Interleave_Mode + 12 , 0b1 , 1 , ((SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 1) && ((L4.ATTR_FUNCTIONAL == 1) && (ATTR_MSS_CACHE_ENABLE != 0))); # MBAXCR01Q_MBA01_Interleave_Mod } diff --git a/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile index 0c3d2ed1f..f51f1f319 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: p8.dmi.scom.initfile,v 1.17 2013/04/18 19:13:44 jgrell Exp $ +#-- $Id: p8.dmi.scom.initfile,v 1.22 2013/07/30 20:45:32 jgrell Exp $ #################################################################### @@ -7,14 +7,18 @@ ## Based on SETUP_ID_MODE DMI_BUS_TR_HW ## from ../../logic/mesa_sim/fusion/run/IODPV_MC_WRAP.IODPV_MC_WRAP.figdb ## -## Created on Mon Apr 15 15:03:50 CDT 2013, by jgrell +## Created on Tue Jul 30 10:22:10 CDT 2013, by jgrell #################################################################### ## -- CHANGE HISTORY: ## -------------------------------------------------------------------------------- ## -- VersionID: |Author: | Date: | Comment: ## -- -----------|---------|--------|------------------------------------------------- + ## -- jfg13072400| jfg |07-24-13| HW253558: change pgooddly to MAX from lab feedback + ## -- mbs13071200| mbs |07-12-13| Updates for HW239870 and HW258990 + ## -- | | | Disable recal adjustment for allv1 (DFE bug) ## -- jgr13041800| jgr |04-18-13| Added rx_max_ber_check_count setting to 0x03 + ## -- smr13032500| SMR |03-25-13| Changed rx_dyn_recal_overall_timeout_sel init to 0b100 & rx_sls_timeout_sel init to 0b110 ## -- jgr13031300| jgr |03-13-13| Added missing entries from rel 0128 ## -- mbs13011802| mbs |01-18-13| Added rx_fence to run_mode dial (HW236326) ## -- mbs12121100| mbs |12-11-12| Added rx_prot_speed_slct and rx_c4_sel @@ -66,8 +70,8 @@ include edi.io.define define def_bus_id3 = ((ATTR_CHIP_UNIT_POS == 0) || (ATTR_CHIP_UNIT_POS == 4)); define def_bus_id2 = ((ATTR_CHIP_UNIT_POS == 1) || (ATTR_CHIP_UNIT_POS == 5)); -define def_bus_id1 = ((ATTR_CHIP_UNIT_POS == 2) || (ATTR_CHIP_UNIT_POS == 7)); -define def_bus_id0 = ((ATTR_CHIP_UNIT_POS == 3) || (ATTR_CHIP_UNIT_POS == 6)); +define def_bus_id1 = ((ATTR_CHIP_UNIT_POS == 3) || (ATTR_CHIP_UNIT_POS == 7)); +define def_bus_id0 = ((ATTR_CHIP_UNIT_POS == 2) || (ATTR_CHIP_UNIT_POS == 6)); @@ -93,19 +97,19 @@ scom 0x800AF06002011A3F { #RX3.RXCTL.RX_CTL_REGS.RX_DFE_CONFIG_PP scom 0x800B786002011A3F { bits, scom_data, expr; - rx_amin_cfg, 0b010, def_IS_HW && def_bus_id3; - rx_amin_cfg, 0b010, def_IS_HW && def_bus_id0; + rx_amin_cfg, 0b111, def_IS_HW && def_bus_id3; + rx_amin_cfg, 0b111, def_IS_HW && def_bus_id0; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_amin_cfg, 0b010, def_IS_HW && def_bus_id1; + rx_amin_cfg, 0b111, def_IS_HW && def_bus_id1; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_amin_cfg, 0b010, def_IS_HW && def_bus_id2; + rx_amin_cfg, 0b111, def_IS_HW && def_bus_id2; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id3; - rx_amin_cfg, 0b010, def_IS_HW && def_bus_id0; + rx_amin_cfg, 0b111, def_IS_HW && def_bus_id0; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_amin_cfg, 0b010, def_IS_HW && def_bus_id1; + rx_amin_cfg, 0b111, def_IS_HW && def_bus_id1; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_amin_cfg, 0b010, def_IS_HW && def_bus_id2; + rx_amin_cfg, 0b111, def_IS_HW && def_bus_id2; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_anap_cfg, 0b10, def_IS_HW && def_bus_id3; rx_anap_cfg, 0b10, def_IS_HW && def_bus_id0; @@ -121,20 +125,20 @@ scom 0x800B786002011A3F { rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id1; rx_anap_cfg, 0b10, def_IS_HW && def_bus_id2; rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id2; - rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id3; - rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id0; - rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id1; - rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id2; - rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id2; - rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id3; - rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id0; - rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id1; - rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id2; - rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id2; + rx_h1_cfg, 0b01, def_IS_HW && def_bus_id3; + rx_h1_cfg, 0b01, def_IS_HW && def_bus_id0; + rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id0; + rx_h1_cfg, 0b01, def_IS_HW && def_bus_id1; + rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id1; + rx_h1_cfg, 0b01, def_IS_HW && def_bus_id2; + rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id2; + rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id3; + rx_h1_cfg, 0b01, def_IS_HW && def_bus_id0; + rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id0; + rx_h1_cfg, 0b01, def_IS_HW && def_bus_id1; + rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id1; + rx_h1_cfg, 0b01, def_IS_HW && def_bus_id2; + rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id2; rx_peak_cfg, 0b10, def_IS_HW && def_bus_id3; rx_peak_cfg, 0b10, def_IS_HW && def_bus_id0; rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id0; @@ -154,19 +158,61 @@ scom 0x800B786002011A3F { #RX3.RXCTL.RX_CTL_REGS.RX_DFE_TIMERS_PP scom 0x800B806002011A3F { bits, scom_data, expr; - rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id3; - rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id0; + rx_ber_cfg, 0b100, def_IS_HW && def_bus_id3; + rx_ber_cfg, 0b100, def_IS_HW && def_bus_id0; + rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id0; + rx_ber_cfg, 0b100, def_IS_HW && def_bus_id1; + rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id1; + rx_ber_cfg, 0b100, def_IS_HW && def_bus_id2; + rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id2; + rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id3; + rx_ber_cfg, 0b100, def_IS_HW && def_bus_id0; + rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id0; + rx_ber_cfg, 0b100, def_IS_HW && def_bus_id1; + rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id1; + rx_ber_cfg, 0b100, def_IS_HW && def_bus_id2; + rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id2; + rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id3; + rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id0; + rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id0; + rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id1; + rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id1; + rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id2; + rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id2; + rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id3; + rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id0; + rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id0; + rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id1; + rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id1; + rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id2; + rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id2; + rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id3; + rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id0; + rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id0; + rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id1; + rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id1; + rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id2; + rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id2; + rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id3; + rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id0; + rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id0; + rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id1; + rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id1; + rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id2; + rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id2; + rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id3; + rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id0; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id1; + rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id1; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id2; + rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id2; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id3; - rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id0; + rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id0; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id1; + rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id1; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id2; + rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id2; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_prot_cfg, 0b10, def_IS_HW && def_bus_id3; rx_prot_cfg, 0b10, def_IS_HW && def_bus_id0; @@ -187,10 +233,19 @@ scom 0x800B806002011A3F { #RX3.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_CONFIG_PG scom 0x800A186002011A3F { bits, scom_data, expr; - rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id3; - rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id0; - rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id1; - rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id2; + rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id3; + rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id0; + rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id1; + rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id2; +} + +#RX3.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_TIMEOUTS_PP +scom 0x800B406002011A3F { + bits, scom_data, expr; + rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id3; + rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id0; + rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id1; + rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG @@ -458,25 +513,6 @@ scom 0x8009C06002011A3F { rx_prot_speed_slct, 0b0, def_IS_VBU && def_bus_id2; } -#RX3.RXCTL.RX_CTL_REGS.RX_MODE1_PP -scom 0x800B086002011A3F { - bits, scom_data, expr; - rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id3; - rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id0; - rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id0; - rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id1; - rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id1; - rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id2; - rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id2; - rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id3; - rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id0; - rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id0; - rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id1; - rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id1; - rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id2; - rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id2; -} - #RX3.RXCTL.RX_CTL_REGS.RX_MODE_PG scom 0x8008186002011A3F { bits, scom_data, expr; @@ -531,34 +567,14 @@ scom 0x800AB86002011A3F { rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id3; - rx_rc_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id3; - rx_rc_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id3; - rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id3; - rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id2; + rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id3; + rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id0; + rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id1; + rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id2; + rx_rc_enable_h1ap_tweak, 0b0, def_bus_id3; + rx_rc_enable_h1ap_tweak, 0b0, def_bus_id0; + rx_rc_enable_h1ap_tweak, 0b0, def_bus_id1; + rx_rc_enable_h1ap_tweak, 0b0, def_bus_id2; rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id3; rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id0; rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id0; @@ -603,108 +619,141 @@ scom 0x800AB86002011A3F { rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2; } +#RX3.RXCTL.RX_CTL_REGS.RX_RECAL_TO1_PP +scom 0x800B906002011A3F { + bits, scom_data, expr; + rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id3; + rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id0; + rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; + rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id3; + rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id0; + rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; +} + #RX3.RXCTL.RX_CTL_REGS.RX_RECAL_TO2_PP scom 0x800B986002011A3F { bits, scom_data, expr; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id3; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id0; + rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id0; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id3; + rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; + rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id3; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id0; + rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id0; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id3; - rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; + rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id3; + rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id3; - rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_RECAL_TO3_PP scom 0x800BA06002011A3F { bits, scom_data, expr; - rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id3; - rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id3; + rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id3; - rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id3; - rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id3; - rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id2; + rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id3; + rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0; + rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; + rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id3; + rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0; + rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; + rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id3; + rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id0; + rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2; + rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id3; + rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id0; + rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP scom 0x800B606002011A3F { bits, scom_data, expr; - rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id3; - rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id0; + rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id3; + rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id0; + rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id0; + rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; + rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; + rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id3; + rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id0; + rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id0; + rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; + rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; + rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id3; + rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id3; - rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id0; + rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP scom 0x800B686002011A3F { bits, scom_data, expr; - rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id3; - rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id3; - rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id3; rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id0; @@ -719,19 +768,19 @@ scom 0x800B686002011A3F { rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id3; - rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id0; + rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id3; + rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id3; - rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id0; + rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; } @@ -752,19 +801,19 @@ scom 0x800B706002011A3F { rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id3; - rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id0; + rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id3; + rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id3; - rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id0; + rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id3; rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id0; @@ -888,10 +937,10 @@ scom 0x8008986002011A3F { rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id1; rx_ds_timeout_sel, 0b110, def_IS_HW && def_bus_id2; rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id2; - rx_sls_timeout_sel, 0b001, def_bus_id3; - rx_sls_timeout_sel, 0b001, def_bus_id0; - rx_sls_timeout_sel, 0b001, def_bus_id1; - rx_sls_timeout_sel, 0b001, def_bus_id2; + rx_sls_timeout_sel, 0b110, def_bus_id3; + rx_sls_timeout_sel, 0b110, def_bus_id0; + rx_sls_timeout_sel, 0b110, def_bus_id1; + rx_sls_timeout_sel, 0b110, def_bus_id2; rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id3; rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id0; rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id0; @@ -933,19 +982,19 @@ scom 0x8009586002011A3F { #RX3.RXCTL.RX_CTL_REGS.RX_WIRETEST_PLL_CNTL_PG scom 0x800A306002011A3F { bits, scom_data, expr; - rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id3; - rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id0; + rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id3; + rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id0; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id0; - rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id1; + rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id1; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id1; - rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id2; + rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id2; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id2; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id3; - rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id0; + rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id0; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id0; - rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id1; + rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id1; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id1; - rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id2; + rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id2; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id2; rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id3; rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id0; @@ -1188,6 +1237,15 @@ scom 0x800CC46002011A3F { tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id2; } +#TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_DYN_RECAL_TIMEOUTS_PP +scom 0x800EAC6002011A3F { + bits, scom_data, expr; + tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id3; + tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id0; + tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id1; + tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id2; +} + #TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_ID1_PG scom 0x800C946002011A3F { bits, scom_data, expr; diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.C index e754d482c..67dc21d8b 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_bulk_pwr_throttles.C,v 1.11 2012/12/12 20:10:41 pardeik Exp $ +// $Id: mss_bulk_pwr_throttles.C,v 1.13 2013/07/22 14:10:45 pardeik Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/ // centaur/working/procedures/ipl/fapi/mss_bulk_pwr_throttles.C,v $ //------------------------------------------------------------------------------ @@ -70,6 +70,13 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.13 | pardeik |19-JUL-13| removed code to identify if throttles are +// | | | based on thermal or power reasons since the +// | | | runtime throttles will now be determined +// | | | whenever mss_eff_config_thermal runs +// 1.12 | pardeik |08-JUL-13| Update to use CUSTOM_DIMM instead of DIMM_TYPE +// | | | removed incrementing of throttle denominator +// | | | set throttle per_mba at end of procedure // 1.11 | pardeik |04-DEC-12| update lines to have a max width of 80 chars // | | | added FAPI_ERR before return code lines // | | | made trace statements for procedure FAPI_IMP @@ -125,7 +132,9 @@ extern "C" { //------------------------------------------------------------------------------ // Funtions in this file //------------------------------------------------------------------------------ - fapi::ReturnCode mss_bulk_pwr_throttles(const fapi::Target & i_target_mba); + fapi::ReturnCode mss_bulk_pwr_throttles( + const fapi::Target & i_target_mba + ); //------------------------------------------------------------------------------ @@ -137,21 +146,16 @@ extern "C" { // @return fapi::ReturnCode //------------------------------------------------------------------------------ - fapi::ReturnCode mss_bulk_pwr_throttles(const fapi::Target & i_target_mba) + fapi::ReturnCode mss_bulk_pwr_throttles(const fapi::Target & i_target_mba + ) { fapi::ReturnCode rc; char procedure_name[32]; sprintf(procedure_name, "mss_bulk_pwr_throttles"); - FAPI_IMP("*** Running %s ***", procedure_name); + FAPI_IMP("*** Running %s on %s ***", procedure_name, + i_target_mba.toEcmdString()); - enum - { - CDIMM = fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM, - RDIMM = fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, - UDIMM = fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM, - LRDIMM = fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM, - }; // other variables used in this procedure const uint8_t MAX_NUM_PORTS = 2; @@ -182,18 +186,18 @@ extern "C" { bool not_enough_available_power; bool channel_pair_throttle_done; float channel_pair_power; - uint8_t dimm_type; + uint8_t custom_dimm; uint8_t num_mba_with_dimms; uint32_t power_int_array[MAX_NUM_PORTS][MAX_NUM_DIMMS]; - bool thermal_throttle_active; uint8_t mba_index; // Get input attributes - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, dimm_type); + rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, custom_dimm); if (rc) { - FAPI_ERR("Error getting attribute ATTR_EFF_DIMM_TYPE"); + FAPI_ERR("Error getting attribute ATTR_EFF_CUSTOM_DIMM"); return rc; } + rc = FAPI_ATTR_GET(ATTR_MSS_MEM_WATT_TARGET, &i_target_mba, channel_pair_watt_target); if (rc) { @@ -205,29 +209,9 @@ extern "C" { FAPI_ERR("Error getting attribute ATTR_MSS_POWER_INT"); return rc; } -// runtime throttles will be the thermal throttle values (or zero if not -// initialized yet) - rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA, - &i_target_mba, throttle_n_per_mba); - if (rc) { - FAPI_ERR("Error getting attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA"); - return rc; - } - rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP, - &i_target_mba, throttle_n_per_chip); - if (rc) { - FAPI_ERR("Error getting attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP"); - return rc; - } - rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR, - &i_target_mba, throttle_d); - if (rc) { - FAPI_ERR("Error getting attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR"); - return rc; - } -// get number of mba's with dimms for a CDIMM - if (dimm_type == CDIMM) +// get number of mba's with dimms for a CDIMM + if (custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) { // Get Centaur target for the given MBA rc = fapiGetParentChip(i_target_mba, target_chip); @@ -278,44 +262,16 @@ extern "C" { // If over limit, then increase throttle value until it is at or below limit // If unable to get power below limit, then call out an error -// Determine whether to base throttles on thermal or power reasons (power -// throttles can give you better performance than thermal throttles) - if ( - (throttle_n_per_mba == 0) && - (throttle_n_per_chip == 0) && - (throttle_d == 0) - ) - { -// runtime throttles are all zero here, they have not been defined yet and need -// to be - thermal_throttle_active = true; // Set runtime throttles to default values as a starting value - throttle_n_per_mba = MEM_THROTTLE_N_DEFAULT_PER_MBA; - throttle_n_per_chip = MEM_THROTTLE_N_DEFAULT_PER_CHIP * - num_mba_with_dimms; - throttle_d = MEM_THROTTLE_D_DEFAULT; - } - else if ( - (throttle_n_per_mba != MEM_THROTTLE_N_DEFAULT_PER_MBA) || - (throttle_n_per_chip != - (MEM_THROTTLE_N_DEFAULT_PER_CHIP * num_mba_with_dimms)) || - (throttle_d != MEM_THROTTLE_D_DEFAULT) - ) - { -// if runtime throttles are not equal to the default values, then thermal -// throttles are in place - thermal_throttle_active = true; - } - else - { -// runtime throttles are not all zero and equal to the defaults, so no thermal -// throttles are in place - so now any throttles will be power based - thermal_throttle_active = false; - } + throttle_n_per_mba = MEM_THROTTLE_N_DEFAULT_PER_MBA; + throttle_n_per_chip = MEM_THROTTLE_N_DEFAULT_PER_CHIP * + num_mba_with_dimms; + throttle_d = MEM_THROTTLE_D_DEFAULT; + // Adjust power limit value as needed here // For CDIMM, we want the throttles to be per-chip, and to allow all commands to // go to one MBA to get to the power limit - if (dimm_type == CDIMM) + if (custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) { // Set channel pair power limit to whole CDIMM power limit (multiply by number // of MBAs used) and subtract off idle power for dimms on other MBA @@ -353,92 +309,37 @@ extern "C" { // compare channel pair power to mss_watt_target for channel and decrease // throttles if it is above this limit -// throttle decrease will decrement throttle numerator by one (or increase -// throttle denominator) and recalculate power until utilization (N/M) reaches a -// lower limit +// throttle decrease will decrement throttle numerator by one +// and recalculate power until utilization (N/M) reaches a lower limit if (channel_pair_power > channel_pair_watt_target) { // check to see if dimm utilization is greater than the min utilization limit, // continue if it is, error if it is not - if ( - ( - ((((float)throttle_n_per_chip * 100 * 4) / throttle_d) > - MIN_UTIL) && - (dimm_type != CDIMM) && - (thermal_throttle_active == false) - ) - || - ( - ((((float)throttle_n_per_chip * 100 * 4) / throttle_d) > - MIN_UTIL) && - (dimm_type != CDIMM) && - (thermal_throttle_active == true) - ) - || - ( - ((((float)throttle_n_per_chip * 100 * 4) / throttle_d) > - MIN_UTIL) && - (dimm_type == CDIMM) - ) - ) + if ((((float)throttle_n_per_chip * 100 * 4) / throttle_d) > + MIN_UTIL) { - if ( - ( - (throttle_n_per_chip > 1) && - (dimm_type != CDIMM) && - (thermal_throttle_active == false) - ) - || - ( - (throttle_n_per_chip > 1) && - (dimm_type != CDIMM) && - (thermal_throttle_active == true) - ) - || - ( - (throttle_n_per_chip > 1) && - (dimm_type == CDIMM) - ) - ) + if (throttle_n_per_chip > 1) { - if (dimm_type == CDIMM) + if (custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) { // CDIMMs, use per chip throttling for any thermal or available power limits throttle_n_per_chip--; } else { -// ISDIMMs, use per slot throttling for thermal power limits - if (thermal_throttle_active == true) - { +// ISDIMMs, use per mba throttling for available power limit // per_mba throttling (ie. per dimm for ISDIMMs) will limit performance if all // traffic is sent to one dimm, so use the per_chip -// This works as long as the other dimm is providing termination (for 2 dimms -// per channel) -// If the other dimm is not providing termination, then we would want to -// redefine the power curve in mss_eff_config_thermal and use the per_mba -// throttle here -// It there is only one dimm on channel, then it will provide its own -// termination and the per_mba and per_chip will effectively do the same -// throttling (ie. doesn't matter which one we do in this case) -// Warning: If this changes, then the two if statements above need to be -// modified - throttle_n_per_chip--; - } - else - { -// ISDIMMs, use per mba throttling for available power limit -// Warning: If this changes, then the two if statements above need to be -// modified - throttle_n_per_chip--; - } + throttle_n_per_chip--; } } -// increment throttle denominator if numerator is at one (its lowest setting) +// This was increment throttle_d++, but don't want to change the denominator since OCC does not set it. +// Done if we reach this point (ie. not enough power) else { - throttle_d++; + channel_pair_throttle_done = true; + not_enough_available_power = true; } FAPI_DBG("Throttle update [N_per_mba/N_per_chip/M %d/%d/%d]", throttle_n_per_mba, throttle_n_per_chip, throttle_d); } @@ -458,6 +359,16 @@ extern "C" { } } +// Set per_mba throttle to per_chip throttle if it is greater +// This way, when OCC throttles using per_mba due to thermal reasons, +// it has a higher chance of making an immediate impact +// NOTE: If above throttle determination uses throttle_n_per_mba, then +// we need to change this around + if (throttle_n_per_mba > throttle_n_per_chip) + { + throttle_n_per_mba = throttle_n_per_chip; + } + FAPI_DBG("Final Throttle Settings [N_per_mba/N_per_chip/M %d/%d/%d]", throttle_n_per_mba, throttle_n_per_chip, throttle_d); //------------------------------------------------------------------------------ @@ -497,7 +408,8 @@ extern "C" { if (rc) fapiLogError(rc); } - FAPI_IMP("*** %s COMPLETE ***", procedure_name); + FAPI_IMP("*** %s COMPLETE on %s ***", procedure_name, + i_target_mba.toEcmdString()); return rc; } diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C index 6a9027c70..fe7b458ad 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_config_thermal.C,v 1.15 2013/02/11 18:42:45 pardeik Exp $ +// $Id: mss_eff_config_thermal.C,v 1.17 2013/07/22 14:09:20 pardeik Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/ // centaur/working/procedures/ipl/fapi/mss_eff_config_thermal.C,v $ //------------------------------------------------------------------------------ @@ -43,7 +43,7 @@ // values are in cW. // -- ISDIMM will calculate values based on various attributes // -- CDIMM will get values from VPD -// -- The throttle attributes will setup values for safemode and runtime +// -- The throttle attributes will setup values for IPL and runtime // // //------------------------------------------------------------------------------ @@ -53,6 +53,15 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.17 | pardeik |19-JUL-13| Use runtime throttles for IPL for scominit +// | | | Removed MRW safemode throttle stuff +// | | | Always determine runtime throttles now +// 1.16 | pardeik |08-JUL-13| Using CUSTOM_DIMM attribute +// | | | Initialize some termination variables to zero +// | | | changed handling of TYPE_1D +// | | | only get NUM_OF_REGISTERS_USED_ON_RDIMM +// | | | for RDIMM (non custom) +// | | | get thermal power limit from MRW // 1.15 | pardeik |11-FEB-13| set safemode throttles to unthrottled value // | | | for lab until fw sets runtime throttles // 1.14 | pardeik |03-DEC-12| update lines to have a max width of 80 chars @@ -98,13 +107,8 @@ TODO ITEMS: Waiting for platinit attributes to enable sections in this procedure: 1. Power Curves to originate from CDIMM VPD (platinit) -2. Thermal memory power limit from MRW (platinit) -3. Safemode throttles from MRW (platinit) -5. Need runtime throttles non-volatile and initialized to zero by firmware on - the first IPL -6. Call out error for CDIMM and lab VPD power curves when it makes sense -7. Update power table after hardware measurements are done - +2. Call out error for CDIMM and lab VPD power curves when it makes sense +3. Update ISDIMM power table after hardware measurements are done */ //------------------------------------------------------------------------------ @@ -143,7 +147,9 @@ extern "C" { //------------------------------------------------------------------------------ // Funtions in this file //------------------------------------------------------------------------------ - fapi::ReturnCode mss_eff_config_thermal(const fapi::Target & i_target_mba); + fapi::ReturnCode mss_eff_config_thermal( + const fapi::Target & i_target_mba + ); fapi::ReturnCode mss_eff_config_thermal_term ( @@ -154,7 +160,9 @@ extern "C" { uint32_t i_dimm_voltage, uint8_t i_dram_width, uint8_t i_dram_tdqs, - uint8_t i_ibm_type[NUM_PORTS][NUM_DIMMS], + uint8_t i_dimm_type, + uint8_t i_stack_type, + uint8_t i_dimm_master_ranks_array[NUM_PORTS][NUM_DIMMS], uint8_t i_dimm_ranks_configed_array[NUM_PORTS][NUM_DIMMS], uint8_t i_dimm_dram_ron[NUM_PORTS][NUM_DIMMS], uint8_t i_dimm_rank_odt_rd[NUM_PORTS][NUM_DIMMS][NUM_RANKS], @@ -189,20 +197,18 @@ extern "C" { // @return fapi::ReturnCode //------------------------------------------------------------------------------ - fapi::ReturnCode mss_eff_config_thermal(const fapi::Target & i_target_mba) + fapi::ReturnCode mss_eff_config_thermal(const fapi::Target & i_target_mba + ) { fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS; char procedure_name[32]; sprintf(procedure_name, "mss_eff_config_thermal"); - FAPI_IMP("*** Running %s ***", procedure_name); + FAPI_IMP("*** Running %s on %s ***", procedure_name, + i_target_mba.toEcmdString()); enum { - CDIMM = fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM, - RDIMM = fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, - UDIMM = fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM, - LRDIMM = fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM, DDR3 = fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3, DDR4 = fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4, X4 = fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -253,6 +259,7 @@ extern "C" { // Gen Width Ranks idle,full Adder Volt Freq // cW U,LR,RDIMM mV MHz //------------------------------------------------------------------------------ +// TODO: Update ISDIMM power table values after measurements have been taken power_data_t power_table[] = { { DDR3, X4, 1, { 70,373}, {0,93,104}, 1350, 1066 }, @@ -272,6 +279,8 @@ extern "C" { uint8_t rank; uint8_t entry; uint8_t dimm_type; + uint8_t stack_type[NUM_PORTS][NUM_DIMMS]; + uint8_t custom_dimm; uint8_t dimm_ranks_array[NUM_PORTS][NUM_DIMMS]; uint32_t power_table_size; uint32_t power_slope_array[NUM_PORTS][NUM_DIMMS]; @@ -291,14 +300,14 @@ extern "C" { float dimm_power_mulitiplier_freq; float dimm_idle_power; float dimm_active_power; - float dimm_power_adder_termination; + float dimm_power_adder_termination = 0; float dimm_power_adder_termination_largest = 0; uint8_t dimm_rank_odt_rd[NUM_PORTS][NUM_DIMMS][NUM_RANKS]; uint8_t dimm_rank_odt_wr[NUM_PORTS][NUM_DIMMS][NUM_RANKS]; uint8_t dimm_dram_ron[NUM_PORTS][NUM_DIMMS]; uint8_t cen_dq_dqs_rcv_imp[NUM_PORTS]; uint8_t cen_dq_dqs_drv_imp[NUM_PORTS]; - float dimm_power_adder_termination_wc; + float dimm_power_adder_termination_wc = 0; float dimm_power_adder_termination_largest_wc = 0; uint8_t cen_dq_dqs_rcv_imp_wc[NUM_PORTS]; uint8_t cen_dq_dqs_drv_imp_wc[NUM_PORTS]; @@ -311,7 +320,6 @@ extern "C" { uint32_t runtime_throttle_d; uint8_t dram_rtt_nom[NUM_PORTS][NUM_DIMMS][NUM_RANKS]; uint8_t dram_rtt_wr[NUM_PORTS][NUM_DIMMS][NUM_RANKS]; - uint8_t ibm_type[NUM_PORTS][NUM_DIMMS]; char dram_gen_str[4]; uint32_t dimm_thermal_power_limit; uint32_t channel_pair_thermal_power_limit; @@ -323,15 +331,20 @@ extern "C" { uint32_t cdimm_master_power_intercept; uint32_t cdimm_supplier_power_slope; uint32_t cdimm_supplier_power_intercept; - uint32_t safemode_throttle_n_per_mba; - uint32_t safemode_throttle_n_per_chip; - uint32_t safemode_throttle_d; power_table_size = (sizeof(power_table))/(sizeof(power_data_t)); //------------------------------------------------------------------------------ // Get input attributes //------------------------------------------------------------------------------ + +// Get Centaur target for the given MBA + rc = fapiGetParentChip(i_target_mba, target_chip); + if (rc) { + FAPI_ERR("Error from fapiGetParentChip"); + return rc; + } + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target_mba, dram_gen); if (rc) { FAPI_ERR("Error getting attribute ATTR_EFF_DRAM_GEN"); @@ -342,6 +355,16 @@ extern "C" { FAPI_ERR("Error getting attribute ATTR_EFF_DIMM_TYPE"); return rc; } + rc = FAPI_ATTR_GET(ATTR_EFF_STACK_TYPE, &i_target_mba, stack_type); + if (rc) { + FAPI_ERR("Error getting attribute ATTR_EFF_STACK_TYPE"); + return rc; + } + rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, custom_dimm); + if (rc) { + FAPI_ERR("Error getting attribute ATTR_EFF_CUSTOM_DIMM"); + return rc; + } rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, dram_width); if (rc) { FAPI_ERR("Error getting attribute ATTR_EFF_DRAM_WIDTH"); @@ -407,11 +430,6 @@ extern "C" { FAPI_ERR("Error getting attribute ATTR_EFF_DRAM_RTT_WR"); return rc; } - rc = FAPI_ATTR_GET(ATTR_EFF_IBM_TYPE, &i_target_mba, ibm_type); - if (rc) { - FAPI_ERR("Error getting attribute ATTR_EFF_IBM_TYPE"); - return rc; - } rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba, num_dimms_on_port); if (rc) { @@ -425,95 +443,39 @@ extern "C" { cdimm_supplier_power_slope = CDIMM_POWER_SLOPE_DEFAULT; cdimm_supplier_power_intercept = CDIMM_POWER_INT_DEFAULT; /* - rc = FAPI_ATTR_GET(ATTR_SPD_CDIMM_MASTER_POWER_SLOPE, - &i_target_mba, cdimm_master_power_slope); - if (rc) { - FAPI_ERR("Error getting attribute ATTR_SPD_CDIMM_MASTER_POWER_SLOPE"); - return rc; - } - rc = FAPI_ATTR_GET(ATTR_SPD_CDIMM_MASTER_POWER_INTERCEPT, - &i_target_mba, cdimm_master_power_intercept); - if (rc) { - FAPI_ERR("Error getting attribute ATTR_SPD_CDIMM_MASTER_POWER_INTERCEPT"); - return rc; - } - rc = FAPI_ATTR_GET(ATTR_SPD_CDIMM_SUPPLIER_POWER_SLOPE, - &i_target_mba, cdimm_supplier_power_slope); + rc = FAPI_ATTR_GET(ATTR_CDIMM_VPD_MASTER_POWER_SLOPE, + &target_chip, cdimm_master_power_slope); if (rc) { - FAPI_ERR("Error getting attribute ATTR_SPD_CDIMM_SUPPLIER_POWER_SLOPE"); + FAPI_ERR("Error getting attribute ATTR_CDIMM_VPD_MASTER_POWER_SLOPE"); return rc; } - rc = FAPI_ATTR_GET(ATTR_SPD_CDIMM_SUPPLIER_POWER_INTERCEPT, - &i_target_mba, cdimm_supplier_power_intercept); - if (rc) { - FAPI_ERR("Error getting attribute ATTR_SPD_CDIMM_SUPPLIER_POWER_INTERCEPT"); - return rc; - } -*/ -// TODO: Get Safemode throttles from MRW (platinit), hardcode until available -// Do not use safe mode throttles until firmware programs runtime throttles (ie. don't impact lab with throttles) - if (dimm_type == CDIMM) - { - safemode_throttle_n_per_mba = 96; - } - else - { - safemode_throttle_n_per_mba = 96; - } -// safemode_throttle_n_per_chip = 32; - if (dimm_type == CDIMM) - { - safemode_throttle_n_per_chip = 192; - } - else - { - safemode_throttle_n_per_chip = 96; - } - safemode_throttle_d = 512; -/* - rc = FAPI_ATTR_GET(ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA, - &i_target_mba, safemode_throttle_n_per_mba); + rc = FAPI_ATTR_GET(ATTR_CDIMM_VPD_MASTER_POWER_INTERCEPT, + &target_chip, cdimm_master_power_intercept); if (rc) { - FAPI_ERR("Error getting attribute ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA"); + FAPI_ERR("Error getting attribute ATTR_CDIMM_VPD_MASTER_POWER_INTERCEPT"); return rc; } - rc = FAPI_ATTR_GET(ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP, - &i_target_mba, safemode_throttle_n_per_chip); + rc = FAPI_ATTR_GET(ATTR_CDIMM_VPD_SUPPLIER_POWER_SLOPE, + &target_chip, cdimm_supplier_power_slope); if (rc) { - FAPI_ERR("Error getting attribute ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP"); + FAPI_ERR("Error getting attribute ATTR_CDIMM_VPD_SUPPLIER_POWER_SLOPE"); return rc; } - rc = FAPI_ATTR_GET(ATTR_MRW_SAFEMODE_MEM_THROTTLE_DENOMINATOR, - &i_target_mba, safemode_throttle_d); + rc = FAPI_ATTR_GET(ATTR_CDIMM_VPD_SUPPLIER_POWER_INTERCEPT, + &target_chip, cdimm_supplier_power_intercept); if (rc) { - FAPI_ERR("Error getting attribute ATTR_MRW_SAFEMODE_MEM_THROTTLE_DENOMINATOR"); + FAPI_ERR("Error getting attribute ATTR_CDIMM_VPD_SUPPLIER_POWER_INTERCEPT"); return rc; } */ -// TODO: Get Thermal power Limit from MRW (platinit), hardcode until available - if (dimm_type == CDIMM) - { - dimm_thermal_power_limit = 5000; // in cW, per CDIMM, high limit - } - else - { - dimm_thermal_power_limit = 2000; // in cW, per ISDIMM, high limit - } -/* + rc = FAPI_ATTR_GET(ATTR_MRW_THERMAL_MEMORY_POWER_LIMIT, - &i_target_mba, dimm_thermal_power_limit); + NULL, dimm_thermal_power_limit); if (rc) { FAPI_ERR("Error getting attribute ATTR_MRW_THERMAL_MEMORY_POWER_LIMIT"); return rc; } -*/ -// Get Centaur target for the given MBA - rc = fapiGetParentChip(i_target_mba, target_chip); - if (rc) { - FAPI_ERR("Error from fapiGetParentChip"); - return rc; - } // Get voltage and frequency attributes rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &target_chip, dimm_voltage); if (rc) { @@ -528,7 +490,10 @@ extern "C" { // get any attributes from DIMM SPD - if (dimm_type != CDIMM) + if ( + (custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_NO) + && (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) + ) { rc = fapiGetAssociatedDimms(i_target_mba, target_dimm_array, fapi::TARGET_STATE_PRESENT); @@ -563,7 +528,7 @@ extern "C" { } // Get number of Centaur MBAs that have dimms present - if (dimm_type == CDIMM) + if (custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) { rc = fapiGetChildChiplets(target_chip, fapi::TARGET_TYPE_MBA_CHIPLET, @@ -591,7 +556,7 @@ extern "C" { } // determine worst case termination settings here for ISDIMMs (to be used later) - if (dimm_type != CDIMM) + if (custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_NO) { // get worst case termination values that will be used // Only look at Centaur DQ/DQS Driver and Receiver termination settings @@ -621,7 +586,7 @@ extern "C" { for (port=0; port < NUM_PORTS; port++) { // Get termination power for ISDIMM - if (dimm_type != CDIMM) + if (custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_NO) { dimm_power_adder_termination_largest=0; dimm_power_adder_termination_largest_wc=0; @@ -642,7 +607,9 @@ extern "C" { dimm_voltage, dram_width, dram_tdqs, - ibm_type, + dimm_type, + stack_type[port][dimm], + dimm_master_ranks_array, dimm_ranks_configed_array, dimm_dram_ron, dimm_rank_odt_rd, @@ -675,7 +642,9 @@ extern "C" { dimm_voltage, dram_width, dram_tdqs, - ibm_type, + dimm_type, + stack_type[port][dimm], + dimm_master_ranks_array, dimm_ranks_configed_array, dimm_dram_ron, dimm_rank_odt_rd, @@ -716,7 +685,7 @@ extern "C" { // CDIMM power slope/intercept will come from VPD // Data in VPD needs to be the power per virtual dimm on the CDIMM - if (dimm_type == CDIMM) + if (custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) { power_slope_array[port][dimm] = cdimm_master_power_slope; @@ -828,12 +797,12 @@ extern "C" { ) { // get adder for dimm type - if (dimm_type == UDIMM) + if (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM) { dimm_power_adder_type = power_table[entry].dimm_type_adder.udimm; } - else if (dimm_type == LRDIMM) + else if (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) { dimm_power_adder_type = power_table[entry].dimm_type_adder.lrdimm; @@ -845,7 +814,7 @@ extern "C" { } - if (dimm_type == RDIMM) { + if (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) { dimm_power_adder_type = dimm_power_adder_type * dimm_number_registers[port][dimm]; @@ -974,6 +943,7 @@ extern "C" { //------------------------------------------------------------------------------ if (found_entry_in_table == 0) { + FAPI_ERR("Failed to Find DIMM Power Values on %s. Default values will be used [P%d:D%d][Slope=%d:INT=%d cW]", i_target_mba.toEcmdString(), port, dimm, power_slope_array[port][dimm], power_int_array[port][dimm]); // get dimm target, we should always find a valid dimm target from this @@ -1046,60 +1016,8 @@ extern "C" { // Memory Throttle Determination //------------------------------------------------------------------------------ -// Runtime throttles will be non-volatile, so don't recalculate them if they -// have already been set - -// TODO: remove this section when firmware initializes attributes to zero AND -// runtime throttles are non-volatile - runtime_throttle_n_per_mba = 0; - runtime_throttle_n_per_chip = 0; - runtime_throttle_d = 0; - rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA, - &i_target_mba, runtime_throttle_n_per_mba); - if (rc) { - FAPI_ERR("Error writing attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA"); - return rc; - } - rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP, - &i_target_mba, runtime_throttle_n_per_chip); - if (rc) { - FAPI_ERR("Error writing attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP"); - return rc; - } - rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR, - &i_target_mba, runtime_throttle_d); - if (rc) { - FAPI_ERR("Error writing attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR"); - return rc; - } +// Determine memory throttle settings needed based on dimm thermal power limit -// Get the runtime throttle attributes here - rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA, - &i_target_mba, runtime_throttle_n_per_mba); - if (rc) { - FAPI_ERR("Error getting attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA"); - return rc; - } - rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP, - &i_target_mba, runtime_throttle_n_per_chip); - if (rc) { - FAPI_ERR("Error getting attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP"); - return rc; - } - rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR, - &i_target_mba, runtime_throttle_d); - if (rc) { - FAPI_ERR("Error getting attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR"); - return rc; - } -// check to see if runtime throttles are all zero here - if ( - (runtime_throttle_n_per_mba == 0) && - (runtime_throttle_n_per_chip == 0) && - (runtime_throttle_d == 0) - ) - { -// Values have not been initialized, so get them initialized //------------------------------------------------------------------------------ // Determine the thermal power limit to use, which represents a single channel // pair power limit for the dimms on that channel pair (ie. power for all dimms @@ -1112,7 +1030,7 @@ extern "C" { // This means that the power limit for a MBA channel pair must be the total // CDIMM power limit minus the idle power of the other MBAs logical dimms //------------------------------------------------------------------------------ - if (dimm_type == CDIMM) + if (custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) { channel_pair_thermal_power_limit = dimm_thermal_power_limit / num_mba_with_dimms; @@ -1143,7 +1061,8 @@ extern "C" { return rc; } -// Read back in the updated throttle attribute values (these are now set to values that will give dimm/channel power underneath the thermal power limit) +// Read back in the updated throttle attribute values (these are now set to +// values that will give dimm/channel power underneath the thermal power limit) rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA, &i_target_mba, runtime_throttle_n_per_mba); if (rc) { @@ -1183,13 +1102,13 @@ extern "C" { return rc; } - } -// Initialize the generic throttle attributes to safemode throttles (since the -// IPL will be done at the safemode throttles) - throttle_n_per_mba = safemode_throttle_n_per_mba; - throttle_n_per_chip = safemode_throttle_n_per_chip; - throttle_d = safemode_throttle_d; +// Initialize the generic throttle attributes to be used for scominit +// These throttles will be the runtime throttles for mcbist/msdiag +// safemode throttles will be set in thermal_init step + throttle_n_per_mba = runtime_throttle_n_per_mba; + throttle_n_per_chip = runtime_throttle_n_per_chip; + throttle_d = runtime_throttle_d; // write output attributes rc = FAPI_ATTR_SET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA, @@ -1211,7 +1130,8 @@ extern "C" { return rc; } - FAPI_IMP("*** %s COMPLETE ***", procedure_name); + FAPI_IMP("*** %s COMPLETE on %s ***", procedure_name, + i_target_mba.toEcmdString()); return rc; } @@ -1227,8 +1147,9 @@ extern "C" { // @param[in] uint32_t i_dimm_voltage: DIMM Voltage // @param[in] uint8_t i_dram_width: DRAM Width // @param[in] uint8_t i_dram_tdqs: DRAM TDQS enable/disable -// @param[in] uint8_t i_ibm_type[NUM_PORTS][NUM_DIMMS]: IBM bus topology -// type +// @param[in] uint8_t i_dimm_type: DIMM Type +// @param[in] uint8_t i_stack_type: DRAM Stack Type +// @param[in] uint8_t i_dimm_master_ranks_array: Number of Master Ranks // @param[in] uint8_t i_dimm_ranks_configed_array[NUM_PORTS][NUM_DIMMS]: // Master Ranks configured // @param[in] uint8_t i_dimm_dram_ron[NUM_PORTS][NUM_DIMMS]: DRAM RON driver @@ -1260,7 +1181,9 @@ extern "C" { uint32_t i_dimm_voltage, uint8_t i_dram_width, uint8_t i_dram_tdqs, - uint8_t i_ibm_type[NUM_PORTS][NUM_DIMMS], + uint8_t i_dimm_type, + uint8_t i_stack_type, + uint8_t i_dimm_master_ranks_array[NUM_PORTS][NUM_DIMMS], uint8_t i_dimm_ranks_configed_array[NUM_PORTS][NUM_DIMMS], uint8_t i_dimm_dram_ron[NUM_PORTS][NUM_DIMMS], uint8_t i_dimm_rank_odt_rd[NUM_PORTS][NUM_DIMMS][NUM_RANKS], @@ -1328,7 +1251,19 @@ extern "C" { // Also need to consider if ODT is tied high for writes (if rtt_wr is set for // the rank being written to, then it will be assumed that ODT is tied high) - if (i_ibm_type[i_port][i_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_1D) +// Type_1D is also the following (use these instead of attribute) +// 1. RDIMM or UDIMM +// 2. 4 Master Ranks +// 3. Planar or DDP/QDP + if ( + ((i_dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) + || (i_dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM)) + && + (i_dimm_master_ranks_array[i_port][i_dimm] == 4) + && + ((i_stack_type == fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE) + || (i_stack_type == fapi::ENUM_ATTR_EFF_STACK_TYPE_DDP_QDP)) + ) { ma0odt01_dimm = 0; ma1odt01_dimm = 1; @@ -1859,7 +1794,12 @@ extern "C" { ); FAPI_DBG("%s TERM:[P%d:D%d:R%d] CEN[DRV=%d RCV=%d] DRAM[DRV=%d ODT_RD=%4.2f ODT_WR=%4.2f]", i_nom_or_wc_term, i_port, i_dimm, i_rank, cen_dq_dqs_drv_imp_value, i_cen_dq_dqs_rcv_imp[i_port], i_dimm_dram_ron[i_port][i_dimm], eff_term_rd, eff_term_wr); FAPI_DBG("%s TERM POWER:[P%d:D%d:R%d] RD[Nets=%d EffTerm=%3.2f ODTMult=%1.2f] WR[Nets=%d EffTerm=%3.2f ODTMult=%1.2f] TermPower(%d%%)=%2.2f W", i_nom_or_wc_term, i_port, i_dimm, i_rank, number_nets_term_rd, eff_net_term_rd, term_odt_mult_rd, number_nets_term_wr, eff_net_term_wr, term_odt_mult_wr, ACTIVE_DIMM_UTILIZATION, o_dimm_power_adder_termination); - } + } + else + { +// rank not configured, so it has no termination power associated with it + o_dimm_power_adder_termination = 0; + } FAPI_IMP("*** %s COMPLETE ***", procedure_name); return rc; diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.C index 239541921..c049b8b5d 100644 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_cpu_special_wakeup.C,v 1.7 2013/04/16 12:14:14 pchatnah Exp $ +// $Id: p8_cpu_special_wakeup.C,v 1.13 2013/08/02 18:59:13 stillgs Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_cpu_special_wakeup.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -79,10 +79,7 @@ #include "p8_pm.H" #include "p8_cpu_special_wakeup.H" -#include <ecmdDataBufferBase.H> -//#include <ecmdClientCapi.H> -#include <fapi.H> - +#include "p8_pcb_scom_errors.H" extern "C" { @@ -101,33 +98,32 @@ p8_cpu_special_wakeup( const fapi::Target& i_target, PROC_SPCWKUP_ENTITY i_entity ) { - fapi::ReturnCode l_rc; + fapi::ReturnCode rc; + fapi::ReturnCode oha_rc; uint32_t e_rc = 0; ecmdDataBufferBase data(64); + ecmdDataBufferBase fsi_data(64); ecmdDataBufferBase polldata(64); - //TODO RTC: 71328 - hack to indicate unused - bool __attribute__((unused)) error_flag = false; - //TODO RTC: 71328 - needs to be const - const char* PROC_SPCWKUP_ENTITY_NAMES[] = - { - "HOST", - "FSP", - "OCC", - "PHYP", - "SPW_ALL" - }; - - - - //TODO RTC: 71328 - needs to be const + + fapi::Target l_parentTarget; + uint8_t attr_chip_unit_pos = 0; + + const char* PROC_SPCWKUP_ENTITY_NAMES[] = + { + "HOST", + "FSP", + "OCC", + "PHYP", + "SPW_ALL" + }; + const char* PROC_SPCWKUP_OPS_NAMES[] = - { - "DISABLE", - "ENABLE", - "INIT" - }; - - + { + "DISABLE", + "ENABLE", + "INIT" + }; + uint32_t special_wakeup_max_polls; /// Time (binary in milliseconds) for the first poll check (running/nap @@ -136,8 +132,9 @@ p8_cpu_special_wakeup( const fapi::Target& i_target, /// Get an attribute that defines the maximum special wake-up polling /// timing (binary in milliseconds). + /// Increased timeout to 200ms - 6/10/13 - uint32_t special_wakeup_timeout = 25; + uint32_t special_wakeup_timeout = 200; /// Get an attribute that defines the special wake-up polling interval /// (binary in milliseconds). @@ -149,49 +146,70 @@ p8_cpu_special_wakeup( const fapi::Target& i_target, std::vector<fapi::Target> l_chiplets; std::vector<Target>::iterator itr; - uint64_t SP_WKUP_REG_ADDRS; + uint8_t oha_spwkup_flag = 0; + uint8_t ignore_xstop_flag = 0; //-------------------------------------------------------------------------- // Read the counts of different ENTITY (FSP,OCC,PHYP) from the Attributes //-------------------------------------------------------------------------- - uint32_t PHYP_SPWKUP_COUNT = 0; - uint32_t FSP_SPWKUP_COUNT = 0; - uint32_t OCC_SPWKUP_COUNT = 0; + uint32_t phyp_spwkup_count = 0; + uint32_t fsp_spwkup_count = 0; + uint32_t occ_spwkup_count = 0; + + uint64_t spwkup_address = 0; do { - + FAPI_INF("Executing p8_cpu_special_wakeup %s for %s ...", PROC_SPCWKUP_OPS_NAMES[i_operation], PROC_SPCWKUP_ENTITY_NAMES[i_entity]); - + // Initialize the attributes to 0. if (i_operation == SPCWKUP_INIT) { + FAPI_INF("Processing target %s", i_target.toEcmdString()); FAPI_INF("Initializing ATTR_PM_SPWUP_FSP"); - l_rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_FSP, &i_target, FSP_SPWKUP_COUNT); - if (l_rc) + rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_FSP, &i_target, fsp_spwkup_count); + if (rc) { - FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_FSP with l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_FSP with rc = 0x%x", (uint32_t)rc); + break ; } FAPI_INF("Initializing ATTR_PM_SPWUP_OCC"); - l_rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OCC, &i_target, OCC_SPWKUP_COUNT); - if (l_rc) + rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OCC, &i_target, occ_spwkup_count); + if (rc) { - FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_OCC with l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_OCC with rc = 0x%x", (uint32_t)rc); break; } FAPI_INF("Initializing ATTR_PM_SPWUP_PHYP"); - l_rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_PHYP, &i_target, PHYP_SPWKUP_COUNT); - if (l_rc) + rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_PHYP, &i_target, phyp_spwkup_count); + if (rc) { - FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_PHYP with l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_PHYP with rc = 0x%x", (uint32_t)rc); break; } + FAPI_INF("Initializing ATTR_PM_SPWUP_OHA_FLAG"); + rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OHA_FLAG, &i_target, oha_spwkup_flag); + if (rc) + { + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)rc); + break; + } + + FAPI_INF("Initializing ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG"); + rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG, &i_target, ignore_xstop_flag); + if (rc) + { + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG with rc = 0x%x", (uint32_t)rc); + break ; + } + // Leave the procedure break; } @@ -200,55 +218,43 @@ p8_cpu_special_wakeup( const fapi::Target& i_target, // Checking the ENTITY who raised this OPERATION //-------------------------------------------------------------------------- - fapi::Target l_parentTarget; - uint8_t attr_chip_unit_pos = 0; - // Get the parent chip to target the registers - l_rc = fapiGetParentChip(i_target, l_parentTarget); - if (l_rc) + rc = fapiGetParentChip(i_target, l_parentTarget); + if (rc) { break; // throw error } - // Check whether system is checkstopped - l_rc=fapiGetScom(l_parentTarget, PCBMS_INTERRUPT_TYPE_REG_0x000F001A, data); - if( data.isBitSet( 2 ) ) - { - FAPI_ERR( "This chip is xstopped, so ignoring the special wakeup request\n" ); - FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_CHKSTOP); - break; - } - // Get the core number - l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, attr_chip_unit_pos); - if (l_rc) + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, attr_chip_unit_pos); + if (rc) { - FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)rc); break; } - // CORE_NUM = attr_chip_unit_pos; + FAPI_DBG("Core number = %d", attr_chip_unit_pos); - // Read the Attributes to know the Special_wake counts form each entities . + // Read the Attributes to know the Special_wake counts from each entity // This should be different for different EX chiplets. - l_rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_FSP, &i_target, FSP_SPWKUP_COUNT); - if (l_rc) + rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_FSP, &i_target, fsp_spwkup_count); + if (rc) { - FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_FSP with l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_FSP with rc = 0x%x", (uint32_t)rc); break; } - l_rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_OCC, &i_target, OCC_SPWKUP_COUNT ); - if (l_rc) + rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_OCC, &i_target, occ_spwkup_count ); + if (rc) { - FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_FSP with l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_OCC with rc = 0x%x", (uint32_t)rc); break; } - l_rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_PHYP,&i_target , PHYP_SPWKUP_COUNT ); - if (l_rc) + rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_PHYP,&i_target , phyp_spwkup_count ); + if (rc) { - FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_FSP with l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_PHYP with rc = 0x%x", (uint32_t)rc); break; } @@ -261,23 +267,23 @@ p8_cpu_special_wakeup( const fapi::Target& i_target, // Process counts based on the calling entity if (i_entity == OCC) { - count = OCC_SPWKUP_COUNT ; + count = occ_spwkup_count ; FAPI_INF("OCC count before = %d" , count); - SP_WKUP_REG_ADDRS = PM_SPECIAL_WKUP_OCC_0x100F010C + + spwkup_address = PM_SPECIAL_WKUP_OCC_0x100F010C + (attr_chip_unit_pos * 0x01000000) ; } else if (i_entity == FSP) { - count = FSP_SPWKUP_COUNT ; + count = fsp_spwkup_count ; FAPI_INF("FSP count before = %d" , count); - SP_WKUP_REG_ADDRS = PM_SPECIAL_WKUP_FSP_0x100F010B + + spwkup_address = PM_SPECIAL_WKUP_FSP_0x100F010B + (attr_chip_unit_pos * 0x01000000); } else if (i_entity == PHYP) { - count = PHYP_SPWKUP_COUNT ; + count = phyp_spwkup_count ; FAPI_INF("PHYP count before = %d" , count); - SP_WKUP_REG_ADDRS = PM_SPECIAL_WKUP_PHYP_0x100F010D + + spwkup_address = PM_SPECIAL_WKUP_PHYP_0x100F010D + (attr_chip_unit_pos * 0x01000000); } else @@ -285,7 +291,7 @@ p8_cpu_special_wakeup( const fapi::Target& i_target, FAPI_ERR("Unknown entity passed to proc_special_wakeup. Entity %x ....", i_entity); // I_ENTITY = i_entity; PROC_SPCWKUP_ENTITY & I_ENTITY = i_entity ; - FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_SPCWKUP_CODE_BAD_ENTITY); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_SPCWKUP_CODE_BAD_ENTITY); break; } @@ -293,106 +299,313 @@ p8_cpu_special_wakeup( const fapi::Target& i_target, // Checking the type of OPERATION and process the request ///////////////////////////////////////////////////////////////////////////// - l_rc=fapiGetScom(l_parentTarget, EX_PMGP0_0x1X0F0100, data); - if(l_rc) + rc=fapiGetScom(l_parentTarget, EX_PMGP0_0x1X0F0100, data); + if(rc) { break; } if (i_operation == SPCWKUP_ENABLE) { + + // If the OHA flag is set, then any subsequent calls to the this + // procedure must return a "good" response or else an infinite + // loop results for any calling algorithm that first sets + // special wake-up, does a SCOM, and then clears special + // wake-up. + rc = FAPI_ATTR_GET( ATTR_PM_SPWUP_OHA_FLAG, + &i_target, + oha_spwkup_flag); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)rc); + break; + } + + if (oha_spwkup_flag) + { + FAPI_INF("OHA special wakeup flag is set so returning with good response to break recursion. Counts are NOT updated."); + // This is a purposeful mid-procedure return + return rc; + } + + // Determine if xstop checking should be ignored base on a caller + // set attribute. + // + // This is used during MPIPL clean-up to a core to clear FIRs that + // will eventually clear the xstop condition. However, to do so + // needs the xstop check to not keep the special wake-up operation + // from happening. + rc = FAPI_ATTR_GET( ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG, + &i_target, + ignore_xstop_flag); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG with rc = 0x%x", (uint32_t)rc); + break ; + } + + if (!ignore_xstop_flag) + { + // Check whether system is checkstopped.. + rc=fapiGetScom(l_parentTarget, PCBMS_INTERRUPT_TYPE_REG_0x000F001A, data); + if(rc) + { + break; + } + + if( data.isBitSet( 2 ) ) + { + FAPI_ERR( "This chip is xstopped, so ignoring the special wakeup request\n" ); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_CHKSTOP); + break; + } + } + else + { + FAPI_INF("Ignore checkstop flag is set so checkstop checking is NOT being performed"); + } + FAPI_INF("Setting Special Wake-up ...") ; - // FAPI_INF("Count value after the increment is %x ...", count); if (count == 0) { - GETSCOM(i_target, SP_WKUP_REG_ADDRS, data); + GETSCOM(rc, i_target, spwkup_address, data); e_rc = data.flushTo0(); e_rc |= data.setBit(0); - E_RC_CHECK(e_rc, l_rc); + E_RC_CHECK(e_rc, rc); - PUTSCOM(i_target, SP_WKUP_REG_ADDRS, data); + PUTSCOM(rc, i_target, spwkup_address, data); // poll for the set completion pollcount = 0; e_rc=data.flushTo0(); - E_RC_CHECK(e_rc, l_rc); + E_RC_CHECK(e_rc, rc); while (data.isBitClear(31) && pollcount < special_wakeup_max_polls) { - GETSCOM(l_parentTarget, EX_PMGP0_0x1X0F0100, data); - FAPI_DBG(" Loop get for PMGP0(31) to goto 1 => 0x%16llx", data.getDoubleWord(0)); - - fapiDelay(special_wakeup_poll_interval*1000, 1000000); + GETSCOM(rc, l_parentTarget, EX_PMGP0_0x1X0F0100, data); + FAPI_DBG(" Loop get for PMGP0(31) to goto 1 => 0x%016llx", data.getDoubleWord(0)); + + rc = fapiDelay(special_wakeup_poll_interval*1000, 1000000); + if (rc) + { + break; + } pollcount ++ ; + } + if (!rc.ok()) + { + break; + } + + // Workaround for HW255321 start here + // at timeout time: + // - check for existing external interrupts or malf alerts pending : PMGP0 bit52 + // AND if OHA is in the AISS-FSM-state P7_SEQ_WAIT_INT_PENDING EX_OHA_RO_STATUS_REG_0x1002000B + // If yes - then OHA hangs + // To leave this FSM state: + // - Set Bit 9 of OHA_ARCH_IDLE_STATE_REG( RESET_IDLE_STATE_SEQUENCER). EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 + // This resets the idle sequencer and force OHA into the DO_NOTHING_STATE ...should be completed in the next cycle + // + // Continue further down and check special_wakeup completion by checking bit31 of EX_PMGP0_0x1X0F0100 + // If set then is OHA awake else error + + GETSCOM(rc, l_parentTarget, EX_PMGP0_0x1X0F0100, data); + + if (data.isBitClear(31) && data.isBitSet(52) ) + { + FAPI_DBG("Timed out setting Special wakeup with regular wake-up available, the logical OR of external interrupt and malfunction alert ... "); + FAPI_DBG("Checking for Hang-Situation in AISS-FSM-State P7_SEQ_WAIT_INT_PENDING ... "); + FAPI_DBG("Special Wake-up Done NOT asserted (PMGP0(31,52)!! =>0x%016llx", data.getDoubleWord(0)); + + oha_spwkup_flag = 1; + + rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OHA_FLAG, &i_target, oha_spwkup_flag); + if (rc) + { + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)rc); + break; + } + FAPI_INF("Set OHA special wakeup flag"); + + // Check now if OHA is in the AISS-FSM-state P7_SEQ_WAIT_INT_PENDING EX_OHA_RO_STATUS_REG_0x1002000B (bit 13-19) 0b0011100 + GETSCOM(rc, i_target, EX_OHA_RO_STATUS_REG_0x1002000B, data); + + FAPI_DBG("\tCURRENT_AISS_FSM_STATE_VECTOR (OHA_RO_STATUS(13:19) => 0x%016llx", data.getDoubleWord(0)); + + if (data.isBitClear(13) && // 0 + data.isBitClear(14) && // 0 + data.isBitSet(15) && // 1 + data.isBitSet(16) && // 1 + data.isBitSet(17) && // 1 + data.isBitClear(18) && // 0 + data.isBitClear(19) ) // 0 + { + FAPI_DBG("OHA hanging in AISS-FSM-state P7_SEQ_WAIT_INT_PENDING (0b11100) (OHA_RO_STATUS_REG(13:19) => 0x%016llx", data.getDoubleWord(0)); + FAPI_DBG("Start reset of IDLE STATE SEQUENCER: Set OHA_ARCH_IDLE_STATE_REG(9)"); + + GETSCOM(rc, i_target, EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011, data); + FAPI_DBG("\tEX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 : 0x%016llx", data.getDoubleWord(0)); + + //Set RESET_IDLE_STATE_SEQUENCER ... Bit 9 of OHA_ARCH_IDLE_STATE_REG + e_rc=data.setBit(9); + E_RC_CHECK(e_rc, rc); + + PUTSCOM(rc, i_target, EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011, data); + + // This resets the idle sequencer and force OHA into the + // DO_NOTHING_STATE ... should be completed in the next + // cycle since special wakeup is still asserted, OHA should + // not leave the DO_NOTHING_STATE + + // Check again for AISS-FSM-state P7_SEQ_WAIT_INT_PENDING EX_OHA_RO_STATUS_REG_0x1002000B (bit 13-19) 0b11100 + GETSCOM(rc, i_target, EX_OHA_RO_STATUS_REG_0x1002000B, data); + FAPI_DBG("\tCURRENT_AISS_FSM_STATE_VECTOR (OHA_RO_STATUS(13:19) => 0x%016llx", data.getDoubleWord(0)); + + // We're done accessing the OHA so clear the flag + oha_spwkup_flag = 0; + rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OHA_FLAG, &i_target, oha_spwkup_flag); + if (rc) + { + FAPI_ERR("fapiSetAttribute to clear ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)rc); + // This is a purposeful mid-procedure return + return rc; + } + FAPI_INF("Cleared OHA special wakeup flag"); + } } + + // Check again if special_wakeup completed + GETSCOM(rc, l_parentTarget, EX_PMGP0_0x1X0F0100, data); + + // Workaround for HW255321 ends here + if (data.isBitClear(31)) { FAPI_ERR("Timed out in setting the CPU in Special wakeup ... "); - FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_SPCWKUP_TIMEOUT); - break; - } - GETSCOM(l_parentTarget, EX_PMGP0_0x1X0F0100, data); - FAPI_DBG(" Special Wake-up Done asserted (PMGP0(31)!! =>0x%16llx", data.getDoubleWord(0)); - GETSCOM(i_target, EX_OHA_RO_STATUS_REG_0x1002000B, data); - FAPI_DBG(" Special Wake-up complete (OHA_RO_STATUS(1)!! => 0x%16llx", data.getDoubleWord(0)); + GETSCOM(rc, l_parentTarget, EX_PMGP0_0x1X0F0100, data); + FAPI_DBG("Special Wake-up Done asserted (PMGP0(31)!! =>0x%016llx", data.getDoubleWord(0)); + const uint64_t& PMGP0 = data.getDoubleWord(0); + + // Removing per SW205177 as the following GETSCOM creates an + // infinite loop during execution on the FSP. It is not + // clear why that is so we'll address its reinstatement as + // part of the RAS review process. + + // GETSCOM(rc, i_target, EX_OHA_RO_STATUS_REG_0x1002000B, data); + // FAPI_DBG(" Special Wake-up complete (OHA_RO_STATUS(1)!! => 0x%016llx", data.getDoubleWord(0)); + // const uint64_t& OHA_RO_STATUS = data.getDoubleWord(0); - GETSCOM(l_parentTarget, SP_WKUP_REG_ADDRS , data); - FAPI_DBG(" After set of SPWKUP_REG (0x%08llx) => 0x%16llx", SP_WKUP_REG_ADDRS, data.getDoubleWord(0)); + GETSCOM(rc, l_parentTarget, spwkup_address , data); + FAPI_DBG(" After set of SPWKUP_REG (0x%08llx) => 0x%016llx", spwkup_address, data.getDoubleWord(0)); + const uint64_t& SP_WKUP_REG_ADDRESS = spwkup_address; + const uint64_t& SP_WKUP_REG_VALUE = data.getDoubleWord(0); + const uint64_t& POLLCOUNT = (uint64_t)pollcount; + const uint64_t& EX = (uint64_t)attr_chip_unit_pos; + const uint64_t& ENTITY = (uint64_t)i_entity; + PROC_SPCWKUP_OPS& I_OPERATION = i_operation ; + + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_SPCWKUP_TIMEOUT); + break; + + } + else + { + FAPI_INF("Special wakeup done is set. SUCCESS! ... "); + } } count++ ; - } else if (i_operation == SPCWKUP_DISABLE) { FAPI_INF("Clearing Special Wake-up..."); + // If the OHA flag is set, then any subsequent calls to the this + // procedure must return a "good" response or elso an infinite + // loop results for any calling algorithm that first sets + // special wake-up, does a SCOM, and then clears special + // wake-up. + + rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_OHA_FLAG, &i_target, oha_spwkup_flag); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)rc); + break; + } + + if (oha_spwkup_flag) + { + FAPI_INF("OHA special wakeup flag is set so returning with good response to break recursion. Counts are NOT updated."); + // This is a purposeful mid-procedure return + return rc; + } + + if ( count == 1 ) { - GETSCOM(l_parentTarget, SP_WKUP_REG_ADDRS , data); - FAPI_DBG(" Before clear of SPWKUP_REG (0x%08llx) => =>0x%16llx", SP_WKUP_REG_ADDRS, data.getDoubleWord(0)); + GETSCOM(rc, l_parentTarget, spwkup_address , data); + FAPI_DBG(" Before clear of SPWKUP_REG (0x%08llx) => =>0x%016llx", spwkup_address, data.getDoubleWord(0)); e_rc=data.flushTo0(); - E_RC_CHECK(e_rc, l_rc); + E_RC_CHECK(e_rc, rc); - PUTSCOM(l_parentTarget, SP_WKUP_REG_ADDRS , data); - FAPI_DBG(" After clear putscom of SPWKUP_REG (0x%08llx) => 0x%16llx", SP_WKUP_REG_ADDRS, data.getDoubleWord(0)); + PUTSCOM(rc, l_parentTarget, spwkup_address , data); + FAPI_DBG(" After clear putscom of SPWKUP_REG (0x%08llx) => 0x%016llx", spwkup_address, data.getDoubleWord(0)); // This puts an inherent delay in the propagation of the reset transition. - GETSCOM(l_parentTarget, SP_WKUP_REG_ADDRS , data); - FAPI_DBG(" After read (delay) of SPWKUP_REG (0x%08llx) 0x%16llx", SP_WKUP_REG_ADDRS, data.getDoubleWord(0)); + GETSCOM(rc, l_parentTarget, spwkup_address , data); + FAPI_DBG(" After read (delay) of SPWKUP_REG (0x%08llx) 0x%016llx", spwkup_address, data.getDoubleWord(0)); count -- ; } else if ( count > 1 ) { - FAPI_INF("Other processes having clear Special Wake-up pending. Chiplet is still in Special Wake-up state."); + FAPI_INF("Other processes have clear Special Wake-up pending. Chiplet is still in Special Wake-up state."); count -- ; } - else + else // this should never happen { - FAPI_ERR("Illegal Special wake up operation : already Disabled on this platform %x", i_entity); - FAPI_ERR (" FSP_COUNT = %d , OCC_COUNT = %d , PHYP_COUNT = %d ", FSP_SPWKUP_COUNT ,OCC_SPWKUP_COUNT ,PHYP_SPWKUP_COUNT); + FAPI_ERR("Ineffective Special wake up Disable operation as it is already disabled for this platform %x", i_entity); + FAPI_ERR (" FSP_COUNT = %d , OCC_COUNT = %d , PHYP_COUNT = %d ", fsp_spwkup_count ,occ_spwkup_count ,phyp_spwkup_count); PROC_SPCWKUP_OPS & I_OPERATION = i_operation ; - FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_SPCWKUP_CODE_BAD_OP); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_SPCWKUP_CODE_BAD_OP); break; } - GETSCOM(l_parentTarget, SP_WKUP_REG_ADDRS , data); - FAPI_DBG(" After configuring SPWKUP_REG value =>0x%16llx", data.getDoubleWord(0)); + GETSCOM(rc, l_parentTarget, spwkup_address , data); + FAPI_DBG(" After configuring SPWKUP_REG value =>0x%016llx", data.getDoubleWord(0)); + + } + else if (i_operation == SPCWKUP_FORCE_DEASSERT) + { + + GETSCOM(rc, l_parentTarget, spwkup_address , data); + FAPI_DBG(" Before clear of SPWKUP_REG (0x%08llx) => =>0x%016llx", spwkup_address, data.getDoubleWord(0)); + + e_rc=data.flushTo0(); + E_RC_CHECK(e_rc, rc); + PUTSCOM(rc, l_parentTarget, spwkup_address , data); + FAPI_DBG(" After clear putscom of SPWKUP_REG (0x%08llx) => 0x%016llx", spwkup_address, data.getDoubleWord(0)); + + // This puts an inherent delay in the propagation of the reset transition. + GETSCOM(rc, l_parentTarget, spwkup_address , data); + FAPI_DBG(" After read (delay) of SPWKUP_REG (0x%08llx) 0x%016llx", spwkup_address, data.getDoubleWord(0)); + + count = 0; } else { - FAPI_ERR("Please specify operation either ENABLE or DISABLE. Operation %x", i_operation ); + FAPI_ERR("ENABLE, DISABLE or INIT must be specified. Operation %x", i_operation ); PROC_SPCWKUP_OPS & I_OPERATION = i_operation ; - FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_SPCWKUP_CODE_BAD_OP); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_SPCWKUP_CODE_BAD_OP); break; } @@ -402,39 +615,83 @@ p8_cpu_special_wakeup( const fapi::Target& i_target, if ( i_entity == OCC ) { - OCC_SPWKUP_COUNT = count ; - l_rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OCC, &i_target, OCC_SPWKUP_COUNT ); - if (l_rc) + occ_spwkup_count = count ; + rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OCC, &i_target, occ_spwkup_count ); + if (rc) { - FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_OCC with l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_OCC with rc = 0x%x", (uint32_t)rc); break; } } else if (i_entity == FSP) { - FSP_SPWKUP_COUNT = count ; - l_rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_FSP, &i_target, FSP_SPWKUP_COUNT ); - if (l_rc) + fsp_spwkup_count = count ; + rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_FSP, &i_target, fsp_spwkup_count ); + if (rc) { - FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_FSP with l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_FSP with rc = 0x%x", (uint32_t)rc); break; } } else if (i_entity == PHYP) { - PHYP_SPWKUP_COUNT = count; - l_rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_PHYP, &i_target, PHYP_SPWKUP_COUNT ); - if (l_rc) + phyp_spwkup_count = count; + rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_PHYP, &i_target, phyp_spwkup_count ); + if (rc) { - FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_PHYP1 with l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_PHYP with rc = 0x%x", (uint32_t)rc); break; } } - FAPI_INF (" FSP_COUNT = %d , OCC_COUNT = %d , PHYP_COUNT = %d ", FSP_SPWKUP_COUNT ,OCC_SPWKUP_COUNT ,PHYP_SPWKUP_COUNT); + FAPI_INF (" FSP_COUNT = %d , OCC_COUNT = %d , PHYP_COUNT = %d ", fsp_spwkup_count ,occ_spwkup_count ,phyp_spwkup_count); } while (0); - return l_rc ; + // Clean up the OHA flag as it should not be set out of this exit (normal + // and error) path. Note: there is ia mid-procedure return above. + oha_rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_OHA_FLAG, &i_target, oha_spwkup_flag); + if (oha_rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)oha_rc); + } + else + { + if (oha_spwkup_flag) + { + oha_spwkup_flag = 0; + + oha_rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OHA_FLAG, &i_target, oha_spwkup_flag); + if (oha_rc) + { + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)oha_rc); + } + + FAPI_ERR("Clearing OHA flag attribute upon procedure exit. This is NOT expected"); + PROC_SPCWKUP_OPS& I_OPERATION = i_operation ; + const uint64_t& EX = (uint64_t)attr_chip_unit_pos; + const uint64_t& ENTITY = (uint64_t)i_entity; + const uint64_t& PHYP_SPCWKUP_COUNT = (uint64_t)phyp_spwkup_count; + const uint64_t& FSP_SPCWKUP_COUNT = (uint64_t)fsp_spwkup_count; + const uint64_t& OCC_SPCWKUP_COUNT = (uint64_t)occ_spwkup_count; + FAPI_SET_HWP_ERROR(oha_rc, RC_PROCPM_SPCWKUP_OHA_FLAG_SET_ON_EXIT); + + } + } + + // Exit with the proper return code. rc has priority over oha_rc as it indicates + // the first failure. + if (!rc.ok()) + { + return rc ; + } + else if (!oha_rc.ok()) + { + return oha_rc ; + } + else + { + return rc; + } } diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.H index 99b3686de..616ccd119 100644 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.H +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_cpu_special_wakeup.H,v 1.5 2013/04/16 12:14:35 pchatnah Exp $ +// $Id: p8_cpu_special_wakeup.H,v 1.6 2013/08/02 18:59:22 stillgs Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_cpu_special_wakeup.H,v $ //------------------------------------------------------------------------------ // *| @@ -65,7 +65,8 @@ enum PROC_SPCWKUP_OPS { SPCWKUP_DISABLE, SPCWKUP_ENABLE, - SPCWKUP_INIT + SPCWKUP_INIT, + SPCWKUP_FORCE_DEASSERT }; diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C index c9247ee01..6059dcc57 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_pcbs_init.C,v 1.18 2013/05/23 02:18:02 stillgs Exp $ +// $Id: p8_pcbs_init.C,v 1.19 2013/08/02 19:03:12 stillgs Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pcbs_init.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -185,7 +185,7 @@ /// -- PCBS_OCC_Heartbeat_Reg[8] /// /// // IVRM Setup -/// get the mrwb attribute ivrms_enabled -- If '0' Salerno, if '1' Venice +/// get the mrwb `ibute ivrms_enabled -- If '0' Salerno, if '1' Venice /// if ivrms_enabled { /// set ivrm_fsm_enable = 0 -- PCBS_iVRM_Control_Status_Reg[0] /// -- ivrm_fsm_enable have be '0' to enable bypass_b writes @@ -346,13 +346,13 @@ using namespace fapi; if(e_rc) \ { \ FAPI_ERR("Set DoubleWord failed. With rc = 0x%x", (uint32_t)e_rc); \ - l_rc.setEcmdError(e_rc); \ + rc.setEcmdError(e_rc); \ break; \ } \ FAPI_DBG("Scan0 equivalent reset of 0x%08llx to 0x%16llX", \ _mi_address, _mi_reset_value); \ - l_rc = fapiPutScom(_mi_target, _mi_address, _mi_buffer); \ - if(!l_rc.ok()) \ + rc = fapiPutScom(_mi_target, _mi_address, _mi_buffer); \ + if(!rc.ok()) \ { \ FAPI_ERR("PutScom error to address 0x%08llx", _mi_address); \ break; \ @@ -365,13 +365,13 @@ using namespace fapi; if(e_rc) \ { \ FAPI_ERR("Set Word failed. With rc = 0x%x", (uint32_t)e_rc); \ - l_rc.setEcmdError(e_rc); \ + rc.setEcmdError(e_rc); \ break; \ } \ FAPI_DBG("Scan0 equivalent reset of 0x%08llx to 0x%08X", \ _mi_address, _mi_reset_value); \ - l_rc = fapiPutScom(_mi_target, _mi_address, _mi_buffer); \ - if(!l_rc.ok()) \ + rc = fapiPutScom(_mi_target, _mi_address, _mi_buffer); \ + if(!rc.ok()) \ { \ FAPI_ERR("PutScom error to address 0x%08llx", _mi_address); \ break; \ @@ -467,7 +467,7 @@ p8_pcbs_init_scan0(const Target &i_target, uint8_t i_ex_number); fapi::ReturnCode p8_pcbs_init( const Target& i_target, uint32_t i_mode) { - fapi::ReturnCode l_rc; + fapi::ReturnCode rc; //Declare parms struct struct_pcbs_val_init_type pcbs_val_init; @@ -479,10 +479,10 @@ p8_pcbs_init( const Target& i_target, uint32_t i_mode) if ( i_mode == PM_CONFIG ) { - l_rc=p8_pcbs_init_config(i_target); - if (l_rc) + rc=p8_pcbs_init_config(i_target); + if (rc) { - FAPI_ERR("p8_pcbs_init_config failed. With l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("p8_pcbs_init_config failed. With rc = 0x%x", (uint32_t)rc); break; } @@ -490,10 +490,10 @@ p8_pcbs_init( const Target& i_target, uint32_t i_mode) else if ( i_mode == PM_INIT ) { - l_rc=p8_pcbs_init_init(i_target); - if (l_rc) + rc=p8_pcbs_init_init(i_target); + if (rc) { - FAPI_ERR("p8_pcbs_init_init failed. With l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("p8_pcbs_init_init failed. With rc = 0x%x", (uint32_t)rc); break; } } @@ -502,8 +502,9 @@ p8_pcbs_init( const Target& i_target, uint32_t i_mode) // ---------------------------------------------------------------------- // Assign default values // ---------------------------------------------------------------------- + // These are only needed to put the hardware back to a known state from + // which the OCC can start again in enabling Pstates - /// \todo CHECK: Review those defaults pcbs_val_init.MAX_PSAFE_FSM_LOOPS = 20; // PMSR poll attempts pcbs_val_init.MAX_DELAY = 1000000; // in ns; 1ms pcbs_val_init.MAX_SIM_CYCLES = 1000; @@ -517,46 +518,46 @@ p8_pcbs_init( const Target& i_target, uint32_t i_mode) pcbs_val_init.KUV = 0; // Default pcbs_val_init.ivrms_enabled = 1 ; - // l_rc = FAPI_ATTR_GET( ATTR_PM_IVRMS_ENABLED, + // rc = FAPI_ATTR_GET( ATTR_PM_IVRMS_ENABLED, // &i_target, // pcbs_val_init.ivrms_enabled); - if (l_rc) + if (rc) { - FAPI_ERR("fapiGetAttribute of ATTR_PM_IVRMS_ENABLED with rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetAttribute of ATTR_PM_IVRMS_ENABLED with rc = 0x%x", (uint32_t)rc); break; } -// l_rc = FAPI_ATTR_GET( ATTR_PM_SAFE_PSTATE, +// rc = FAPI_ATTR_GET( ATTR_PM_SAFE_PSTATE, // &i_target, // pcbs_val_init.PSAFE); - if (l_rc) + if (rc) { - FAPI_ERR("fapiGetAttribute of ATTR_PM_SAFE_PSTATE with rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetAttribute of ATTR_PM_SAFE_PSTATE with rc = 0x%x", (uint32_t)rc); break; } -// l_rc = FAPI_ATTR_GET( ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM, +// rc = FAPI_ATTR_GET( ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM, // &i_target, // pcbs_val_init.PUV_MIN); - if (l_rc) + if (rc) { - FAPI_ERR("fapiGetAttribute of ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM with rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetAttribute of ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM with rc = 0x%x", (uint32_t)rc); break; } - // l_rc = FAPI_ATTR_GET( ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM, + // rc = FAPI_ATTR_GET( ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM, // &i_target, // pcbs_val_init.PUV_MAX); - if (l_rc) + if (rc) { - FAPI_ERR("fapiGetAttribute of ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM with rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetAttribute of ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM with rc = 0x%x", (uint32_t)rc); break; } - l_rc = p8_pcbs_init_reset( i_target, pcbs_val_init); - if (l_rc) + rc = p8_pcbs_init_reset( i_target, pcbs_val_init); + if (rc) { - FAPI_ERR("p8_pcbs_init_reset failed. With l_rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("p8_pcbs_init_reset failed. With rc = 0x%x", (uint32_t)rc); break; } } @@ -564,12 +565,12 @@ p8_pcbs_init( const Target& i_target, uint32_t i_mode) { FAPI_ERR("Unknown mode passed to p8_pcbs_init. Mode %x ....", i_mode); const uint64_t& MODE = (uint32_t)i_mode; - FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PCBS_CODE_BAD_MODE); + FAPI_SET_HWP_ERROR(rc, RC_PROC_PCBS_CODE_BAD_MODE); } } while(0); FAPI_INF("Exiting p8_pcbs_init ..."); - return l_rc; + return rc; } @@ -586,7 +587,7 @@ p8_pcbs_init( const Target& i_target, uint32_t i_mode) fapi::ReturnCode p8_pcbs_init_config(const Target& i_target) { - fapi::ReturnCode l_rc; + fapi::ReturnCode rc; /// Function moved in p8_pfet_int.C /// FAPI_DBG("*************************************"); @@ -594,7 +595,7 @@ p8_pcbs_init_config(const Target& i_target) /// FAPI_DBG("*************************************"); /// - return l_rc; + return rc; } //end CONFIG @@ -610,29 +611,28 @@ p8_pcbs_init_config(const Target& i_target) fapi::ReturnCode p8_pcbs_init_init(const Target& i_target) { - fapi::ReturnCode l_rc; + fapi::ReturnCode rc; uint32_t e_rc; // eCmd returncode ecmdDataBufferBase data(64); // Variables std::vector<fapi::Target> l_exChiplets; - fapi::TargetState l_state = TARGET_STATE_FUNCTIONAL; - uint8_t l_functional = 0; uint8_t l_ex_number = 0; uint64_t address; + uint64_t ex_offset; FAPI_INF("p8_pcbs_init_init beginning for target %s ...", i_target.toEcmdString()); do { - l_rc = fapiGetChildChiplets(i_target, + rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_EX_CHIPLET, l_exChiplets, - l_state); - if (l_rc) + TARGET_STATE_FUNCTIONAL); + if (rc) { - FAPI_ERR("fapiGetChildChiplets with rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetChildChiplets with rc = 0x%x", (uint32_t)rc); break; } @@ -641,60 +641,42 @@ p8_pcbs_init_init(const Target& i_target) // For each chiplet in the functional list for (uint8_t c=0; c< l_exChiplets.size(); c++) { - FAPI_DBG("\tLoop Variable %d ",c); - l_rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_exChiplets[c], l_functional); - if (l_rc) + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[c], l_ex_number); + if (rc) { - FAPI_ERR("fapiGetAttribute of ATTR_FUNCTIONAL with rc = 0x%x", (uint32_t)l_rc); - break; - } - - - if (!l_functional) - { - FAPI_DBG("Core number = %d is not functional", c); - // Iterate - continue; - } - - // The ex is functional let's build the SCOM address - l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[c], l_ex_number); - if (l_rc) - { - FAPI_ERR("No functional chiplets exist"); - FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)rc); break; } FAPI_DBG("Core number = %d", l_ex_number); + ex_offset = l_ex_number * 0x01000000; + // Set DPLL Lock Replacement value (15:23) = 2 (eg bit 22 = 1) FAPI_INF ("Set DPLL Lock Replacement value of EX_DPLL_CPM_PARM_REG_0x1*0F0152 "); - address = EX_DPLL_CPM_PARM_REG_0x100F0152 + - (l_ex_number * 0x01000000); - GETSCOM(i_target, address, data); + address = EX_DPLL_CPM_PARM_REG_0x100F0152 + ex_offset; + GETSCOM(rc, i_target, address, data); e_rc = data.setBit(22); - E_RC_CHECK(e_rc, l_rc); + E_RC_CHECK(e_rc, rc); - PUTSCOM(i_target, address, data); + PUTSCOM(rc, i_target, address, data); // ****************************************************************** // - Enable DPLL Lock Replacement mode // ****************************************************************** FAPI_INF("Set DPLL Lock Replacement mode"); - address = EX_PCBSPM_MODE_REG_0x100F0156 + - (l_ex_number * 0x01000000); + address = EX_PCBSPM_MODE_REG_0x100F0156 + ex_offset; - GETSCOM(i_target, address, data ); + GETSCOM(rc, i_target, address, data ); e_rc |= data.setBit(7); - E_RC_CHECK(e_rc, l_rc); + E_RC_CHECK(e_rc, rc); - PUTSCOM(i_target, address, data ); + PUTSCOM(rc, i_target, address, data ); // ****************************************************************** // - set PCBS_PM_PMGP1_REG_1 @@ -706,10 +688,10 @@ p8_pcbs_init_init(const Target& i_target) // Clear buffer e_rc = data.flushTo0(); e_rc |= data.setBit(11); // Force OCC SPR Mode = 1 - E_RC_CHECK(e_rc, l_rc); + E_RC_CHECK(e_rc, rc); - address = EX_PMGP1_OR_0x100F0105 + (l_ex_number * 0x01000000); - PUTSCOM(i_target, address, data ); + address = EX_PMGP1_OR_0x100F0105 + ex_offset; + PUTSCOM(rc, i_target, address, data ); FAPI_INF("Forced OCC SPR Mode"); @@ -720,11 +702,10 @@ p8_pcbs_init_init(const Target& i_target) // Clear buffer e_rc = data.flushTo0(); - E_RC_CHECK(e_rc, l_rc); + E_RC_CHECK(e_rc, rc); - address = EX_PCBS_Power_Management_Control_Reg_0x100F0159 + - (l_ex_number * 0x01000000); - PUTSCOM(i_target, address, data); + address = EX_PCBS_Power_Management_Control_Reg_0x100F0159 + ex_offset; + PUTSCOM(rc, i_target, address, data); // ****************************************************************** // - Power Management Idle Control Reg @@ -733,22 +714,21 @@ p8_pcbs_init_init(const Target& i_target) // Clear buffer e_rc = data.flushTo0(); - E_RC_CHECK(e_rc, l_rc); + E_RC_CHECK(e_rc, rc); - address = EX_PCBS_Power_Management_Idle_Control_Reg_0x100F0158 + - (l_ex_number * 0x01000000); - PUTSCOM(i_target, address, data); + address = EX_PCBS_Power_Management_Idle_Control_Reg_0x100F0158 + ex_offset; + PUTSCOM(rc, i_target, address, data); FAPI_INF ("PMCR default value adjustment (Hardware flush 0) of EX_PCBS_Power_Management_Idle_Control_Reg_0x1*0F0158 " ); } //END FOR - if (!l_rc.ok() ) + if (!rc.ok() ) { break; } } while(0); - return l_rc; + return rc; } //end INIT @@ -767,7 +747,7 @@ p8_pcbs_init_init(const Target& i_target) fapi::ReturnCode p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_init) { - fapi::ReturnCode l_rc; + fapi::ReturnCode rc; uint32_t e_rc; // ecmd returncode ecmdDataBufferBase data(64); @@ -776,22 +756,56 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i // Variables std::vector<fapi::Target> l_exChiplets; - fapi::TargetState l_state = TARGET_STATE_FUNCTIONAL; - uint8_t l_functional = 0; uint8_t l_ex_number = 0; uint64_t address; - uint32_t loopcount = 0; // number of times PCBS-PMSR has been checked + uint64_t ex_offset; + + uint32_t loopcount = 0; + // PCBSPM MODE bits + const uint32_t PCBSPMMODE_ENABLE_PSTATE_MODE_BIT = 0; + const uint32_t PCBSPMMODE_ENABLE_GLOBAL_PSTATE_REQ_BIT = 2; + + // PMGP1 bits + const uint32_t PMGP1_DPLL_FREQ_OVERRIDE_ENABLE = 10; + const uint32_t PMGP1_PM_SPR_OVERRIDE_EN_BIT = 11; + const uint32_t PMGP1_FORCE_SAFE_MODE_BIT = 12; + + // PMSR bits + const uint32_t PMSR_PSAFE_MODE_ACTIVE_BIT = 33; + const uint32_t PMSR_ALL_FSMS_IN_SAFE_STATE_BIT = 36; + + // PMCR bits + const uint32_t PMSR_AUTO_OVERRIDE0_PSTATE_LIMIT_EN_BIT = 16; + const uint32_t PMSR_AUTO_OVERRIDE1_PSTATE_LIMIT_EN_BIT = 17; + + // PMICR bits + const uint32_t PMICR_NAP_PSTATE_EN_BIT = 8; + const uint32_t PMICR_SLEEP_PSTATE_EN_BIT = 24; + const uint32_t PMICR_WINKLE_PSTATE_EN_BIT = 40; + + // GP3 bits + const uint32_t GP3_RESCLK_DIS_BIT = 22; + + // PCBS OCC Heartbeat bits + const uint32_t POHR_OCC_HEARTBEAT_EN_BIT = 8; + + // PCBS OCC Heartbeat bits + const uint32_t IVRMCS_IVRM_FSM_ENABLE_BIT = 0; + const uint32_t IVRMCS_IVRM_CORE_VDD_BYPASS_B_BIT = 4; + const uint32_t IVRMCS_IVRM_CORE_VCS_BYPASS_B_BIT = 6; + const uint32_t IVRMCS_IVRM_ECO_VDD_BYPASS_B_BIT = 8; + const uint32_t IVRMCS_IVRM_ECO_VCS_BYPASS_B_BIT = 10; FAPI_INF("p8_pcbs_init_reset beginning for target %s ...", i_target.toEcmdString()); do { - l_rc = fapiGetChildChiplets(i_target, + rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_EX_CHIPLET, l_exChiplets, - l_state); - if (l_rc) + TARGET_STATE_FUNCTIONAL); + if (rc) { - FAPI_ERR("fapiGetChildChiplets with rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetChildChiplets with rc = 0x%x", (uint32_t)rc); break; } @@ -800,43 +814,17 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i // For each chiplet for (uint8_t c=0; c< l_exChiplets.size(); c++) { - FAPI_DBG("\tLoop Variable %d ",c); - l_rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_exChiplets[c], l_functional); - if (l_rc) + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[c], l_ex_number); + if (rc) { - FAPI_ERR("fapiGetAttribute of ATTR_FUNCTIONAL with rc = 0x%x", (uint32_t)l_rc); - break; - } - - if (!l_functional) - { - FAPI_DBG("Core number = %d is not functional", c); - // Iterate - continue; - } - - // The ex is functional let's build the SCOM address - l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[c], l_ex_number); - if (l_rc) - { - FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)rc); break; } FAPI_DBG("\tCore number = %d", l_ex_number); - // ****************************************************************** - // Set the regs back to scan0 state - NO... NOT HERE! - // ****************************************************************** - - l_rc = p8_pcbs_init_scan0(i_target, l_ex_number); - if (l_rc) - { - FAPI_ERR(" p8_pcbs_init_scan0 failed. With l_rc = 0x%x", (uint32_t)l_rc); - break; - } - + ex_offset = l_ex_number * 0x01000000; // ****************************************************************** // Force safe mode if Pstates are enabled. @@ -845,12 +833,11 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i // [12] force_safe_mode = 1 // ****************************************************************** - address = EX_PCBSPM_MODE_REG_0x100F0156 + - (l_ex_number * 0x01000000); - GETSCOM(i_target, address, data); + address = EX_PCBSPM_MODE_REG_0x100F0156 + ex_offset; + GETSCOM(rc, i_target, address, data); FAPI_DBG("\tPCBS_MODE_REG value 0x%16llX", data.getDoubleWord(0)); - if (data.isBitSet(0)) // Pstates enabled + if (data.isBitSet(PCBSPMMODE_ENABLE_PSTATE_MODE_BIT)) // Pstates enabled { FAPI_INF("Pstate enabled - Force safe mode"); @@ -858,14 +845,13 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i // Using Write OR to just set bit12 // Clear buffer e_rc = data.flushTo0(); - E_RC_CHECK(e_rc, l_rc); + E_RC_CHECK(e_rc, rc); - e_rc = data.setBit(12); // force_safe_mode = 1 - E_RC_CHECK(e_rc, l_rc); + e_rc = data.setBit(PMGP1_FORCE_SAFE_MODE_BIT); // force_safe_mode = 1 + E_RC_CHECK(e_rc, rc); - address = EX_PMGP1_OR_0x100F0105 + - (l_ex_number * 0x01000000);; - PUTSCOM(i_target, address, data); + address = EX_PMGP1_OR_0x100F0105 + ex_offset; + PUTSCOM(rc, i_target, address, data); FAPI_INF("Forced Safe Mode"); @@ -875,27 +861,28 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i // ****************************************************************** // - PCBS_POWER_MANAGEMENT_STATUS_REG[33] safe_mode_active // - PCBS_POWER_MANAGEMENT_STATUS_REG[36] all_fsms_in_safe_state - // // ****************************************************************** FAPI_INF("Psafe Pstate and FSM-stable?"); loopcount = 0; - address = EX_PCBS_POWER_MANAGEMENT_STATUS_REG_0x100F0153 + - (l_ex_number * 0x01000000); - GETSCOM(i_target, address, data); - + address = EX_PCBS_POWER_MANAGEMENT_STATUS_REG_0x100F0153 + ex_offset; // loop until (safe_mode_active AND all_fsms_in_safe_state) - while( data.isBitClear( 33 ) || data.isBitClear( 36 ) ) + do { + + // Read PMSR + GETSCOM(rc, i_target, address, data); + FAPI_DBG("\t loopcount => %d ",loopcount ); // OR timeout .... set to 20 loops if( ++loopcount > pcbs_val_init.MAX_PSAFE_FSM_LOOPS ) { FAPI_ERR("Gave up waiting for Psafe Pstate and FSM-stable!" ); + const fapi::Target& PROC_CHIP = i_target; const uint64_t& LOOPCOUNT = (uint32_t)loopcount; const uint64_t& PMSR = data.getDoubleWord(0); - FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PCBS_CODE_SAFE_FSM_TIMEOUT); + FAPI_SET_HWP_ERROR(rc, RC_PROC_PCBS_CODE_SAFE_FSM_TIMEOUT); break; } @@ -906,19 +893,17 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i FAPI_DBG("\t Wait DELAY: %d ", pcbs_val_init.MAX_DELAY); FAPI_DBG("\t Wait SimCycles: %d ", pcbs_val_init.MAX_SIM_CYCLES); - l_rc = fapiDelay(pcbs_val_init.MAX_DELAY, pcbs_val_init.MAX_SIM_CYCLES); - if (l_rc) + rc = fapiDelay(pcbs_val_init.MAX_DELAY, pcbs_val_init.MAX_SIM_CYCLES); + if (rc) { - FAPI_ERR("fapiDelay(MAX_DELAY, MAX_SIM_CYCLES) failed. With rc = 0x%x", (uint32_t)l_rc); + FAPI_ERR("fapiDelay(MAX_DELAY, MAX_SIM_CYCLES) failed. With rc = 0x%x", (uint32_t)rc); break; } - // Read PMSR again - GETSCOM(i_target, address, data); - - } + } while ( data.isBitClear(PMSR_PSAFE_MODE_ACTIVE_BIT) || + data.isBitClear(PMSR_ALL_FSMS_IN_SAFE_STATE_BIT)); // if error, break the outer loop - if (!l_rc.ok()) + if (!rc.ok()) { break; } @@ -946,26 +931,26 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i FAPI_INF("Hold the DPLL to the value that the last Pstate represents"); // Write calculated values to FREQ_CTRL_REG - address = EX_FREQCNTL_0x100F0151 + (l_ex_number * 0x01000000); - GETSCOM(i_target, address, data); + address = EX_FREQCNTL_0x100F0151 + ex_offset; + GETSCOM(rc, i_target, address, data); FAPI_DBG(" Pre write content of FREQ_CTRL_REG_0x1*0F0151 : %016llX", data.getDoubleWord(0)); // Clear the DPLL bias; did not clear other fields e_rc = data.clearBit(18, 4); - E_RC_CHECK(e_rc, l_rc); + E_RC_CHECK(e_rc, rc); - PUTSCOM(i_target, address, data); + PUTSCOM(rc, i_target, address, data); // Lock the DPLL in via the override mode. Note: this DOES // allow for continued CPM enablement e_rc |= data.flushTo0(); - e_rc |= data.setBit(10); // dpll_freq_override_enable - E_RC_CHECK(e_rc, l_rc); + e_rc |= data.setBit(PMGP1_DPLL_FREQ_OVERRIDE_ENABLE); + E_RC_CHECK(e_rc, rc); - address = EX_PMGP1_OR_0x100F0105 + (l_ex_number * 0x01000000); - PUTSCOM(i_target, address, data); + address = EX_PMGP1_OR_0x100F0105 + ex_offset; + PUTSCOM(rc, i_target, address, data); // ****************************************************************** // - Disable Pstate mode @@ -973,16 +958,15 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i // ****************************************************************** FAPI_INF("Disable Pstate mode and disable Pstate requests"); - address = EX_PCBSPM_MODE_REG_0x100F0156 + - (l_ex_number * 0x01000000); + address = EX_PCBSPM_MODE_REG_0x100F0156 + ex_offset; - GETSCOM(i_target, address, data ); + GETSCOM(rc, i_target, address, data ); - e_rc |= data.clearBit(0); //Disable Pstate mode - e_rc |= data.clearBit(2); //Disable Pstate requests - E_RC_CHECK(e_rc, l_rc); + e_rc |= data.clearBit(PCBSPMMODE_ENABLE_PSTATE_MODE_BIT); + e_rc |= data.clearBit(PCBSPMMODE_ENABLE_GLOBAL_PSTATE_REQ_BIT); + E_RC_CHECK(e_rc, rc); - PUTSCOM(i_target, address, data ); + PUTSCOM(rc, i_target, address, data ); FAPI_INF("Disabled Pstate mode"); @@ -998,11 +982,11 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i // Using Write OR to set bit11 // Clear buffer e_rc = data.flushTo0(); - e_rc |= data.setBit(11); // Force OCC SPR Mode = 1 - E_RC_CHECK(e_rc, l_rc); + e_rc |= data.setBit(PMGP1_PM_SPR_OVERRIDE_EN_BIT); + E_RC_CHECK(e_rc, rc); - address = EX_PMGP1_OR_0x100F0105 + (l_ex_number * 0x01000000); - PUTSCOM(i_target, address, data ); + address = EX_PMGP1_OR_0x100F0105 + ex_offset; + PUTSCOM(rc, i_target, address, data ); FAPI_INF("Forced OCC SPR Mode"); @@ -1014,26 +998,25 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i FAPI_INF("Disabling Global Pstate Request bits "); address = EX_PCBS_Power_Management_Idle_Control_Reg_0x100F0158 + - (l_ex_number * 0x01000000); - GETSCOM(i_target, address, data ); + ex_offset; + GETSCOM(rc, i_target, address, data ); - e_rc |= data.clearBit(8); // Disable Nap Pstate Enable - e_rc |= data.clearBit(24); // Disable Sleep Pstate Enable - e_rc |= data.clearBit(40); // Disable Winkle Pstate Enable - E_RC_CHECK(e_rc, l_rc); + e_rc |= data.clearBit(PMICR_NAP_PSTATE_EN_BIT); + e_rc |= data.clearBit(PMICR_SLEEP_PSTATE_EN_BIT); + e_rc |= data.clearBit(PMICR_WINKLE_PSTATE_EN_BIT); + E_RC_CHECK(e_rc, rc); - PUTSCOM(i_target, address, data ); + PUTSCOM(rc, i_target, address, data ); // Auto overrides - address = EX_PCBS_Power_Management_Control_Reg_0x100F0159 + - (l_ex_number * 0x01000000); - GETSCOM(i_target, address, data ); + address = EX_PCBS_Power_Management_Control_Reg_0x100F0159 + ex_offset; + GETSCOM(rc, i_target, address, data ); - e_rc |= data.clearBit(16); // Disable Auto Override 0 - e_rc |= data.clearBit(17); // Disable Auto Override 1 - E_RC_CHECK(e_rc, l_rc); + e_rc |= data.clearBit(PMSR_AUTO_OVERRIDE0_PSTATE_LIMIT_EN_BIT); + e_rc |= data.clearBit(PMSR_AUTO_OVERRIDE1_PSTATE_LIMIT_EN_BIT); + E_RC_CHECK(e_rc, rc); - PUTSCOM(i_target, address, data ); + PUTSCOM(rc, i_target, address, data ); FAPI_INF("Disabled Global Pstate Requests"); @@ -1046,11 +1029,10 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i e_rc |= data.flushTo0(); e_rc |= data.setByte(0, pcbs_val_init.PMIN_CLIP); //Pmin_clip = -128 e_rc |= data.setByte(1, pcbs_val_init.PMAX_CLIP); //Pmax_clip = 127 - E_RC_CHECK(e_rc, l_rc); + E_RC_CHECK(e_rc, rc); - address = EX_PCBS_Power_Management_Bounds_Reg_0x100F015D + - (l_ex_number * 0x01000000); - PUTSCOM(i_target, address, data ); + address = EX_PCBS_Power_Management_Bounds_Reg_0x100F015D + ex_offset; + PUTSCOM(rc, i_target, address, data ); FAPI_DBG("Pmin/Pmax written to PCBS_Power_Management_Bounds_Reg : %016llX", data.getDoubleWord(0)); @@ -1067,28 +1049,27 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i // Using Write OR to just set bit22 // Clear buffer e_rc = data.flushTo0(); - e_rc = data.setBit(22); //disable RESCLK - E_RC_CHECK(e_rc, l_rc); + e_rc = data.setBit(GP3_RESCLK_DIS_BIT); + E_RC_CHECK(e_rc, rc); - address = EX_GP3_OR_0x100F0014 + (l_ex_number * 0x01000000); - PUTSCOM(i_target, address, data); + address = EX_GP3_OR_0x100F0014 + ex_offset; + PUTSCOM(rc, i_target, address, data); FAPI_INF ("Disabled RESCLK, set bit 22 of GP3_REG_0_RWXx1*0F0012 " ); // ****************************************************************** // Disable OCC Heartbeat // ****************************************************************** - address = EX_PCBS_OCC_Heartbeat_Reg_0x100F0164 + - (l_ex_number * 0x01000000); - GETSCOM(i_target, address, data); + address = EX_PCBS_OCC_Heartbeat_Reg_0x100F0164 + ex_offset; + GETSCOM(rc, i_target, address, data); FAPI_DBG(" Pre write content of PCBS_OCC_HEARTBEAT_REG_0x1*0F0164 : %016llX", data.getDoubleWord(0)); - e_rc = data.clearBit(8); //OCC Heartbeat disable - E_RC_CHECK(e_rc, l_rc); + e_rc = data.clearBit(POHR_OCC_HEARTBEAT_EN_BIT); + E_RC_CHECK(e_rc, rc); - PUTSCOM(i_target, address, data); + PUTSCOM(rc, i_target, address, data); FAPI_INF ("OCC Heartbeat disabled, cleared bit 8 of PCBS_OCC_HEARTBEAT_REG_0x1*0F0164" ); @@ -1104,22 +1085,21 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i if (pcbs_val_init.ivrms_enabled) { - address = EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 + - (l_ex_number * 0x01000000); - GETSCOM(i_target, address, data); + address = EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 + ex_offset; + GETSCOM(rc, i_target, address, data); FAPI_DBG(" Pre write content of PCBS_iVRM_Control_Status_Reg_0x1*0F0154 : %016llX", data.getDoubleWord(0)); - e_rc = data.clearBit(0); // disable ivrms - e_rc |= data.clearBit(4); // ivrm_core_vdd_bypass_b - e_rc |= data.clearBit(6); // ivrm_core_vcs_bypass_b - e_rc |= data.clearBit(8); // ivrm_eco_vdd_bypass_b - e_rc |= data.clearBit(10); // ivrm_eco_vcs_bypass_b - E_RC_CHECK(e_rc, l_rc); + e_rc = data.clearBit(IVRMCS_IVRM_FSM_ENABLE_BIT); + e_rc |= data.clearBit(IVRMCS_IVRM_CORE_VDD_BYPASS_B_BIT); + e_rc |= data.clearBit(IVRMCS_IVRM_CORE_VCS_BYPASS_B_BIT); + e_rc |= data.clearBit(IVRMCS_IVRM_ECO_VDD_BYPASS_B_BIT); + e_rc |= data.clearBit(IVRMCS_IVRM_ECO_VCS_BYPASS_B_BIT); + E_RC_CHECK(e_rc, rc); - PUTSCOM(i_target, address, data); + PUTSCOM(rc, i_target, address, data); // Write twice since ivrm_fsm_enable have to be 0 to enable the set the bypass modes - PUTSCOM(i_target, address, data); + PUTSCOM(rc, i_target, address, data); FAPI_INF ("iVRMs disabled and in bypass-mode" ); } @@ -1127,9 +1107,8 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i // ****************************************************************** // Disable undervolting // ****************************************************************** - address = EX_PCBS_UNDERVOLTING_REG_0x100F015B + - (l_ex_number * 0x01000000); - GETSCOM(i_target, address, data); + address = EX_PCBS_UNDERVOLTING_REG_0x100F015B + ex_offset; + GETSCOM(rc, i_target, address, data); FAPI_DBG(" Pre write content of PCBS_UNDERVOLTING_REG_0x1*0F015B : %016llX", data.getDoubleWord(0)); @@ -1137,11 +1116,9 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i e_rc |= data.setByte(0, pcbs_val_init.PUV_MIN); //Puv_min = -128 e_rc |= data.setByte(1, pcbs_val_init.PUV_MAX); //Puv_max = -128 e_rc |= data.setByte(2, pcbs_val_init.KUV); //Kuv = 0 - E_RC_CHECK(e_rc, l_rc); - - PUTSCOM(i_target, address, data); - + E_RC_CHECK(e_rc, rc); + PUTSCOM(rc, i_target, address, data); FAPI_DBG("\t PUV_MIN => %d ", pcbs_val_init.PUV_MIN ); FAPI_DBG("\t PUV_MAX => %d ", pcbs_val_init.PUV_MAX ); @@ -1153,25 +1130,36 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i // Disable Local Pstate Frequency Target mechanism // ****************************************************************** address = EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168 - + (l_ex_number * 0x01000000); - GETSCOM(i_target, address, data); + + ex_offset; + GETSCOM(rc, i_target, address, data); e_rc |= data.clearBit(20); - E_RC_CHECK(e_rc, l_rc); - - PUTSCOM(i_target, address, data); + E_RC_CHECK(e_rc, rc); + PUTSCOM(rc, i_target, address, data); FAPI_INF ("Local Pstate Frequency Target mechanism disabled" ); + + // ****************************************************************** + // Set other regs back to scan0 state + // ****************************************************************** + + rc = p8_pcbs_init_scan0(i_target, l_ex_number); + if (rc) + { + FAPI_ERR(" p8_pcbs_init_scan0 failed. With rc = 0x%x", (uint32_t)rc); + break; + } + } // Chiplet loop } while(0); - if (l_rc.ok()) + if (rc.ok()) { - FAPI_INF("Reset complete ...."); + FAPI_INF("Reset complete ...\n"); } - return l_rc; + return rc; } // end RESET //------------------------------------------------------------------------------ @@ -1188,17 +1176,20 @@ p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_i fapi::ReturnCode p8_pcbs_init_scan0(const Target &i_target, uint8_t i_ex_number) { - fapi::ReturnCode l_rc; + fapi::ReturnCode rc; uint32_t e_rc; // ecmd returncode ecmdDataBufferBase data(64); uint64_t address; + uint64_t ex_offset; uint64_t reset_doubleword; uint32_t reset_word; do { + ex_offset = i_ex_number * 0x01000000; + // ****************************************************************** - // initialize all pm_reg with scan-zero values upfront + // Initialize PM Regs with scan-zero values // ***************************************************************** FAPI_INF("Put selective PCBSLV_PM registers to the scan0 value that are touched by OCC firmware"); @@ -1210,7 +1201,7 @@ p8_pcbs_init_scan0(const Target &i_target, uint8_t i_ex_number) // VDD to operational chiplets. // EX_PFVddCntlStat_REG_0x100F010E not reset has this would disrupt // VCS to operational chiplets - // EX_FREQCNTL_0x100F0151not reset has this would disrupt the frequency + // EX_FREQCNTL_0x100F0151 not reset has this would disrupt the frequency // of operational chiplets // EX_DPLL_CPM_PARM_REG_0x100F0152 not reset has this has DPLL control // bits that could/would disrupt operational chiplets @@ -1225,74 +1216,64 @@ p8_pcbs_init_scan0(const Target &i_target, uint8_t i_ex_number) // by register accesses //---- - address = EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165 - + (i_ex_number * 0x01000000); + address = EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165 + ex_offset; reset_doubleword = EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165_scan0; SETDWSCAN0(i_target, address, data, reset_doubleword ); //---- - address = EX_PMErrMask_REG_0x100F010A - + (i_ex_number * 0x01000000); + address = EX_PMErrMask_REG_0x100F010A + ex_offset; reset_word = EX_PMErrMask_REG_0x100F010A_scan0; SETSCAN0(i_target, address, data, reset_word ); // OCC does not mess with the PFET delays so these are left in tact. // This can only be done IF the IVRM is previously disabled. - address = EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 - + (i_ex_number * 0x01000000); + address = EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 + ex_offset; reset_word = EX_PCBS_iVRM_Control_Status_Reg_0x100F0154_scan0; SETSCAN0(i_target, address, data, reset_word ); //---- - address = EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155 - + (i_ex_number * 0x01000000); + address = EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155 + ex_offset; reset_word = EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155_scan0; SETSCAN0(i_target, address, data, reset_word ); //---- - address = EX_PCBS_PMC_VF_CTRL_REG_0x100F015A - + (i_ex_number * 0x01000000); + address = EX_PCBS_PMC_VF_CTRL_REG_0x100F015A + ex_offset; reset_word = EX_PCBS_PMC_VF_CTRL_REG_0x100F015A_scan0; SETSCAN0(i_target, address, data, reset_word ); //---- - address = EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C - + (i_ex_number * 0x01000000); + address = EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C + ex_offset; reset_word = EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C_scan0; SETSCAN0(i_target, address, data, reset_word ); //---- - address = EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E - + (i_ex_number * 0x01000000); + address = EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E + ex_offset; reset_word = EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E_scan0; SETSCAN0(i_target, address, data, reset_word ); //---- - address = EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162 - + (i_ex_number * 0x01000000); + address = EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162 + ex_offset; reset_word = EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162_scan0; SETSCAN0(i_target, address, data, reset_word ); //---- - address = EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163 - + (i_ex_number * 0x01000000); + address = EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163 + ex_offset; reset_word = EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163_scan0; SETSCAN0(i_target, address, data, reset_word ); //---- - address = EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166 - + (i_ex_number * 0x01000000); + address = EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166 + ex_offset; reset_word = EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166_scan0; SETSCAN0(i_target, address, data, reset_word ); /// \todo Regcheck error check at latest model // address = EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168 - // + (i_ex_number * 0x01000000); + // + ex_offset; // reset_word = EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168_scan0; // SETSCAN0(i_target, address, data, reset_word ); } while(0); - return l_rc; + return rc; } } //end extern C @@ -1303,6 +1284,13 @@ This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: p8_pcbs_init.C,v $ +Revision 1.19 2013/08/02 19:03:12 stillgs + +- Fix for SW209736 (OCC Reset Procedure incorrectly sets Freq to Turbo Value) +- Removed redundant check of functional attribute (Gerrit) +- Moved reg bit definitions to literals for clarity +- General clean-up in prep for RAS reviews. Added some FFDC info. + Revision 1.18 2013/05/23 02:18:02 stillgs Fix error_flag compile issue by removing it as coming header change will do anyway diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C index faa456221..4545c8be4 100644 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_pmc_init.C,v 1.35 2013/06/07 19:17:24 stillgs Exp $ +// $Id: p8_pmc_init.C,v 1.36 2013/08/02 19:09:07 stillgs Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pmc_init.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -100,19 +100,20 @@ pmc_config_spivid_settings(const Target& l_pTarget) uint32_t attr_pm_spivid_inter_retry_delay_value; uint32_t attr_pm_spivid_inter_retry_delay; - + FAPI_INF("pmc_config_spivid start..."); do { - FAPI_INF("Entering the config function"); //---------------------------------------------------------- - GETATTR( ATTR_FREQ_PB, + GETATTR( rc, + ATTR_FREQ_PB, "ATTR_FREQ_PB", NULL, attr_proc_nest_frequency); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_FREQUENCY, + GETATTR_DEFAULT( rc, + ATTR_PM_SPIVID_FREQUENCY, "ATTR_PM_SPIVID_FREQUENCY", NULL, attr_pm_spivid_frequency, @@ -123,7 +124,8 @@ pmc_config_spivid_settings(const Target& l_pTarget) (attr_pm_spivid_frequency*8)-1 ); - SETATTR( ATTR_PM_SPIVID_CLOCK_DIVIDER, + SETATTR( rc, + ATTR_PM_SPIVID_CLOCK_DIVIDER, "ATTR_PM_SPIVID_CLOCK_DIVIDER", &l_pTarget, attr_pm_spivid_clock_divider); @@ -132,7 +134,8 @@ pmc_config_spivid_settings(const Target& l_pTarget) // Delay between command and status frames of a SPIVID WRITE operation // (binary in nanoseconds) - GETATTR_DEFAULT( ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS, + GETATTR_DEFAULT( rc, + ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS, "ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS", &l_pTarget, attr_pm_spivid_interframe_delay_write_status, @@ -144,7 +147,8 @@ pmc_config_spivid_settings(const Target& l_pTarget) attr_pm_spivid_interframe_delay_write_status_value = attr_pm_spivid_interframe_delay_write_status / 100; - SETATTR( ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE, + SETATTR( rc, + ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE, "ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE", &l_pTarget, attr_pm_spivid_interframe_delay_write_status_value); @@ -154,7 +158,8 @@ pmc_config_spivid_settings(const Target& l_pTarget) // Delay between SPIVID reture attempts when WRITE command status // indicates an error (binary in nanoseconds) - GETATTR_DEFAULT( ATTR_PM_SPIVID_INTER_RETRY_DELAY, + GETATTR_DEFAULT( rc, + ATTR_PM_SPIVID_INTER_RETRY_DELAY, "ATTR_PM_SPIVID_INTER_RETRY_DELAY", &l_pTarget, attr_pm_spivid_inter_retry_delay, @@ -169,15 +174,17 @@ pmc_config_spivid_settings(const Target& l_pTarget) attr_pm_spivid_inter_retry_delay_value = attr_pm_spivid_inter_retry_delay / 100; - SETATTR( ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE, + SETATTR( rc, + ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE, "ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE", &l_pTarget, attr_pm_spivid_inter_retry_delay_value); - FAPI_INF("Exiting the config function"); } while(0); + FAPI_INF("pmc_config_spivid end..."); + return rc ; } @@ -193,11 +200,15 @@ pmc_config_spivid_settings(const Target& l_pTarget) * @retval ERROR defined in xml */ fapi::ReturnCode -pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 ) +pmc_reset_function( const fapi::Target& i_target1 , + const fapi::Target& i_target2, + uint32_t i_mode) { fapi::ReturnCode rc; ecmdDataBufferBase data(64); + ecmdDataBufferBase pmcmode_master(64); + ecmdDataBufferBase pmcmode_slave(64); // ecmdDataBufferBase mask(64); uint32_t e_rc = 0; uint32_t count = 0 ; @@ -228,6 +239,8 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 uint8_t attr_dcm_installed_2 = 0; uint64_t any_error = 0; + FAPI_INF("pmc_reset start..."); + do { // Check for validity of passed parms @@ -246,8 +259,8 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 if (attr_dcm_installed_1 == 0) { - // target2 should be NULL - // if not NULL, exit with config error + // target2 should be NULL + // if not NULL, exit with config error if (i_target2.getType() != TARGET_TYPE_NONE ) { FAPI_ERR ("config error : target2 is not null for target1 dcm not installed case"); @@ -267,24 +280,26 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // break; //} - if (i_target2.getType() != TARGET_TYPE_NONE ) - { rc = FAPI_ATTR_GET(ATTR_PROC_DCM_INSTALLED, &i_target2, attr_dcm_installed_2); - if (rc) - { - FAPI_ERR("fapiGetAttribute of ATTR_DCM_INSTALLED with rc = 0x%x", (uint32_t)rc); - break; - } - FAPI_INF (" ATTR_DCM_INSTALLED value in reset function = 0x%x", attr_dcm_installed_2 ); + if (i_target2.getType() != TARGET_TYPE_NONE ) + { + rc = FAPI_ATTR_GET(ATTR_PROC_DCM_INSTALLED, &i_target2, attr_dcm_installed_2); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_DCM_INSTALLED with rc = 0x%x", (uint32_t)rc); + break; + } + FAPI_INF (" ATTR_DCM_INSTALLED value in reset function = 0x%x", attr_dcm_installed_2 ); - if (attr_dcm_installed_2 != 1) - { - FAPI_ERR ("config error: DCM_INSTALLED target2 does not match target1"); - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_DCM_INSTALL_ERROR); - break; - } + if (attr_dcm_installed_2 != 1) + { + FAPI_ERR ("config error: DCM_INSTALLED target2 does not match target1"); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_DCM_INSTALL_ERROR); + break; + } - dcm = true; - } + dcm = true; + + } } //////////////////////////////////////////////////////////////////////////// @@ -295,7 +310,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 //////////////////////////////////////////////////////////////////////////// - FAPI_INF("Performing STEP 1"); + FAPI_INF("Determine master chip and slave targets"); rc = FAPI_ATTR_GET( ATTR_PM_SPIVID_PORT_ENABLE, &i_target1, attr_pm_spivid_port_enable1); @@ -307,58 +322,20 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 FAPI_INF (" value read from the attribute attr_pm_spivid_port_enable in reset function = 0x%x", attr_pm_spivid_port_enable1); - // \todo Removing until as the secondary port enable attrributes are irrelevant - /* - if (dcm) - { - rc = FAPI_ATTR_GET( ATTR_PM_SPIVID_PORT_ENABLE, - &i_target2, - attr_pm_spivid_port_enable2); - if (rc) - { - FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_PORT_ENABLE with rc = 0x%x", (uint32_t)rc); - break; - } - FAPI_INF (" value read from the attribute attr_pm_spivid_port_enable in reset function = 0x%x", - attr_pm_spivid_port_enable2); - } - - if (attr_pm_spivid_port_enable2 != 0 && attr_pm_spivid_port_enable1 != 0 ) + if (attr_pm_spivid_port_enable1 != 0 ) { - FAPI_ERR("Both targets have SPIVIDs enabled: check the configuration setup."); - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_TARGET_ERROR); - break; + master_target = i_target1; + slave_target = i_target2; } - else if (attr_pm_spivid_port_enable2 == 0 && attr_pm_spivid_port_enable1 == 0 ) + else { - FAPI_ERR("Neither target has SPIVID enabled: check the configuration setup."); - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_TARGET_ERROR); + FAPI_ERR("Master target does not have SPIVID ports enabled: ATTR_PM_SPIVID_PORT_ENABLE must be non-zero."); + const fapi::Target& MASTER_TARGET = i_target1; + const uint64_t& ATTR_SPIVID_PORT_ENABLE = (uint64_t)attr_pm_spivid_port_enable1; + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_SPIVID_CONFIG_ERROR); break; } - else - { - - if (attr_pm_spivid_port_enable2 != 0 ) - { - master_target = i_target2; - slave_target = i_target1; - } - */ - if (attr_pm_spivid_port_enable1 != 0 ) - { - master_target = i_target1; - slave_target = i_target2; - } - else - { - FAPI_ERR("Master target does not have SPIVID ports enabled: check the configuration setup."); - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_TARGET_ERROR); - break; - } - //} - - //////////////////////////////////////////////////////////////////////////// // 2.0 cRQ_TD_IntMaskRQ: Mask OCC interrupts in OIMR1 @@ -383,7 +360,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // Master // ****************************************************** - FAPI_INF("Performing STEP 2.00"); + FAPI_INF("Mask OCC interrupts in OIMR0 and OIMR1 on Master"); // CHECKING PMC_FIRS @@ -405,11 +382,8 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 if (any_error) { FAPI_DBG(" PMC_FIR has error(s) active. Continuing though 0x%16llX ", data.getDoubleWord(0)); - //FAPI_SET_HWP_ERROR(rc, RC_PROCPM_FIR_ERROR); break; - //return rc ; } - e_rc = data.flushTo0(); if (e_rc) { @@ -418,12 +392,13 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 } rc = fapiGetScom(master_target, OCB_OCI_OIMR1_0x0006a014 , data ); - if (rc) { - FAPI_ERR("fapiGetScom(OCB_OCI_OIMR1_0x0006a014) failed."); break; + if (rc) + { + FAPI_ERR("fapiGetScom(OCB_OCI_OIMR1_0x0006a014) failed."); + break; } - - e_rc = data.setBit(12); + e_rc |= data.setBit(12); e_rc |= data.setBit(13); e_rc |= data.setBit(14); e_rc |= data.setBit(15); @@ -438,17 +413,20 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 } rc = fapiPutScom(master_target, OCB_OCI_OIMR1_0x0006a014 , data ); - if (rc) { - FAPI_ERR("fapiPutScom(OCB_OCI_OIMR1_0x0006a014) failed."); break; + if (rc) + { + FAPI_ERR("fapiPutScom(OCB_OCI_OIMR1_0x0006a014) failed."); + break; } rc = fapiGetScom(master_target, OCB_OCI_OIMR0_0x0006a004 , data ); - if (rc) { - FAPI_ERR("fapiGetScom(OCB_OCI_OIMR0_0x0006a004) failed."); break; + if (rc) + { + FAPI_ERR("fapiGetScom(OCB_OCI_OIMR0_0x0006a004) failed."); + break; } - - e_rc = data.setBit(9); + e_rc |= data.setBit(9); e_rc |= data.setBit(13); e_rc |= data.setBit(21); if (e_rc) @@ -458,8 +436,6 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 break; } - - rc = fapiPutScom(master_target, OCB_OCI_OIMR0_0x0006a004 , data ); if (rc) { @@ -474,7 +450,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 if (dcm) { - FAPI_INF("Performing STEP 2.01"); + FAPI_INF("Mask OCC interrupts in OIMR0 and OIMR1 on Slave"); // CHECKING PMC_FIRS @@ -487,18 +463,17 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 } rc = fapiGetScom(slave_target, PMC_LFIR_0x01010840 , data ); - if (rc) { - FAPI_ERR("fapiGetScom(PMC_LFIR_0x01010840) failed."); - break; + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_LFIR_0x01010840) failed."); + break; } any_error = data.getDoubleWord(0); if (any_error) { - FAPI_ERR(" PMC_FIR has error(s) active. 0x%16llX ", data.getDoubleWord(0)); - //FAPI_SET_HWP_ERROR(rc, RC_PROCPM_FIR_ERROR); break; - //return rc ; + FAPI_DBG(" PMC_FIR has error(s) active. Continuing though 0x%16llX ", data.getDoubleWord(0)); } e_rc = data.flushTo0(); @@ -515,7 +490,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 FAPI_ERR("fapiGetScom(OCB_OCI_OIMR1_0x0006a014) failed."); break; } - e_rc = data.setBit(12); + e_rc |= data.setBit(12); e_rc |= data.setBit(13); e_rc |= data.setBit(14); e_rc |= data.setBit(15); @@ -543,7 +518,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 break; } - e_rc = data.setBit(9); + e_rc |= data.setBit(9); e_rc |= data.setBit(13); e_rc |= data.setBit(21); if (e_rc) @@ -576,7 +551,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // ****************************************************** // Master // ****************************************************** - FAPI_INF("Performing STEP 3.00"); + FAPI_INF("Halt Pstates and Idles on Master"); rc = fapiGetScom(master_target, PMC_MODE_REG_0x00062000 , data ); if (rc) @@ -585,7 +560,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 break; } - e_rc = data.setBit(05); + e_rc |= data.setBit(05); e_rc |= data.setBit(14); if (e_rc) { @@ -606,6 +581,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 master_enable_fw_pstate_mode = data.isBitSet(2) ; master_is_enable_interchip_interface = data.isBitSet(6) ; + pmcmode_master = data; // ****************************************************** // Slave @@ -613,7 +589,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 if (dcm) { - FAPI_INF("Performing STEP 3.01"); + FAPI_INF("Halt Pstates and Idles on Slave"); rc = fapiGetScom(slave_target, PMC_MODE_REG_0x00062000 , data ); if (rc) { @@ -622,7 +598,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 } - e_rc = data.setBit(05); + e_rc |= data.setBit(05); e_rc |= data.setBit(14); if (e_rc) { @@ -643,32 +619,46 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 slave_enable_fw_pstate_mode = data.isBitSet(2) ; slave_is_enable_interchip_interface = data.isBitSet(6) ; + pmcmode_slave = data; // Check with Greg about return // TODO : if ATTR_DCM_INSTALLED = 1 chip level attribute + /* if (master_is_MasterPMC == 0) { - FAPI_ERR(" MasterPMC bit of Master PMC is not set"); - + FAPI_ERR(" MasterPMC bit of Master PMC is not set"); + const uint64_t& MASTERPMCMODE = pmcmode_master.getDoubleWord(0); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMC_MASTER_CONFIG_ERROR); + break; } if (slave_is_MasterPMC == 1) { FAPI_ERR(" MasterPMC bit of Slave PMC is set"); + const uint64_t& SLAVEPMCMODE = pmcmode_slave.getDoubleWord(0); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMC_SLAVE_CONFIG_ERROR); + break; } if ((master_is_enable_interchip_interface ==1) && (slave_is_enable_interchip_interface == 0)) { - FAPI_ERR (" Configuration Error : Master is enabled with interchip interface but slave is not "); - + FAPI_ERR (" Configuration Error : Master is enabled with interchip interface but slave is not "); + const uint64_t& MASTERPMCMODE = pmcmode_master.getDoubleWord(0); + const uint64_t& SLAVEPMCMODE = pmcmode_slave.getDoubleWord(0); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMC_INTERCHIP_CONFIG_ERROR); + break; } if ( (master_enable_fw_pstate_mode == 1) && (slave_enable_fw_pstate_mode == 0)) { FAPI_ERR (" Configuration Error : Master is enabled with FW pstate mode but slave is not "); - + const uint64_t& MASTERPMCMODE = pmcmode_master.getDoubleWord(0); + const uint64_t& SLAVEPMCMODE = pmcmode_slave.getDoubleWord(0); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMC_INTERCHIP_CONFIG_ERROR); + break; } + */ } @@ -705,7 +695,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // ****************************************************** if (dcm) { - FAPI_INF("Performing STEP 4.00"); + FAPI_INF("Halt interchip interface on Master"); if (master_is_enable_interchip_interface == 1) { @@ -818,9 +808,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // ****************************************************** // Slave // ****************************************************** - - - FAPI_INF("Performing STEP 4.01"); + FAPI_INF("Halt interchip interface on Slave"); if (slave_is_enable_interchip_interface ==1) { @@ -950,10 +938,10 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // else -->MPS_HaltWait //////////////////////////////////////////////////////////////////////////// - FAPI_INF("Performing STEP 5.00"); - if (master_enable_pstate_voltage_changes==1) { + FAPI_INF("Halt SPIVID controller on Master"); + // HaltSpivid: PMC_SPIV_COMMAND_REG.spivid_halt_fsm<-1 rc = fapiGetScom(master_target, PMC_SPIV_COMMAND_REG_0x00062047 , data ); if (rc) @@ -1003,7 +991,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // Timeout check if (count > VOLTAGE_CHANGE_POLL_COUNT) { - FAPI_ERR("Timed out in polling spiv ongoing : Reset_suspicious ... "); + FAPI_ERR("Timed out in polling SPIVID ongoing : Reset_suspicious ... "); // \todo // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); // break; @@ -1030,8 +1018,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // if (!is_stopped) then -->MPS_HaltWait (Wait limit) //////////////////////////////////////////////////////////////////////////// - FAPI_INF("Performing STEP 6.00 "); - + FAPI_INF("Check for Pstate FSM being stopped on Master"); // ****************************************************** // Master @@ -1079,7 +1066,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // ****************************************************** if (dcm) { - FAPI_INF("Performing STEP 6.01 "); + FAPI_INF("Check for Pstate FSM being stopped on Slave"); for (count = 0 , is_stopped = 0 ; count <= PSTATE_HALT_POLL_COUNT && is_stopped == 0 ; count++) { @@ -1158,7 +1145,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // Master // ****************************************************** - FAPI_INF("Performing STEP 7.00 "); + FAPI_INF("Poll for O2P bridge being complete on Master"); rc = fapiGetScom(master_target, PMC_O2S_COMMAND_REG_0x00062057 , data ); if (rc) { @@ -1244,7 +1231,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 if (dcm) { - FAPI_INF("Performing STEP 7.01 "); + FAPI_INF("Poll for O2P bridge being complete on Slave"); for (count = 0 , is_stopped = 0 ; count <= O2P_POLL_COUNT && is_stopped == 0 ; count++) { @@ -1292,7 +1279,11 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // the execution of p8_poreslw_recovery.C will have taken place. /////////////////////////////////////////////////////////////////////////////////////////////////////////// - FAPI_INF("Performing STEP 8.00 "); + // ****************************************************** + // Master + // ****************************************************** + + FAPI_INF("Poll for Idle FSM being quiesced on Master"); for (count = 0 , is_stopped = 0 ; count <= PORE_REQ_POLL_COUNT && is_stopped == 0 ; count++) { rc = fapiGetScom(master_target, PMC_PORE_REQ_REG0_0x0006208E , data ); @@ -1320,6 +1311,41 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // break; } + // ****************************************************** + // Slave + // ****************************************************** + + if (dcm) + { + FAPI_INF("Poll for Idle FSM being quiesced on Slave"); + for (count = 0 , is_stopped = 0 ; count <= PORE_REQ_POLL_COUNT && is_stopped == 0 ; count++) + { + rc = fapiGetScom(slave_target, PMC_PORE_REQ_REG0_0x0006208E , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_O2P_STATUS_REG__0x00062061) failed."); + break; + } + + is_stopped = (data.isBitClear(20)) ; + FAPI_DBG("Polling pore_busy bit ..."); + } + + // Error check + if (!rc.ok()) + { + break; + } + + // Timeout check + if (count > PORE_REQ_POLL_COUNT) + { + FAPI_ERR("Timed out in polling pore_busy bit . : Reset_suspicious .. "); + // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); + // break; + } + } + /////////////////////////////////////////////////////////////////////////////// // GREG: // Issue interchip interface reset (if enabled) on master_chiptarget @@ -1340,7 +1366,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 // ****************************************************** - FAPI_INF("Performing STEP 9.00 "); + FAPI_INF("Reset interchip interface on Master"); if ( master_is_enable_interchip_interface == 1) { @@ -1389,7 +1415,7 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 if (dcm) { - FAPI_INF("Performing STEP 9.01 "); + FAPI_INF("Reset interchip interface on Slave"); if ( slave_is_enable_interchip_interface == 1) { @@ -1433,101 +1459,117 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 } } - /////////////////////////////////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////// // Issue reset to the PMC - // Note: this action will wipe out the Idle Pending queue so that requests for idle transitions (entry and exit) will be lost which means that PHYP notification needs to happen. + // Note: this action will wipe out the Idle Pending queue so that + // requests for idle transitions (entry and exit) will be lost which + // means that PHYP notification needs to happen. + // // Write PMC_MODE_REG.pmc_reset_all_voltage_registers = 1. // Clearing LFIRs will have been done by PRD // Note: this will remove CONFIG settings // This puts the PMC into firmware mode which halts any future Global Actual operations - /////////////////////////////////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////// // ****************************************************** // Master // ****************************************************** // RESET_ALL_PMC_REGISTERS - rc = fapiGetScom(master_target, PMC_MODE_REG_0x00062000 , data ); - if (rc) - { - FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); - break; - } - - e_rc = data.setBit(12); - if (e_rc) - { - FAPI_ERR("ecmdDataBufferBase error setting up PMC_INTCHP_COMMAND_REG_0x00062014 on Master reset"); - rc.setEcmdError(e_rc); - break; - } - if (rc) - { - FAPI_ERR("fapiPutScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); - break; - } - - rc = fapiPutScom(master_target, PMC_MODE_REG_0x00062000 , data ); - if (rc) - { - FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); - break; - } - - // ****************************************************** - // Slave - // ****************************************************** - if (dcm) + + if (i_mode == PM_RESET) { - - rc = fapiGetScom(slave_target, PMC_MODE_REG_0x00062000 , data ); + FAPI_INF("Hard reset detected"); + FAPI_INF("Reset PMC on Master"); + rc = fapiGetScom(master_target, PMC_MODE_REG_0x00062000 , data ); if (rc) { - FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); - break; - } - - e_rc = data.setBit(12); - if (e_rc) - { - FAPI_ERR("ecmdDataBufferBase error setting up PMC_MODE_REG_0x00062000 on Slave reset"); - rc.setEcmdError(e_rc); + FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); break; } - rc = fapiPutScom(slave_target, PMC_MODE_REG_0x00062000 , data ); + e_rc = data.setBit(12); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_INTCHP_COMMAND_REG_0x00062014 on Master reset"); + rc.setEcmdError(e_rc); + break; + } if (rc) { - FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); + FAPI_ERR("fapiPutScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); break; } - // \todo remove in deference to init path - // Restored only for slave - // SAFE_MODE_WITHOUT_SPIVID - rc = fapiGetScom(slave_target, PMC_MODE_REG_0x00062000 , data ); + rc = fapiPutScom(master_target, PMC_MODE_REG_0x00062000 , data ); if (rc) { - FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); - break; + FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); + break; } - e_rc = data.setBit(13); - if (e_rc) + // ****************************************************** + // Slave + // ****************************************************** + if (dcm) { - FAPI_ERR("ecmdDataBufferBase error for PMC_MODE_REG_0x00062000 on Slave reset"); - rc.setEcmdError(e_rc); - break; - } + FAPI_INF("Reset PMC on Slave"); - rc = fapiPutScom(slave_target, PMC_MODE_REG_0x00062000 , data ); - if (rc) - { - FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); - break; + rc = fapiGetScom(slave_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + + e_rc = data.setBit(12); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_MODE_REG_0x00062000 on Slave reset"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiPutScom(slave_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + + // \todo remove in deference to init path + // Restored only for slave + // SAFE_MODE_WITHOUT_SPIVID + rc = fapiGetScom(slave_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + + e_rc = data.setBit(13); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error for PMC_MODE_REG_0x00062000 on Slave reset"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiPutScom(slave_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); + break; + } } } + else + { + FAPI_INF("Soft reset detected. PMC register reset skipped."); + } } while(0); + FAPI_INF("pmc_reset end..."); + return rc; } @@ -1593,99 +1635,113 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) interchip_clock_divider = ( proc_nest_frequency /(attr_pm_interchip_frequency*8)-1 ); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_FRAME_SIZE, - "ATTR_PM_SPIVID_FRAME_SIZE", - &i_target1, - attr_pm_spivid_frame_size, - default_spivid_frame_size ); + GETATTR_DEFAULT(rc, + ATTR_PM_SPIVID_FRAME_SIZE, + "ATTR_PM_SPIVID_FRAME_SIZE", + &i_target1, + attr_pm_spivid_frame_size, + default_spivid_frame_size ); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_IN_DELAY_FRAME1, - "ATTR_PM_SPIVID_IN_DELAY_FRAME1", - &i_target1, - attr_pm_spivid_in_delay_frame1, - default_spivid_in_delay_frame1 ); + GETATTR_DEFAULT(rc, + ATTR_PM_SPIVID_IN_DELAY_FRAME1, + "ATTR_PM_SPIVID_IN_DELAY_FRAME1", + &i_target1, + attr_pm_spivid_in_delay_frame1, + default_spivid_in_delay_frame1 ); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_IN_DELAY_FRAME1, - "ATTR_PM_SPIVID_IN_DELAY_FRAME1", - &i_target1, - attr_pm_spivid_in_delay_frame2, - default_spivid_in_delay_frame2 ); + GETATTR_DEFAULT(rc, + ATTR_PM_SPIVID_IN_DELAY_FRAME1, + "ATTR_PM_SPIVID_IN_DELAY_FRAME1", + &i_target1, + attr_pm_spivid_in_delay_frame2, + default_spivid_in_delay_frame2 ); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_CLOCK_POLARITY, - "ATTR_PM_SPIVID_CLOCK_POLARITY", - &i_target1, - attr_pm_spivid_clock_polarity, - default_spivid_clock_polarity ); + GETATTR_DEFAULT(rc, + ATTR_PM_SPIVID_CLOCK_POLARITY, + "ATTR_PM_SPIVID_CLOCK_POLARITY", + &i_target1, + attr_pm_spivid_clock_polarity, + default_spivid_clock_polarity ); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_CLOCK_PHASE, - "ATTR_PM_SPIVID_CLOCK_PHASE", - &i_target1, - attr_pm_spivid_clock_phase, - default_spivid_clock_phase ); + GETATTR_DEFAULT(rc, + ATTR_PM_SPIVID_CLOCK_PHASE, + "ATTR_PM_SPIVID_CLOCK_PHASE", + &i_target1, + attr_pm_spivid_clock_phase, + default_spivid_clock_phase ); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_CRC_GEN_ENABLE, - "ATTR_PM_SPIVID_CRC_GEN_ENABLE", - &i_target1, - attr_pm_spivid_crc_gen_enable, - default_spivid_crc_gen_enable ); + GETATTR_DEFAULT(rc, + ATTR_PM_SPIVID_CRC_GEN_ENABLE, + "ATTR_PM_SPIVID_CRC_GEN_ENABLE", + &i_target1, + attr_pm_spivid_crc_gen_enable, + default_spivid_crc_gen_enable ); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_CRC_CHECK_ENABLE, - "ATTR_PM_SPIVID_CRC_CHECK_ENABLE", - &i_target1, - attr_pm_spivid_crc_check_enable, - default_spivid_crc_check_enable ); + GETATTR_DEFAULT(rc, + ATTR_PM_SPIVID_CRC_CHECK_ENABLE, + "ATTR_PM_SPIVID_CRC_CHECK_ENABLE", + &i_target1, + attr_pm_spivid_crc_check_enable, + default_spivid_crc_check_enable ); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE, - "ATTR_PM_SPIVID_CRC_CHECK_ENABLE", - &i_target1, - attr_pm_spivid_majority_vote_enable, - default_spivid_majority_vote_enable ); + GETATTR_DEFAULT(rc, + ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE, + "ATTR_PM_SPIVID_CRC_CHECK_ENABLE", + &i_target1, + attr_pm_spivid_majority_vote_enable, + default_spivid_majority_vote_enable ); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_MAX_RETRIES, - "ATTR_PM_SPIVID_MAX_RETRIES", - &i_target1, - attr_pm_spivid_max_retries, - default_spivid_max_retries ); + GETATTR_DEFAULT(rc, + ATTR_PM_SPIVID_MAX_RETRIES, + "ATTR_PM_SPIVID_MAX_RETRIES", + &i_target1, + attr_pm_spivid_max_retries, + default_spivid_max_retries ); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES, - "ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES", - &i_target1, - attr_pm_spivid_crc_polynomial_enables, - default_spivid_crc_polynomial_enables ); + GETATTR_DEFAULT(rc, + ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES, + "ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES", + &i_target1, + attr_pm_spivid_crc_polynomial_enables, + default_spivid_crc_polynomial_enables ); //---------------------------------------------------------- - GETATTR_DEFAULT( ATTR_PM_SPIVID_PORT_ENABLE, - "ATTR_PM_SPIVID_PORT_ENABLE", - &i_target1, - attr_pm_spivid_port_enable, - default_spivid_port_enable ); + GETATTR_DEFAULT(rc, + ATTR_PM_SPIVID_PORT_ENABLE, + "ATTR_PM_SPIVID_PORT_ENABLE", + &i_target1, + attr_pm_spivid_port_enable, + default_spivid_port_enable ); //---------------------------------------------------------- - GETATTR( ATTR_PM_SPIVID_CLOCK_DIVIDER, - "ATTR_PM_SPIVID_CLOCK_DIVIDER", - &i_target1, - attr_pm_spivid_clock_divider); + GETATTR( rc, + ATTR_PM_SPIVID_CLOCK_DIVIDER, + "ATTR_PM_SPIVID_CLOCK_DIVIDER", + &i_target1, + attr_pm_spivid_clock_divider); //---------------------------------------------------------- - GETATTR( ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE, - "ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE", - &i_target1, - attr_pm_spivid_interframe_delay_write_status_value); + GETATTR( rc, + ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE, + "ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE", + &i_target1, + attr_pm_spivid_interframe_delay_write_status_value); //---------------------------------------------------------- - GETATTR( ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE, - "ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE", - &i_target1, - attr_pm_spivid_inter_retry_delay_value); + GETATTR( rc, + ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE, + "ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE", + &i_target1, + attr_pm_spivid_inter_retry_delay_value); FAPI_INF("PMC initialization..."); @@ -1761,9 +1817,11 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) if (any_error) { - FAPI_ERR(" PMC_FIR has error(s) active. 0x%16llX ", data.getDoubleWord(0)); - //FAPI_SET_HWP_ERROR(rc, RC_PROCPM_FIR_ERROR); break; - //return rc ; + // Once clear FIRs are established, this will throw errors. + FAPI_INF("WARNING: PMC_FIR has error(s) active. 0x%016llX ", data.getDoubleWord(0)); + //FAPI_ERR(" PMC_FIR has error(s) active. 0x%16llX ", data.getDoubleWord(0)); + //FAPI_SET_HWP_ERROR(rc, RC_PROCPM_FIR_ERROR); + //break; } // ****************************************************************** @@ -2336,7 +2394,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) * * @param[in] i_target1 Primary Chip target: Murano - chip0; Venice - chip * @param[in] i_target2 Secondary Chip target: Murano - chip1; Venice - NULL - * @param[in] mode (PM_INIT , PM_CONFIG, PM_RESET) + * @param[in] mode (PM_INIT , PM_CONFIG, PM_RESET, PM_RESET_SOFT) * * @retval ECMD_SUCCESS * @retval ERROR defined in xml @@ -2398,11 +2456,26 @@ p8_pmc_init(const fapi::Target& i_target1, const fapi::Target& i_target2, uint32 } /// ------------------------------- - /// Reset: perform reset of PMC + /// Reset: perform hard reset of PMC /// ------------------------------- else if (mode == PM_RESET) { - rc = pmc_reset_function(i_target1 , i_target2); + FAPI_INF("Hard reset detected. Calling pmc_reset_function"); + rc = pmc_reset_function(i_target1 , i_target2, mode); + if (rc) + { + FAPI_ERR("Error from pmc_reset_function"); + break; + } + } + + // ------------------------------- + /// Reset: perform soft reset of PMC + /// ------------------------------- + else if (mode == PM_RESET_SOFT) + { + FAPI_INF("Soft reset detected. Calling pmc_reset_function"); + rc = pmc_reset_function(i_target1 , i_target2, mode); if (rc) { FAPI_ERR("Error from pmc_reset_function"); @@ -2410,13 +2483,14 @@ p8_pmc_init(const fapi::Target& i_target1, const fapi::Target& i_target2, uint32 } } + /// ------------------------------- /// Unsupported Mode /// ------------------------------- else { FAPI_ERR("Unknown mode passed to p8_pmc_init. Mode %x ", mode); - uint32_t & MODE = mode; + const uint64_t & MODE = (uint64_t)mode; FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMC_CODE_BAD_MODE); } @@ -2434,6 +2508,13 @@ This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: p8_pmc_init.C,v $ +Revision 1.36 2013/08/02 19:09:07 stillgs + +- Support for p8_pm.H. +- Temporarily changed the detection of set FIR bit from FAPI_ERR to FAPI_INF until fully complete with testing. +This keeps "FAPI ERR" from showing up in log for things that do not give non-zero RCs. +- Added plumbing support for "soft" rest. FUNCTION IS NOT YET SUPPORTED + Revision 1.35 2013/06/07 19:17:24 stillgs Fix swap of Pmin and PMax rail settings diff --git a/src/usr/hwpf/hwp/runtime_attributes/pm_hwp_attributes.xml b/src/usr/hwpf/hwp/runtime_attributes/pm_hwp_attributes.xml index f58dd6d01..1e02c4f46 100644 --- a/src/usr/hwpf/hwp/runtime_attributes/pm_hwp_attributes.xml +++ b/src/usr/hwpf/hwp/runtime_attributes/pm_hwp_attributes.xml @@ -20,6 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> +<!-- $Id: pm_hwp_attributes.xml,v 1.8 2013/07/18 22:03:52 stillgs Exp $ --> <!-- XML file specifying Power Management HWPF attributes. These attributes are initialized to zero by the platform and set to a @@ -32,17 +33,16 @@ <attribute> <id>ATTR_PROC_DPLL_DIVIDER</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>The product of the DPLL internal prescalar divide (CD_DIV124_DC) and the output divider(CD_DPLLOUT124_DC). This estalishes the step size of the DPLL in terms of this number divided into the processor reference clock. - </description> + <description>The product of the DPLL internal prescalar divide (CD_DIV124_DC) and the output divider(CD_DPLLOUT124_DC). This estalishes the step size of the DPLL in terms of this number divided into the processor reference clock.</description> <valueType>uint32</valueType> <writeable/> </attribute> + <attribute> <id>ATTR_PM_POWER_PROXY_TRACE_TIMER</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>The Power Proxy Trace timer (binary in microseconds) defines the time between Power Proxy Trace records when no other event that would otherwise produce a record has occured. Values must be within a range of 32us to 64ms. - </description> + <description>The Power Proxy Trace timer (binary in microseconds) defines the time between Power Proxy Trace records when no other event that would otherwise produce a record has occured. Values must be within a range of 32us to 64ms.</description> <valueType>uint32</valueType> <writeable/> </attribute> @@ -50,8 +50,7 @@ <attribute> <id>ATTR_PM_PPT_TIMER_MATCH_VALUE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>The delay is 32us * ATTR_PM_PPT_TIMER_MATCH_VALUE - </description> + <description>The delay is 32us * ATTR_PM_PPT_TIMER_MATCH_VALUE</description> <valueType>uint32</valueType> <writeable/> </attribute> @@ -59,8 +58,7 @@ <attribute> <id>ATTR_PM_PPT_TIMER_TICK</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Defines the Power Proxy Trace interval timer tick (0=25us, 1=0.5us, 2=1us, and 3=2us) - </description> + <description>Defines the Power Proxy Trace interval timer tick (0=25us, 1=0.5us, 2=1us, and 3=2us)</description> <valueType>uint32</valueType> <writeable/> </attribute> @@ -68,8 +66,7 @@ <attribute> <id>ATTR_PM_AISS_TIMEOUT</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Defines the timeout value for the Architected Idle State Sequencer (AISS). - </description> + <description>Defines the timeout value for the Architected Idle State Sequencer (AISS).</description> <valueType>uint8</valueType> <enum>1MS=0, 2MS=1, 4MS=2, 8MS=3, 16MS=4, 32MS=5, 64MS=6, 128MS=7, 256MS=8, 512MS=9</enum> <writeable/> @@ -84,8 +81,7 @@ Used to setup the PMC voltage controller Producer: proc_build_pstate_tables.C -Consumer: OCC pstate_init() - </description> +Consumer: OCC pstate_init()</description> <valueType>uint8</valueType> <writeable/> </attribute> @@ -97,8 +93,7 @@ Consumer: OCC pstate_init() A 4 bit field selects one of the the upper 16bit of a 19bit counter (16+3) incremented in the nest/4 domain -Consumer: proc_pm.scominit - </description> +Consumer: proc_pm.scominit</description> <valueType>uint8</valueType> <writeable/> </attribute> @@ -108,8 +103,7 @@ Consumer: proc_pm.scominit <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description>Step delay after a voltage change in increments of vrm_stepdelay_range. Setting this dial to a value N causes a delay of N cycles of the divided nest clk (see dial vrm_stepdelay_range). The closed formula is as follows: Delay_seconds = vrm_stepdelay_value * ( 2^(3 + vrm_stepdelay_range) / (Nest_frequency_Hz/4)) -Consumer: proc_pm.scominit - </description> +Consumer: proc_pm.scominit</description> <valueType>uint8</valueType> <writeable/> </attribute> @@ -121,8 +115,7 @@ Consumer: proc_pm.scominit Producer: proc_pm_init -Consumer: proc_pm.scominit - </description> +Consumer: proc_pm.scominit</description> <valueType>uint8</valueType> <writeable/> </attribute> @@ -135,8 +128,7 @@ Pstate that is invoked in the PMC voltage controller upon the loss of the OCC He Producer: proc_pm_init.C -Consumer: proc_pm.scominit - </description> +Consumer: proc_pm.scominit</description> <valueType>uint8</valueType> <writeable/> </attribute> @@ -148,8 +140,7 @@ Consumer: proc_pm.scominit Supported values: 0x20 (32d) -Chip Select assertion duration is spi_frame_size + 2 - </description> +Chip Select assertion duration is spi_frame_size + 2</description> <valueType>uint8</valueType> <writeable/> </attribute> @@ -159,8 +150,7 @@ Chip Select assertion duration is spi_frame_size + 2 <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description>Number of SPIVID clocks after chip select to wait before capturing MISO input in frame 1 -Supported values: 0x00 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured - </description> +Supported values: 0x00 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured</description> <valueType>uint8</valueType> <writeable/> </attribute> @@ -170,8 +160,7 @@ Supported values: 0x00 to spi_frame_size. Values beyond spi_frame_size result i <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description>Number of SPI clocks after chip select to wait before capturing MISO input in frame 2 -Supported values: 0x00 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured - </description> +Supported values: 0x00 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured</description> <valueType>uint8</valueType> <writeable/> </attribute> @@ -179,8 +168,7 @@ Supported values: 0x00 to spi_frame_size. Values beyond spi_frame_size result i <attribute> <id>ATTR_PM_SPIVID_CLOCK_POLARITY</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>SPVID Clock Polarity (CPOL=0 means that clk idle is deasserted, CPOL=1 means that clk idle is asserted) - </description> + <description>SPVID Clock Polarity (CPOL=0 means that clk idle is deasserted, CPOL=1 means that clk idle is asserted)</description> <valueType>uint8</valueType> <enum>IDLELOW=0, IDLEHIGH = 1</enum> <writeable/> @@ -189,8 +177,7 @@ Supported values: 0x00 to spi_frame_size. Values beyond spi_frame_size result i <attribute> <id>ATTR_PM_SPIVID_CLOCK_PHASE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>SPI clock phase (CPHA=0 means to change/sample values of data signals on first edge, otherwise on 2nd) - </description> + <description>SPI clock phase (CPHA=0 means to change/sample values of data signals on first edge, otherwise on 2nd)</description> <valueType>uint8</valueType> <enum>FIRSTEDGE=0, SECONDEDGE=1</enum> @@ -201,8 +188,7 @@ SECONDEDGE=1</enum> <id>ATTR_PM_SPIVID_CLOCK_DIVIDER</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description>SPIVID clock speed divider to divide the nest_nclk/4 mesh clock, which results in a divider = (nest_freq/ (SPI_freq*8))-1 -For a 2.4GHz nest clock, this means that the SPI clk can be theoretically adjusted between 600MHz and 0.29MHz (cycle time 1.66ns...3.41us, in 1.66ns steps). However, a practical range is 0.5...25MHz. - </description> +For a 2.4GHz nest clock, this means that the SPI clk can be theoretically adjusted between 600MHz and 0.29MHz (cycle time 1.66ns...3.41us, in 1.66ns steps). However, a practical range is 0.5...25MHz.</description> <valueType>uint32</valueType> <writeable/> </attribute> @@ -211,8 +197,7 @@ For a 2.4GHz nest clock, this means that the SPI clk can be theoretically adjust <id>ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description>Delay between command and status frames of a SPIVID WRITE operation (binary in nanoseconds) -Consumer: proc_pmc_init - </description> +Consumer: proc_pmc_init</description> <valueType>uint32</valueType> <writeable/> </attribute> @@ -227,8 +212,7 @@ Delay is computed as: (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time 0x00000: Wait 1 SPI Clock 0x00001 - 0x1FFFF: value = number of ~100ns_hang_pulses -For values greater than 0x00000, the actual delay is 1 SPI Clock + the time delay designated by the value defined. Max. delay at 0x1FFFF: 13.1ms + 1 SPI clock cycle. - </description> +For values greater than 0x00000, the actual delay is 1 SPI Clock + the time delay designated by the value defined. Max. delay at 0x1FFFF: 13.1ms + 1 SPI clock cycle.</description> <valueType>uint32</valueType> <writeable/> </attribute> @@ -243,8 +227,7 @@ Delay is computed as: (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time 0x0000: Wait 1 SPI Clock 0x0001 - 0xFFFF: value = number of ~100ns_hang_pulses -For values greater than 0x00000, the actual delay is 1 SPI Clock + the time delay designated by the value defined. Max. delay at 0x1FFFF: 13.1ms + 1 SPI clock cycle. - </description> +For values greater than 0x00000, the actual delay is 1 SPI Clock + the time delay designated by the value defined. Max. delay at 0x1FFFF: 13.1ms + 1 SPI clock cycle.</description> <valueType>uint32</valueType> <writeable/> </attribute> @@ -253,8 +236,7 @@ For values greater than 0x00000, the actual delay is 1 SPI Clock + the time dela <id>ATTR_PM_SPIVID_INTER_RETRY_DELAY</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description>Delay between SPIVID reture attempts when WRITE command status indicates an error (binary in nanoseconds) -Consumer: proc_pmc_init - </description> +Consumer: proc_pmc_init</description> <valueType>uint32</valueType> <writeable/> </attribute> @@ -262,8 +244,7 @@ Consumer: proc_pmc_init <attribute> <id>ATTR_PM_SPIVID_CRC_GEN_ENABLE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>EnableS CRC generation from processor to VRM device. This will produce an 8b CRC per the enabled polynomial. If CRC generation is disabled, the full 32 bits at the data input of the SPI master are transmitted. - </description> + <description>EnableS CRC generation from processor to VRM device. This will produce an 8b CRC per the enabled polynomial. If CRC generation is disabled, the full 32 bits at the data input of the SPI master are transmitted.</description> <valueType>uint8</valueType> <enum>TRUE = 1, FALSE = 0</enum> <writeable/> @@ -272,8 +253,7 @@ Consumer: proc_pmc_init <attribute> <id>ATTR_PM_SPIVID_CRC_CHECK_ENABLE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Enables CRC checking in the processor of frames from the VRM device. - </description> + <description>Enables CRC checking in the processor of frames from the VRM device.</description> <valueType>uint8</valueType> <enum>TRUE = 1, FALSE = 0</enum> <writeable/> @@ -282,8 +262,7 @@ Consumer: proc_pmc_init <attribute> <id>ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>enables the a majority vote on the 3B of status payload on a frame received by the master as each of these have a 1 byte status field replicated three (3) times by the slave. - </description> + <description>enables the a majority vote on the 3B of status payload on a frame received by the master as each of these have a 1 byte status field replicated three (3) times by the slave.</description> <valueType>uint8</valueType> <enum>TRUE = 1, FALSE = 0</enum> <writeable/> @@ -295,8 +274,7 @@ Consumer: proc_pmc_init <description>Number retries upon detected errors. 0x00: No retry -0x01 to 0x1F: 1 to 31 respectively - </description> +0x01 to 0x1F: 1 to 31 respectively</description> <valueType>uint8</valueType> <writeable/> </attribute> @@ -309,8 +287,7 @@ Consumer: proc_pmc_init An 8 bit mask vector to enable XORs in the CRC generation and checking LFSRs at the respective bit position. MSB (x^8) is omitted since it is always enabled, so the mask layout is (x^7,x^6,x^5,x^4,x^3,x^2,x^1,1) Planned CRC8 polynomial: x^8 + x^7 + x^6 + x^4 + x^2 + 1 -Value to enable planned polynomial: 0b1101_0101 (=0xD5) - </description> +Value to enable planned polynomial: 0b1101_0101 (=0xD5)</description> <valueType>uint8</valueType> <writeable/> </attribute> @@ -319,10 +296,8 @@ Value to enable planned polynomial: 0b1101_0101 (=0xD5) <id>ATTR_PM_OCC_HEARTBEAT_TIME</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description>Time within which the OCC firmware must access the PMC or the OCC will be considered faulty whereby FIRs and malfunction alerts will be produced . (binary in nanoseconds) -Consumer: OCC FW - </description> +Consumer: OCC FW</description> <valueType>uint32</valueType> - <writeable/> </attribute> <attribute> @@ -330,78 +305,16 @@ Consumer: OCC FW <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description>Time (binary in ns) that will be the threshold value for the PMC PORE request timeout. -Consumer: proc_pmc_init.C. Will be translated to a DYNAMIC ATTRIBUTE for use by proc_pm..scominit as a multiple of PM hang pulses.. Counter starts at 0, is increased with every tp_pmc_hang_pulse as long as PORE is busy and set the PMC local FIR bit 19 when count = threshold. - </description> +Consumer: proc_pmc_init.C. Will be translated to a DYNAMIC ATTRIBUTE for use by proc_pm..scominit as a multiple of PM hang pulses.. Counter starts at 0, is increased with every tp_pmc_hang_pulse as long as PORE is busy and set the PMC local FIR bit 19 when count = threshold.</description> <valueType>uint32</valueType> <writeable/> </attribute> -<attribute> - <id>ATTR_PM_SLEEP_ENTRY</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Setting depends on di/dt charateristics of the system. - -Set Assisted if power off serialization is needed and SLEEP_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency - -Producer: MRWB - -Consumer: proc_pm_init and proc_pcbs_init - </description> - <valueType>uint8</valueType> - <enum>HARDWARE=0, ASSISTED=1</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SLEEP_EXIT</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Setting depends on di/dt charateristics of the system and the setting of ATTR_PM_SLEEP_TYPE. - -Set to Assisted if power on serialization is needed and SLEEP_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency -Must be set to Assisted if ATTR_PM_SLEEP_TYPE=Deep as this necessary for restore. - -Setting to Hardware is a test mode for Fast only. - -Producer: MRWB - -Consumer: proc_pm_init and proc_pcbs_init. - </description> - <valueType>uint8</valueType> - <enum>HARDWARE=0, ASSISTED=1</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_SLEEP_TYPE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Sleep Power Off Select: -Selects which voltage level to place the Core domain PFETs upon Sleep entry. 0 = Vret (Fast Sleep Mode), 1 = Voff (Deep Sleep Mode) - -Producer: MRWB - -Consumer: proc_pm_init and proc_pcbs_init - </description> - <valueType>uint8</valueType> - <enum>FAST=0, DEEP=1</enum> - <writeable/> -</attribute> - -<attribute> - <id>ATTR_PM_WINKLE_TYPE</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Winkle Power Off Select: -Selects which voltage level to place the Core and ECO domain PFETs upon Winkle entry. 0 = Vret (Fast Winkle Mode), 1 = Voff (Deep Winkle Mode) - </description> - <valueType>uint8</valueType> - <enum>FAST=0, DEEP=1</enum> - <writeable/> -</attribute> <attribute> <id>ATTR_PM_PFET_POWERUP_CORE_DELAY0</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) after a step in the Core power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT - </description> + <description>Delay (binary in nanoseconds) after a step in the Core power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT</description> <valueType>uint32</valueType> <platInit/> </attribute> @@ -409,8 +322,7 @@ Selects which voltage level to place the Core and ECO domain PFETs upon Winkle e <attribute> <id>ATTR_PM_PFET_POWERUP_CORE_DELAY1</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) after a step in the Core power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT - </description> + <description>Delay (binary in nanoseconds) after a step in the Core power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT</description> <valueType>uint32</valueType> <platInit/> </attribute> @@ -418,19 +330,15 @@ Selects which voltage level to place the Core and ECO domain PFETs upon Winkle e <attribute> <id>ATTR_PM_PFET_POWERUP_CORE_DELAY0_VALUE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 0 between any step in the Core power-up PFET sequence. - </description> + <description>Delay value 0 between any step in the Core power-up PFET sequence.</description> <valueType>uint8</valueType> - <writeable/> </attribute> <attribute> <id>ATTR_PM_PFET_POWERUP_CORE_DELAY1_VALUE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 1 between any step in the Core power-up PFET sequence. - </description> + <description>Delay value 1 between any step in the Core power-up PFET sequence.</description> <valueType>uint8</valueType> - <writeable/> </attribute> <attribute> @@ -440,8 +348,7 @@ Selects which voltage level to place the Core and ECO domain PFETs upon Winkle e 0 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY0; -1 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY1 - </description> +1 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY1</description> <valueType>uint32</valueType> <writeable/> </attribute> @@ -449,8 +356,7 @@ Selects which voltage level to place the Core and ECO domain PFETs upon Winkle e <attribute> <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY0</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) between a step in the Core power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT - </description> + <description>Delay (binary in nanoseconds) between a step in the Core power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT</description> <valueType>uint32</valueType> <platInit/> </attribute> @@ -458,8 +364,7 @@ Selects which voltage level to place the Core and ECO domain PFETs upon Winkle e <attribute> <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY1</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) between a step in the Core power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT - </description> + <description>Delay (binary in nanoseconds) between a step in the Core power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT</description> <valueType>uint32</valueType> <platInit/> </attribute> @@ -467,19 +372,15 @@ Selects which voltage level to place the Core and ECO domain PFETs upon Winkle e <attribute> <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY0_VALUE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 0 between any step in the Core power-up PFET sequence. - </description> + <description>Delay value 0 between any step in the Core power-up PFET sequence.</description> <valueType>uint8</valueType> - <writeable/> </attribute> <attribute> <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY1_VALUE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 1 between any step in the Core power-up PFET sequence. - </description> + <description>Delay value 1 between any step in the Core power-up PFET sequence.</description> <valueType>uint8</valueType> - <writeable/> </attribute> <attribute> @@ -489,8 +390,7 @@ Selects which voltage level to place the Core and ECO domain PFETs upon Winkle e 0 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY0; -1 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY1 - </description> +1 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY1</description> <valueType>uint32</valueType> <writeable/> </attribute> @@ -498,8 +398,7 @@ Selects which voltage level to place the Core and ECO domain PFETs upon Winkle e <attribute> <id>ATTR_PM_PFET_POWERUP_ECO_DELAY0</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) after a step in the ECO power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT - </description> + <description>Delay (binary in nanoseconds) after a step in the ECO power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT</description> <valueType>uint32</valueType> <platInit/> </attribute> @@ -507,8 +406,7 @@ Selects which voltage level to place the Core and ECO domain PFETs upon Winkle e <attribute> <id>ATTR_PM_PFET_POWERUP_ECO_DELAY1</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) after a step in the ECO power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT - </description> + <description>Delay (binary in nanoseconds) after a step in the ECO power-up PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT</description> <valueType>uint32</valueType> <platInit/> </attribute> @@ -516,19 +414,15 @@ Selects which voltage level to place the Core and ECO domain PFETs upon Winkle e <attribute> <id>ATTR_PM_PFET_POWERUP_ECO_DELAY0_VALUE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 0 between any step in the ECO power-up PFET sequence. - </description> + <description>Delay value 0 between any step in the ECO power-up PFET sequence.</description> <valueType>uint8</valueType> - <writeable/> </attribute> <attribute> <id>ATTR_PM_PFET_POWERUP_ECO_DELAY1_VALUE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 1 between any step in the ECO power-up PFET sequence. - </description> + <description>Delay value 1 between any step in the ECO power-up PFET sequence.</description> <valueType>uint8</valueType> - <writeable/> </attribute> <attribute> @@ -538,8 +432,7 @@ Selects which voltage level to place the Core and ECO domain PFETs upon Winkle e 0 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY0; -1 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY1 - </description> +1 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY1</description> <valueType>uint32</valueType> <writeable/> </attribute> @@ -547,8 +440,7 @@ Selects which voltage level to place the Core and ECO domain PFETs upon Winkle e <attribute> <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY0</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) between a step in the ECO power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT - </description> + <description>Delay (binary in nanoseconds) between a step in the ECO power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT</description> <valueType>uint32</valueType> <platInit/> </attribute> @@ -556,8 +448,7 @@ Selects which voltage level to place the Core and ECO domain PFETs upon Winkle e <attribute> <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY1</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay (binary in nanoseconds) between a step in the ECO power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT - </description> + <description>Delay (binary in nanoseconds) between a step in the ECO power-down PFET sequence. Enabled per step by the vector defined in ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT</description> <valueType>uint32</valueType> <platInit/> </attribute> @@ -565,26 +456,21 @@ Selects which voltage level to place the Core and ECO domain PFETs upon Winkle e <attribute> <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY0_VALUE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 0 between any step in the ECO power-up PFET sequence. - </description> + <description>Delay value 0 between any step in the ECO power-up PFET sequence.</description> <valueType>uint8</valueType> - <writeable/> </attribute> <attribute> <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY1_VALUE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Delay value 1 between any step in the ECO power-up PFET sequence. - </description> + <description>Delay value 1 between any step in the ECO power-up PFET sequence.</description> <valueType>uint8</valueType> - <writeable/> </attribute> <attribute> <id>ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Binary vector where the most significant bits (0:11) identify the delay to be used for that step of the ECO power up sequence. Power up goes from 11, then 10, then 9,.... then 0. 0 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY0; 1 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY1 - </description> + <description>Binary vector where the most significant bits (0:11) identify the delay to be used for that step of the ECO power up sequence. Power up goes from 11, then 10, then 9,.... then 0. 0 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY0; 1 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY1</description> <valueType>uint32</valueType> <writeable/> </attribute> @@ -596,17 +482,14 @@ Selects which voltage level to place the Core and ECO domain PFETs upon Winkle e Producer: proc_build_gpstate.C -Consumers: proc_pcbs_init.C, proc_pcbs_lpst_init.C, - </description> +Consumers: proc_pcbs_init.C, proc_pcbs_lpst_init.C, </description> <valueType>uint32</valueType> - <writeable/> </attribute> <attribute> <id>ATTR_PM_IVRMS_ENABLED</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Indicates whether available internal voltage regulation macros (iVRMs) are to enabled. This indicates that module VPD has valid #M keywords available. - </description> + <description>Indicates whether available internal voltage regulation macros (iVRMs) are to enabled. This indicates that module VPD has valid #M keywords available.</description> <valueType>uint8</valueType> <enum>TRUE = 1, FALSE = 0</enum> <writeable/> @@ -633,8 +516,7 @@ PMGP0[force_safe_mode] is set If psafe greater-than PMSR[global_actual_pstate], the global_actual_pstate is forced. -The value of Psafe needs to be at or below the nominal Pstate to make sure safe operation of all chiplets. - </description> +The value of Psafe needs to be at or below the nominal Pstate to make sure safe operation of all chiplets.</description> <valueType>uint8</valueType> <writeable/> </attribute> @@ -642,8 +524,7 @@ The value of Psafe needs to be at or below the nominal Pstate to make sure safe <attribute> <id>ATTR_PM_RESONANT_CLOCK_ENABLE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Resonant Clock Enable - </description> + <description>Resonant Clock Enable</description> <valueType>uint8</valueType> <writeable/> </attribute> @@ -661,8 +542,7 @@ Defines the Pstate for the point at which clock sector buffers should be at full <attribute> <id>ATTR_PM_RESONANT_CLOCK_LFRLOW_PSTATE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>LFRLower Low Frequency Resonant Lower. Defines the Pstate for the lower end of the Low Frequency Resonant band - </description> + <description>LFRLower Low Frequency Resonant Lower. Defines the Pstate for the lower end of the Low Frequency Resonant band</description> <valueType>uint8</valueType> <writeable/> </attribute> @@ -670,8 +550,7 @@ Defines the Pstate for the point at which clock sector buffers should be at full <attribute> <id>ATTR_PM_RESONANT_CLOCK_LFRUPPER_PSTATE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>LFRUpper Low Frequency Resonant Upper. Defines the Pstate for the upper end of the Low Frequency Resonant band - </description> + <description>LFRUpper Low Frequency Resonant Upper. Defines the Pstate for the upper end of the Low Frequency Resonant band</description> <valueType>uint8</valueType> <writeable/> </attribute> @@ -679,8 +558,7 @@ Defines the Pstate for the point at which clock sector buffers should be at full <attribute> <id>ATTR_PM_RESONANT_CLOCK_HFRLOW_PSTATE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>HFRLower High Frequency Resonant Low. Defines the Pstate for the lower end of the High Frequency Resonant band - </description> + <description>HFRLower High Frequency Resonant Low. Defines the Pstate for the lower end of the High Frequency Resonant band</description> <valueType>uint8</valueType> <writeable/> </attribute> @@ -688,8 +566,7 @@ Defines the Pstate for the point at which clock sector buffers should be at full <attribute> <id>ATTR_PM_RESONANT_CLOCK_HFRHIGH_PSTATE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>HFRUpper High Frequency Resonant Upper. Defines the Pstate for the upper end of the High Frequency Resonant band - </description> + <description>HFRUpper High Frequency Resonant Upper. Defines the Pstate for the upper end of the High Frequency Resonant band</description> <valueType>uint8</valueType> <writeable/> </attribute> @@ -701,8 +578,7 @@ Defines the Pstate for the point at which clock sector buffers should be at full Supported values: 0x10 (16d), -Chip Select assertion duration is spi_frame_size + 2 - </description> +Chip Select assertion duration is spi_frame_size + 2</description> <valueType>uint8</valueType> <writeable/> </attribute> @@ -712,8 +588,7 @@ Chip Select assertion duration is spi_frame_size + 2 <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description>Number of bits sent out MOSI of the frame -Supported values: 0x000 to spi_frame_size. Values beyond spi_frame_size are ignored. - </description> +Supported values: 0x000 to spi_frame_size. Values beyond spi_frame_size are ignored.</description> <valueType>uint8</valueType> <writeable/> </attribute> @@ -723,8 +598,7 @@ Supported values: 0x000 to spi_frame_size. Values beyond spi_frame_size are ign <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description>Number of SPI clocks after chip select to wait before capturing MISO input -Supported values: 0x000 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured - </description> +Supported values: 0x000 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured</description> <valueType>uint8</valueType> <writeable/> </attribute> @@ -734,8 +608,7 @@ Supported values: 0x000 to spi_frame_size. Values beyond spi_frame_size result <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description>Number of bits captured on MISO input -Supported values: 0x000 to spi_frame_size. The actual number of bits captured is spi_frame_size - spi_in_delay - </description> +Supported values: 0x000 to spi_frame_size. The actual number of bits captured is spi_frame_size - spi_in_delay</description> <valueType>uint8</valueType> <writeable/> </attribute> @@ -743,8 +616,7 @@ Supported values: 0x000 to spi_frame_size. The actual number of bits captured i <attribute> <id>ATTR_PM_SPIPSS_CLOCK_POLARITY</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>SPIPSS Clock Polarity (CPOL=0 means that clk idle is deasserted, CPOH=1 means that clk idle is asserted) - </description> + <description>SPIPSS Clock Polarity (CPOL=0 means that clk idle is deasserted, CPOH=1 means that clk idle is asserted)</description> <valueType>uint8</valueType> <enum>CPOL=0, CPOH=1</enum> <writeable/> @@ -753,8 +625,7 @@ Supported values: 0x000 to spi_frame_size. The actual number of bits captured i <attribute> <id>ATTR_PM_SPIPSS_CLOCK_PHASE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>SPIPSS clock phase (CPHA=0 means to change/sample values of data signals on first edge, otherwise on 2nd) - </description> + <description>SPIPSS clock phase (CPHA=0 means to change/sample values of data signals on first edge, otherwise on 2nd)</description> <valueType>uint8</valueType> <enum>FIRSTEDGE=0, SECONDEDGE=1</enum> <writeable/> @@ -763,8 +634,7 @@ Supported values: 0x000 to spi_frame_size. The actual number of bits captured i <attribute> <id>ATTR_PM_SPIPSS_CLOCK_DIVIDER</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>SPI clock speed divider to divide the nest_nclk/4 mesh clock, which results in a divider = (nest_freq/ (SPI_freq*8))-1 - </description> + <description>SPI clock speed divider to divide the nest_nclk/4 mesh clock, which results in a divider = (nest_freq/ (SPI_freq*8))-1</description> <valueType>uint8</valueType> <writeable/> </attribute> @@ -782,8 +652,7 @@ For values greater than 0x00000, the actual delay is 1 PSS Clock + the time dela Producer: proc_pm_init -Consumer: proc_pss_init - </description> +Consumer: proc_pss_init</description> <valueType>uint32</valueType> <writeable/> </attribute> @@ -795,8 +664,7 @@ Consumer: proc_pss_init Consumer: proc_pm_init -Produces ATTR_PM_SPIPSS_INTER_FRAME_DELAY_SETTING - </description> +Produces ATTR_PM_SPIPSS_INTER_FRAME_DELAY_SETTING</description> <valueType>uint32</valueType> <writeable/> </attribute> @@ -814,20 +682,16 @@ Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang 00010 divided hang pulse = PBAX hang pulse/2 00011 divided hang pulse = PBAX hang pulse/3 . . . -11111 divided hang pulse = PBAX hang pulse/31 - </description> +11111 divided hang pulse = PBAX hang pulse/31</description> <valueType>uint8</valueType> - <writeable/> </attribute> <attribute> <id>ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description>PBAX Send Retry count overcommit -Mode bit to count overcommit retries for the send retry threshold when sending PBAX commands on the powerbus. - </description> +Mode bit to count overcommit retries for the send retry threshold when sending PBAX commands on the powerbus.</description> <valueType>uint8</valueType> - <writeable/> </attribute> <attribute> @@ -840,10 +704,8 @@ Defines the maximum number of retry attempts by the Send Engine for any phase of 0x01 : 1 attempt 0x02 : 2 attempts .etc. -0xFF : 255 attempts - </description> +0xFF : 255 attempts</description> <valueType>uint8</valueType> - <writeable/> </attribute> <attribute> @@ -857,17 +719,14 @@ Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang 00010 divided hang pulse = PBAX hang pulse/2 00011 divided hang pulse = PBAX hang pulse/3 . . . -11111 divided hang pulse = PBAX hang pulse/31 - </description> +11111 divided hang pulse = PBAX hang pulse/31</description> <valueType>uint8</valueType> - <writeable/> </attribute> <attribute> <id>ATTR_PM_SPWUP_FSP</id> <targetType>TARGET_TYPE_EX_CHIPLET</targetType> - <description>Arbitration Attribute for FSP special wakeups: upon set, increment, upon clear, decrement; hardware bit only cleared upon attribute being 0. - </description> + <description>Arbitration Attribute for FSP special wakeups: upon set, increment, upon clear, decrement; hardware bit only cleared upon attribute being 0.</description> <valueType>uint32</valueType> <writeable/> </attribute> @@ -875,8 +734,7 @@ Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang <attribute> <id>ATTR_PM_SPWUP_OCC</id> <targetType>TARGET_TYPE_EX_CHIPLET</targetType> - <description>Arbitration Attribute for OCC special wakeups: upon set, increment, upon clear, decrement; hardware bit only cleared upon attribute being 0. - </description> + <description>Arbitration Attribute for OCC special wakeups: upon set, increment, upon clear, decrement; hardware bit only cleared upon attribute being 0.</description> <valueType>uint32</valueType> <writeable/> </attribute> @@ -884,9 +742,46 @@ Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang <attribute> <id>ATTR_PM_SPWUP_PHYP</id> <targetType>TARGET_TYPE_EX_CHIPLET</targetType> - <description>Arbitration Attribute for PHUP special wakeups: upon set, increment, upon clear, decrement; hardware bit only cleared upon attribute being 0. + <description>Arbitration Attribute for PHUP special wakeups: upon set, increment, upon clear, decrement; hardware bit only cleared upon attribute being 0.</description> + <valueType>uint32</valueType> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_PM_SPWUP_OHA_FLAG</id> + <targetType>TARGET_TYPE_EX_CHIPLET</targetType> + <description>Flag storage to break the recursive calling loop for when accessing the OHA address space from the Special Wakeup procedure.</description> + <valueType>uint8</valueType> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG</id> + <targetType>TARGET_TYPE_EX_CHIPLET</targetType> + <description>Flag storage to have the Special Wakeup procedure ignore a checkstop condition.</description> + <valueType>uint8</valueType> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_CPM_INFLECTION_POINTS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Structure to communicate the CPM inflection points from the CPM code to the Pstate code + + Datablock consisting of: + 8 Inflection Point frequency entries (binary in ATTR_FREQ_PROC_REFCLOCK_KHZ / ATTR_PROC_DPLL_DIVIDER units) + 1 ValidRanges entry - the number of valid inflection points in the previous locations (unit origin) + 1 pMax frequency entry - the maximum allowed boosted frequency (binary in ATTR_FREQ_PROC_REFCLOCK_KHZ / ATTR_DPLL_DIVIDER units) + 6 spare entries + + + Producer: p8_cpm_cal_load + + Consumer: p8_pstate_datablock </description> + <valueType>uint32</valueType> + <array>16</array> <writeable/> </attribute> diff --git a/src/usr/hwpf/hwp/runtime_errors/p8_pcbs_init_errors.xml b/src/usr/hwpf/hwp/runtime_errors/p8_pcbs_init_errors.xml index 2b12ec6b3..d20d33d0b 100644 --- a/src/usr/hwpf/hwp/runtime_errors/p8_pcbs_init_errors.xml +++ b/src/usr/hwpf/hwp/runtime_errors/p8_pcbs_init_errors.xml @@ -20,7 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: p8_pcbs_init_errors.xml,v 1.5 2013/05/23 18:44:17 stillgs Exp $ --> +<!-- $Id: p8_pcbs_init_errors.xml,v 1.6 2013/08/02 19:15:39 stillgs Exp $ --> <!-- Error definitions for proc_pcbs_init procedure --> <hwpErrors> <!-- *********************************************************************** --> @@ -29,6 +29,7 @@ <description>Psafe Pstate and FSM-stable timeout in proc_pcbs_init.</description> <ffdc>LOOPCOUNT</ffdc> <ffdc>PMSR</ffdc> + <callout><target>PROC_CHIP</target><priority>HIGH</priority></callout> </hwpError> <!-- *********************************************************************** --> <hwpError> diff --git a/src/usr/hwpf/hwp/runtime_errors/p8_pmc_errors.xml b/src/usr/hwpf/hwp/runtime_errors/p8_pmc_errors.xml index 28bc86d04..31a38c305 100644 --- a/src/usr/hwpf/hwp/runtime_errors/p8_pmc_errors.xml +++ b/src/usr/hwpf/hwp/runtime_errors/p8_pmc_errors.xml @@ -20,6 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> +<!-- $Id: p8_pmc_errors.xml,v 1.6 2013/08/02 19:15:41 stillgs Exp $ --> <!-- Error definitions for proc_pmc_init procedure --> <hwpErrors> <!-- *********************************************************************** --> @@ -35,20 +36,46 @@ </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROCPM_PMCRESET_TARGET_ERROR</rc> - <description>Either both targets are masters or slaves in reset mode.</description> + <rc>RC_PROCPM_PMCRESET_SPIVID_CONFIG_ERROR</rc> + <description>Master target does not have SPIVID ports enabled: check the configuration setup.</description> + <ffdc>MASTER_TARGET</ffdc> + <ffdc>ATTR_SPIVID_PORT_ENABLE</ffdc> </hwpError> - <!-- *********************************************************************** --> <hwpError> <rc>RC_PROCPM_FIR_ERROR</rc> <description>Either both targets are masters or slaves in reset mode.</description> </hwpError> - <!-- *********************************************************************** --> <hwpError> <rc>RC_PROCPM_PMCRESET_DCM_INSTALL_ERROR</rc> <description>Error found in DCM installment..</description> </hwpError> <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROCPM_PMC_MASTER_CONFIG_ERROR</rc> + <description>MasterPMC bit of Master PMC is not set.</description> + <ffdc>MASTERPMCMODE</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROCPM_PMC_SLAVE_CONFIG_ERROR</rc> + <description>MasterPMC bit of Slave PMC is not set.</description> + <ffdc>SLAVEPMCMODE</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROCPM_PMC_INTERCHIP_CONFIG_ERROR</rc> + <description>Master is enabled with interchip interface but slave is not.</description> + <ffdc>MASTERPMCMODE</ffdc> + <ffdc>SLAVEPMCMODE</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROCPM_PMC_FW_MODE_ERROR</rc> + <description>Master is enabled with FW pstate mode but slave is not </description> + <ffdc>MASTERPMCMODE</ffdc> + <ffdc>SLAVEPMCMODE</ffdc> + </hwpError> + <!-- *********************************************************************** --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/runtime_errors/proc_cpu_special_wakeup_errors.xml b/src/usr/hwpf/hwp/runtime_errors/proc_cpu_special_wakeup_errors.xml index 380686157..4428d5730 100644 --- a/src/usr/hwpf/hwp/runtime_errors/proc_cpu_special_wakeup_errors.xml +++ b/src/usr/hwpf/hwp/runtime_errors/proc_cpu_special_wakeup_errors.xml @@ -20,12 +20,20 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_cpu_special_wakeup_errors.xml,v 1.5 2013/06/20 13:28:18 stillgs Exp $ --> <!-- Error definitions for proc_cpu_special_wakeup procedure --> <hwpErrors> <!-- *********************************************************************** --> <hwpError> <rc>RC_PROCPM_SPCWKUP_TIMEOUT</rc> <description>Special wakeup to all EX chiplets timed out.</description> + <ffdc>I_OPERATION</ffdc> + <ffdc>EX</ffdc> + <ffdc>ENTITY</ffdc> + <ffdc>POLLCOUNT</ffdc> + <ffdc>PMGP0</ffdc> + <ffdc>SP_WKUP_REG_ADDRESS</ffdc> + <ffdc>SP_WKUP_REG_VALUE</ffdc> </hwpError> <!-- *********************************************************************** --> <hwpError> @@ -37,12 +45,29 @@ <hwpError> <rc>RC_PROCPM_SPCWKUP_CODE_BAD_OP</rc> <description>An invalid operation (eg besides Set or Clear ENUM) was passed to proc_cpu_special_wakeup</description> - <ffdc>I_OPERATION</ffdc> + <ffdc>I_OPERATION</ffdc> </hwpError> <!-- *********************************************************************** --> <hwpError> <rc>RC_PROCPM_CHKSTOP</rc> <description>system is checkstopped before proc_cpu_special_wakeup</description> </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROCPM_SPCWKUP_PUTGETSCOM_FAILED</rc> + <description>Register read/write failed in proc_cpu_special_wakeup</description> + <ffdc>ERRORS</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROCPM_SPCWKUP_OHA_FLAG_SET_ON_EXIT</rc> + <description>Register read/write failed in proc_cpu_special_wakeup</description> + <ffdc>I_OPERATION</ffdc> + <ffdc>EX</ffdc> + <ffdc>ENTITY</ffdc> + <ffdc>PHYP_SPCWKUP_COUNT</ffdc> + <ffdc>FSP_SPCWKUP_COUNT</ffdc> + <ffdc>OCC_SPCWKUP_COUNT</ffdc> + </hwpError> </hwpErrors> diff --git a/src/usr/runtime/common/hsvc_procdata.C b/src/usr/runtime/common/hsvc_procdata.C index 73cd6755b..e01f95eb3 100644 --- a/src/usr/runtime/common/hsvc_procdata.C +++ b/src/usr/runtime/common/hsvc_procdata.C @@ -20,77 +20,29 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// Generated on Wed Jul 17 21:21:59 CDT 2013 by cswenson from -// ./create_hsvc_data.pl -w ../../xml/attribute_info/common_attributes.xml ../../xml/attribute_info/chip_attributes.xml ../../xml/attribute_info/poreve_memory_attributes.xml ../../xml/attribute_info/p8_xip_customize_attributes.xml ../../xml/attribute_info/proc_pll_ring_attributes.xml ../../xml/attribute_info/L2_L3_attributes.xml ../../xml/attribute_info/proc_fab_smp_fabric_attributes.xml ../../xml/attribute_info/proc_setup_bars_l3_attributes.xml ../../xml/attribute_info/freq_attributes.xml ../../xml/attribute_info/unit_attributes.xml ../../xml/attribute_info/pm_hwp_attributes.xml ../../xml/attribute_info/scratch_attributes.xml ../../xml/attribute_info/pm_plat_attributes.xml ../../xml/attribute_info/system_attributes.xml ../../xml/attribute_info/proc_winkle_scan_override_attributes.xml -// -- Input: ../../xml/attribute_info/common_attributes.xml -- +// Generated on Wed Feb 20 15:44:15 CST 2013 by dcrowell from +// src/usr/runtime/common/create_hsvc_data.pl src/usr/runtime/common/extra_runtime_attributes.xml src/usr/hwpf/hwp/chip_attributes.xml src/usr/hwpf/hwp/runtime_attributes/pm_plat_attributes.xml src/usr/hwpf/hwp/runtime_attributes/pm_hwp_attributes.xml -w -d +// -- Input: src/usr/runtime/common/extra_runtime_attributes.xml -- HSVC_LOAD_ATTR( ATTR_FUNCTIONAL ); -HSVC_LOAD_ATTR( ATTR_POS ); -// -- Input: ../../xml/attribute_info/chip_attributes.xml -- +// -- Input: src/usr/hwpf/hwp/chip_attributes.xml -- HSVC_LOAD_ATTR( ATTR_CHIP_HAS_SBE ); HSVC_LOAD_ATTR( ATTR_CHIP_ID ); HSVC_LOAD_ATTR( ATTR_CHIP_REGIONS_TO_ENABLE ); HSVC_LOAD_ATTR_P( ATTR_EC ); -HSVC_LOAD_ATTR( ATTR_EX_L2_SINGLE_MEMBER_ENABLE ); HSVC_LOAD_ATTR( ATTR_FABRIC_CHIP_ID ); HSVC_LOAD_ATTR( ATTR_FABRIC_NODE_ID ); HSVC_LOAD_ATTR( ATTR_FSI_GP_REG_SCOM_ACCESS ); HSVC_LOAD_ATTR_P( ATTR_NAME ); HSVC_LOAD_ATTR( ATTR_PROC_DCM_INSTALLED ); -// -- Input: ../../xml/attribute_info/poreve_memory_attributes.xml -- -HSVC_LOAD_ATTR( ATTR_PNOR_I2C_ADDRESS_BYTES ); -HSVC_LOAD_ATTR( ATTR_SBE_SEEPROM_I2C_ADDRESS_BYTES ); -HSVC_LOAD_ATTR( ATTR_SBE_SEEPROM_I2C_DEVICE_ADDRESS ); -HSVC_LOAD_ATTR( ATTR_SBE_SEEPROM_I2C_PORT ); -// -- Input: ../../xml/attribute_info/p8_xip_customize_attributes.xml -- -HSVC_LOAD_ATTR( ATTR_PROC_ADU_UNTRUSTED_BAR_BASE_ADDR ); -HSVC_LOAD_ATTR( ATTR_PROC_ADU_UNTRUSTED_BAR_SIZE ); -HSVC_LOAD_ATTR( ATTR_PROC_A_ENABLE ); -HSVC_LOAD_ATTR( ATTR_PROC_NX_ENABLE ); -HSVC_LOAD_ATTR( ATTR_PROC_PCIE_ENABLE ); -HSVC_LOAD_ATTR( ATTR_PROC_PSI_UNTRUSTED_BAR0_BASE_ADDR ); -HSVC_LOAD_ATTR( ATTR_PROC_PSI_UNTRUSTED_BAR0_SIZE ); -HSVC_LOAD_ATTR( ATTR_PROC_PSI_UNTRUSTED_BAR1_BASE_ADDR ); -HSVC_LOAD_ATTR( ATTR_PROC_PSI_UNTRUSTED_BAR1_SIZE ); -HSVC_LOAD_ATTR( ATTR_PROC_SECURITY_SETUP_VECTOR ); -HSVC_LOAD_ATTR( ATTR_PROC_X_ENABLE ); -// -- Input: ../../xml/attribute_info/proc_pll_ring_attributes.xml -- -HSVC_LOAD_ATTR( ATTR_PROC_AB_BNDY_PLL_CHIPLET_ID ); -HSVC_LOAD_ATTR( ATTR_PROC_AB_BNDY_PLL_DATA ); -HSVC_LOAD_ATTR( ATTR_PROC_AB_BNDY_PLL_FLUSH ); -HSVC_LOAD_ATTR( ATTR_PROC_AB_BNDY_PLL_FOR_DCCAL_DATA ); -//HSVC_LOAD_ATTR( ATTR_PROC_AB_BNDY_PLL_FOR_DCCAL_LENGTH ); -HSVC_LOAD_ATTR( ATTR_PROC_AB_BNDY_PLL_LENGTH ); -HSVC_LOAD_ATTR( ATTR_PROC_AB_BNDY_PLL_SCAN_SELECT ); -HSVC_LOAD_ATTR( ATTR_PROC_PB_BNDY_DMIPLL_CHIPLET_ID ); -HSVC_LOAD_ATTR( ATTR_PROC_PB_BNDY_DMIPLL_DATA ); -HSVC_LOAD_ATTR( ATTR_PROC_PB_BNDY_DMIPLL_FLUSH ); -HSVC_LOAD_ATTR( ATTR_PROC_PB_BNDY_DMIPLL_FOR_DCCAL_DATA ); -//HSVC_LOAD_ATTR( ATTR_PROC_PB_BNDY_DMIPLL_FOR_DCCAL_LENGTH ); -HSVC_LOAD_ATTR( ATTR_PROC_PB_BNDY_DMIPLL_LENGTH ); -HSVC_LOAD_ATTR( ATTR_PROC_PB_BNDY_DMIPLL_SCAN_SELECT ); -HSVC_LOAD_ATTR( ATTR_PROC_PCI_BNDY_PLL_CHIPLET_ID ); -HSVC_LOAD_ATTR( ATTR_PROC_PCI_BNDY_PLL_DATA ); -HSVC_LOAD_ATTR( ATTR_PROC_PCI_BNDY_PLL_FLUSH ); -HSVC_LOAD_ATTR( ATTR_PROC_PCI_BNDY_PLL_LENGTH ); -HSVC_LOAD_ATTR( ATTR_PROC_PCI_BNDY_PLL_SCAN_SELECT ); -HSVC_LOAD_ATTR( ATTR_PROC_PERV_BNDY_PLL_CHIPLET_ID ); -HSVC_LOAD_ATTR( ATTR_PROC_PERV_BNDY_PLL_DATA ); -HSVC_LOAD_ATTR( ATTR_PROC_PERV_BNDY_PLL_FLUSH ); -HSVC_LOAD_ATTR( ATTR_PROC_PERV_BNDY_PLL_LENGTH ); -HSVC_LOAD_ATTR( ATTR_PROC_PERV_BNDY_PLL_SCAN_SELECT ); -// -- Input: ../../xml/attribute_info/L2_L3_attributes.xml -- -// No attributes found -// -- Input: ../../xml/attribute_info/proc_fab_smp_fabric_attributes.xml -- -HSVC_LOAD_ATTR( ATTR_PROC_PCIE_NOT_F_LINK ); -// -- Input: ../../xml/attribute_info/proc_setup_bars_l3_attributes.xml -- -HSVC_LOAD_ATTR( ATTR_PROC_L3_BAR1_REG ); -HSVC_LOAD_ATTR( ATTR_PROC_L3_BAR2_REG ); -HSVC_LOAD_ATTR( ATTR_PROC_L3_BAR_GROUP_MASK_REG ); -// -- Input: ../../xml/attribute_info/freq_attributes.xml -- -// No attributes found -// -- Input: ../../xml/attribute_info/unit_attributes.xml -- -// No attributes found -// -- Input: ../../xml/attribute_info/pm_hwp_attributes.xml -- +// -- Input: src/usr/hwpf/hwp/runtime_attributes/pm_plat_attributes.xml -- +HSVC_LOAD_ATTR( ATTR_PM_APSS_CHIP_SELECT ); +HSVC_LOAD_ATTR( ATTR_PM_PBAX_BRDCST_ID_VECTOR ); +HSVC_LOAD_ATTR( ATTR_PM_PBAX_CHIPID ); +HSVC_LOAD_ATTR( ATTR_PM_PBAX_NODEID ); +HSVC_LOAD_ATTR( ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM ); +HSVC_LOAD_ATTR( ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM ); +HSVC_LOAD_ATTR( ATTR_PM_SPIVID_PORT_ENABLE ); +// -- Input: src/usr/hwpf/hwp/runtime_attributes/pm_hwp_attributes.xml -- HSVC_LOAD_ATTR( ATTR_PM_AISS_TIMEOUT ); HSVC_LOAD_ATTR( ATTR_PM_EXTERNAL_VRM_STEPDELAY_RANGE ); HSVC_LOAD_ATTR( ATTR_PM_EXTERNAL_VRM_STEPDELAY_VALUE ); @@ -134,9 +86,10 @@ HSVC_LOAD_ATTR( ATTR_PM_RESONANT_CLOCK_HFRLOW_PSTATE ); HSVC_LOAD_ATTR( ATTR_PM_RESONANT_CLOCK_LFRLOW_PSTATE ); HSVC_LOAD_ATTR( ATTR_PM_RESONANT_CLOCK_LFRUPPER_PSTATE ); HSVC_LOAD_ATTR( ATTR_PM_SAFE_PSTATE ); -HSVC_LOAD_ATTR( ATTR_PM_SLEEP_ENTRY ); -HSVC_LOAD_ATTR( ATTR_PM_SLEEP_EXIT ); -HSVC_LOAD_ATTR( ATTR_PM_SLEEP_TYPE ); +// TODO - Issue 78944 +//HSVC_LOAD_ATTR( ATTR_PM_SLEEP_ENTRY ); +//HSVC_LOAD_ATTR( ATTR_PM_SLEEP_EXIT ); +//HSVC_LOAD_ATTR( ATTR_PM_SLEEP_TYPE ); HSVC_LOAD_ATTR( ATTR_PM_SLEEP_WINKLE_REQUEST_TIMEOUT ); HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_CLOCK_DIVIDER ); HSVC_LOAD_ATTR( ATTR_PM_SPIPSS_CLOCK_PHASE ); @@ -162,20 +115,6 @@ HSVC_LOAD_ATTR( ATTR_PM_SPIVID_IN_DELAY_FRAME1 ); HSVC_LOAD_ATTR( ATTR_PM_SPIVID_IN_DELAY_FRAME2 ); HSVC_LOAD_ATTR( ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE ); HSVC_LOAD_ATTR( ATTR_PM_SPIVID_MAX_RETRIES ); -HSVC_LOAD_ATTR( ATTR_PM_WINKLE_TYPE ); +// TODO - Issue 78944 +//HSVC_LOAD_ATTR( ATTR_PM_WINKLE_TYPE ); HSVC_LOAD_ATTR( ATTR_PROC_DPLL_DIVIDER ); -// -- Input: ../../xml/attribute_info/scratch_attributes.xml -- -// No attributes found -// -- Input: ../../xml/attribute_info/pm_plat_attributes.xml -- -HSVC_LOAD_ATTR( ATTR_PM_APSS_CHIP_SELECT ); -HSVC_LOAD_ATTR( ATTR_PM_PBAX_BRDCST_ID_VECTOR ); -HSVC_LOAD_ATTR( ATTR_PM_PBAX_CHIPID ); -HSVC_LOAD_ATTR( ATTR_PM_PBAX_NODEID ); -HSVC_LOAD_ATTR( ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM ); -HSVC_LOAD_ATTR( ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM ); -HSVC_LOAD_ATTR( ATTR_PM_SPIVID_PORT_ENABLE ); -// -- Input: ../../xml/attribute_info/system_attributes.xml -- -// No attributes found -// -- Input: ../../xml/attribute_info/proc_winkle_scan_override_attributes.xml -- -HSVC_LOAD_ATTR( ATTR_PROC_EX_FUNC_L3_DELTA_DATA ); -HSVC_LOAD_ATTR( ATTR_PROC_EX_FUNC_L3_LENGTH ); diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index b8123c422..c38fa1282 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -12895,4 +12895,60 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </hwpfToHbAttrMap> </attribute> +<attribute> + <id>PM_SPWUP_OHA_FLAG</id> + <description>Flag storage to break the recursive calling loop for when accessing the OHA address space from the Special Wakeup procedure.</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPWUP_OHA_FLAG</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>PM_SPWUP_IGNORE_XSTOP_FLAG</id> + <description>Flag storage to have the Special Wakeup procedure ignore a checkstop condition.</description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>CPM_INFLECTION_POINTS</id> + <description>Structure to communicate the CPM inflection points from the CPM code to the Pstate code + Datablock consisting of: + 8 Inflection Point frequency entries (binary in ATTR_FREQ_PROC_REFCLOCK_KHZ / ATTR_PROC_DPLL_DIVIDER units) + 1 ValidRanges entry - the number of valid inflection points in the previous locations (unit origin) + 1 pMax frequency entry - the maximum allowed boosted frequency (binary in ATTR_FREQ_PROC_REFCLOCK_KHZ / ATTR_DPLL_DIVIDER units) + 6 spare entries + Producer: p8_cpm_cal_load + Consumer: p8_pstate_datablock + </description> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + <array>16</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_CPM_INFLECTION_POINTS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + </attributes> |
