INITPROC: Hostboot - Low Priority HW Init Procedures for week of 5/7

SW202434

Change-Id: I6bf082deb2cbe927c0ba92d670906b232482578f
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4627
Tested-by: Jenkins Server
Reviewed-by: Mark W. Wenning <wenning@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

2 files changed, 126 insertions, 34 deletions

diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C b/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C
index d31a0d68f..9dfbe1523 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_start_clocks_chiplets.C,v 1.13 2013/01/20 19:26:07 jmcgill Exp $
+// $Id: proc_start_clocks_chiplets.C,v 1.16 2013/05/16 21:08:54 mjjones Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_start_clocks_chiplets.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -231,9 +231,14 @@ fapi::ReturnCode proc_start_clocks_chiplet_clear_clk_scansel_reg(
 // function: utility subroutine to get partial good vector from SEEPROM
 // parameters: i_target                 => chip target
 //             i_chiplet_base_addr      => base SCOM address for chiplet
-//             i_chiplet_reg_vec        => output vector
+//             o_chiplet_reg_vec        => output vector
 // returns: FAPI_RC_SUCCESS if operation was successful, else error
 //------------------------------------------------------------------------------
+
+// note:
+// expected value out of SEEPROM (in case of "all good", the "Partial Good Region"-Pattern are:
+// XBUS = 0xF00, ABUS = 0xE100, PCIE = 0xF700
+
 fapi::ReturnCode proc_start_clocks_get_partial_good_vector(
     const fapi::Target& i_target,
     const uint32_t i_chiplet_base_addr,
@@ -241,9 +246,6 @@ fapi::ReturnCode proc_start_clocks_get_partial_good_vector(
     )
 {
     fapi::ReturnCode rc;
-//  uint32_t rc_ecmd = 0;
-
-//  uint8_t  chiplet = 0;
     uint64_t partial_good_regions[32];
 
     FAPI_DBG("proc_start_clocks_get_partial_good_vector: Start");
@@ -260,13 +262,6 @@ fapi::ReturnCode proc_start_clocks_get_partial_good_vector(
         }
 
 
-// expectecd value out of SEEPROM (all good)
-// Partial Good Region Pattern are:
-// XBUS = 0xF000
-// ABUS = 0xE100
-// PCIE = 0xF700
-
-
         FAPI_DBG("proc_start_clocks_get_partial_good_vector: start assignment of the partial good vector per chiplet");
 
         switch (i_chiplet_base_addr)
@@ -309,12 +304,14 @@ fapi::ReturnCode proc_start_clocks_get_partial_good_vector(
 
 //------------------------------------------------------------------------------
 // function: utility subroutine to set clock region register (starts clocks)
-// parameters: i_target                 => chip target
-//             i_chiplet_base_addr => base SCOM address for chiplet
-//             i_chiplet_reg_vec   => vector from SEEPROM with partial good
-//                                    clock regions
+// parameters: i_target              => chip target
+//             i_chiplet_base_addr   => base SCOM address for chiplet
+//             i_chiplet_reg_vec     => vector from SEEPROM with partial good
+//                                      clock regions
+//             o_chiplet_clkreg_vec  => output vector which contains
+//                                      the masked vector -> used to set the
+//					clock region register	
 // returns: FAPI_RC_SUCCESS if operation was successful, else error
-
 //------------------------------------------------------------------------------
 fapi::ReturnCode proc_start_clocks_chiplet_set_clk_region_reg(
     const fapi::Target& i_target,
@@ -400,10 +397,10 @@ fapi::ReturnCode proc_start_clocks_chiplet_set_clk_region_reg(
 //------------------------------------------------------------------------------
 // function: utility subroutine to check clock status register to ensure
 //           all desired clock domains have been started
-// parameters: i_target            => chip target
-//             i_chiplet_base_addr => base SCOM address for chiplet
-//             i_chiplet_reg_vec   => region vector of SEEPROM for clock regions
-//                                    need to be turned on
+// parameters: i_target             => chip target
+//             i_chiplet_base_addr  => base SCOM address for chiplet
+//             i_chiplet_clkreg_vec => region vector of SEEPROM for clock regions
+//                                     need to be turned on
 // returns: FAPI_RC_SUCCESS if operation was successful, else
 //          RC_PROC_START_CLOCKS_CHIPLETS_CLK_STATUS_ERR if status register
 //          data does not match expected pattern
@@ -421,6 +418,8 @@ fapi::ReturnCode proc_start_clocks_chiplet_check_clk_status_reg(
     uint32_t scom_addr = i_chiplet_base_addr |
                          GENERIC_CLK_STATUS_0x00030008;
     const uint32_t xbus = X_BUS_CHIPLET_0x04000000;
+    const uint32_t abus = A_BUS_CHIPLET_0x08000000;
+    const uint32_t pcie = PCIE_CHIPLET_0x09000000;
 
     FAPI_DBG("proc_start_clocks_chiplet_check_clk_status_reg: Start");
 
@@ -481,9 +480,25 @@ fapi::ReturnCode proc_start_clocks_chiplet_check_clk_status_reg(
             FAPI_ERR("proc_start_clocks_chiplet_check_clk_status_reg: Clock status register actual value (%016llX) does not match expected value (%016llX)",
                      status_data.getDoubleWord(0), exp_data.getDoubleWord(0));
             ecmdDataBufferBase & STATUS_REG = status_data;
-            uint32_t CHIPLET_BASE_SCOM_ADDR = i_chiplet_base_addr;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_CHIPLETS_CLK_STATUS_ERR);
-            break;
+            ecmdDataBufferBase & EXPECTED_REG = exp_data;
+
+            if ( i_chiplet_base_addr == xbus)
+            {
+               FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_XBUS_CHIPLET_CLK_STATUS_ERR);
+               break;
+            }
+            if ( i_chiplet_base_addr == abus)
+            {
+               FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_ABUS_CHIPLET_CLK_STATUS_ERR);
+               break;
+            }
+            if ( i_chiplet_base_addr == pcie)
+            {
+               const fapi::Target & CHIP_IN_ERROR  = i_target;
+               FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_PCIE_CHIPLET_CLK_STATUS_ERR);
+               break;
+            }
+
         }
 
     } while(0);
@@ -607,6 +622,10 @@ fapi::ReturnCode proc_start_clocks_chiplet_check_fir(
     ecmdDataBufferBase fir_data(64);
     uint32_t scom_addr = i_chiplet_base_addr |
                          GENERIC_XSTOP_0x00040000;
+    const uint32_t xbus = X_BUS_CHIPLET_0x04000000;
+    const uint32_t abus = A_BUS_CHIPLET_0x08000000;
+    const uint32_t pcie = PCIE_CHIPLET_0x09000000;
+
 
     FAPI_DBG("proc_start_clocks_chiplet_check_fir: Start");
 
@@ -629,9 +648,27 @@ fapi::ReturnCode proc_start_clocks_chiplet_check_fir(
             FAPI_ERR("proc_start_clocks_chiplet_check_fir: FIR register actual value (%016llX) does not match expected value (%016llX)",
                      fir_data.getDoubleWord(0), PROC_START_CLOCKS_CHIPLETS_CHIPLET_FIR_REG_EXP);
             ecmdDataBufferBase & FIR_REG = fir_data;
-            uint32_t CHIPLET_BASE_SCOM_ADDR = i_chiplet_base_addr;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_CHIPLETS_FIR_ERR);
-            break;
+            const uint64_t & FIR_EXP_REG = PROC_START_CLOCKS_CHIPLETS_CHIPLET_FIR_REG_EXP;
+
+
+            if ( i_chiplet_base_addr == xbus)
+            {
+               FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_XBUS_CHIPLET_FIR_ERR);
+               break;
+            }
+            if ( i_chiplet_base_addr == abus)
+            {
+               FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_ABUS_CHIPLET_FIR_ERR);
+               break;
+            }
+            if ( i_chiplet_base_addr == pcie)
+            {
+
+               const fapi::Target & CHIP_IN_ERROR  = i_target;
+               FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_PCIE_CHIPLET_FIR_ERR);
+               break;
+            }
+
         }
 
     } while(0);
@@ -646,8 +683,6 @@ fapi::ReturnCode proc_start_clocks_chiplet_check_fir(
 // function: utility subroutine to run clock start sequence on a generic chiplet
 // parameters: i_target            => chip target
 //             i_chiplet_base_addr => base SCOM address for chiplet
-//             i_status_reg_exp    => expected value for clock status register
-//                                    after clock start
 // returns: FAPI_RC_SUCCESS if operation was successful, else error
 //------------------------------------------------------------------------------
 fapi::ReturnCode proc_start_clocks_generic_chiplet(
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets_errors.xml b/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets_errors.xml
index 2fd2d6925..505e425c4 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets_errors.xml
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets_errors.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- IBM CONFIDENTIAL                                                       -->
 <!--                                                                        -->
-<!-- COPYRIGHT International Business Machines Corp. 2012                   -->
+<!-- COPYRIGHT International Business Machines Corp. 2012,2013              -->
 <!--                                                                        -->
 <!-- p1                                                                     -->
 <!--                                                                        -->
@@ -20,26 +20,83 @@
 <!-- Origin: 30                                                             -->
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- $Id: proc_start_clocks_chiplets_errors.xml,v 1.4 2013/05/06 12:33:48 rkoester Exp $ -->
 <!-- Error definitions for proc_start_clocks_chiplets procedure -->
 <hwpErrors>
   <!-- *********************************************************************** -->
   <hwpError>
-    <rc>RC_PROC_START_CLOCKS_CHIPLETS_CLK_STATUS_ERR</rc>
+    <rc>RC_PROC_START_CLOCKS_XBUS_CHIPLET_CLK_STATUS_ERR</rc>
+    <description>Unexpected XBUS clock status register returned after clock start operation.</description>
+    <ffdc>STATUS_REG</ffdc>
+    <ffdc>EXPECTED_REG</ffdc>
+  </hwpError>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_START_CLOCKS_ABUS_CHIPLET_CLK_STATUS_ERR</rc>
+    <description>Unexpected ABUS clock status register returned after clock start operation.</description>
+    <ffdc>STATUS_REG</ffdc>
+    <ffdc>EXPECTED_REG</ffdc>
+  </hwpError>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_START_CLOCKS_PCIE_CHIPLET_CLK_STATUS_ERR</rc>
     <description>Unexpected clock status register returned after clock start operation.</description>
     <ffdc>STATUS_REG</ffdc>
-    <ffdc>CHIPLET_BASE_SCOM_ADDR</ffdc>
+    <ffdc>EXPECTED_REG</ffdc>
+    <callout>
+     <target>CHIP_IN_ERROR</target>
+     <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>CHIP_IN_ERROR</target>
+    </deconfigure>
+    <gard>
+      <target>CHIP_IN_ERROR</target>
+    </gard>
   </hwpError>
   <!-- *********************************************************************** -->
   <hwpError>
-    <rc>RC_PROC_START_CLOCKS_CHIPLETS_FIR_ERR</rc>
+    <rc>RC_PROC_START_CLOCKS_XBUS_CHIPLET_FIR_ERR</rc>
     <description>Unexpected chiplet FIR bit set after clock start operation.</description>
     <ffdc>FIR_REG</ffdc>
-    <ffdc>CHIPLET_BASE_SCOM_ADDR</ffdc>
+    <ffdc>FIR_EXP_REG</ffdc>
+  </hwpError>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_START_CLOCKS_ABUS_CHIPLET_FIR_ERR</rc>
+    <description>Unexpected chiplet FIR bit set after clock start operation.</description>
+    <ffdc>FIR_REG</ffdc>
+    <ffdc>FIR_EXP_REG</ffdc>
+  </hwpError>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_START_CLOCKS_PCIE_CHIPLET_FIR_ERR</rc>
+    <description>Unexpected chiplet FIR bit set after clock start operation.</description>
+    <ffdc>FIR_REG</ffdc>
+    <ffdc>FIR_EXP_REG</ffdc>
+    <callout>
+      <target>CHIP_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>CHIP_IN_ERROR</target>
+    </deconfigure>
+    <gard>
+      <target>CHIP_IN_ERROR</target>
+    </gard>
   </hwpError>
   <!-- *********************************************************************** -->
   <hwpError>
     <rc>RC_PROC_START_CLOCKS_CHIPLETS_PARTIAL_GOOD_ERR</rc>
     <description>Unexpected chiplet selection when reading the partial good vector.</description>
     <ffdc>CHIPLET_BASE_SCOM_ADDR</ffdc>
+   <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+      </callout>
   </hwpError>
 </hwpErrors>
+  <!-- *********************************************************************** -->
+  <!-- TODO Callout all chiplets of a specified type on a chip: story 69794    -->
+  <!-- TODO Callout the PCI refclock: story 69766                              -->
+  <!-- *********************************************************************** -->