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| author | Thi Tran <thi@us.ibm.com> | 2013-05-21 12:35:38 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-05-30 13:07:24 -0500 |
| commit | f74626d33553b1f5b557e57bf1a3672a6afb4e5a (patch) | |
| tree | 71455321c532294e2939352bd7f6e16100f0e78f | |
| parent | a9d662d90defa280bf8e3f98cd115cbb84d718b0 (diff) | |
| download | talos-hostboot-f74626d33553b1f5b557e57bf1a3672a6afb4e5a.tar.gz talos-hostboot-f74626d33553b1f5b557e57bf1a3672a6afb4e5a.zip | |
INITPROC: Hostboot - Low Priority HW Init Procedures for week of 5/7
SW202434
Change-Id: I6bf082deb2cbe927c0ba92d670906b232482578f
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4627
Tested-by: Jenkins Server
Reviewed-by: Mark W. Wenning <wenning@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
13 files changed, 1249 insertions, 661 deletions
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.H b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.H index e437b03e1..1122ea508 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.H +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.H @@ -20,12 +20,14 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_image_help_base.H,v 1.16 2013/03/27 18:31:57 cmolsen Exp $ +// $Id: p8_image_help_base.H,v 1.17 2013/05/01 15:49:00 dcrowell Exp $ //------------------------------------------------------------------------------ // Title: p8_image_help_base.H // Description: Contains the most basic structures and defines needed for // image building and interpretation. //------------------------------------------------------------------------------ +#ifndef _P8_IMAGE_HELP_BASE_H_ +#define _P8_IMAGE_HELP_BASE_H_ #include <sbe_xip_image.h> @@ -118,3 +120,4 @@ int over_write_ring_data_in_image( void *io_image, } #endif +#endif //_P8_IMAGE_HELP_BASE_H_ diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api.H b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api.H index 8acb9aaf1..4ba6dedf6 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api.H +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_pore_table_gen_api.H,v 1.19 2013/01/31 21:10:10 cmolsen Exp $ +// $Id: p8_pore_table_gen_api.H,v 1.20 2013/05/08 20:18:50 cmolsen Exp $ /*------------------------------------------------------------------------------*/ /* *! (C) Copyright International Business Machines Corp. 2012 */ /* *! All Rights Reserved -- Property of IBM */ @@ -205,13 +205,14 @@ CONST_UINT64_T( SCRATCH0_RESET_VALUE, (0xABBA99EBBA33DADA) ); #define SCAN_MAX_ROTATE_38XXX_NAME "scan_max_rotate_38xxx" #define SCAN_ROTATE_DEFAULT 110 // Limit suggested by Tilman. #define SCAN_MAX_ROTATE 0x00000FE0 -#define SCAN_MAX_ROTATE_LONG 0x000FFFFF // BITS 12->31. +//#define SCAN_MAX_ROTATE_LONG 0x000FFFFF // BITS 12->31. +#define SCAN_MAX_ROTATE_LONG 0x000007C7 // Experimental max val // RAM table defines #define XIPSIZE_RAM_ENTRY ( (sizeof(RamTableEntry)+7)/8*8 ) #define SLW_MAX_CORES 16 -#define SLW_MAX_CPUREGS_CORE 9 -#define SLW_MAX_CPUREGS_THREADS 2 +#define SLW_MAX_CPUREGS_CORE 10 +#define SLW_MAX_CPUREGS_THREADS 5 #define SLW_CORE_THREADS 8 #define SLW_MAX_CPUREGS_OPS ( SLW_MAX_CPUREGS_CORE + \ SLW_CORE_THREADS*SLW_MAX_CPUREGS_THREADS ) @@ -228,9 +229,13 @@ enum { P8_SPR_HID1 = 1009, P8_SPR_HID4 = 1012, P8_SPR_HID5 = 1014, + P8_CORE_XTRA8 =10008, + P8_CORE_XTRA9 =10009, P8_SPR_HSPRG0 = 304, P8_SPR_LPCR = 318, - P8_MSR_MSR = 2000 + P8_MSR_MSR = 2000, + P8_THRD_XTRA3 =20003, + P8_THRD_XTRA4 =20004 }; // SCOM table defines - Common diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_static_data.c b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_static_data.c index 6cce13ed7..48d3b8460 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_static_data.c +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_static_data.c @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_pore_table_static_data.c,v 1.4 2012/09/13 19:42:59 cmolsen Exp $ +// $Id: p8_pore_table_static_data.c,v 1.6 2013/05/08 20:19:41 cmolsen Exp $ /*------------------------------------------------------------------------------*/ /* *! (C) Copyright International Business Machines Corp. 2012 */ /* *! All Rights Reserved -- Property of IBM */ @@ -33,6 +33,7 @@ /* *! COMMENTS : This file is exclusively for PHYP environment. */ // /*------------------------------------------------------------------------------*/ +#include <HvPlicModule.H> #include <p8_pore_table_gen_api.H> const SlwSprRegs SLW_SPR_REGS[] = { @@ -46,10 +47,14 @@ const SlwSprRegs SLW_SPR_REGS[] = { { "P8_SPR_HID1", P8_SPR_HID1, ( P8_SPR_HID1 >>5 | ( P8_SPR_HID1 &0x1f)<<5 ) }, { "P8_SPR_HID4", P8_SPR_HID4, ( P8_SPR_HID4 >>5 | ( P8_SPR_HID4 &0x1f)<<5 ) }, { "P8_SPR_HID5", P8_SPR_HID5, ( P8_SPR_HID5 >>5 | ( P8_SPR_HID5 &0x1f)<<5 ) }, - { "P8_MSR_MSR", P8_MSR_MSR, ( P8_MSR_MSR ) }, + { "P8_CORE_XTRA8", P8_CORE_XTRA8,( P8_CORE_XTRA8 ) }, + { "P8_CORE_XTRA9", P8_CORE_XTRA9,( P8_CORE_XTRA9 ) }, // ...thread regs { "P8_SPR_HSPRG0", P8_SPR_HSPRG0,( P8_SPR_HSPRG0>>5 | ( P8_SPR_HSPRG0&0x1f)<<5 ) }, { "P8_SPR_LPCR", P8_SPR_LPCR, ( P8_SPR_LPCR >>5 | ( P8_SPR_LPCR &0x1f)<<5 ) }, + { "P8_MSR_MSR", P8_MSR_MSR, ( P8_MSR_MSR ) }, + { "P8_THRD_XTRA3", P8_THRD_XTRA3,( P8_THRD_XTRA3 ) }, + { "P8_THRD_XTRA4", P8_THRD_XTRA4,( P8_THRD_XTRA4 ) }, }; const int SLW_SPR_REGS_SIZE = sizeof(SLW_SPR_REGS)/sizeof(SLW_SPR_REGS[0]); diff --git a/src/usr/hwpf/hwp/dram_training/memory_errors.xml b/src/usr/hwpf/hwp/dram_training/memory_errors.xml index b12665f62..cf0704487 100644 --- a/src/usr/hwpf/hwp/dram_training/memory_errors.xml +++ b/src/usr/hwpf/hwp/dram_training/memory_errors.xml @@ -21,6 +21,7 @@ <!-- --> <!-- IBM_PROLOG_END_TAG --> <hwpErrors> +<!-- $Id: memory_errors.xml,v 1.39 2013/05/20 16:51:14 gollub Exp $ --> <!-- EDIT THIS FILE DIRECTLY. THE ODS FILE METHOD IS NO LONGER VALID --> <!-- *********************************************************************** --> @@ -211,6 +212,24 @@ </hwpError> <hwpError> + <rc>RC_MSS_SETUP_BARS_MULTIPLE_GROUP_ERR</rc> + <description>MCS is listed as a member in multiple groups.</description> + <ffdc>MCS_POS</ffdc> + <ffdc>GROUP_INDEX_A</ffdc> + <ffdc>GROUP_INDEX_B</ffdc> + </hwpError> + + <hwpError> + <rc>RC_MSS_SETUP_BARS_NM_ALT_BAR_ERR</rc> + <description>Invalid non-mirrored alternate BAR configuration.</description> + </hwpError> + + <hwpError> + <rc>RC_MSS_SETUP_BARS_M_ALT_BAR_ERR</rc> + <description>Invalid mirrored alternate BAR configuration.</description> + </hwpError> + + <hwpError> <rc>RC_MSS_MAINT_START_NOT_RESET</rc> <description>MBMCCQ[0]: maint_cmd_start not reset by hw.</description> <!-- FFDC: Capture register we are checking --> @@ -223,7 +242,7 @@ <callout><target>MBA</target><priority>HIGH</priority></callout> <!-- Deconfigure MBA --> <deconfigure><target>MBA</target></deconfigure> - <!-- Create GARD record for MASTER_CHIP --> + <!-- Create GARD record for MBA --> <gard><target>MBA</target></gard> </hwpError> @@ -240,7 +259,7 @@ <callout><target>MBA</target><priority>HIGH</priority></callout> <!-- Deconfigure MBA --> <deconfigure><target>MBA</target></deconfigure> - <!-- Create GARD record for MASTER_CHIP --> + <!-- Create GARD record for MBA --> <gard><target>MBA</target></gard> </hwpError> @@ -258,7 +277,7 @@ <callout><target>MBA</target><priority>LOW</priority></callout> <!-- Deconfigure MBA --> <deconfigure><target>MBA</target></deconfigure> - <!-- Create GARD record for MASTER_CHIP --> + <!-- Create GARD record for MBA --> <gard><target>MBA</target></gard> </hwpError> @@ -357,7 +376,7 @@ <callout><target>MBA</target><priority>LOW</priority></callout> <!-- Deconfigure MBA --> <deconfigure><target>MBA</target></deconfigure> - <!-- Create GARD record for MASTER_CHIP --> + <!-- Create GARD record for MBA --> <gard><target>MBA</target></gard> </hwpError> @@ -419,8 +438,6 @@ <description>ATTR_MSS_FREQ set to zero so can't calculate scrub rate.</description> <!-- FFDC: MBA target --> <ffdc>MBA</ffdc> - <!-- FFDC: DDR_FREQ --> - <ffdc>DDR_FREQ</ffdc> <!-- FFDC: Capture command type we are trying to run --> <ffdc>CMD_TYPE</ffdc> <!-- TODO: Callout FW HIGH --> @@ -433,6 +450,8 @@ <ffdc>MBA</ffdc> <!-- FFDC: Capture register we are checking --> <ffdc>MBAXCR</ffdc> + <!-- FFDC: DRAM width --> + <ffdc>DRAM_WIDTH</ffdc> <!-- TODO: Callout FW HIGH --> </hwpError> @@ -607,7 +626,7 @@ <callout><target>MBA</target><priority>HIGH</priority></callout> <!-- Deconfigure MBA --> <deconfigure><target>MBA</target></deconfigure> - <!-- Create GARD record for MASTER_CHIP --> + <!-- Create GARD record for MBA --> <gard><target>MBA</target></gard> </hwpError> @@ -655,7 +674,7 @@ <hwpError> <rc>RC_MSS_MAINT_PUT_STEER_MUX_BAD_INPUT</rc> - <description>i_rank or i_muxType or i_steerType or i_symbol input to mss_get_steer_mux out of range</description> + <description>i_rank or i_muxType or i_steerType or i_symbol input to mss_put_steer_mux out of range</description> <!-- FFDC: MBA target --> <ffdc>MBA</ffdc> <!-- FFDC: RANK we are writing steer mux for --> @@ -696,7 +715,7 @@ <callout><target>MBA</target><priority>HIGH</priority></callout> <!-- Deconfigure MBA --> <deconfigure><target>MBA</target></deconfigure> - <!-- Create GARD record for MASTER_CHIP --> + <!-- Create GARD record for MBA --> <gard><target>MBA</target></gard> </hwpError> @@ -872,11 +891,13 @@ <hwpError> <rc>RC_MSS_NON_CHECKER_BOARD_MODE_GROUPING_NOT_POSSIBLE</rc> <description>FABRIC IS IN NON-CHECKER BOARD MODE. SET ATTRIBUTE 'ATTR_MSS_INTERLEAVE_ENABLE' TO SUPPORT '2MCS/GROUP, 4MCS/GROUP AND 8MCS/GROUP'. OR ENABLE CHECKER BOARD, TO SUPPORT '1MCS/GROUP'. MRW NEEDS TO BE UPDATED. </description> + <collectFfdc>hwpCollectMemGrouping, PROC_CHIP</collectFfdc> </hwpError> <hwpError> <rc>RC_MSS_CHECKER_BOARD_MODE_GROUPING_NOT_POSSIBLE</rc> <description>FABRIC IS IN CHECKER BOARD MODE BUT IT DOES NOT SUPPORT 1MCS/GROUP. SET ATTRIBUTE 'ATTR_MSS_INTERLEAVE_ENABLE' TO SUPPORT '1MCS/GROUP'. OR DISABLE CHECKER BOARD, TO SUPPORT '2MCS/GROUP, 4MCS/GROUP AND 8MCS/GROUP'. MRW NEEDS TO BE UPDATED. </description> + <collectFfdc>hwpCollectMemGrouping, PROC_CHIP</collectFfdc> </hwpError> <hwpError> @@ -887,6 +908,27 @@ </hwpError> <hwpError> + <rc>RC_ERROR_MSS_GROUPING_ATTRS</rc> + <description>MEM grouping Attributes collection and printing function</description> + <ffdc>_ATTR_PROC_POS</ffdc> + <ffdc>_ATTR_CEN_POS</ffdc> + <ffdc>_ATTR_CHIP_UNIT_POS_MBA0</ffdc> + <ffdc>_ATTR_CHIP_UNIT_POS_MBA1</ffdc> + <ffdc>_ATTR_EFF_DIMM_SIZE0</ffdc> + <ffdc>_ATTR_EFF_DIMM_SIZE1</ffdc> + <ffdc>_ATTR_MSS_INTERLEAVE_ENABLE</ffdc> + <ffdc>_ATTR_ALL_MCS_IN_INTERLEAVING_GROUP</ffdc> + <ffdc>_ATTR_PROC_MEM_BASE</ffdc> + <ffdc>_ATTR_PROC_MIRROR_BASE</ffdc> + <ffdc>_ATTR_MSS_MEM_MC_IN_GROUP</ffdc> + <ffdc>_ATTR_PROC_MEM_BASES</ffdc> + <ffdc>_ATTR_PROC_MEM_SIZES</ffdc> + <ffdc>_ATTR_MSS_MCS_GROUP_32</ffdc> + <ffdc>_ATTR_PROC_MIRROR_BASES</ffdc> + <ffdc>_ATTR_PROC_MIRROR_SIZES</ffdc> +</hwpError> + +<hwpError> <rc>RC_MSS_UNABLE_TO_GROUP_SUMMARY</rc> <description>MCS COULD NOT BE GROUPED. SEE PREVIOUS ERROR MESSAGES FOR WHICH MCS HAS BEEN RC_MSS_UNABLE_TO_GROUP_MCS</description> </hwpError> @@ -894,7 +936,153 @@ <hwpError> <rc>RC_MSS_BASE_ADDRESS_OVERLAPS_MIRROR_ADDRESS</rc> <description>MIRROR BASE ADDRESS OVERLAPS WITH MEMORY BASE ADDRESS.</description> + <collectFfdc>hwpCollectMemGrouping, PROC_CHIP</collectFfdc> </hwpError> +<hwpError> + <rc>RC_ERROR_MSS_FIRS</rc> + <description>MEM FIR REGISTERS</description> + +<!-- DMI_FIR --> + <collectRegisterFfdc> + <id>REG_FFDC_DMI_FIR_REGS</id> + <target>CENCHIP</target> + </collectRegisterFfdc> +<!-- MBIFIRQ --> + <collectRegisterFfdc> + <id>REG_FFDC_MBI_FIR_REGS</id> + <target>CENCHIP</target> + </collectRegisterFfdc> + +<!-- MBSFIRQ --> + <collectRegisterFfdc> + <id>REG_FFDC_MBS_FIR_REGS</id> + <target>CENCHIP</target> + </collectRegisterFfdc> + +<!-- SCAC_LFIR --> + <collectRegisterFfdc> + <id>REG_FFDC_SCAC_FIR_REGS</id> + <target>CENCHIP</target> + </collectRegisterFfdc> + +</hwpError> + +<hwpError> + <rc>RC_ERROR_MBA_FIRS</rc> + <description>MEM MBA FIR REGISTERS</description> + +<!-- MBA01_MBACALFIR --> +<!-- MBA01_MBAFIRQ --> +<!-- MBA01_MBSPAQ --> + <collectRegisterFfdc> + <id>REG_FFDC_MBA_FIR_REGS</id> + <target>CENCHIP_MBA</target> + </collectRegisterFfdc> + +<!-- PHY01_DDRPHY_FIR_REG --> + <collectRegisterFfdc> + <id>REG_FFDC_DDR_PHY_FIR_REGS</id> + <target>CENCHIP_MBA</target> + </collectRegisterFfdc> + + + +</hwpError> + + +<registerFfdc> + <id>REG_FFDC_MBA_FIR_REGS</id> + + <!-- MBA Special Attention Registers --> + <scomRegister>MBA01_MBSPAQ_0x03010611</scomRegister> + <scomRegister>MBA01_MBSPAMSKQ_0x03010614</scomRegister> + + <!-- MBA Fault Isolation Registers --> + <scomRegister>MBA01_MBAFIRQ_0x03010600</scomRegister> + <scomRegister>MBA01_MBAFIRMASK_0x03010603</scomRegister> + <scomRegister>MBA01_MBAFIRACT0_0x03010606</scomRegister> + <scomRegister>MBA01_MBAFIRACT1_0x03010607</scomRegister> + <!-- MBA Error Report Register --> + <scomRegister>MBA01_MBA_MCBERRPTQ_0x030106e7</scomRegister> + + <!-- MBA CAL FIR Registers --> + <scomRegister>MBA01_MBACALFIR_0x03010400</scomRegister> + <scomRegister>MBA01_MBACALFIR_MASK_0x03010403</scomRegister> + <scomRegister>MBA01_MBACALFIR_ACTION0_0x03010406</scomRegister> + <scomRegister>MBA01_MBACALFIR_ACTION1_0x03010407</scomRegister> + <!-- MBA Error report register --> + <scomRegister>MBA01_MBA_ERR_REPORTQ_0x0301041A</scomRegister> +</registerFfdc> + +<registerFfdc> + <id>REG_FFDC_MBI_FIR_REGS</id> + <scomRegister>CEN_MBIFIRQ_0x02010800</scomRegister> + <scomRegister>CEN_MBIFIRMASK_0x02010803</scomRegister> + <scomRegister>CEN_MBIFIRACT0_0x02010806</scomRegister> + <scomRegister>CEN_MBIFIRACT1_0x02010807</scomRegister> +</registerFfdc> + +<registerFfdc> + <id>REG_FFDC_MBS_FIR_REGS</id> + <scomRegister>MBS_FIR_REG_0x02011400</scomRegister> + <scomRegister>MBS_FIR_MASK_REG_0x02011403</scomRegister> + <scomRegister>MBS_FIR_ACTION0_REG_0x02011406</scomRegister> + <scomRegister>MBS_FIR_ACTION1_REG_0x02011407</scomRegister> + <scomRegister>MBS_FIR_WOF_REG_0x02011408</scomRegister> + + <scomRegister>MBS_ECC0_MBECCFIR_0x02011440</scomRegister> + <scomRegister>MBS_ECC0_MBECCFIR_MASK_0x02011443</scomRegister> + <scomRegister>MBS_ECC0_MBECCFIR_ACTION0_0x02011446</scomRegister> + <scomRegister>MBS_ECC0_MBECCFIR_ACTION1_0x02011447</scomRegister> + <scomRegister>MBS_ECC0_MBECCFIR_WOF_0x02011448</scomRegister> + + <scomRegister>MBS_ECC1_MBECCFIR_0x02011480</scomRegister> + <scomRegister>MBS_ECC1_MBECCFIR_MASK_0x02011483</scomRegister> + <scomRegister>MBS_ECC1_MBECCFIR_ACTION0_0x02011486</scomRegister> + <scomRegister>MBS_ECC1_MBECCFIR_ACTION1_0x02011487</scomRegister> + <scomRegister>MBS_ECC1_MBECCFIR_WOF_0x02011488</scomRegister> + + <scomRegister>CEN_MBS01_MBSFIRQ_0x02011600</scomRegister> + <scomRegister>CEN_MBS01_MBSFIRMASK_0x02011603</scomRegister> + <scomRegister>CEN_MBS01_MBSFIRACT0_0x02011606</scomRegister> + <scomRegister>CEN_MBS01_MBSFIRACT1_0x02011607</scomRegister> + <scomRegister>CEN_MBS01_MBSFIRWOF_0x02011608</scomRegister> + + <scomRegister>CEN_MBS23_MBSFIRQ_0x02011700</scomRegister> + <scomRegister>CEN_MBS23_MBSFIRMASK_0x02011703</scomRegister> + <scomRegister>CEN_MBS23_MBSFIRACT0_0x02011706</scomRegister> + <scomRegister>CEN_MBS23_MBSFIRACT1_0x02011707</scomRegister> + <scomRegister>CEN_MBS23_MBSFIRWOF_0x02011708</scomRegister> +</registerFfdc> + +<registerFfdc> + <id>REG_FFDC_SCAC_FIR_REGS</id> + <scomRegister>CEN_SCAC_LFIR_0x020115c0</scomRegister> + <scomRegister>CEN_SCAC_FIRMASK_0x020115c3</scomRegister> + <scomRegister>CEN_SCAC_FIRACTION0_0x020115c6</scomRegister> + <scomRegister>CEN_SCAC_FIRACTION1_0x020115c7</scomRegister> + <scomRegister>CEN_SCAC_FIRWOF_0x020115c8</scomRegister> +</registerFfdc> + +<registerFfdc> + <id>REG_FFDC_DDR_PHY_FIR_REGS</id> + <scomRegister>PHY01_DDRPHY_FIR_REG_0x800200900301143fULL</scomRegister> + <scomRegister>PHY01_DDRPHY_FIR_MASK_REG_0x800200930301143fULL</scomRegister> + <scomRegister>PHY01_DDRPHY_FIR_ACTION0_REG_0x800200960301143fULL</scomRegister> + <scomRegister>PHY01_DDRPHY_FIR_ACTION1_REG_0x800200970301143fULL</scomRegister> + <scomRegister>PHY01_DDRPHY_FIR_WOF_REG_0x800200980301143fULL</scomRegister> +</registerFfdc> + + +<registerFfdc> + <id>REG_FFDC_DMI_FIR_REGS</id> + <scomRegister>CEN_DMIFIR_0x02010400</scomRegister> + <scomRegister>CEN_DMIFIR_MASK_0x02010403</scomRegister> + <scomRegister>CEN_DMIFIR_ACT0_0x02010406</scomRegister> + <scomRegister>CEN_DMIFIR_ACT0_0x02010407</scomRegister> + <scomRegister>CEN_DMIFIR_ACT0_0x02010408</scomRegister> +</registerFfdc> + <!-- EDIT THIS FILE DIRECTLY. THE ODS FILE METHOD IS NO LONGER VALID --> </hwpErrors> diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C index 2d59480c4..f36b459b8 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_mcbist_address.C,v 1.9 2013/04/04 20:56:10 bellows Exp $ +// $Id: mss_mcbist_address.C,v 1.11 2013/05/16 22:00:24 sasethur Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998, 2013 // *! All Rights Reserved -- Property of IBM @@ -38,9 +38,12 @@ //------------------------------------------------------------------------------- // Version:|Author: | Date: | Comment: // --------|--------|---------|-------------------------------------------------- +// 1.11 |preeragh|17-May-13| Fixed FW Review Comments +// 1.10 |preeragh|30-Apr-13| Fixed FW Review Comment // 1.9 |bellows |04-Apr-13| Changed program to be Hostboot compliant // 1.2 |bellows |03-Apr-13| Added Id and cleaned up a warning msg. // 1.1 | |xx-Apr-13| Copied from original which is now known as mss_mcbist_address_default/_lab.C +// 1.2 Preetham | xx - Apr -13| Fixed rc_num call //------------------------------------------------------------------------------ #include "mss_mcbist_address.H" @@ -48,15 +51,17 @@ extern "C" { using namespace fapi; -#define MAX_STRING_LEN 80 +#define MAX_ADDR_BITS 37 +#define MAX_VALUE_TWO 2 + #define DELIMITERS "," fapi::ReturnCode address_generation(const fapi:: Target & i_target_mba,uint8_t i_port,mcbist_addr_mode i_addr_type,interleave_type i_add_inter_type,uint8_t i_rank,uint64_t &io_start_address, uint64_t &io_end_address) { fapi::ReturnCode rc; -uint8_t l_num_ranks_per_dimm[2][2]; -uint8_t l_num_master_ranks[2][2]; +uint8_t l_num_ranks_per_dimm[MAX_VALUE_TWO][MAX_VALUE_TWO]; +uint8_t l_num_master_ranks[MAX_VALUE_TWO][MAX_VALUE_TWO]; uint8_t l_dram_gen=0; uint8_t l_dram_banks=0; uint8_t l_dram_rows=0; @@ -66,7 +71,7 @@ uint8_t l_dram_width=0; uint8_t l_addr_inter=0; uint8_t l_num_ranks_p0_dim0,l_num_ranks_p0_dim1,l_num_ranks_p1_dim0,l_num_ranks_p1_dim1; uint8_t mr3_valid,mr2_valid,mr1_valid; -uint32_t __attribute__((unused)) rc_num; // SW198827 +uint32_t rc_num; char S0[] = "b"; //char l_my_addr[MAX_STRING_LEN]; @@ -76,8 +81,10 @@ char S0[] = "b"; ecmdDataBufferBase l_default_add_buffer(64); ecmdDataBufferBase l_new_add_buffer(64); - rc_num = l_default_add_buffer.flushTo0(); - rc_num = l_new_add_buffer.flushTo0(); +rc_num = l_default_add_buffer.flushTo0(); +if (rc_num){FAPI_ERR( "Error in function addr_gen:");rc.setEcmdError(rc_num);return rc;} +rc_num = l_new_add_buffer.flushTo0(); +if (rc_num){FAPI_ERR( "Error in function addr_gen:");rc.setEcmdError(rc_num);return rc;} rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm); if(rc) return rc; @@ -101,7 +108,7 @@ FAPI_INF("ATTR_EFF_NUM_RANKS_PER_DIMM is %d ",l_num_ranks_per_dimm[1][1]); FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p0_dim0 is %d ",l_num_master_ranks[0][0]); FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p0_dim1 is %d ",l_num_master_ranks[0][1]); FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p1_dim0 is %d ",l_num_master_ranks[1][0]); -FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM is l_num_master_p1_dim1 %d ",l_num_master_ranks[1][1]); +FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p1_dim1 is %d ",l_num_master_ranks[1][1]); //------------------------------------------------------------------------------- @@ -181,14 +188,14 @@ return rc; fapi::ReturnCode parse_addr(const fapi:: Target & i_target_mba, char addr_string[],uint8_t mr3_valid,uint8_t mr2_valid,uint8_t mr1_valid,uint8_t l_dram_rows,uint8_t l_dram_cols,uint8_t l_addr_inter) { fapi::ReturnCode rc; -uint8_t i=37; +uint8_t i=MAX_ADDR_BITS; uint8_t l_slave_rank = 0; uint8_t l_value; uint32_t l_value32 = 0; uint32_t l_sbit,rc_num; uint32_t l_start=0; -uint32_t l_len = 6; +uint32_t l_len = 0; uint64_t l_readscom_value = 0; uint64_t l_end = 0; uint64_t l_start_addr = 0; @@ -196,7 +203,7 @@ uint8_t l_value_zero = 0; uint8_t l_user_end_addr = 0; ecmdDataBufferBase l_data_buffer_64(64); ecmdDataBufferBase l_data_buffer_rd64(64); -uint8_t l_attr_addr_mode = 3; +uint8_t l_attr_addr_mode = 3; //default Value - FULL Address Mode uint8_t l_num_cols = 0; uint8_t l_num_rows = 0; @@ -222,17 +229,18 @@ if(l_num_rows == 0 ) rc_num = l_data_buffer_64.flushTo0(); - l_sbit = 0;l_value =i; - rc = fapiGetScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; - rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} - rc = fapiPutScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; - i--; + l_sbit = 0;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + i--; l_sbit = 54;l_value =i; rc = fapiGetScom(i_target_mba,0x030106c8,l_data_buffer_64); rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6); rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; i--; + //FAPI_INF("Inside strcmp ba2"); l_sbit = 48;l_value =i; rc = fapiGetScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; @@ -939,7 +947,7 @@ rc = fapiPutScom(i_target_mba,0x030106d3,l_data_buffer_rd64); if(rc) return rc; else { -l_attr_addr_mode = 3; +l_attr_addr_mode = 3; //Default it for FW with Full Address Range if(l_attr_addr_mode == 0) { diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C index 54db45502..f7de7db2a 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_mcbist_common.C,v 1.36 2013/04/09 09:02:14 ppcaelab Exp $ +// $Id: mss_mcbist_common.C,v 1.38 2013/04/30 08:53:46 ppcaelab Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -38,6 +38,8 @@ //------------------------------------------------------------------------------ // Version:|Author: | Date: | Comment: // --------|--------|--------|-------------------------------------------------- +// 1.38 |aditya |05/30/13|Minor fix for firmware +// 1.37 |aditya |04/22/13|Minor Fix // 1.36 |aditya |04/09/13|Updated cfg_byte_mask and setup_mcbist functions // 1.35 |aditya |03/18/13|Updated cfg_byte_mask and error map functions // 1.34 |aditya |03/15/13|Added ISDIMM error map @@ -146,6 +148,7 @@ fapi::ReturnCode setup_mcbist(const fapi::Target & i_target_mba, uint8_t i_port uint8_t l_index = 0; uint8_t l_index1 = 0; uint8_t l_flag = 0; + uint8_t l_new_addr = 1; uint64_t scom_array[24] = {0x03010440,0x03010441,0x03010442,0x03010443,0x03010444,0x03010445,0x03010446,0x03010447,0x0201145E,0x0201145F,0x02011460,0x02011461,0x02011462,0x02011463,0x02011464,0x02011465,0x0201149E,0x0201149F,0x020114A0,0x020114A1,0x020114A2,0x020114A3,0x020114A4,0x020114A5}; @@ -266,11 +269,13 @@ fapi::ReturnCode setup_mcbist(const fapi::Target & i_target_mba, uint8_t i_port //preet //FAPI_INF("DEBUG-----Print----Address Gen "); - //if (new_address_map == 1) - //{ + rc = FAPI_ATTR_GET(ATTR_MCBIST_ADDR_MODES, &i_target_mba, l_new_addr); if(rc) return rc; + + if (l_new_addr != 0) + { rc = address_generation(i_target_mba,i_port,SF,BANK_RANK,i_rank,io_start_address,io_end_address); if(rc) {FAPI_INF("BAD - RC ADDR Generation\n");return rc;} - //} + } @@ -1094,7 +1099,7 @@ fapi::ReturnCode cfg_byte_mask(const fapi::Target & i_target_mba,uint8_t i_rank l_max_1 = num_ranks_per_dimm[1][0]+num_ranks_per_dimm[1][1]; -//SW198827 uint32_t __attribute__((unused)) rc_num = 0; + // uint32_t rc_num = 0; rc_num = l_data_buffer3_64.flushTo0();if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} diff --git a/src/usr/hwpf/hwp/initfiles/mba_def.initfile b/src/usr/hwpf/hwp/initfiles/mba_def.initfile index 195df9e3c..f69cc6400 100644 --- a/src/usr/hwpf/hwp/initfiles/mba_def.initfile +++ b/src/usr/hwpf/hwp/initfiles/mba_def.initfile @@ -1,9 +1,14 @@ -#-- $Id: mba_def.initfile,v 1.39 2013/04/17 16:55:32 yctschan Exp $ +#-- $Id: mba_def.initfile,v 1.44 2013/05/06 15:28:35 yctschan Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.44|tschang | 5/06/13|added 2n_mode to timing parms equations +#-- 1.43|tschang | 5/01/13|def_refresh_interval optimized to avoid divide by 0 condition +#-- 1.42|tschang | 5/01/13|cfg_min_domain_reduction disabled as requested by performance team +#-- 1.41|tschang | 4/24/13|fixed typos for a couple type cfgs +#-- 1.40|tschang | 4/24/13|fixed 1d type cfg #-- 1.39|tschang | 4/17/13|commented out maxall_min0 power controls until decision has been made for default value #-- 1.38|tschang | 4/08/13|set cfg_min_domain_reduction_enable to 1 and maxall_min0 power controls #-- 1.37|tschang | 4/04/13|ACT signal in CCS idle pattern set to 1 for DDR4 and 0 for non DDR4 @@ -276,34 +281,30 @@ define def_1b_2socket = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_T #define def_1b_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 2 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 2 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 0)); # same as type1A 2 socket RDIMM cfg for DDR3/4 ## 1C 1 and 2 sockets not supported -#define def_1c_1socket = 0; -#define def_1c_2socket = 0; -define def_1c_1socket = (CENTAUR.ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_1c_2socket = (CENTAUR.ATTR_MSS_FREQ == 1400) ; # will evaluate to false +define def_1c_1socket_nodt = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 3 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 3 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || def_1d_1socket); +define def_1c_2socket_nodt = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 3 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 3 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || def_1d_2socket); +define def_1c_1socket_odt = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 3 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 3 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)); +define def_1c_2socket_odt = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 3 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 3 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)); define def_1c_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 3 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 3 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 0)); # same as type1B 2 socket RDIMM cfg for DDR3/4 ## Current they is no 1D IBM type in the attribute -#define def_1d_1socket = 0; -#define def_1d_2socket = 0; -#define def_1d_1socket = (CENTAUR.ATTR_MSS_FREQ == 1400) ; # will evaluate to false -#define def_1d_2socket = (CENTAUR.ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_1d_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 4 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -define def_1d_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 4 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)); +define def_1d_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 4 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)); +define def_1d_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 4 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)); ## note the CDIMMs 2A-2C CDIMMs are wired just like the single slot ISDIMMs -define def_2a_1socket = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2a_cdimm)); -define def_2a_2socket = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_2c_cdimm) || (def_3a_cdimm)); -define def_2a_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 1 socket cfg -define def_2a_1socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2a_ddr4_cdimm)); -define def_2a_2socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_3a_ddr4_cdimm)); -define def_2a_ddr4_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 1 socket DDR4 cfg - -define def_2b_1socket = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2b_cdimm)); -define def_2b_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)); -define def_2b_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 1 socket cfg -define def_2b_1socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2b_ddr4_cdimm)); -define def_2b_2socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_3b_ddr4_cdimm)); -define def_2b_ddr4_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 1 socket DDR4 cfg +define def_2a_1socket = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2a_cdimm)); +define def_2a_2socket = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_2c_cdimm) || (def_3a_cdimm)); +define def_2a_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 1 socket cfg +define def_2a_1socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2a_ddr4_cdimm)); +define def_2a_2socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_3a_ddr4_cdimm)); +define def_2a_ddr4_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 1 socket DDR4 cfg + +define def_2b_1socket = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2b_cdimm)); +define def_2b_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)); +define def_2b_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 1 socket cfg +define def_2b_1socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2b_ddr4_cdimm)); +define def_2b_2socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_3b_ddr4_cdimm)); +define def_2b_ddr4_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 1 socket DDR4 cfg # centuar spec only has DDR4 for 2C cfg define def_2c_1socket = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2a_cdimm)); @@ -365,7 +366,7 @@ define def_7c_2socket_ddr4 = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TY define def_mtype_1a = ((def_1a_1socket )||(def_1a_2socket )); #||(def_1b_cdimm)); define def_mtype_1b = ((def_1b_1socket )||(def_1b_2socket )||(def_1c_cdimm)); -define def_mtype_1c = ((def_1c_1socket )||(def_1c_2socket)); +define def_mtype_1c = ((def_1c_1socket_nodt )||(def_1c_2socket_nodt)); define def_mtype_2a = ((def_2a_1socket )||(def_2a_2socket )||(def_2a_1socket_ddr4)||(def_2a_2socket_ddr4)||(def_3a_cdimm )||(def_3a_ddr4_cdimm)); define def_mtype_2b = ((def_2b_1socket )||(def_2b_2socket )||(def_2b_1socket_ddr4)||(def_2b_2socket_ddr4)||(def_3b_cdimm )||(def_3b_ddr4_cdimm)); define def_mtype_2c = ((def_2c_1socket )||(def_2c_2socket )||(def_2c_1socket_ddr4)||(def_2c_2socket_ddr4)||(def_3c_cdimm )||(def_3c_ddr4_cdimm)); @@ -398,22 +399,20 @@ define def_prim_map_a = ((def_mtype_1a )||(def_mtype_1b )||(def_mtype_1c #define def_prim_map_b not used define def_prim_map_c = (def_mtype_5d); -#define def_type1 = ((def_1a_1socket )||( def_1a_2socket )||( def_1b_1socket )||( def_1b_2socket )||( def_1c_1socket )||( def_1c_2socket)); +#define def_type1 = ((def_1a_1socket )||( def_1a_2socket )||( def_1b_1socket )||( def_1b_2socket )||( def_1c_1socket_nodt )||( def_1c_2socket_nodt)); #define def_type2 = ((def_2a_1socket )||( def_2a_2socket )||( def_2b_1socket )||( def_2b_2socket )||( def_2c_1socket )||( def_2c_2socket)); #define def_type3 = ((def_3a_1socket )||( def_3a_2socket )||( def_3b_1socket )||( def_3b_2socket )||( def_3c_1socket )||( def_3c_2socket)); #define def_type4 = ((def_4a_1socket )||( def_4a_2socket )||( def_4b_1socket )||( def_4b_2socket )||( def_4c_1socket )||( def_4c_2socket)); #define def_subtypea = ((def_1a_1socket )||( def_1a_2socket )||( def_2a_1socket )||( def_2a_2socket )||( def_3a_1socket )||( def_3a_2socket )||( def_4a_1socket )||( def_4a_2socket)); #define def_subtypeb = ((def_1b_1socket )||( def_1b_2socket )||( def_2b_1socket )||( def_2b_2socket )||( def_3b_1socket )||( def_3b_2socket )||( def_4b_1socket )||( def_4b_2socket)); -#define def_subtypec = ((def_1c_1socket )||( def_1c_2socket )||( def_2c_1socket )||( def_2c_2socket )||( def_3c_1socket )||( def_3c_2socket )||( def_4c_1socket )||( def_4c_2socket)); +#define def_subtypec = ((def_1c_1socket_nodt )||( def_1c_2socket_nodt )||( def_2c_1socket )||( def_2c_2socket )||( def_3c_1socket )||( def_3c_2socket )||( def_4c_1socket )||( def_4c_2socket)); -#define def_1socket = ((def_1a_1socket )||( def_1b_1socket )||( def_1c_1socket )||( def_2a_1socket )||( def_2b_1socket )||( def_2c_1socket )||( def_3a_1socket )||( def_3b_1socket )||( def_3c_1socket )||( def_4a_1socket )||( def_4b_1socket )||( def_4c_1socket)); -#define def_2socket = ((def_1a_2socket )||( def_1b_2socket )||( def_1c_2socket )||( def_2a_2socket )||( def_2b_2socket )||( def_2c_2socket )||( def_3a_2socket )||( def_3b_2socket )||( def_3c_2socket )||( def_4a_2socket )||( def_4b_2socket )||( def_4c_2socket)); +#define def_1socket = ((def_1a_1socket )||( def_1b_1socket )||( def_1c_1socket_nodt )||( def_2a_1socket )||( def_2b_1socket )||( def_2c_1socket )||( def_3a_1socket )||( def_3b_1socket )||( def_3c_1socket )||( def_4a_1socket )||( def_4b_1socket )||( def_4c_1socket)); +#define def_2socket = ((def_1a_2socket )||( def_1b_2socket )||( def_1c_2socket_nodt )||( def_2a_2socket )||( def_2b_2socket )||( def_2c_2socket )||( def_3a_2socket )||( def_3b_2socket )||( def_3c_2socket )||( def_4a_2socket )||( def_4b_2socket )||( def_4c_2socket)); -#define def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C = ((def_1a_1socket )||(def_1a_2socket )||(def_1b_cdimm )||(def_1b_1socket )||(def_1b_2socket )||(def_1c_cdimm )||(def_1c_1socket )||(def_1c_2socket )||(def_5b_1socket )||(def_5b_2socket )||(def_5c_1socket )||(def_5c_2socket)); -# removed def_1b_cdimm -define def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C = ((def_1a_1socket )||(def_1a_2socket )||(def_1b_1socket )||(def_1b_2socket )||(def_1c_cdimm )||(def_1c_1socket )||(def_1c_2socket )||(def_5b_1socket )||(def_5b_2socket )||(def_5c_1socket )||(def_5c_2socket)); +define def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C = ((def_1a_1socket )||(def_1a_2socket )||(def_1b_1socket )||(def_1b_2socket )||(def_1c_cdimm )||(def_1c_1socket_nodt )||(def_1c_2socket_nodt )||(def_5b_1socket )||(def_5b_2socket )||(def_5c_1socket )||(def_5c_2socket)); define def_IS7a_C4a_C3a = ((def_3a_1socket )||(def_3a_2socket )||(def_4a_cdimm )||(def_7a_1socket )||(def_7a_2socket)); define def_IS3b_IS7b = ((def_3b_1socket )||(def_3b_2socket )||(def_4b_ddr4_cdimm )||(def_7b_1socket )||(def_7b_2socket)); define def_IS7C = ((def_7c_1socket )||(def_7c_2socket)); @@ -484,100 +483,100 @@ define def_2400_8gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( -define def_ddr3_1066_6_6_6 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 6 ) && ( ATTR_EFF_DRAM_TRCD == 6 ) && ( ATTR_EFF_DRAM_TRP == 6 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1066_6_6_6R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 6 ) && ( ATTR_EFF_DRAM_TRCD == 6 ) && ( ATTR_EFF_DRAM_TRP == 6 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr3_1066_6_6_6_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 6 ) && ( ATTR_EFF_DRAM_TRCD == 6 ) && ( ATTR_EFF_DRAM_TRP == 6 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1066_6_6_6_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 6 ) && ( ATTR_EFF_DRAM_TRCD == 6 ) && ( ATTR_EFF_DRAM_TRP == 6 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1066_6_6_6_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 6 ) && ( ATTR_EFF_DRAM_TRCD == 6 ) && ( ATTR_EFF_DRAM_TRP == 6 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr3_1066_6_6_6 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 6 ) && ( ATTR_EFF_DRAM_TRCD == 6 ) && ( ATTR_EFF_DRAM_TRP == 6 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr3_1066_6_6_6R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 6 ) && ( ATTR_EFF_DRAM_TRCD == 6 ) && ( ATTR_EFF_DRAM_TRP == 6 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); +define def_ddr3_1066_6_6_6_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 6 ) && ( ATTR_EFF_DRAM_TRCD == 6 ) && ( ATTR_EFF_DRAM_TRP == 6 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr3_1066_6_6_6_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 6 ) && ( ATTR_EFF_DRAM_TRCD == 6 ) && ( ATTR_EFF_DRAM_TRP == 6 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr3_1066_6_6_6_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 6 ) && ( ATTR_EFF_DRAM_TRCD == 6 ) && ( ATTR_EFF_DRAM_TRP == 6 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr3_1066_6_6_6_group = ((def_ddr3_1066_6_6_6 )||( def_ddr3_1066_6_6_6_2N )||( def_ddr3_1066_6_6_6R )||( def_ddr3_1066_6_6_6_LR )||( def_ddr3_1066_6_6_6_L2)); -define def_ddr3_1066_7_7_7 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 7 ) && ( ATTR_EFF_DRAM_TRCD == 7 ) && ( ATTR_EFF_DRAM_TRP == 7 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1066_7_7_7R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 7 ) && ( ATTR_EFF_DRAM_TRCD == 7 ) && ( ATTR_EFF_DRAM_TRP == 7 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr3_1066_7_7_7_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 7 ) && ( ATTR_EFF_DRAM_TRCD == 7 ) && ( ATTR_EFF_DRAM_TRP == 7 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1066_7_7_7_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 7 ) && ( ATTR_EFF_DRAM_TRCD == 7 ) && ( ATTR_EFF_DRAM_TRP == 7 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1066_7_7_7_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 7 ) && ( ATTR_EFF_DRAM_TRCD == 7 ) && ( ATTR_EFF_DRAM_TRP == 7 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr3_1066_7_7_7 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 7 ) && ( ATTR_EFF_DRAM_TRCD == 7 ) && ( ATTR_EFF_DRAM_TRP == 7 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr3_1066_7_7_7R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 7 ) && ( ATTR_EFF_DRAM_TRCD == 7 ) && ( ATTR_EFF_DRAM_TRP == 7 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); +define def_ddr3_1066_7_7_7_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 7 ) && ( ATTR_EFF_DRAM_TRCD == 7 ) && ( ATTR_EFF_DRAM_TRP == 7 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr3_1066_7_7_7_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 7 ) && ( ATTR_EFF_DRAM_TRCD == 7 ) && ( ATTR_EFF_DRAM_TRP == 7 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr3_1066_7_7_7_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 7 ) && ( ATTR_EFF_DRAM_TRCD == 7 ) && ( ATTR_EFF_DRAM_TRP == 7 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr3_1066_7_7_7_group = ((def_ddr3_1066_7_7_7 )||( def_ddr3_1066_7_7_7_2N )||( def_ddr3_1066_7_7_7R )||( def_ddr3_1066_7_7_7_LR )||( def_ddr3_1066_7_7_7_L2)); -define def_ddr3_1066_8_8_8 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1066_8_8_8R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr3_1066_8_8_8_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1066_8_8_8_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1066_8_8_8_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr3_1066_8_8_8 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr3_1066_8_8_8R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); +define def_ddr3_1066_8_8_8_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr3_1066_8_8_8_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr3_1066_8_8_8_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr3_1066_8_8_8_group = ((def_ddr3_1066_8_8_8 )||( def_ddr3_1066_8_8_8_2N )||( def_ddr3_1066_8_8_8R )||( def_ddr3_1066_8_8_8_LR )||( def_ddr3_1066_8_8_8_L2)); -define def_ddr3_1333_8_8_8 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1333_8_8_8R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr3_1333_8_8_8_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1333_8_8_8_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1333_8_8_8_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1333_9_9_9 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1333_9_9_9R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr3_1333_9_9_9_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1333_9_9_9_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1333_9_9_9_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1600_10_10_10 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1600_10_10_10R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr3_1600_10_10_10_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1600_10_10_10_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1600_10_10_10_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1600_11_11_11 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1600_11_11_11R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr3_1600_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1600_11_11_11_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1600_11_11_11_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1600_9_9_9 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1600_9_9_9R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr3_1600_9_9_9_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1600_9_9_9_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1600_9_9_9_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1866_11_11_11 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1866_11_11_11R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr3_1866_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1866_11_11_11_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1866_11_11_11_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1866_12_12_12 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1866_12_12_12R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr3_1866_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1866_12_12_12_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1866_12_12_12_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr3_1333_8_8_8 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr3_1333_8_8_8R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); +define def_ddr3_1333_8_8_8_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr3_1333_8_8_8_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr3_1333_8_8_8_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr3_1333_9_9_9 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr3_1333_9_9_9R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); +define def_ddr3_1333_9_9_9_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr3_1333_9_9_9_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr3_1333_9_9_9_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr3_1600_10_10_10 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr3_1600_10_10_10R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); +define def_ddr3_1600_10_10_10_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr3_1600_10_10_10_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr3_1600_10_10_10_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr3_1600_11_11_11 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr3_1600_11_11_11R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); +define def_ddr3_1600_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr3_1600_11_11_11_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr3_1600_11_11_11_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr3_1600_9_9_9 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr3_1600_9_9_9R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); +define def_ddr3_1600_9_9_9_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr3_1600_9_9_9_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr3_1600_9_9_9_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr3_1866_11_11_11 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr3_1866_11_11_11R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); +define def_ddr3_1866_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr3_1866_11_11_11_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr3_1866_11_11_11_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr3_1866_12_12_12 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr3_1866_12_12_12R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); +define def_ddr3_1866_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr3_1866_12_12_12_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr3_1866_12_12_12_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); # DDR4 1600 -define def_ddr4_1600_9_9_9 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr4_1600_9_9_9R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr4_1600_9_9_9_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr4_1600_9_9_9_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr4_1600_9_9_9_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr4_1600_10_10_10 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr4_1600_10_10_10R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr4_1600_10_10_10_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr4_1600_10_10_10_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr4_1600_10_10_10_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr4_1600_11_11_11 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr4_1600_11_11_11R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr4_1600_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr4_1600_11_11_11_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr4_1600_11_11_11_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); - -define def_ddr4_1600_12_12_12 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr4_1600_12_12_12R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr4_1600_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr4_1600_12_12_12_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr4_1600_12_12_12_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr4_1600_9_9_9 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr4_1600_9_9_9R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); +define def_ddr4_1600_9_9_9_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr4_1600_9_9_9_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr4_1600_9_9_9_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr4_1600_10_10_10 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr4_1600_10_10_10R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); +define def_ddr4_1600_10_10_10_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr4_1600_10_10_10_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr4_1600_10_10_10_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr4_1600_11_11_11 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr4_1600_11_11_11R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); +define def_ddr4_1600_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr4_1600_11_11_11_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr4_1600_11_11_11_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); + +define def_ddr4_1600_12_12_12 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr4_1600_12_12_12R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); +define def_ddr4_1600_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr4_1600_12_12_12_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr4_1600_12_12_12_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); # DDR4 1866 -define def_ddr4_1866_11_11_11 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr4_1866_11_11_11R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr4_1866_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr4_1866_11_11_11_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr4_1866_11_11_11_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr4_1866_12_12_12 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr4_1866_12_12_12R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr4_1866_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr4_1866_12_12_12_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr4_1866_12_12_12_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); - -define def_ddr4_1866_13_13_13 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr4_1866_13_13_13R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr4_1866_13_13_13_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr4_1866_13_13_13_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr4_1866_13_13_13_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr4_1866_11_11_11 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr4_1866_11_11_11R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); +define def_ddr4_1866_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr4_1866_11_11_11_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr4_1866_11_11_11_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr4_1866_12_12_12 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr4_1866_12_12_12R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); +define def_ddr4_1866_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr4_1866_12_12_12_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr4_1866_12_12_12_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); + +define def_ddr4_1866_13_13_13 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr4_1866_13_13_13R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); +define def_ddr4_1866_13_13_13_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +define def_ddr4_1866_13_13_13_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); +define def_ddr4_1866_13_13_13_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); # DDR4 2133 12 -13 - not supported #define def_ddr4_2133_12_12_12 = 0; @@ -601,16 +600,16 @@ define def_ddr4_2133_13_13_13_2N = (CENTAUR.ATTR_MSS_FREQ == 1400); define def_ddr4_2133_13_13_13_L2 = (CENTAUR.ATTR_MSS_FREQ == 1400); define def_ddr4_2133_13_13_13_LR = (CENTAUR.ATTR_MSS_FREQ == 1400); -#define def_ddr4_2133_12_12_12 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_2133_12_12_12R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -#define def_ddr4_2133_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_2133_12_12_12_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -#define def_ddr4_2133_12_12_12_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -#define def_ddr4_2133_13_13_13 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_2133_13_13_13R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -#define def_ddr4_2133_13_13_13_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_2133_13_13_13_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -#define def_ddr4_2133_13_13_13_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); +#define def_ddr4_2133_12_12_12 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +#define def_ddr4_2133_12_12_12R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); +#define def_ddr4_2133_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +#define def_ddr4_2133_12_12_12_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); +#define def_ddr4_2133_12_12_12_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); +#define def_ddr4_2133_13_13_13 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +#define def_ddr4_2133_13_13_13R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); +#define def_ddr4_2133_13_13_13_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +#define def_ddr4_2133_13_13_13_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); +#define def_ddr4_2133_13_13_13_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); # DDR4 2400 13-14 not supported #define def_ddr4_2400_13_13_13 = 0; @@ -634,33 +633,33 @@ define def_ddr4_2400_14_14_14_2N = (CENTAUR.ATTR_MSS_FREQ == 1400); define def_ddr4_2400_14_14_14_L2 = (CENTAUR.ATTR_MSS_FREQ == 1400); define def_ddr4_2400_14_14_14_LR = (CENTAUR.ATTR_MSS_FREQ == 1400); -#define def_ddr4_2400_13_13_13 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_2400_13_13_13R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -#define def_ddr4_2400_13_13_13_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_2400_13_13_13_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -#define def_ddr4_2400_13_13_13_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -#define def_ddr4_2400_14_14_14 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_2400_14_14_14R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -#define def_ddr4_2400_14_14_14_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_2400_14_14_14_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -#define def_ddr4_2400_14_14_14_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); - -#define def_ddr4_1600_10_10_10 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr3_1600_10_10_10R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -#define def_ddr4_1600_10_10_10_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_1600_11_11_11 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_1600_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_1600_9_9_9 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_1600_9_9_9_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_1866_11_11_11 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_1866_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_1866_12_12_12 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_1866_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_2133_12_12_12 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_2133_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_2133_13_13_13 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_2400_13_13_13 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_2400_14_14_14 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +#define def_ddr4_2400_13_13_13 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +#define def_ddr4_2400_13_13_13R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); +#define def_ddr4_2400_13_13_13_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +#define def_ddr4_2400_13_13_13_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); +#define def_ddr4_2400_13_13_13_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); +#define def_ddr4_2400_14_14_14 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +#define def_ddr4_2400_14_14_14R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); +#define def_ddr4_2400_14_14_14_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +#define def_ddr4_2400_14_14_14_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); +#define def_ddr4_2400_14_14_14_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); + +#define def_ddr4_1600_10_10_10 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +#define def_ddr3_1600_10_10_10R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); +#define def_ddr4_1600_10_10_10_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +#define def_ddr4_1600_11_11_11 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +#define def_ddr4_1600_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +#define def_ddr4_1600_9_9_9 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +#define def_ddr4_1600_9_9_9_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +#define def_ddr4_1866_11_11_11 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +#define def_ddr4_1866_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +#define def_ddr4_1866_12_12_12 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +#define def_ddr4_1866_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +#define def_ddr4_2133_12_12_12 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +#define def_ddr4_2133_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +#define def_ddr4_2133_13_13_13 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +#define def_ddr4_2400_13_13_13 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); +#define def_ddr4_2400_14_14_14 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ( ATTR_EFF_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2)); # new 7,8,9 @@ -952,8 +951,8 @@ define def_odt_mapping_1b1dimm = (def_1b_1socket ||def_3a_1socket define def_odt_mapping_1b2dimm = (def_3c_2socket_ddr4 ||def_1b_2socket ||def_3a_2socket ||def_3a_2socket_ddr4 ||def_3b_2socket); #define def_odt_mapping_1bcdimm = (def_1a_2socket ||def_1b_cdimm ||def_3a_cdimm ||def_3a_ddr4_cdimm ||def_3b_cdimm ||def_3b_ddr4_cdimm ||def_3c_cdimm ||def_3c_ddr4_cdimm); define def_odt_mapping_1bcdimm = (def_1a_2socket ||def_3a_cdimm ||def_3a_ddr4_cdimm ||def_3b_cdimm ||def_3b_ddr4_cdimm ||def_3c_cdimm ||def_3c_ddr4_cdimm); -define def_odt_mapping_1c2dimm = (def_1c_2socket); -define def_odt_mapping_1c1dimm = (def_1c_1socket); +define def_odt_mapping_1c2dimm = (def_1c_2socket_odt); +define def_odt_mapping_1c1dimm = (def_1c_1socket_odt); define def_odt_mapping_1ccdimm = (def_1c_cdimm ||def_4a_cdimm ||def_4a_ddr4_cdimm ||def_4b_ddr4_cdimm ||def_4c_ddr4_cdimm); define def_odt_mapping_1dx82dimm = (def_1d_2socket); define def_odt_mapping_1dx4 = (def_1d_1socket); @@ -2007,10 +2006,6 @@ scom 0x0301040C { 0:6 , 0b0101011 , 1 , (def_mba_tmr1q_cfg_trap43 == 1); # cfg_trap 16 0:6 , 0b0101100 , 1 , (def_mba_tmr1q_cfg_trap44 == 1); # cfg_trap 16 0:6 , 0b0101110 , 1 , (def_mba_tmr1q_cfg_trap46 == 1); # cfg_trap 16 -# 0:6 , 0b0110000 , 1 , (def_mba_tmr1q_cfg_trap48 == 1); # cfg_trap ## 2133 and 2400 DRM not supported 16 -# 0:6 , 0b0110001 , 1 , (def_mba_tmr1q_cfg_trap49 == 1); # cfg_trap ## 2133 and 2400 DRM not supported 16 -# 0:6 , 0b0110100 , 1 , (def_mba_tmr1q_cfg_trap52 == 1); # cfg_trap ## 2133 and 2400 DRM not supported 16 -# 0:6 , 0b0110101 , 1 , (def_mba_tmr1q_cfg_trap53 == 1); # cfg_trap ## 2133 and 2400 DRM not supported 16 7:13 , 0b0011110 , 1 , (def_mba_tmr1q_cfg_twap30 == 1); # cfg_twap 17 7:13 , 0b0100000 , 1 , (def_mba_tmr1q_cfg_twap32 == 1); # cfg_twap 17 7:13 , 0b0100010 , 1 , (def_mba_tmr1q_cfg_twap34 == 1); # cfg_twap 17 @@ -2023,10 +2018,6 @@ scom 0x0301040C { 7:13 , 0b0110001 , 1 , (def_mba_tmr1q_cfg_twap49 == 1); # cfg_twap 17 7:13 , 0b0110011 , 1 , (def_mba_tmr1q_cfg_twap51 == 1); # cfg_twap 17 7:13 , 0b0110101 , 1 , (def_mba_tmr1q_cfg_twap53 == 1); # cfg_twap 17 -# 7:13 , 0b0110110 , 1 , (def_mba_tmr1q_cfg_twap54 == 1); # cfg_twap ## 2133 and 2400 DRM not supported 17 -# 7:13 , 0b0111000 , 1 , (def_mba_tmr1q_cfg_twap56 == 1); # cfg_twap ## 2133 and 2400 DRM not supported 17 -# 7:13 , 0b0111011 , 1 , (def_mba_tmr1q_cfg_twap59 == 1); # cfg_twap ## 2133 and 2400 DRM not supported 17 -# 7:13 , 0b0111101 , 1 , (def_mba_tmr1q_cfg_twap61 == 1); # cfg_twap ## 2133 and 2400 DRM not supported 17 14:19 , 0b010100 , 1 , (def_mba_tmr1q_cfg_tfaw_dly20 == 1); # cfg_tfaw 18 14:19 , 0b010110 , 1 , (def_mba_tmr1q_cfg_tfaw_dly22 == 1); # cfg_tfaw 18 14:19 , 0b010111 , 1 , (def_mba_tmr1q_cfg_tfaw_dly23 == 1); # cfg_tfaw 18 @@ -2109,13 +2100,6 @@ scom 0x0301040A { 36:41 , 0b011011 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly27 == 1); # rdtag_dly 27 36:41 , 0b011100 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly28 == 1); # rdtag_dly 27 36:41 , 0b011101 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly29 == 1); # rdtag_dly 27 -# 36:41 , 0b100100 , 1 , any ; # rdtag_dly 36 temporary fix for testfloor -# 36:41 , 0b011000 , 1 , any ; # rdtag_dly 24 temporary fix for testfloor -# 36:41 , 0b010111 , 1 , any ; # rdtag_dly 23 temporary fix for testfloor -# setting 22 works for 1600 11-11-11 -# 36:41 , 0b010110 , 1 , any ; # rdtag_dly 22 temporary fix for testfloor -# setting 21 failed -# 36:41 , 0b010101 , 1 , any ; # rdtag_dly 21 temporary fix for testfloor 43:48 , 0b000101 , 1 , (def_mba_dsm0q_CFG_RODT_BC4_END_DLY5 == 1); # CFG_RODT_BC4_END_DLY 28 43:48 , 0b000110 , 1 , (def_mba_dsm0q_CFG_RODT_BC4_END_DLY6 == 1); # CFG_RODT_BC4_END_DLY 28 43:48 , 0b000111 , 1 , (def_mba_dsm0q_CFG_RODT_BC4_END_DLY7 == 1); # CFG_RODT_BC4_END_DLY 28 @@ -2125,44 +2109,21 @@ scom 0x0301040A { } ## Refresh Interval Calculuation -define def_num_ranks = ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[0][1] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][1])/2); -define def_refresh_interval = ((ATTR_EFF_DRAM_TRFI/def_num_ranks)/8); +## refresh_interval = ((ATTR_EFF_DRAM_TRFI/(def_num_ranks/2))/8); +define def_num_ranks = (ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[0][1] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][1]); +define def_refresh_interval = ((2*ATTR_EFF_DRAM_TRFI)/(8*def_num_ranks)); # MBAREF0Q mba01 refresh settings # scom 0x03010432 { bits , scom_data , ATTR_FUNCTIONAL, expr; 4:7 , 0b0111 , 1 , any; # MBAREF0Q_refresh priority threshold is 0x7 for all cfgs 30 ?# refresh interval = tREFI(7.8) / # ranks per port / DRAM clk(ns) / 0.008 -# 8:18 , 0b00010110000, 1 , any; # MBAREF0Q_refresh intveral set to 176 decimal 31 ? !!FIXME# reset check interval = tREFI(7.8) / DRAM clk(ns) / 0.008 8:18 , def_refresh_interval, 1 , any; # MBAREF0Q_refresh intveral set to 176 decimal 31 ? !!FIXME# reset check interval = tREFI(7.8) / DRAM clk(ns) / 0.008 19:29 , 0b00011000010, 1 , any; # MBAREF0Q_refresh reset interval set to 194 decimal 32 ? !!FIXME 30:39 , ATTR_EFF_DRAM_TRFC, 1 , any; # MBAREF0Q_cfg_trfc 33 -# 30:39 , 0b0001010110 , 1 , (def_MBAREF0Q_cfg_trfc_dly86 == 1); # MBAREF0Q_cfg_trfc 33 -# 30:39 , 0b0001101011 , 1 , (def_MBAREF0Q_cfg_trfc_dly107 == 1); # MBAREF0Q_cfg_trfc 33 -# 30:39 , 0b0010000000 , 1 , (def_MBAREF0Q_cfg_trfc_dly128 == 1); # MBAREF0Q_cfg_trfc 33 -# 30:39 , 0b0010010110 , 1 , (def_MBAREF0Q_cfg_trfc_dly150 == 1); # MBAREF0Q_cfg_trfc 33 -# 30:39 , 0b0010100000 , 1 , (def_MBAREF0Q_cfg_trfc_dly160 == 1); # MBAREF0Q_cfg_trfc 33 -# 30:39 , 0b0010101011 , 1 , (def_MBAREF0Q_cfg_trfc_dly171 == 1); # MBAREF0Q_cfg_trfc 33 -# 30:39 , 0b0010111011 , 1 , (def_MBAREF0Q_cfg_trfc_dly187 == 1); # MBAREF0Q_cfg_trfc 33 -# 30:39 , 0b0011000000 , 1 , (def_MBAREF0Q_cfg_trfc_dly192 == 1); # MBAREF0Q_cfg_trfc 33 -# 30:39 , 0b0011001000 , 1 , (def_MBAREF0Q_cfg_trfc_dly200 == 1); # MBAREF0Q_cfg_trfc 33 -# 30:39 , 0b0011010000 , 1 , (def_MBAREF0Q_cfg_trfc_dly208 == 1); # MBAREF0Q_cfg_trfc 33 -# 30:39 , 0b0011101010 , 1 , (def_MBAREF0Q_cfg_trfc_dly234 == 1); # MBAREF0Q_cfg_trfc 33 -# 30:39 , 0b0011110000 , 1 , (def_MBAREF0Q_cfg_trfc_dly240 == 1); # MBAREF0Q_cfg_trfc 33 -# 30:39 , 0b0011110011 , 1 , (def_MBAREF0Q_cfg_trfc_dly243 == 1); # MBAREF0Q_cfg_trfc 33 -# 30:39 , 0b0100010110 , 1 , (def_MBAREF0Q_cfg_trfc_dly278 == 1); # MBAREF0Q_cfg_trfc 33 -# 30:39 , 0b0100011000 , 1 , (def_MBAREF0Q_cfg_trfc_dly280 == 1); # MBAREF0Q_cfg_trfc 33 -# 30:39 , 0b0100011001 , 1 , (def_MBAREF0Q_cfg_trfc_dly281 == 1); # MBAREF0Q_cfg_trfc 33 -# 30:39 , 0b0100111000 , 1 , (def_MBAREF0Q_cfg_trfc_dly312 == 1); # MBAREF0Q_cfg_trfc 33 -# 30:39 , 0b0101000111 , 1 , (def_MBAREF0Q_cfg_trfc_dly327 == 1); # MBAREF0Q_cfg_trfc 33 -# 30:39 , 0b0101001000 , 1 , (def_MBAREF0Q_cfg_trfc_dly328 == 1); # MBAREF0Q_cfg_trfc 33 -# 30:39 , 0b0101110110 , 1 , (def_MBAREF0Q_cfg_trfc_dly374 == 1); # MBAREF0Q_cfg_trfc 33 -# 30:39 , 0b0110100100 , 1 , (def_MBAREF0Q_cfg_trfc_dly420 == 1); # MBAREF0Q_cfg_trfc 33 -## 30:39 , 0b0001101011 , 1 , any; # MBAREF0Q_cfg_trfc set to 107 decimal 40:49 , 0b0000100000 , 1 , (def_MBAREF0Q_cfg_refr_tsv_stack_dly32 == 1); # MBAREF0Q_cfg_refr_tsv_stack 33 40:49 , 0b0000110000 , 1 , (def_MBAREF0Q_cfg_refr_tsv_stack_dly48 == 1); # MBAREF0Q_cfg_refr_tsv_stack 33 40:49 , 0b0001000000 , 1 , (def_MBAREF0Q_cfg_refr_tsv_stack_dly64 == 1); # MBAREF0Q_cfg_refr_tsv_stack 33 -# 40:49 , 0b0000011000 , 1 , any; # MBAREF0Q_cfg_refr_tsv_stack is 24 for all cfgs 34 D 50:60 , 0b01100001100, 1 , any; # MBAREF0Q_refresh check intveral set to 780 decimal 35 } @@ -2190,7 +2151,7 @@ scom 0x03010434 { 16:20 , 0b00100 , 1 , (def_MBARPC0Q_cfg_pup_pdn_dly4 == 1); # MBARPC0Q_cfg_pup_pdn 38 16:20 , 0b00101 , 1 , (def_MBARPC0Q_cfg_pup_pdn_dly5 == 1); # MBARPC0Q_cfg_pup_pdn 38 16:20 , 0b00110 , 1 , (def_MBARPC0Q_cfg_pup_pdn_dly6 == 1); # MBARPC0Q_cfg_pup_pdn 38 - 22 , 0b1 , 1 , any; # cfg_min_domain_reduction_enable set to 1 to enable power controls +# 22 , 0b1 , 1 , any; # cfg_min_domain_reduction_enable set to 1 to enable power controls } # MBAPC1Q power control settings reg 1 diff --git a/src/usr/hwpf/hwp/mc_config/makefile b/src/usr/hwpf/hwp/mc_config/makefile index f0a7fc5eb..bd373169e 100644 --- a/src/usr/hwpf/hwp/mc_config/makefile +++ b/src/usr/hwpf/hwp/mc_config/makefile @@ -40,19 +40,20 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_eff_config EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_volt EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_freq -OBJS = mc_config.o \ - mss_volt.o \ - mss_freq.o \ - mss_eff_config.o \ - mss_eff_grouping.o \ - opt_memmap.o \ - mss_eff_config_thermal.o \ - mss_eff_config_termination.o \ - mss_eff_config_rank_group.o \ - mss_eff_config_cke_map.o \ - mss_bulk_pwr_throttles.o \ - mss_throttle_to_power.o \ - mss_eff_config_shmoo.o +OBJS = mc_config.o \ + mss_volt.o \ + mss_freq.o \ + mss_eff_config.o \ + mss_eff_grouping.o \ + opt_memmap.o \ + mss_eff_config_thermal.o \ + mss_eff_config_termination.o \ + mss_eff_config_rank_group.o \ + mss_eff_config_cke_map.o \ + mss_bulk_pwr_throttles.o \ + mss_throttle_to_power.o \ + mss_eff_config_shmoo.o \ + mss_error_support.o ## NOTE: add a new directory onto the vpaths when you add a new HWP ##@ VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/??? diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C index 2bfadd4be..0017cac92 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C @@ -260,7 +260,7 @@ extern "C" { { FAPI_ERR("UNABLE TO GROUP"); FAPI_ERR("FABRIC IS IN NON-CHECKER BOARD MODE. SET ATTRIBUTE 'ATTR_MSS_INTERLEAVE_ENABLE' , TO SUPPORT 2MCS , 4MCS AND 8MCS GROUPING. OR ENABLE CHECKER BOARD. "); -//@thi - hack const fapi::Target & PROC_CHIP = i_target; + const fapi::Target & PROC_CHIP = i_target; FAPI_SET_HWP_ERROR(rc, RC_MSS_NON_CHECKER_BOARD_MODE_GROUPING_NOT_POSSIBLE); return rc; } @@ -289,7 +289,7 @@ extern "C" { { FAPI_ERR("UNABLE TO GROUP"); FAPI_ERR("FABRIC IS IN CHECKER BOARD MODE . SET ATTRIBUTE 'ATTR_MSS_INTERLEAVE_ENABLE' "); -//@thi - hack const fapi::Target & PROC_CHIP = i_target; + const fapi::Target & PROC_CHIP = i_target; FAPI_SET_HWP_ERROR(rc, RC_MSS_CHECKER_BOARD_MODE_GROUPING_NOT_POSSIBLE); return rc; @@ -668,7 +668,7 @@ extern "C" { else { FAPI_ERR("Mirror Base address overlaps with memory base address. "); -//@thi - hack const fapi::Target & PROC_CHIP = i_target; + const fapi::Target & PROC_CHIP = i_target; FAPI_SET_HWP_ERROR(rc, RC_MSS_BASE_ADDRESS_OVERLAPS_MIRROR_ADDRESS); return rc; } diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_error_support.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_error_support.C new file mode 100644 index 000000000..4e11554e7 --- /dev/null +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_error_support.C @@ -0,0 +1,243 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_error_support.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: mss_error_support.C,v 1.1 2013/03/21 19:04:19 bellows Exp $ + +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : mss_error_support.C +// *! DESCRIPTION : common and hwp error collecting programs +// *! OWNER NAME : bellows@us.ibm.com +// *! BACKUP NAME : +// #! ADDITIONAL COMMENTS : +// + +//------------------------------------------------------------------------------ +// Don't forget to create CVS comments when you check in your changes! +//------------------------------------------------------------------------------ +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version:| Author: | Date: | Comment: +//---------|----------|---------|----------------------------------------------- +// 1.1 | 03/08/13 | bellows | Initial Version + +//---------------------------------------------------------------------- +// Includes +//---------------------------------------------------------------------- + +#include <fapi.H> +#include <mss_error_support.H> +#include <cen_scom_addresses.H> +using namespace fapi; + +// This is the FFDC HWP specially written to collect the data specified by RC_ERROR_MEM_GROUPING +fapi::ReturnCode hwpCollectMemGrouping(const fapi::Target & i_target,fapi::ReturnCode & o_rc) +{ + fapi::ReturnCode l_rc; + + uint32_t _ATTR_PROC_POS; + uint32_t _ATTR_CEN_POS; + uint8_t _ATTR_CHIP_UNIT_POS_MBA0; + uint8_t _ATTR_CHIP_UNIT_POS_MBA1; + uint8_t _ATTR_EFF_DIMM_SIZE0[2][2]; + uint8_t _ATTR_EFF_DIMM_SIZE1[2][2]; + uint8_t _ATTR_MSS_INTERLEAVE_ENABLE; + uint8_t _ATTR_ALL_MCS_IN_INTERLEAVING_GROUP; + uint64_t _ATTR_PROC_MEM_BASE; + uint64_t _ATTR_PROC_MIRROR_BASE; + uint8_t _ATTR_MSS_MEM_MC_IN_GROUP[8]; + uint64_t _ATTR_PROC_MEM_BASES[8]; + uint64_t _ATTR_PROC_MEM_SIZES[8]; + uint32_t _ATTR_MSS_MCS_GROUP_32[16][16]; + uint64_t _ATTR_PROC_MIRROR_BASES[4]; + uint64_t _ATTR_PROC_MIRROR_SIZES[4]; + + std::vector<fapi::Target> l_mba_chiplets; + std::vector<fapi::Target> l_memb; + + unsigned i; + + l_rc = FAPI_ATTR_GET(ATTR_POS, &i_target, _ATTR_PROC_POS); + + if (l_rc) + { + FAPI_ERR("Error reading ATTR_POS (Proc), ignoring"); + } + + l_rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_MEMBUF_CHIP, l_memb); + + if (l_rc) + { + FAPI_ERR("Error fapiGetChildChiplets, ignoring"); + } + + for(i=0;i<l_memb.size();i++) { + l_rc = FAPI_ATTR_GET(ATTR_POS, &l_memb[i], _ATTR_CEN_POS); + + if (l_rc) + { + FAPI_ERR("Error reading ATTR_POS (cen), ignoring"); + } + + l_rc = fapiGetChildChiplets(l_memb[i], fapi::TARGET_TYPE_MBA_CHIPLET, l_mba_chiplets); + + if (l_rc) + { + FAPI_ERR("Error fapiGetChildChiplets, ignoring"); + } + + + l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_mba_chiplets[0], _ATTR_CHIP_UNIT_POS_MBA0); + + if (l_rc) + { + FAPI_ERR("Error reading ATTR_CHIP_UNIT_POS (0), ignoring"); + } + + l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_mba_chiplets[1], _ATTR_CHIP_UNIT_POS_MBA1); + + if (l_rc) + { + FAPI_ERR("Error reading ATTR_CHIP_UNIT_POS (1), ignoring"); + } + + l_rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_SIZE, &l_mba_chiplets[0], _ATTR_EFF_DIMM_SIZE0); + + if (l_rc) + { + FAPI_ERR("Error reading ATTR_EFF_DIMM_SIZE (0), ignoring"); + } + + l_rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_SIZE, &l_mba_chiplets[1], _ATTR_EFF_DIMM_SIZE1); + + if (l_rc) + { + FAPI_ERR("Error reading ATTR_EFF_DIMM_SIZE (1), ignoring"); + } + } + + l_rc = FAPI_ATTR_GET(ATTR_MSS_INTERLEAVE_ENABLE,&i_target, _ATTR_MSS_INTERLEAVE_ENABLE); + + if (l_rc) + { + FAPI_ERR("Error reading ATTR_MSS_INTERLEAVE_ENABLE, ignoring"); + } + + l_rc = FAPI_ATTR_GET(ATTR_ALL_MCS_IN_INTERLEAVING_GROUP, NULL,_ATTR_ALL_MCS_IN_INTERLEAVING_GROUP); // system level attribute + + if (l_rc) + { + FAPI_ERR("Error reading ATTR_ALL_MCS_IN_INTERLEAVING_GROUP, ignoring"); + } + + l_rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASE,&i_target,_ATTR_PROC_MEM_BASE); + + if (l_rc) + { + FAPI_ERR("Error reading ATTR_PROC_MEM_BASE, ignoring"); + } + + l_rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASE,&i_target,_ATTR_PROC_MIRROR_BASE); + + if (l_rc) + { + FAPI_ERR("Error reading ATTR_PROC_MIRROR_BASE, ignoring"); + } + + l_rc = FAPI_ATTR_GET(ATTR_MSS_MEM_MC_IN_GROUP, &i_target, _ATTR_MSS_MEM_MC_IN_GROUP); + + if (l_rc) + { + FAPI_ERR("Error reading ATTR_MSS_MEM_MC_IN_GROUP, ignoring"); + } + + l_rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASES, &i_target, _ATTR_PROC_MEM_BASES); + + if (l_rc) + { + FAPI_ERR("Error reading ATTR_PROC_MEM_BASES, ignoring"); + } + + l_rc = FAPI_ATTR_GET(ATTR_PROC_MEM_SIZES, &i_target, _ATTR_PROC_MEM_SIZES); + + if (l_rc) + { + FAPI_ERR("Error reading ATTR_PROC_MEM_SIZES, ignoring"); + } + + l_rc = FAPI_ATTR_GET(ATTR_MSS_MCS_GROUP_32,&i_target, _ATTR_MSS_MCS_GROUP_32); + + if (l_rc) + { + FAPI_ERR("Error reading ATTR_MSS_MCS_GROUP_32, ignoring"); + } + + l_rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASES, &i_target, _ATTR_PROC_MIRROR_BASES); + + if (l_rc) + { + FAPI_ERR("Error reading ATTR_PROC_MIRROR_BASES, ignoring"); + } + + l_rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_SIZES, &i_target, _ATTR_PROC_MIRROR_SIZES); + + if (l_rc) + { + FAPI_ERR("Error reading ATTR_PROC_MIRROR_SIZES, ignoring"); + } + + + FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_ERROR_MSS_GROUPING_ATTRS); + + return fapi::FAPI_RC_SUCCESS; +} + +fapi::ReturnCode hwpCollectMemFIRs(const fapi::Target & i_target,fapi::ReturnCode & o_rc) +{ + fapi::ReturnCode l_rc; + + const fapi::Target & CENCHIP = i_target; + + FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_ERROR_MSS_FIRS); + + + std::vector<fapi::Target> l_mba_chiplets; + unsigned i; + l_rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_MBA_CHIPLET, l_mba_chiplets); + if (l_rc) + { + FAPI_ERR("Error fapiGetChildChiplets, ignoring"); + } + + for(i=0;i<l_mba_chiplets.size(); i++) { + const fapi::Target & CENCHIP_MBA = l_mba_chiplets[i]; + FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_ERROR_MBA_FIRS); + + } + + + + return fapi::FAPI_RC_SUCCESS; +} diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C b/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C index d31a0d68f..9dfbe1523 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_start_clocks_chiplets.C,v 1.13 2013/01/20 19:26:07 jmcgill Exp $ +// $Id: proc_start_clocks_chiplets.C,v 1.16 2013/05/16 21:08:54 mjjones Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_start_clocks_chiplets.C,v $ //------------------------------------------------------------------------------ // *| @@ -231,9 +231,14 @@ fapi::ReturnCode proc_start_clocks_chiplet_clear_clk_scansel_reg( // function: utility subroutine to get partial good vector from SEEPROM // parameters: i_target => chip target // i_chiplet_base_addr => base SCOM address for chiplet -// i_chiplet_reg_vec => output vector +// o_chiplet_reg_vec => output vector // returns: FAPI_RC_SUCCESS if operation was successful, else error //------------------------------------------------------------------------------ + +// note: +// expected value out of SEEPROM (in case of "all good", the "Partial Good Region"-Pattern are: +// XBUS = 0xF00, ABUS = 0xE100, PCIE = 0xF700 + fapi::ReturnCode proc_start_clocks_get_partial_good_vector( const fapi::Target& i_target, const uint32_t i_chiplet_base_addr, @@ -241,9 +246,6 @@ fapi::ReturnCode proc_start_clocks_get_partial_good_vector( ) { fapi::ReturnCode rc; -// uint32_t rc_ecmd = 0; - -// uint8_t chiplet = 0; uint64_t partial_good_regions[32]; FAPI_DBG("proc_start_clocks_get_partial_good_vector: Start"); @@ -260,13 +262,6 @@ fapi::ReturnCode proc_start_clocks_get_partial_good_vector( } -// expectecd value out of SEEPROM (all good) -// Partial Good Region Pattern are: -// XBUS = 0xF000 -// ABUS = 0xE100 -// PCIE = 0xF700 - - FAPI_DBG("proc_start_clocks_get_partial_good_vector: start assignment of the partial good vector per chiplet"); switch (i_chiplet_base_addr) @@ -309,12 +304,14 @@ fapi::ReturnCode proc_start_clocks_get_partial_good_vector( //------------------------------------------------------------------------------ // function: utility subroutine to set clock region register (starts clocks) -// parameters: i_target => chip target -// i_chiplet_base_addr => base SCOM address for chiplet -// i_chiplet_reg_vec => vector from SEEPROM with partial good -// clock regions +// parameters: i_target => chip target +// i_chiplet_base_addr => base SCOM address for chiplet +// i_chiplet_reg_vec => vector from SEEPROM with partial good +// clock regions +// o_chiplet_clkreg_vec => output vector which contains +// the masked vector -> used to set the +// clock region register // returns: FAPI_RC_SUCCESS if operation was successful, else error - //------------------------------------------------------------------------------ fapi::ReturnCode proc_start_clocks_chiplet_set_clk_region_reg( const fapi::Target& i_target, @@ -400,10 +397,10 @@ fapi::ReturnCode proc_start_clocks_chiplet_set_clk_region_reg( //------------------------------------------------------------------------------ // function: utility subroutine to check clock status register to ensure // all desired clock domains have been started -// parameters: i_target => chip target -// i_chiplet_base_addr => base SCOM address for chiplet -// i_chiplet_reg_vec => region vector of SEEPROM for clock regions -// need to be turned on +// parameters: i_target => chip target +// i_chiplet_base_addr => base SCOM address for chiplet +// i_chiplet_clkreg_vec => region vector of SEEPROM for clock regions +// need to be turned on // returns: FAPI_RC_SUCCESS if operation was successful, else // RC_PROC_START_CLOCKS_CHIPLETS_CLK_STATUS_ERR if status register // data does not match expected pattern @@ -421,6 +418,8 @@ fapi::ReturnCode proc_start_clocks_chiplet_check_clk_status_reg( uint32_t scom_addr = i_chiplet_base_addr | GENERIC_CLK_STATUS_0x00030008; const uint32_t xbus = X_BUS_CHIPLET_0x04000000; + const uint32_t abus = A_BUS_CHIPLET_0x08000000; + const uint32_t pcie = PCIE_CHIPLET_0x09000000; FAPI_DBG("proc_start_clocks_chiplet_check_clk_status_reg: Start"); @@ -481,9 +480,25 @@ fapi::ReturnCode proc_start_clocks_chiplet_check_clk_status_reg( FAPI_ERR("proc_start_clocks_chiplet_check_clk_status_reg: Clock status register actual value (%016llX) does not match expected value (%016llX)", status_data.getDoubleWord(0), exp_data.getDoubleWord(0)); ecmdDataBufferBase & STATUS_REG = status_data; - uint32_t CHIPLET_BASE_SCOM_ADDR = i_chiplet_base_addr; - FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_CHIPLETS_CLK_STATUS_ERR); - break; + ecmdDataBufferBase & EXPECTED_REG = exp_data; + + if ( i_chiplet_base_addr == xbus) + { + FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_XBUS_CHIPLET_CLK_STATUS_ERR); + break; + } + if ( i_chiplet_base_addr == abus) + { + FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_ABUS_CHIPLET_CLK_STATUS_ERR); + break; + } + if ( i_chiplet_base_addr == pcie) + { + const fapi::Target & CHIP_IN_ERROR = i_target; + FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_PCIE_CHIPLET_CLK_STATUS_ERR); + break; + } + } } while(0); @@ -607,6 +622,10 @@ fapi::ReturnCode proc_start_clocks_chiplet_check_fir( ecmdDataBufferBase fir_data(64); uint32_t scom_addr = i_chiplet_base_addr | GENERIC_XSTOP_0x00040000; + const uint32_t xbus = X_BUS_CHIPLET_0x04000000; + const uint32_t abus = A_BUS_CHIPLET_0x08000000; + const uint32_t pcie = PCIE_CHIPLET_0x09000000; + FAPI_DBG("proc_start_clocks_chiplet_check_fir: Start"); @@ -629,9 +648,27 @@ fapi::ReturnCode proc_start_clocks_chiplet_check_fir( FAPI_ERR("proc_start_clocks_chiplet_check_fir: FIR register actual value (%016llX) does not match expected value (%016llX)", fir_data.getDoubleWord(0), PROC_START_CLOCKS_CHIPLETS_CHIPLET_FIR_REG_EXP); ecmdDataBufferBase & FIR_REG = fir_data; - uint32_t CHIPLET_BASE_SCOM_ADDR = i_chiplet_base_addr; - FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_CHIPLETS_FIR_ERR); - break; + const uint64_t & FIR_EXP_REG = PROC_START_CLOCKS_CHIPLETS_CHIPLET_FIR_REG_EXP; + + + if ( i_chiplet_base_addr == xbus) + { + FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_XBUS_CHIPLET_FIR_ERR); + break; + } + if ( i_chiplet_base_addr == abus) + { + FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_ABUS_CHIPLET_FIR_ERR); + break; + } + if ( i_chiplet_base_addr == pcie) + { + + const fapi::Target & CHIP_IN_ERROR = i_target; + FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_PCIE_CHIPLET_FIR_ERR); + break; + } + } } while(0); @@ -646,8 +683,6 @@ fapi::ReturnCode proc_start_clocks_chiplet_check_fir( // function: utility subroutine to run clock start sequence on a generic chiplet // parameters: i_target => chip target // i_chiplet_base_addr => base SCOM address for chiplet -// i_status_reg_exp => expected value for clock status register -// after clock start // returns: FAPI_RC_SUCCESS if operation was successful, else error //------------------------------------------------------------------------------ fapi::ReturnCode proc_start_clocks_generic_chiplet( diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets_errors.xml b/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets_errors.xml index 2fd2d6925..505e425c4 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets_errors.xml +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> <!-- --> <!-- p1 --> <!-- --> @@ -20,26 +20,83 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_start_clocks_chiplets_errors.xml,v 1.4 2013/05/06 12:33:48 rkoester Exp $ --> <!-- Error definitions for proc_start_clocks_chiplets procedure --> <hwpErrors> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_START_CLOCKS_CHIPLETS_CLK_STATUS_ERR</rc> + <rc>RC_PROC_START_CLOCKS_XBUS_CHIPLET_CLK_STATUS_ERR</rc> + <description>Unexpected XBUS clock status register returned after clock start operation.</description> + <ffdc>STATUS_REG</ffdc> + <ffdc>EXPECTED_REG</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_START_CLOCKS_ABUS_CHIPLET_CLK_STATUS_ERR</rc> + <description>Unexpected ABUS clock status register returned after clock start operation.</description> + <ffdc>STATUS_REG</ffdc> + <ffdc>EXPECTED_REG</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_START_CLOCKS_PCIE_CHIPLET_CLK_STATUS_ERR</rc> <description>Unexpected clock status register returned after clock start operation.</description> <ffdc>STATUS_REG</ffdc> - <ffdc>CHIPLET_BASE_SCOM_ADDR</ffdc> + <ffdc>EXPECTED_REG</ffdc> + <callout> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP_IN_ERROR</target> + </deconfigure> + <gard> + <target>CHIP_IN_ERROR</target> + </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_START_CLOCKS_CHIPLETS_FIR_ERR</rc> + <rc>RC_PROC_START_CLOCKS_XBUS_CHIPLET_FIR_ERR</rc> <description>Unexpected chiplet FIR bit set after clock start operation.</description> <ffdc>FIR_REG</ffdc> - <ffdc>CHIPLET_BASE_SCOM_ADDR</ffdc> + <ffdc>FIR_EXP_REG</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_START_CLOCKS_ABUS_CHIPLET_FIR_ERR</rc> + <description>Unexpected chiplet FIR bit set after clock start operation.</description> + <ffdc>FIR_REG</ffdc> + <ffdc>FIR_EXP_REG</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_START_CLOCKS_PCIE_CHIPLET_FIR_ERR</rc> + <description>Unexpected chiplet FIR bit set after clock start operation.</description> + <ffdc>FIR_REG</ffdc> + <ffdc>FIR_EXP_REG</ffdc> + <callout> + <target>CHIP_IN_ERROR</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>CHIP_IN_ERROR</target> + </deconfigure> + <gard> + <target>CHIP_IN_ERROR</target> + </gard> </hwpError> <!-- *********************************************************************** --> <hwpError> <rc>RC_PROC_START_CLOCKS_CHIPLETS_PARTIAL_GOOD_ERR</rc> <description>Unexpected chiplet selection when reading the partial good vector.</description> <ffdc>CHIPLET_BASE_SCOM_ADDR</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> </hwpErrors> + <!-- *********************************************************************** --> + <!-- TODO Callout all chiplets of a specified type on a chip: story 69794 --> + <!-- TODO Callout the PCI refclock: story 69766 --> + <!-- *********************************************************************** --> diff --git a/src/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.C b/src/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.C index e2f6f4a73..72c464ee7 100644 --- a/src/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.C +++ b/src/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.C @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/mss_memdiag/mss_maint_cmds.C $ */ +/* $Source: src/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.C $ */ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* COPYRIGHT International Business Machines Corp. 2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_maint_cmds.C,v 1.20 2013/03/08 22:03:57 gollub Exp $ +// $Id: mss_maint_cmds.C,v 1.24 2013/05/20 16:52:28 gollub Exp $ //------------------------------------------------------------------------------ // Don't forget to create CVS comments when you check in your changes! //------------------------------------------------------------------------------ @@ -44,7 +44,7 @@ // | | | Added stop condition enums // | | | STOP_IMMEDIATE // | | | ENABLE_CMD_COMPLETE_ATTENTION_ON_CLEAN_AND_ERROR -// | | | Now require cleanupCmd() for super fast read +// | | | Now require cleanupCmd() for super fast read // | | | to disable rrq fifo mode when done. // 1.11 | 09/07/12 | gollub | Updates from review. // | | | Support for more patterns. @@ -55,15 +55,22 @@ // | | | Updates to traces. // 1.16 | 11/21/12 | gollub | Updates from review. // 1.17 | 12/19/12 | gollub | Added UE isolation -// 1.18 | 01/15/13 | gollub | Added check for valid dimm before calling +// 1.18 | 01/15/13 | gollub | Added check for valid dimm before calling // | | | dimmGetBadDqBitmap -// 1.19 | 01/31/13 | gollub | Updated MDI bits for random pattern so +// 1.19 | 01/31/13 | gollub | Updated MDI bits for random pattern so // | | | don't get SUEs // | | | Added mss_check_steering // | | | Added mss_do_steering // | | | Added mss_stopCmd // | | | Removed cleanupCmd for cmds that didn't use it // 1.20 | 03/08/13 | gollub | Mask MBSPA[0][8] during increment cmd +// 1.21 | 04/19/13 | gollub | Fix: Slow down fast scrub rate. +// | | | Fix: Was skippng reg update for slow scrub rate +// | | | Fix: Clear MBMCC[1] stop bit after forcing a stop +// | | | Add: Added target to FAPI_ERR traces +// 1.22 | 04/30/13 | mjjones | Removed unused variable +// 1.23 | 05/03/13 | gollub | Clear cmd complete attention in mss_stopCmd +// 1.24 | 05/20/13 | gollub | Updates from review. //------------------------------------------------------------------------------ // Includes @@ -82,40 +89,61 @@ using namespace fapi; /** * @brief Max 8 master ranks per MB - */ + */ const uint8_t MSS_MAX_RANKS = 8; /** * @brief The number of symbols per rank - */ + */ const uint8_t MSS_SYMBOLS_PER_RANK = 72; + +/** + * @brief The used for symbol ranges on port 0: Symbols 71-40, 7-4 + */ +const uint8_t MSS_PORT_0_SYMBOL_71 = 71; +const uint8_t MSS_PORT_0_SYMBOL_40 = 40; +const uint8_t MSS_PORT_0_SYMBOL_7 = 7; +const uint8_t MSS_PORT_0_SYMBOL_4 = 4; + +/** + * @brief The used for symbol ranges on port 1: Symbols 39-8, 3-0 + */ +const uint8_t MSS_PORT_1_SYMBOL_39 = 39; +const uint8_t MSS_PORT_1_SYMBOL_8 = 8; +const uint8_t MSS_PORT_1_SYMBOL_3 = 3; +const uint8_t MSS_PORT_1_SYMBOL_0 = 0; + + + + + /** * @brief 9 x8 DRAMs we can steer, plus one for no steer option - */ + */ const uint8_t MSS_X8_STEER_OPTIONS_PER_PORT = 10; /** * @brief 18 x4 DRAMs we can steer on port0, plus one for no steer option - */ + */ const uint8_t MSS_X4_STEER_OPTIONS_PER_PORT0 = 19; /** * @brief 17 x4 DRAMs we can steer on port1, plus one no steer option - * NOTE: Only 17 DRAMs we can steer since one DRAM is used for the + * NOTE: Only 17 DRAMs we can steer since one DRAM is used for the * ECC spare. - */ + */ const uint8_t MSS_X4_STEER_OPTIONS_PER_PORT1 = 18; /** * @brief 18 on port0, 17 on port1, plus one no steer option * NOTE: Can's use ECC spare to fix bad spare DRAMs - */ + */ const uint8_t MSS_X4_ECC_STEER_OPTIONS = 36; /** * @brief Max 8 patterns - */ + */ const uint8_t MSS_MAX_PATTERNS = 9; @@ -123,14 +151,14 @@ namespace mss_MemConfig { /** * @brief DRAM size in gigabits, used to determine address range for maint cmds - */ + */ enum DramSize { GBIT_2 = 0, GBIT_4 = 1, GBIT_8 = 2, }; - + /** * @brief DRAM width, used to determine address range for maint cmds */ @@ -153,7 +181,7 @@ namespace mss_MemConfig COL_12 = 0x00000FF8, // c2, c1, c0 always 0 BANK_3 = 0x00000007, }; - + /** * @brief Spare DRAM config, used to identify what spares exist */ @@ -164,7 +192,7 @@ namespace mss_MemConfig HIGH_NIBBLE = 2, // x4 spare (high nibble: no plan to use) FULL_BYTE = 3 // x8 dpare }; - + }; @@ -200,7 +228,7 @@ static const uint32_t mss_mbstr[2]={ static const uint32_t mss_mbmmr[2]={ // port0/1 port2/3 MBS_ECC0_MBMMRQ_0x0201145B, MBS_ECC1_MBMMRQ_0x0201149B}; - + static const uint32_t mss_readMuxRegs[8][2]={ // port0/1 port2/3 {MBS_ECC0_MBSBS0_0x0201145E, MBS_ECC1_MBSBS0_0x0201149E}, @@ -211,7 +239,7 @@ static const uint32_t mss_readMuxRegs[8][2]={ {MBS_ECC0_MBSBS5_0x02011463, MBS_ECC1_MBSBS5_0x020114A3}, {MBS_ECC0_MBSBS6_0x02011464, MBS_ECC1_MBSBS6_0x020114A4}, {MBS_ECC0_MBSBS7_0x02011465, MBS_ECC1_MBSBS7_0x020114A5}}; - + static const uint32_t mss_writeMuxRegs[8]={ MBA01_MBABS0_0x03010440, @@ -226,7 +254,7 @@ static const uint32_t mss_writeMuxRegs[8]={ //------------------------------------------------------------------------------ // Conversion from symbol index to galois field stored in markstore //------------------------------------------------------------------------------ -static const uint8_t mss_symbol2Galois[MSS_SYMBOLS_PER_RANK] = +static const uint8_t mss_symbol2Galois[MSS_SYMBOLS_PER_RANK] = { 0x80, 0xa0, 0x90, 0xf0, 0x08, 0x0a, 0x09, 0x0f, // symbols 0- 7 0x98, 0xda, 0xb9, 0x7f, 0x91, 0xd7, 0xb2, 0x78, // symbols 8-15 @@ -239,7 +267,7 @@ static const uint8_t mss_symbol2Galois[MSS_SYMBOLS_PER_RANK] = 0xfe, 0x61, 0x75, 0x5d, 0x51, 0x27, 0xa2, 0x38, // symbols 64-71 }; - + static const uint8_t mss_x8dramSparePort0Index_to_symbol[MSS_X8_STEER_OPTIONS_PER_PORT]={ // symbol @@ -646,19 +674,19 @@ static const uint32_t mss_ECC[MSS_MAX_PATTERNS][4]={ 0x04F3D0DA, // 1st 64B of cachline 0x019764DA, // 2nd 64B of cachline 0x0DC751A1}, // 2nd 64B of cachline - + // PATTERN_6 - verified {0x0CF6B55C, // 1st 64B of cachline 0x08CCE671, // 1st 64B of cachline 0x02D94BBB, // 2nd 64B of cachline 0x030C31B6}, // 2nd 64B of cachline - + // PATTERN_7 - verified {0x09150CD1, // 1st 64B of cachline 0x0F9D48C9, // 1st 64B of cachline 0x073AF236, // 2nd 64B of cachline 0x045D9F0E}, // 2nd 64B of cachline - + // PATTERN_8: random {0x00000000, // 1st 64B of cachline 0x00000000, // 1st 64B of cachline @@ -696,17 +724,42 @@ mss_MaintCmd::mss_MaintCmd(const fapi::Target & i_target, fapi::ReturnCode mss_MaintCmd::stopCmd() { fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; + uint32_t l_ecmd_rc = 0; ecmdDataBufferBase l_mbmsrq(64); ecmdDataBufferBase l_mbmccq(64); - ecmdDataBufferBase l_mbmacaq(64); - + ecmdDataBufferBase l_mbmacaq(64); + ecmdDataBufferBase l_mbspa_mask(64); + ecmdDataBufferBase l_mbspa_mask_original(64); + ecmdDataBufferBase l_mbspa_and(64); + FAPI_INF("ENTER mss_MaintCmd::stopCmd()"); + + // Read MBSPA MASK + l_rc = fapiGetScom(iv_target, MBA01_MBSPAMSKQ_0x03010614, l_mbspa_mask); + if(l_rc) return l_rc; + + // Save original mask value so we can restore it when done + l_ecmd_rc |= l_mbspa_mask_original.insert(l_mbspa_mask, 0, 64, 0); + + // Mask bits 0 and 8, to hide the special attentions when the cmd completes + l_ecmd_rc |= l_mbspa_mask.setBit(0); + l_ecmd_rc |= l_mbspa_mask.setBit(8); + if(l_ecmd_rc) + { + l_rc.setEcmdError(l_ecmd_rc); + return l_rc; + } + // Write MBSPA MASK + l_rc = fapiPutScom(iv_target, MBA01_MBSPAMSKQ_0x03010614, l_mbspa_mask); + if(l_rc) return l_rc; + + // Read MBMSRQ l_rc = fapiGetScom(iv_target, MBA01_MBMSRQ_0x0301060C, l_mbmsrq); if(l_rc) return l_rc; - + + // If MBMSRQ[0], maint_cmd_in_progress, stop the cmd if (l_mbmsrq.isBitSet(0)) { @@ -725,16 +778,30 @@ fapi::ReturnCode mss_MaintCmd::stopCmd() // Write MBMCCQ l_rc = fapiPutScom(iv_target, MBA01_MBMCCQ_0x0301060B, l_mbmccq); if(l_rc) return l_rc; + + // Clear bit 1 again, just in case cmd was already stopped + // in which case, bit 1 doesn't self-clear after we set it. + l_ecmd_rc |= l_mbmccq.clearBit(1); + if(l_ecmd_rc) + { + l_rc.setEcmdError(l_ecmd_rc); + return l_rc; + } + // Write MBMCCQ + l_rc = fapiPutScom(iv_target, MBA01_MBMCCQ_0x0301060B, l_mbmccq); + if(l_rc) return l_rc; + + // Read MBMSRQ l_rc = fapiGetScom(iv_target, MBA01_MBMSRQ_0x0301060C, l_mbmsrq); if(l_rc) return l_rc; - + // If cmd didn't stop as expected if (l_mbmsrq.isBitSet(0)) { - FAPI_ERR("MBMSRQ[0] = 1, unsuccessful forced maint cmd stop."); - + FAPI_ERR("MBMSRQ[0] = 1, unsuccessful forced maint cmd stop on %s.",iv_target.toEcmdString()); + // Calling out MBA target high, deconfig, gard const fapi::Target & MBA = iv_target; // FFDC: Capture register we used to stop cmd @@ -743,13 +810,13 @@ fapi::ReturnCode mss_MaintCmd::stopCmd() ecmdDataBufferBase & MBMSR = l_mbmsrq; // FFDC: Capture command type we are trying to run const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; - + // Create new log FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_UNSUCCESSFUL_FORCED_MAINT_CMD_STOP); - return l_rc; - } + return l_rc; + } } - + // Store the address we stopped at in iv_startAddr l_rc = fapiGetScom(iv_target, MBA01_MBMACAQ_0x0301060D, iv_startAddr); if(l_rc) return l_rc; @@ -761,8 +828,26 @@ fapi::ReturnCode mss_MaintCmd::stopCmd() l_rc.setEcmdError(l_ecmd_rc); return l_rc; } + + // Clear bits 0 and 8 in MBSPA AND register + l_ecmd_rc |= l_mbspa_and.flushTo1(); + l_ecmd_rc |= l_mbspa_and.clearBit(0); + l_ecmd_rc |= l_mbspa_and.clearBit(8); + if(l_ecmd_rc) + { + l_rc.setEcmdError(l_ecmd_rc); + return l_rc; + } + // Write MPSPA AND register + l_rc = fapiPutScom(iv_target, MBA01_MBSPAQ_AND_0x03010612, l_mbspa_and); + if(l_rc) return l_rc; + + // Restore MBSPA MASK + l_rc = fapiPutScom(iv_target, MBA01_MBSPAMSKQ_0x03010614, l_mbspa_mask_original); + if(l_rc) return l_rc; + FAPI_INF("EXIT mss_MaintCmd::stopCmd()"); return l_rc; } @@ -775,9 +860,9 @@ fapi::ReturnCode mss_MaintCmd::cleanupCmd() { fapi::ReturnCode l_rc; FAPI_INF("ENTER mss_MaintCmd::cleanupCmd()"); + - - + FAPI_INF("EXIT mss_MaintCmd::cleanupCmd()"); return l_rc; } @@ -802,7 +887,7 @@ fapi::ReturnCode mss_MaintCmd::preConditionCheck() l_rc = fapiGetParentChip(iv_target, iv_targetCentaur); if(l_rc) { - FAPI_ERR("Error getting Centaur parent target for the given MBA"); + FAPI_ERR("Error getting Centaur parent target for the given MBA on %s.",iv_target.toEcmdString()); return l_rc; } @@ -810,7 +895,7 @@ fapi::ReturnCode mss_MaintCmd::preConditionCheck() l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &iv_target, iv_mbaPosition); if(l_rc) { - FAPI_ERR("Error getting MBA position"); + FAPI_ERR("Error getting MBA position on %s.",iv_target.toEcmdString()); return l_rc; } @@ -833,18 +918,18 @@ fapi::ReturnCode mss_MaintCmd::preConditionCheck() // Read MBSECC l_rc = fapiGetScom(iv_targetCentaur, mss_mbsecc[iv_mbaPosition], l_mbsecc); if(l_rc) return l_rc; - + // Read MBMCT[0:4], cmd type, for FFDC l_rc = fapiGetScom(iv_target, MBA01_MBMCTQ_0x0301060A, l_mbmct); if(l_rc) return l_rc; - + // Check for MBMCCQ[0], maint_cmd_start, to be reset by hw. if (l_mbmccq.isBitSet(0)) { - FAPI_ERR("MBMCCQ[0]: maint_cmd_start not reset by hw."); - + FAPI_ERR("MBMCCQ[0]: maint_cmd_start not reset by hw on %s.",iv_target.toEcmdString()); + // Calling out MBA target high, deconfig, gard const fapi::Target & MBA = iv_target; // FFDC: Capture register we are checking @@ -852,8 +937,8 @@ fapi::ReturnCode mss_MaintCmd::preConditionCheck() // FFDC: Capture command type we are trying to run const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; // FFDC: MBMCT[0:4] contains the cmd type previously run - ecmdDataBufferBase & MBMCT = l_mbmct; - + ecmdDataBufferBase & MBMCT = l_mbmct; + // Create new log FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_START_NOT_RESET); } @@ -864,8 +949,8 @@ fapi::ReturnCode mss_MaintCmd::preConditionCheck() // Log previous error before creating new log if (l_rc) fapiLogError(l_rc); - FAPI_ERR("MBMCCQ[1]: maint_cmd_stop not reset by hw."); - + FAPI_ERR("MBMCCQ[1]: maint_cmd_stop not reset by hw on %s.",iv_target.toEcmdString()); + // Calling out MBA target high, deconfig, gard const fapi::Target & MBA = iv_target; // FFDC: Capture register we are checking @@ -873,8 +958,8 @@ fapi::ReturnCode mss_MaintCmd::preConditionCheck() // FFDC: Capture command type we are trying to run const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; // FFDC: MBMCT[0:4] contains the cmd type previously run - ecmdDataBufferBase & MBMCT = l_mbmct; - + ecmdDataBufferBase & MBMCT = l_mbmct; + // Create new log FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_STOP_NOT_RESET); } @@ -885,7 +970,7 @@ fapi::ReturnCode mss_MaintCmd::preConditionCheck() // Log previous error before creating new log if (l_rc) fapiLogError(l_rc); - FAPI_ERR("MBMSRQ[0]: Can't start new cmd if previous cmd still in progress."); + FAPI_ERR("MBMSRQ[0]: Can't start new cmd if previous cmd still in progress on %s.",iv_target.toEcmdString()); // TODO: Calling out FW high // Calling out MBA target low, deconfig, gard @@ -895,7 +980,7 @@ fapi::ReturnCode mss_MaintCmd::preConditionCheck() // FFDC: Capture command type we are trying to run const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; // FFDC: MBMCT[0:4] contains the cmd type previously run - ecmdDataBufferBase & MBMCT = l_mbmct; + ecmdDataBufferBase & MBMCT = l_mbmct; // Create new log FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_CMD_IN_PROGRESS); @@ -907,7 +992,7 @@ fapi::ReturnCode mss_MaintCmd::preConditionCheck() // Log previous error before creating new log if (l_rc) fapiLogError(l_rc); - FAPI_ERR("MBAXCRn[0:3] = 0, meaning no memory configured behind this MBA."); + FAPI_ERR("MBAXCRn[0:3] = 0, meaning no memory configured behind this MBA on %s.",iv_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target @@ -925,7 +1010,7 @@ fapi::ReturnCode mss_MaintCmd::preConditionCheck() // Log previous error before creating new log if (l_rc) fapiLogError(l_rc); - FAPI_ERR("CCS_MODEQ[29] = 1, meaning mux set for CCS instead of mainline."); + FAPI_ERR("CCS_MODEQ[29] = 1, meaning mux set for CCS instead of mainline on %s.",iv_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target @@ -945,7 +1030,7 @@ fapi::ReturnCode mss_MaintCmd::preConditionCheck() // Log previous error before creating new log if (l_rc) fapiLogError(l_rc); - FAPI_ERR("MBSECC[0] = 1, meaning ECC check/correct disabled."); + FAPI_ERR("MBSECC[0] = 1, meaning ECC check/correct disabled on %s.",iv_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target @@ -979,7 +1064,7 @@ fapi::ReturnCode mss_MaintCmd::loadCmdType() l_rc = fapiGetScom(iv_target, MBA01_MBMCTQ_0x0301060A, l_data); if(l_rc) return l_rc; l_ecmd_rc |= l_data.insert( (uint32_t)iv_cmdType, 0, 5, 32-5 ); - + // NOTE: Setting super fast address increment mode, where COL bits are LSB. // Valid for all cmds. l_ecmd_rc |= l_data.setBit(5); @@ -1040,7 +1125,7 @@ fapi::ReturnCode mss_MaintCmd::loadEndAddress() ecmdDataBufferBase l_data(64); FAPI_INF("ENTER mss_MaintCmd::loadEndAddress()"); - + l_rc = fapiGetScom(iv_target, MBA01_MBMEAQ_0x0301060E, l_data); if(l_rc) return l_rc; @@ -1049,7 +1134,7 @@ fapi::ReturnCode mss_MaintCmd::loadEndAddress() { l_rc.setEcmdError(l_ecmd_rc); return l_rc; - } + } l_rc = fapiPutScom(iv_target, MBA01_MBMEAQ_0x0301060E, l_data); if(l_rc) return l_rc; @@ -1081,7 +1166,7 @@ fapi::ReturnCode mss_MaintCmd::loadStopCondMask() if ( 0 != (iv_stopCondition & STOP_IMMEDIATE) ) l_ecmd_rc |= l_mbasctlq.setBit(0); - // Enable stop end of rank + // Enable stop end of rank if ( 0 != (iv_stopCondition & STOP_END_OF_RANK) ) l_ecmd_rc |= l_mbasctlq.setBit(1); @@ -1111,7 +1196,7 @@ fapi::ReturnCode mss_MaintCmd::loadStopCondMask() // Stop on MPE if ( 0 != (iv_stopCondition & STOP_ON_MPE) ) - l_ecmd_rc |= l_mbasctlq.setBit(8); + l_ecmd_rc |= l_mbasctlq.setBit(8); // Stop on UE if ( 0 != (iv_stopCondition & STOP_ON_UE) ) @@ -1126,9 +1211,9 @@ fapi::ReturnCode mss_MaintCmd::loadStopCondMask() l_ecmd_rc |= l_mbasctlq.setBit(11); // Stop on SUE - if ( 0 != (iv_stopCondition & STOP_ON_SUE) ) + if ( 0 != (iv_stopCondition & STOP_ON_SUE) ) l_ecmd_rc |= l_mbasctlq.setBit(12); - + // Enable command complete attention on clean and error if ( 0 != (iv_stopCondition & ENABLE_CMD_COMPLETE_ATTENTION_ON_CLEAN_AND_ERROR) ) l_ecmd_rc |= l_mbasctlq.setBit(16); @@ -1144,7 +1229,7 @@ fapi::ReturnCode mss_MaintCmd::loadStopCondMask() if(l_rc) return l_rc; FAPI_INF("EXIT mss_MaintCmd::loadStopCondMask()"); - + return l_rc; } @@ -1168,7 +1253,7 @@ fapi::ReturnCode mss_MaintCmd::startMaintCmd() { l_rc.setEcmdError(l_ecmd_rc); return l_rc; - } + } l_rc = fapiPutScom(iv_target, MBA01_MBMCCQ_0x0301060B, l_data); if(l_rc) return l_rc; @@ -1185,7 +1270,7 @@ fapi::ReturnCode mss_MaintCmd::postConditionCheck() ecmdDataBufferBase l_mbmccq(64); ecmdDataBufferBase l_mbafirq(64); ecmdDataBufferBase l_mbmct(64); - + FAPI_INF("ENTER mss_MaintCmd::postConditionCheck()"); // Read MBMCCQ @@ -1195,16 +1280,16 @@ fapi::ReturnCode mss_MaintCmd::postConditionCheck() // Read MBAFIRQ l_rc = fapiGetScom(iv_target, MBA01_MBAFIRQ_0x03010600, l_mbafirq); if(l_rc) return l_rc; - + // Read MBMCT[0:4], cmd type, for FFDC l_rc = fapiGetScom(iv_target, MBA01_MBMCTQ_0x0301060A, l_mbmct); - if(l_rc) return l_rc; - + if(l_rc) return l_rc; + // Check for MBMCCQ[0], maint_cmd_start, to be reset by hw. if (l_mbmccq.isBitSet(0)) { - FAPI_ERR("MBMCCQ[0]: maint_cmd_start not reset by hw."); - + FAPI_ERR("MBMCCQ[0]: maint_cmd_start not reset by hw on %s.",iv_target.toEcmdString()); + // Calling out MBA target high, deconfig, gard const fapi::Target & MBA = iv_target; // FFDC: Capture register we are checking @@ -1212,8 +1297,8 @@ fapi::ReturnCode mss_MaintCmd::postConditionCheck() // FFDC: Capture command type we are trying to run const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; // FFDC: MBMCT[0:4] contains the cmd type set in hw - ecmdDataBufferBase & MBMCT = l_mbmct; - + ecmdDataBufferBase & MBMCT = l_mbmct; + // Create new log FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_START_NOT_RESET); } @@ -1224,8 +1309,8 @@ fapi::ReturnCode mss_MaintCmd::postConditionCheck() // Log previous error before creating new log if (l_rc) fapiLogError(l_rc); - FAPI_ERR("MBAFIRQ[0], invalid_maint_cmd."); - + FAPI_ERR("MBAFIRQ[0], invalid_maint_cmd on %s.",iv_target.toEcmdString()); + // TODO: Calling out FW high // FFDC: MBA target const fapi::Target & MBA = iv_target; @@ -1234,9 +1319,9 @@ fapi::ReturnCode mss_MaintCmd::postConditionCheck() // FFDC: Capture command type we are trying to run const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; // FFDC: MBMCT[0:4] contains the cmd type set in hw - ecmdDataBufferBase & MBMCT = l_mbmct; - - // Create new log + ecmdDataBufferBase & MBMCT = l_mbmct; + + // Create new log FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_CMD); } @@ -1246,7 +1331,7 @@ fapi::ReturnCode mss_MaintCmd::postConditionCheck() // Log previous error before creating new log if (l_rc) fapiLogError(l_rc); - FAPI_ERR("MBAFIRQ[1], cmd started with invalid_maint_address."); + FAPI_ERR("MBAFIRQ[1], cmd started with invalid_maint_address on %s.",iv_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target @@ -1257,8 +1342,8 @@ fapi::ReturnCode mss_MaintCmd::postConditionCheck() const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; // FFDC: MBMCT[0:4] contains the cmd type set in hw ecmdDataBufferBase & MBMCT = l_mbmct; - // NOTE: List of additional FFDC regs specified in memory_errors.xml - + // NOTE: List of additional FFDC regs specified in memory_errors.xml + // Create new log FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_ADDR); } @@ -1303,7 +1388,7 @@ fapi::ReturnCode mss_MaintCmd::pollForMaintCmdComplete() FAPI_DBG("MBMACAQ = 0x%.8X 0x%.8X",l_data.getWord(0), l_data.getWord(1)); // Waiting for MBMSRQ[0] maint cmd in progress bit to turn off - l_rc = fapiGetScom(iv_target, MBA01_MBMSRQ_0x0301060C, l_data); + l_rc = fapiGetScom(iv_target, MBA01_MBMSRQ_0x0301060C, l_data); if(l_rc) return l_rc; FAPI_DBG("MBMSRQ = 0x%.8X 0x%.8X",l_data.getWord(0), l_data.getWord(1)); @@ -1315,8 +1400,8 @@ fapi::ReturnCode mss_MaintCmd::pollForMaintCmdComplete() if (count == loop_limit) { - FAPI_ERR("Maint cmd timeout."); - + FAPI_ERR("Maint cmd timeout on %s.",iv_target.toEcmdString()); + // TODO: Calling out FW high // Calling out MBA target low, deconfig, gard const fapi::Target & MBA = iv_target; @@ -1324,10 +1409,10 @@ fapi::ReturnCode mss_MaintCmd::pollForMaintCmdComplete() const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; // Specify CENTAUR target so we can read some FFDC regs from MBS const fapi::Target & CENTAUR = iv_targetCentaur; - // NOTE: List of additional FFDC regs specified in memory_errors.xml + // NOTE: List of additional FFDC regs specified in memory_errors.xml // Create new log - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_CMD_TIMEOUT); + FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_CMD_TIMEOUT); } else { @@ -1349,7 +1434,7 @@ fapi::ReturnCode mss_MaintCmd::collectFFDC() uint8_t l_dramSparePort1Symbol = MSS_INVALID_SYMBOL; uint8_t l_eccSpareSymbol = MSS_INVALID_SYMBOL; uint8_t l_symbol_mark = MSS_INVALID_SYMBOL; - uint8_t l_chip_mark = MSS_INVALID_SYMBOL; + uint8_t l_chip_mark = MSS_INVALID_SYMBOL; FAPI_INF("ENTER mss_MaintCmd::collectFFDC()"); @@ -1378,19 +1463,19 @@ fapi::ReturnCode mss_MaintCmd::collectFFDC() if(l_rc) return l_rc; FAPI_DBG("MBASCTLQ = 0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); - l_rc = fapiGetScom(iv_target, MBA01_MBMCCQ_0x0301060B, l_data); + l_rc = fapiGetScom(iv_target, MBA01_MBMCCQ_0x0301060B, l_data); if(l_rc) return l_rc; FAPI_DBG("MBMCCQ = 0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); - l_rc = fapiGetScom(iv_target, MBA01_MBMSRQ_0x0301060C, l_data); + l_rc = fapiGetScom(iv_target, MBA01_MBMSRQ_0x0301060C, l_data); if(l_rc) return l_rc; FAPI_DBG("MBMSRQ = 0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); - l_rc = fapiGetScom(iv_target, MBA01_MBAFIRQ_0x03010600, l_data); + l_rc = fapiGetScom(iv_target, MBA01_MBAFIRQ_0x03010600, l_data); if(l_rc) return l_rc; FAPI_DBG("MBAFIRQ = 0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); - l_rc = fapiGetScom(iv_target, MBA01_MBSPAQ_0x03010611, l_data); + l_rc = fapiGetScom(iv_target, MBA01_MBSPAQ_0x03010611, l_data); if(l_rc) return l_rc; FAPI_DBG("MBSPAQ = 0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); @@ -1431,7 +1516,7 @@ fapi::ReturnCode mss_MaintCmd::collectFFDC() l_rc = mss_get_mark_store(iv_target, i, l_symbol_mark, l_chip_mark ); if (l_rc) { - FAPI_ERR("Error reading markstore"); + FAPI_ERR("Error reading markstore on %s.",iv_target.toEcmdString()); return l_rc; } } @@ -1446,7 +1531,7 @@ fapi::ReturnCode mss_MaintCmd::collectFFDC() l_eccSpareSymbol); if(l_rc) return l_rc; } - + FAPI_INF("EXIT mss_MaintCmd::collectFFDC()"); return l_rc; } @@ -1540,7 +1625,7 @@ fapi::ReturnCode mss_MaintCmd::loadPattern(PatternIndex i_initPattern) for(loop=0; loop<16; loop++ ) { - // A write to MAINT_BUFFx_DATAy will not update until the corresponding + // A write to MAINT_BUFFx_DATAy will not update until the corresponding // MAINT_BUFFx_DATA_ECCy is written to. l_ecmd_rc |= l_data.insert(mss_maintBufferData[i_initPattern][loop][0], 0, 32, 0); l_ecmd_rc |= l_data.insert(mss_maintBufferData[i_initPattern][loop][1], 32, 32, 0); @@ -1550,7 +1635,7 @@ fapi::ReturnCode mss_MaintCmd::loadPattern(PatternIndex i_initPattern) return l_rc; } l_rc = fapiPutScom(iv_targetCentaur, maintBufferDataRegs[iv_mbaPosition][loop][0], l_data); - if(l_rc) return l_rc; + if(l_rc) return l_rc; l_rc = fapiPutScom(iv_targetCentaur, maintBufferDataRegs[iv_mbaPosition][loop][1], l_ecc); if(l_rc) return l_rc; @@ -1583,11 +1668,11 @@ fapi::ReturnCode mss_MaintCmd::loadPattern(PatternIndex i_initPattern) l_rc = fapiPutScom(iv_targetCentaur, maintBuffer65thRegs[loop][iv_mbaPosition], l_65th); if(l_rc) return l_rc; - } + } //---------------------------------------------------- // Save i_initPattern in unused maint mark reg - // so we know what pattern was used when we do + // so we know what pattern was used when we do // UE isolation //---------------------------------------------------- @@ -1686,7 +1771,7 @@ fapi::ReturnCode mss_MaintCmd::loadSpeed(TimeBaseSpeed i_speed) l_burst_window_sel = 0; l_timebase_sel = 0; l_timebase_burst_sel = 0; - l_timebase_interval = 32; + l_timebase_interval = 512; l_burst_window = 0; l_burst_interval = 0; } @@ -1695,34 +1780,32 @@ fapi::ReturnCode mss_MaintCmd::loadSpeed(TimeBaseSpeed i_speed) { // Get l_ddr_freq from ATTR_MSS_FREQ // Possible frequencies are 800, 1066, 1333, 1600, 1866, and 2133 MHz - // NOTE: Max 32 address bits using 800 and 1066 result in scrub - // taking longer than 12h, but these is no plan to actually use + // NOTE: Max 32 address bits using 800 and 1066 result in scrub + // taking longer than 12h, but these is no plan to actually use // those frequencies. l_rc = FAPI_ATTR_GET( ATTR_MSS_FREQ, &iv_targetCentaur, l_ddr_freq); if (l_rc) { - FAPI_ERR("Failed to get attribute: ATTR_MSS_FREQ."); + FAPI_ERR("Failed to get attribute: ATTR_MSS_FREQ on %s.",iv_target.toEcmdString()); return l_rc; } // Make sure it's non-zero, to avoid divide by 0 if (l_ddr_freq == 0) { - FAPI_ERR("ATTR_MSS_FREQ set to zero so can't calculate scrub rate."); - + FAPI_ERR("ATTR_MSS_FREQ set to zero so can't calculate scrub rate on %s.",iv_target.toEcmdString()); + // TODO: Calling out FW high // FFDC: MBA target const fapi::Target & MBA = iv_target; - // FFDC: Capture l_ddr_freq - uint32_t DDR_FREQ = l_ddr_freq; // FFDC: Capture command type we are trying to run const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; - // Create new log + // Create new log FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_ZERO_DDR_FREQ); return l_rc; } - + // l_timebase_sel // MBMCTQ[9:10]: 00 = 1 * Maint Clk // 01 = 8192 * Maint Clk @@ -1742,7 +1825,7 @@ fapi::ReturnCode mss_MaintCmd::loadSpeed(TimeBaseSpeed i_speed) l_end_address ); if (l_rc) { - FAPI_ERR("mss_get_address_range failed. "); + FAPI_ERR("mss_get_address_range failed on %s.",iv_target.toEcmdString()); return l_rc; } @@ -1756,7 +1839,7 @@ fapi::ReturnCode mss_MaintCmd::loadSpeed(TimeBaseSpeed i_speed) } // NOTE: Assumption is max 32 address bits, which can be done - // in 12h (+/- 2h). More than 32 address bits would + // in 12h (+/- 2h). More than 32 address bits would // double scrub time for every extra address bit. if (l_num_address_bits > 32) { @@ -1792,7 +1875,7 @@ fapi::ReturnCode mss_MaintCmd::loadSpeed(TimeBaseSpeed i_speed) // Make sure smallest is 1 if (l_timebase_interval == 0) l_timebase_interval = 1; - + FAPI_DBG("l_num_address_bits = %d, l_num_addresses = %d (M), l_cmd_interval = %d nSec, l_timebase_interval = %d", (uint32_t)l_num_address_bits, (uint32_t)l_num_addresses, (uint32_t)l_cmd_interval, (uint32_t)l_timebase_interval); @@ -1800,10 +1883,7 @@ fapi::ReturnCode mss_MaintCmd::loadSpeed(TimeBaseSpeed i_speed) l_timebase_burst_sel = 0; // Disable burst mode l_burst_window_sel = 0; // Don't care since burst mode disabled l_burst_window = 0; // Don't care since burst mode disabled - l_burst_interval = 0; // Don't care since burst mode disabled - - return l_rc; - + l_burst_interval = 0; // Don't care since burst mode disabled } @@ -1878,7 +1958,7 @@ mss_SuperFastInit::mss_SuperFastInit( const fapi::Target & i_target, i_stopCondition, i_poll, cv_cmdType), - iv_initPattern( i_initPattern ) // NOTE: iv_initPattern is instance + iv_initPattern( i_initPattern ) // NOTE: iv_initPattern is instance // variable of SuperFastInit, since not // needed in parent class {} @@ -1899,7 +1979,7 @@ fapi::ReturnCode mss_SuperFastInit::setupAndExecuteCmd() fapi::ReturnCode l_rc; ecmdDataBufferBase l_data(64); - + // Gather data that needs to be stored. For testing purposes we will just // set an abitrary number. //l_rc = setSavedData( 0xdeadbeef ); if(l_rc) return l_rc; @@ -1908,7 +1988,7 @@ fapi::ReturnCode mss_SuperFastInit::setupAndExecuteCmd() // Make sure maint logic in valid state to run new cmd l_rc = preConditionCheck(); if(l_rc) return l_rc; - + // Load pattern l_rc = loadPattern(iv_initPattern); if(l_rc) return l_rc; @@ -1993,7 +2073,7 @@ fapi::ReturnCode mss_SuperFastRandomInit::setupAndExecuteCmd() fapi::ReturnCode l_rc; uint32_t l_ecmd_rc = 0; - + // Gather data that needs to be stored. For testing purposes we will just // set an abitrary number. //l_rc = setSavedData( 0xdeadbeef ); if(l_rc) return l_rc; @@ -2008,7 +2088,7 @@ fapi::ReturnCode mss_SuperFastRandomInit::setupAndExecuteCmd() // Load cmd type: MBMCTQ l_rc = loadCmdType(); if(l_rc) return l_rc; - + // Load start address: MBMACAQ l_rc = loadStartAddress(); if(l_rc) return l_rc; @@ -2055,7 +2135,7 @@ fapi::ReturnCode mss_SuperFastRandomInit::setupAndExecuteCmd() l_rc = collectFFDC(); if(l_rc) return l_rc; FAPI_INF("EXIT mss_SuperFastRandomInit::setupAndExecuteCmd()"); - + return l_rc; } @@ -2175,7 +2255,7 @@ fapi::ReturnCode mss_SuperFastRead::setupAndExecuteCmd() // Start the command: MBMCCQ l_rc = startMaintCmd(); if(l_rc) return l_rc; - + // Check for early problems with maint cmd instead of waiting for // cmd timeout l_rc = postConditionCheck(); if(l_rc) return l_rc; @@ -2222,21 +2302,19 @@ fapi::ReturnCode mss_SuperFastRead::ueTrappingSetup() // Set bit 9 so that hw will generate the fabric ECC. // This is an 8B ECC protecting the data moving on internal buses in // the Centaur. - l_ecmd_rc |= l_ecc.flushTo0(); l_ecmd_rc |= l_ecc.setBit(9); - + // Load unique pattern into both halves of the maint buffer, + // so we can tell which half contains a trapped UE. + l_ecmd_rc |= l_data.insert(0xFACEB00C, 0, 32, 0); + l_ecmd_rc |= l_data.insert(0xD15C0DAD, 32, 32, 0); + if(l_ecmd_rc) + { + l_rc.setEcmdError(l_ecmd_rc); + return l_rc; + } for(loop=0; loop<2; loop++ ) { - // Load unique pattern into both halves of the maint buffer, - // so we can tell which half contains a trapped UE. - l_ecmd_rc |= l_data.insert(0xFACEB00C, 0, 32, 0); - l_ecmd_rc |= l_data.insert(0xD15C0DAD, 32, 32, 0); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } l_rc = fapiPutScom(iv_targetCentaur, maintBufferDataRegs[iv_mbaPosition][loop][0], l_data); if(l_rc) return l_rc; @@ -2287,7 +2365,7 @@ fapi::ReturnCode mss_SuperFastRead::cleanupCmd() FAPI_INF("EXIT mss_SuperFastRead::cleanupCmd()"); - + return l_rc; } @@ -2328,7 +2406,7 @@ fapi::ReturnCode mss_AtomicInject::setupAndExecuteCmd() FAPI_INF("ENTER mss_AtomicInject::setupAndExecuteCmd()"); fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; + uint32_t l_ecmd_rc = 0; // Gather data that needs to be stored. For testing purposes we will just // set an abitrary number. @@ -2555,20 +2633,20 @@ fapi::ReturnCode mss_IncrementAddress::setupAndExecuteCmd() fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; + uint32_t l_ecmd_rc = 0; ecmdDataBufferBase l_mbspa_mask(64); ecmdDataBufferBase l_mbspa_mask_original(64); - ecmdDataBufferBase l_mbspa_and(64); - + ecmdDataBufferBase l_mbspa_and(64); + // Read MBSPA MASK l_rc = fapiGetScom(iv_target, MBA01_MBSPAMSKQ_0x03010614, l_mbspa_mask); if(l_rc) return l_rc; - + // Save original mask value so we can restore it when done - l_ecmd_rc |= l_mbspa_mask_original.insert(l_mbspa_mask, 0, 64, 0); + l_ecmd_rc |= l_mbspa_mask_original.insert(l_mbspa_mask, 0, 64, 0); // Mask bits 0 and 8, to hide the special attentions when the cmd completes - l_ecmd_rc |= l_mbspa_mask.setBit(0); + l_ecmd_rc |= l_mbspa_mask.setBit(0); l_ecmd_rc |= l_mbspa_mask.setBit(8); if(l_ecmd_rc) { @@ -2579,7 +2657,7 @@ fapi::ReturnCode mss_IncrementAddress::setupAndExecuteCmd() // Write MBSPA MASK l_rc = fapiPutScom(iv_target, MBA01_MBSPAMSKQ_0x03010614, l_mbspa_mask); if(l_rc) return l_rc; - + // Make sure maint logic in valid state to run new cmd l_rc = preConditionCheck(); if(l_rc) return l_rc; @@ -2622,11 +2700,11 @@ fapi::ReturnCode mss_IncrementAddress::setupAndExecuteCmd() // Write MPSPA AND register l_rc = fapiPutScom(iv_target, MBA01_MBSPAQ_AND_0x03010612, l_mbspa_and); if(l_rc) return l_rc; - - // Restore MBSPA MASK + + // Restore MBSPA MASK l_rc = fapiPutScom(iv_target, MBA01_MBSPAMSKQ_0x03010614, l_mbspa_mask_original); if(l_rc) return l_rc; - + FAPI_INF("EXIT mss_IncrementAddress::setupAndExecuteCmd()"); @@ -2702,12 +2780,12 @@ fapi::ReturnCode mss_TimeBaseScrub::setupAndExecuteCmd() FAPI_INF("\nDEBUG. Set hard CE threshold to 1: MBSTRQ"); ecmdDataBufferBase l_data(64); uint32_t l_hardCEThreshold = 1; - l_rc = fapiGetScom(iv_target, MBS01_MBSTRQ_0x02011655, l_data); + l_rc = fapiGetScom(iv_target, MBS01_MBSTRQ_0x02011655, l_data); if(l_rc) return l_rc; l_data.insert( l_hardCEThreshold, 28, 12, 32-12 ); // 28:39 hard ce threshold l_data.setBit(2); // Enable hard ce ETE special attention l_data.setBit(57); // Enable per-symbol counters to count hard ces - l_rc = fapiPutScom(iv_target, MBS01_MBSTRQ_0x02011655, l_data); + l_rc = fapiPutScom(iv_target, MBS01_MBSTRQ_0x02011655, l_data); if(l_rc) return l_rc; */ @@ -2726,7 +2804,7 @@ fapi::ReturnCode mss_TimeBaseScrub::setupAndExecuteCmd() // Poll for command complete: MBMSRQ l_rc = pollForMaintCmdComplete(); if(l_rc) return l_rc; - + // Collect FFDC l_rc = collectFFDC(); if(l_rc) return l_rc; @@ -2776,7 +2854,7 @@ fapi::ReturnCode mss_TimeBaseSteerCleanup::setupAndExecuteCmd() FAPI_INF("ENTER mss_TimeBaseSteerCleanup::setupAndExecuteCmd()"); fapi::ReturnCode l_rc; - + // Gather data that needs to be stored. For testing purposes we will just // set an abitrary number. //l_rc = setSavedData( 0xdeadbeef ); if(l_rc) return l_rc; @@ -2849,7 +2927,7 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, static const uint8_t memConfigType[9][4][2]={ // Refer to Centaur Workbook: 5.2 Master and Slave Rank Usage - // + // // SUBTYPE_A SUBTYPE_B SUBTYPE_C SUBTYPE_D // //SLOT_0_ONLY SLOT_0_AND_1 SLOT_0_ONLY SLOT_0_AND_1 SLOT_0_ONLY SLOT_0_AND_1 SLOT_0_ONLY SLOT_0_AND_1 @@ -2889,7 +2967,7 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, l_rc = fapiGetParentChip(i_target, l_targetCentaur); if(l_rc) { - FAPI_ERR("Error getting Centaur parent target for the given MBA"); + FAPI_ERR("Error getting Centaur parent target for the given MBA on %s.",i_target.toEcmdString()); return l_rc; } @@ -2897,7 +2975,7 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbaPosition); if(l_rc) { - FAPI_ERR("Error getting MBA position"); + FAPI_ERR("Error getting MBA position on %s.",i_target.toEcmdString()); return l_rc; } @@ -2905,7 +2983,7 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, l_rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, l_isSIM); if(l_rc) { - FAPI_ERR("Error getting ATTR_IS_SIMULATION"); + FAPI_ERR("Error getting ATTR_IS_SIMULATION on %s.",i_target.toEcmdString()); return l_rc; } @@ -2913,7 +2991,7 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, l_rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_dramWidth); if(l_rc) { - FAPI_ERR("Error getting DRAM width"); + FAPI_ERR("Error getting DRAM width on %s.",i_target.toEcmdString()); return l_rc; } @@ -2922,7 +3000,7 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, if(l_rc) return l_rc; if (l_data.isBitClear(0,4)) { - FAPI_ERR("MBAXCRn[0:3] = 0, meaning no memory configured behind this MBA."); + FAPI_ERR("MBAXCRn[0:3] = 0, meaning no memory configured behind this MBA on %s.",i_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target @@ -2997,15 +3075,16 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, } else { - FAPI_ERR("Invalid l_dramSize = %d or l_dramWidth = %d in MBAXCRn.", l_dramSize, l_dramWidth ); + FAPI_ERR("Invalid l_dramSize = %d or l_dramWidth = %d in MBAXCRn on %s.", l_dramSize, l_dramWidth, i_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target const fapi::Target & MBA = i_target; // FFDC: Capture register we are checking ecmdDataBufferBase & MBAXCR = l_data; - - // Create new log. + // FFDC: DRAM width + uint8_t DRAM_WIDTH = l_dramWidth; + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_DRAM_SIZE_WIDTH); return l_rc; } @@ -3021,7 +3100,7 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, // (4:5) Configuration subtype (A, B, C, D) l_ecmd_rc |= l_data.extractPreserve(&l_configSubType, 4, 2, 8-2); - // (8) Slot Configuration + // (8) Slot Configuration // 0 = Centaur DIMM or IS DIMM, slot0 only, 1 = IS DIMM slots 0 and 1 l_ecmd_rc |= l_data.extractPreserve(&l_slotConfig, 8, 1, 8-1); if(l_ecmd_rc) @@ -3042,7 +3121,7 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, if ((l_end_master_rank == 0x0f) || (l_end_slave_rank == 0x0f)) { - FAPI_ERR("MBAXCRn configured with unsupported combination of l_configType, l_configSubType, l_slotConfig"); + FAPI_ERR("MBAXCRn configured with unsupported combination of l_configType, l_configSubType, l_slotConfig on %s.",i_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target @@ -3085,12 +3164,12 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, l_ecmd_rc |= o_endAddr.insert( l_end_slave_rank, 4, 3, 8-3 ); // BANK = 7:10 - l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_bank, 7, 4, 32-4 ); + l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_bank, 7, 4, 32-4 ); // ROW = 11:27 l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_row_zero, 11, 17, 32-17 ); - // COL = 28:39, note: c2, c1, c0 always 0 + // COL = 28:39, note: c2, c1, c0 always 0 l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_col, 28, 12, 32-12 ); @@ -3127,16 +3206,16 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, // Check for i_rank out of range if (i_rank>=8) { - FAPI_ERR("i_rank input to mss_get_address_range out of range"); + FAPI_ERR("i_rank input to mss_get_address_range out of range on %s.",i_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target const fapi::Target & MBA = i_target; // FFDC: Capture i_rank; uint8_t RANK = i_rank; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_GET_ADDRESS_RANGE_BAD_INPUT); - return l_rc; + return l_rc; } // NOTE: If this rank is not valid, we should see MBAFIR[1]: invalid @@ -3258,7 +3337,7 @@ fapi::ReturnCode mss_get_mark_store( const fapi::Target & i_target, l_rc = fapiGetParentChip(i_target, l_targetCentaur); if(l_rc) { - FAPI_ERR("Error getting Centaur parent target for the given MBA"); + FAPI_ERR("Error getting Centaur parent target for the given MBA on %s.",i_target.toEcmdString()); return l_rc; } @@ -3267,7 +3346,7 @@ fapi::ReturnCode mss_get_mark_store( const fapi::Target & i_target, l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbaPosition); if(l_rc) { - FAPI_ERR("Error getting MBA position"); + FAPI_ERR("Error getting MBA position on %s.",i_target.toEcmdString()); return l_rc; } @@ -3275,23 +3354,23 @@ fapi::ReturnCode mss_get_mark_store( const fapi::Target & i_target, l_rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_dramWidth); if(l_rc) { - FAPI_ERR("Error getting DRAM width"); + FAPI_ERR("Error getting DRAM width on %s.",i_target.toEcmdString()); return l_rc; } // Check for i_rank out of range if (i_rank>=8) { - FAPI_ERR("i_rank input to mss_get_mark_store out of range"); + FAPI_ERR("i_rank input to mss_get_mark_store out of range on %s.",i_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target const fapi::Target & MBA = i_target; // FFDC: Capture i_rank; uint8_t RANK = i_rank; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_GET_MARK_STORE_BAD_INPUT); - return l_rc; + return l_rc; } // Read markstore register for the given rank @@ -3318,11 +3397,11 @@ fapi::ReturnCode mss_get_mark_store( const fapi::Target & i_target, if (l_symbolMarkGalois == 0x00) // No symbol mark { - o_symbolMark = MSS_INVALID_SYMBOL; + o_symbolMark = MSS_INVALID_SYMBOL; } else if (l_dramWidth == mss_MemConfig::X4) { - FAPI_ERR("l_symbolMarkGalois invalid: symbol mark not allowed in x4 mode."); + FAPI_ERR("l_symbolMarkGalois invalid: symbol mark not allowed in x4 mode on %s.",i_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target @@ -3352,7 +3431,7 @@ fapi::ReturnCode mss_get_mark_store( const fapi::Target & i_target, if ( MSS_SYMBOLS_PER_RANK <= o_symbolMark ) { - FAPI_ERR("Invalid galois field in markstore."); + FAPI_ERR("Invalid galois field in markstore on %s.",i_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target @@ -3364,7 +3443,7 @@ fapi::ReturnCode mss_get_mark_store( const fapi::Target & i_target, // FFDC: Capture markstore ecmdDataBufferBase & MARKSTORE = l_markstore; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_MARKSTORE); return l_rc; } @@ -3381,7 +3460,7 @@ fapi::ReturnCode mss_get_mark_store( const fapi::Target & i_target, if (l_chipMarkGalois == 0x00) // No chip mark { - o_chipMark = MSS_INVALID_SYMBOL; + o_chipMark = MSS_INVALID_SYMBOL; } else // Converted from galois field to chip index { @@ -3407,7 +3486,7 @@ fapi::ReturnCode mss_get_mark_store( const fapi::Target & i_target, if ( MSS_SYMBOLS_PER_RANK <= o_chipMark ) { - FAPI_ERR("Invalid galois field in markstore."); + FAPI_ERR("Invalid galois field in markstore on %s.",i_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target @@ -3419,7 +3498,7 @@ fapi::ReturnCode mss_get_mark_store( const fapi::Target & i_target, // FFDC: Capture markstore ecmdDataBufferBase & MARKSTORE = l_markstore; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_MARKSTORE); return l_rc; } @@ -3427,7 +3506,7 @@ fapi::ReturnCode mss_get_mark_store( const fapi::Target & i_target, FAPI_INF("mss_get_mark_store(): rank%d, chip mark = %d, symbol mark = %d", i_rank, o_chipMark, o_symbolMark ); - + return l_rc; } @@ -3460,7 +3539,7 @@ fapi::ReturnCode mss_put_mark_store( const fapi::Target & i_target, l_rc = fapiGetParentChip(i_target, l_targetCentaur); if(l_rc) { - FAPI_ERR("Error getting Centaur parent target for the given MBA"); + FAPI_ERR("Error getting Centaur parent target for the given MBA on %s.",i_target.toEcmdString()); return l_rc; } @@ -3469,7 +3548,7 @@ fapi::ReturnCode mss_put_mark_store( const fapi::Target & i_target, l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbaPosition); if(l_rc) { - FAPI_ERR("Error getting MBA position"); + FAPI_ERR("Error getting MBA position on %s.",i_target.toEcmdString()); return l_rc; } @@ -3478,24 +3557,24 @@ fapi::ReturnCode mss_put_mark_store( const fapi::Target & i_target, l_rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_dramWidth); if(l_rc) { - FAPI_ERR("Error getting DRAM width"); + FAPI_ERR("Error getting DRAM width on %s.",i_target.toEcmdString()); return l_rc; } - + // Check for i_rank out of range if (i_rank>=8) { - FAPI_ERR("i_rank input to mss_put_mark_store out of range"); + FAPI_ERR("i_rank input to mss_put_mark_store out of range on %s.",i_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target const fapi::Target & MBA = i_target; // FFDC: Capture i_rank; uint8_t RANK = i_rank; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_PUT_MARK_STORE_BAD_INPUT); - return l_rc; - } + return l_rc; + } // Get l_symbolMarkGalois if (i_symbolMark == MSS_INVALID_SYMBOL) // No symbol mark @@ -3504,7 +3583,7 @@ fapi::ReturnCode mss_put_mark_store( const fapi::Target & i_target, } else if ( l_dramWidth == mss_MemConfig::X4 ) { - FAPI_ERR("i_symbolMark invalid: symbol mark not allowed in x4 mode."); + FAPI_ERR("i_symbolMark invalid: symbol mark not allowed in x4 mode on %s.",i_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target @@ -3524,7 +3603,7 @@ fapi::ReturnCode mss_put_mark_store( const fapi::Target & i_target, } else if ( MSS_SYMBOLS_PER_RANK <= i_symbolMark ) { - FAPI_ERR("i_symbolMark invalid: symbol index out of range."); + FAPI_ERR("i_symbolMark invalid: symbol index out of range on %s.",i_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target @@ -3556,7 +3635,7 @@ fapi::ReturnCode mss_put_mark_store( const fapi::Target & i_target, } else if ( MSS_SYMBOLS_PER_RANK <= i_chipMark ) { - FAPI_ERR("i_chipMark invalid: symbol index out of range."); + FAPI_ERR("i_chipMark invalid: symbol index out of range on %s.",i_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target @@ -3570,13 +3649,13 @@ fapi::ReturnCode mss_put_mark_store( const fapi::Target & i_target, // FFDC: Capure i_chipMark; uint8_t CHIP_MARK = i_chipMark; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_INDEX); return l_rc; } else if ((l_dramWidth == mss_MemConfig::X8) && (i_chipMark % 4) ) { - FAPI_ERR("i_chipMark invalid: not first symbol index of a x8 chip."); + FAPI_ERR("i_chipMark invalid: not first symbol index of a x8 chip on %s.",i_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target @@ -3597,7 +3676,7 @@ fapi::ReturnCode mss_put_mark_store( const fapi::Target & i_target, } else if ((l_dramWidth == mss_MemConfig::X4) && (i_chipMark % 2) ) { - FAPI_ERR("i_chipMark invalid: not first symbol index of a x4 chip."); + FAPI_ERR("i_chipMark invalid: not first symbol index of a x4 chip on %s.",i_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target @@ -3639,8 +3718,8 @@ fapi::ReturnCode mss_put_mark_store( const fapi::Target & i_target, { // TODO: Can FW distingish this rc from all the others // so they know they just need to retry after clearing MPR FIR? - - FAPI_ERR("Markstore write may have been blocked due to MPE FIR set."); + + FAPI_ERR("Markstore write may have been blocked due to MPE FIR set on %s.",i_target.toEcmdString()); // FFDC: MBA target const fapi::Target & MBA = i_target; @@ -3654,7 +3733,7 @@ fapi::ReturnCode mss_put_mark_store( const fapi::Target & i_target, uint8_t CHIP_MARK = i_chipMark; // FFDC: Capture MBECCFIR ecmdDataBufferBase & MBECCFIR = l_mbeccfir; - + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_MARKSTORE_WRITE_BLOCKED); return l_rc; @@ -3692,13 +3771,13 @@ fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target, o_dramSparePort0Symbol = MSS_INVALID_SYMBOL; o_dramSparePort1Symbol = MSS_INVALID_SYMBOL; - o_eccSpareSymbol = MSS_INVALID_SYMBOL; + o_eccSpareSymbol = MSS_INVALID_SYMBOL; // Get Centaur target for the given MBA l_rc = fapiGetParentChip(i_target, l_targetCentaur); if(l_rc) { - FAPI_ERR("Error getting Centaur parent target for the given MBA"); + FAPI_ERR("Error getting Centaur parent target for the given MBA on %s.",i_target.toEcmdString()); return l_rc; } @@ -3707,7 +3786,7 @@ fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target, l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbaPosition); if(l_rc) { - FAPI_ERR("Error getting MBA position"); + FAPI_ERR("Error getting MBA position on %s.",i_target.toEcmdString()); return l_rc; } @@ -3715,27 +3794,27 @@ fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target, l_rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_dramWidth); if(l_rc) { - FAPI_ERR("Error getting DRAM width"); + FAPI_ERR("Error getting DRAM width on %s.",i_target.toEcmdString()); return l_rc; } // Check for i_rank or i_muxType out of range - if ((i_rank>=8) || + if ((i_rank>=8) || !((i_muxType==mss_SteerMux::READ_MUX) || (i_muxType==mss_SteerMux::WRITE_MUX))) { - FAPI_ERR("i_rank or i_muxType input to mss_get_steer_mux out of range"); + FAPI_ERR("i_rank or i_muxType input to mss_get_steer_mux out of range on %s.",i_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target const fapi::Target & MBA = i_target; // FFDC: Capture i_rank; uint8_t RANK = i_rank; // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; + uint8_t MUX_TYPE = i_muxType; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_GET_STEER_MUX_BAD_INPUT); - return l_rc; + return l_rc; } @@ -3773,8 +3852,8 @@ fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target, } else { - FAPI_ERR("Steer mux l_dramSparePort0Index out of range."); - + FAPI_ERR("Steer mux l_dramSparePort0Index out of range on %s.",i_target.toEcmdString()); + // TODO: Calling out FW high // FFDC: MBA target const fapi::Target & MBA = i_target; @@ -3783,13 +3862,13 @@ fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target, // FFDC: Capure i_rank; uint8_t RANK = i_rank; // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; + uint8_t MUX_TYPE = i_muxType; // FFDC: Capture steer mux ecmdDataBufferBase & STEER_MUX = l_steerMux; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_STEER_MUX); - return l_rc; + return l_rc; } @@ -3813,8 +3892,8 @@ fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target, } else { - FAPI_ERR("Steer mux l_dramSparePort1Index out of range."); - + FAPI_ERR("Steer mux l_dramSparePort1Index out of range on %s.",i_target.toEcmdString()); + // TODO: Calling out FW high // FFDC: MBA target const fapi::Target & MBA = i_target; @@ -3823,13 +3902,13 @@ fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target, // FFDC: Capure i_rank; uint8_t RANK = i_rank; // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; + uint8_t MUX_TYPE = i_muxType; // FFDC: Capture steer mux ecmdDataBufferBase & STEER_MUX = l_steerMux; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_STEER_MUX); - return l_rc; + return l_rc; } @@ -3849,8 +3928,8 @@ fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target, } else { - FAPI_ERR("o_eccSpareSymbol out of range."); - + FAPI_ERR("o_eccSpareSymbol out of range on %s.",i_target.toEcmdString()); + // TODO: Calling out FW high // FFDC: MBA target const fapi::Target & MBA = i_target; @@ -3859,13 +3938,13 @@ fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target, // FFDC: Capure i_rank; uint8_t RANK = i_rank; // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; + uint8_t MUX_TYPE = i_muxType; // FFDC: Capture steer mux ecmdDataBufferBase & STEER_MUX = l_steerMux; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_STEER_MUX); - return l_rc; + return l_rc; } FAPI_INF("mss_get_steer_mux(): rank%d, port0 steer = %d, port1 steer = %d, ecc steer = %d", @@ -3911,7 +3990,7 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, l_rc = fapiGetParentChip(i_target, l_targetCentaur); if(l_rc) { - FAPI_ERR("Error getting Centaur parent target for the given MBA"); + FAPI_ERR("Error getting Centaur parent target for the given MBA on %s.",i_target.toEcmdString()); return l_rc; } @@ -3920,7 +3999,7 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbaPosition); if(l_rc) { - FAPI_ERR("Error getting MBA position"); + FAPI_ERR("Error getting MBA position on %s.",i_target.toEcmdString()); return l_rc; } @@ -3928,33 +4007,33 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, l_rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_dramWidth); if(l_rc) { - FAPI_ERR("Error getting DRAM width"); + FAPI_ERR("Error getting DRAM width on %s.",i_target.toEcmdString()); return l_rc; } // Check for i_rank or i_muxType or i_steerType or i_symbol out of range - if ((i_rank>=8) || + if ((i_rank>=8) || !((i_muxType==mss_SteerMux::READ_MUX) || (i_muxType==mss_SteerMux::WRITE_MUX)) || !((i_steerType == mss_SteerMux::DRAM_SPARE_PORT0) || (i_steerType == mss_SteerMux::DRAM_SPARE_PORT1) || (i_steerType == mss_SteerMux::ECC_SPARE)) || (i_symbol >= 72)) { - FAPI_ERR("i_rank or i_muxType or i_steerType or i_symbol input to mss_get_steer_mux out of range"); + FAPI_ERR("i_rank or i_muxType or i_steerType or i_symbol input to mss_get_steer_mux out of range on %s.",i_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target const fapi::Target & MBA = i_target; // FFDC: Capture i_rank; uint8_t RANK = i_rank; // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; + uint8_t MUX_TYPE = i_muxType; // FFDC: Capure i_steerType - uint8_t STEER_TYPE = i_steerType; + uint8_t STEER_TYPE = i_steerType; // FFDC: Capure i_symbol - uint8_t SYMBOL = i_symbol; + uint8_t SYMBOL = i_symbol; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_PUT_STEER_MUX_BAD_INPUT); - return l_rc; + return l_rc; } @@ -3990,8 +4069,8 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, if ( MSS_X8_STEER_OPTIONS_PER_PORT <= l_dramSparePort0Index ) { - FAPI_ERR("No match for i_symbol = %d in mss_x8dramSparePort0Index_to_symbol[].", i_symbol); - + FAPI_ERR("No match for i_symbol = %d in mss_x8dramSparePort0Index_to_symbol[] on %s.", i_symbol, i_target.toEcmdString()); + // TODO: Calling out FW high // FFDC: MBA target const fapi::Target & MBA = i_target; @@ -4000,13 +4079,13 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, // FFDC: Capure i_rank; uint8_t RANK = i_rank; // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; + uint8_t MUX_TYPE = i_muxType; // FFDC: Capure i_steerType - uint8_t STEER_TYPE = i_steerType; + uint8_t STEER_TYPE = i_steerType; // FFDC: Capure i_symbol - uint8_t SYMBOL = i_symbol; + uint8_t SYMBOL = i_symbol; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER); return l_rc; } @@ -4026,7 +4105,7 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, if ( MSS_X4_STEER_OPTIONS_PER_PORT0 <= l_dramSparePort0Index ) { - FAPI_ERR("No match for i_symbol in mss_x4dramSparePort0Index_to_symbol[]."); + FAPI_ERR("No match for i_symbol in mss_x4dramSparePort0Index_to_symbol[] on %s.",i_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target @@ -4036,13 +4115,13 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, // FFDC: Capure i_rank; uint8_t RANK = i_rank; // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; + uint8_t MUX_TYPE = i_muxType; // FFDC: Capure i_steerType - uint8_t STEER_TYPE = i_steerType; + uint8_t STEER_TYPE = i_steerType; // FFDC: Capure i_symbol - uint8_t SYMBOL = i_symbol; + uint8_t SYMBOL = i_symbol; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER); return l_rc; } @@ -4069,7 +4148,7 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, if ( MSS_X8_STEER_OPTIONS_PER_PORT <= l_dramSparePort1Index ) { - FAPI_ERR("No match for i_symbol in mss_x8dramSparePort1Index_to_symbol[]."); + FAPI_ERR("No match for i_symbol in mss_x8dramSparePort1Index_to_symbol[] on %s.",i_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target @@ -4079,13 +4158,13 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, // FFDC: Capure i_rank; uint8_t RANK = i_rank; // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; + uint8_t MUX_TYPE = i_muxType; // FFDC: Capure i_steerType - uint8_t STEER_TYPE = i_steerType; + uint8_t STEER_TYPE = i_steerType; // FFDC: Capure i_symbol - uint8_t SYMBOL = i_symbol; + uint8_t SYMBOL = i_symbol; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER); return l_rc; } @@ -4105,7 +4184,7 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, if ( MSS_X4_STEER_OPTIONS_PER_PORT1 <= l_dramSparePort1Index ) { - FAPI_ERR("No match for i_symbol in mss_x4dramSparePort1Index_to_symbol[]."); + FAPI_ERR("No match for i_symbol in mss_x4dramSparePort1Index_to_symbol[] on %s.",i_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target @@ -4115,13 +4194,13 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, // FFDC: Capure i_rank; uint8_t RANK = i_rank; // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; + uint8_t MUX_TYPE = i_muxType; // FFDC: Capure i_steerType - uint8_t STEER_TYPE = i_steerType; + uint8_t STEER_TYPE = i_steerType; // FFDC: Capure i_symbol - uint8_t SYMBOL = i_symbol; + uint8_t SYMBOL = i_symbol; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER); return l_rc; } @@ -4149,7 +4228,7 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, if ( MSS_X4_ECC_STEER_OPTIONS <= l_eccSpareIndex ) { - FAPI_ERR("No match for i_symbol in mss_eccSpareIndex_to_symbol[]."); + FAPI_ERR("No match for i_symbol in mss_eccSpareIndex_to_symbol[] on %s.",i_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target @@ -4159,20 +4238,20 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, // FFDC: Capure i_rank; uint8_t RANK = i_rank; // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; + uint8_t MUX_TYPE = i_muxType; // FFDC: Capure i_steerType - uint8_t STEER_TYPE = i_steerType; + uint8_t STEER_TYPE = i_steerType; // FFDC: Capure i_symbol - uint8_t SYMBOL = i_symbol; + uint8_t SYMBOL = i_symbol; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER); return l_rc; } } else if (l_dramWidth == mss_MemConfig::X8) { - FAPI_ERR("ECC_SPARE not valid with x8 mode."); + FAPI_ERR("ECC_SPARE not valid with x8 mode on %s.",i_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target @@ -4182,13 +4261,13 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, // FFDC: Capure i_rank; uint8_t RANK = i_rank; // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; + uint8_t MUX_TYPE = i_muxType; // FFDC: Capure i_steerType - uint8_t STEER_TYPE = i_steerType; + uint8_t STEER_TYPE = i_steerType; // FFDC: Capure i_symbol - uint8_t SYMBOL = i_symbol; + uint8_t SYMBOL = i_symbol; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_NO_X8_ECC_SPARE); return l_rc; } @@ -4263,12 +4342,12 @@ fapi::ReturnCode mss_do_steering(const fapi::Target & i_target, uint8_t l_steerType = 0; // 0 = DRAM_SPARE_PORT0, Spare DRAM on port0 // 1 = DRAM_SPARE_PORT1, Spare DRAM on port1 // 2 = ECC_SPARE, ECC spare (used in x4 mode only) - + // Check for i_rank or i_symbol out of range - if ((i_rank>=8) || (i_symbol>=72)) + if ((i_rank>=MSS_MAX_RANKS) || (i_symbol>=MSS_SYMBOLS_PER_RANK)) { - FAPI_ERR("i_rank or i_symbol input to mss_do_steer out of range"); + FAPI_ERR("i_rank or i_symbol input to mss_do_steer out of range on %s.",i_target.toEcmdString()); // TODO: Calling out FW high // FFDC: MBA target const fapi::Target & MBA = i_target; @@ -4277,81 +4356,82 @@ fapi::ReturnCode mss_do_steering(const fapi::Target & i_target, // FFDC: Capture i_symbol; uint8_t SYMBOL = i_symbol; // FFDC: Capture i_x4EccSpare - uint8_t X4ECCSPARE = i_x4EccSpare; + uint8_t X4ECCSPARE = i_x4EccSpare; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_DO_STEER_INPUT_OUT_OF_RANGE); - return l_rc; + return l_rc; } //------------------------------------------------------ // Determine l_steerType - //------------------------------------------------------ + //------------------------------------------------------ if (i_x4EccSpare) { l_steerType = mss_SteerMux::ECC_SPARE; } else - { - // Symbols 71-40, 7-4 come from port0 - if (((i_symbol<=71)&&(i_symbol>=40)) || ((i_symbol<=7)&&(i_symbol>=4))) + { + // Symbols 71-40, 7-4 come from port0 + if (((i_symbol<=MSS_PORT_0_SYMBOL_71)&&(i_symbol>=MSS_PORT_0_SYMBOL_40)) || + ((i_symbol<=MSS_PORT_0_SYMBOL_7)&&(i_symbol>=MSS_PORT_0_SYMBOL_4))) { l_steerType = mss_SteerMux::DRAM_SPARE_PORT0; } - // Symbols 39-8, 3-0 come from port1 + // Symbols 39-8, 3-0 come from port1 else { - l_steerType = mss_SteerMux::DRAM_SPARE_PORT1; - } + l_steerType = mss_SteerMux::DRAM_SPARE_PORT1; + } } //------------------------------------------------------ // Update write mux //------------------------------------------------------ l_rc = mss_put_steer_mux( - + i_target, // MBA i_rank, // Master rank: 0-7 mss_SteerMux::WRITE_MUX,// write mux l_steerType, // DRAM_SPARE_PORT0/DRAM_SPARE_PORT1/ECC_SPARE i_symbol); // First symbol index of DRAM to steer around - + if (l_rc) { - FAPI_ERR("Error updating write mux"); + FAPI_ERR("Error updating write mux on %s.",i_target.toEcmdString()); return l_rc; } //------------------------------------------------------ // Wait for a periodic cal. - //------------------------------------------------------ + //------------------------------------------------------ // 250 ms delay for HW mode const uint64_t HW_MODE_DELAY = 250000000; - - // 200000 sim cycle delay for SIM mode - const uint64_t SIM_MODE_DELAY = 200000; - + + // 200000 sim cycle delay for SIM mode + const uint64_t SIM_MODE_DELAY = 200000; + fapiDelay(HW_MODE_DELAY, SIM_MODE_DELAY); - + // TODO: Could be precise and find cal interval from: // ATTR_EFF_ZQCAL_INTERVAL (in clocks... so still have to know freq) - // ATTR_EFF_MEMCAL_INTERVAL (in clocks... so still have to know freq) + // ATTR_EFF_MEMCAL_INTERVAL (in clocks... so still have to know freq) //------------------------------------------------------ // Update read mux - //------------------------------------------------------ + //------------------------------------------------------ l_rc = mss_put_steer_mux( - + i_target, // MBA i_rank, // Master rank: 0-7 mss_SteerMux::READ_MUX, // read mux l_steerType, // DRAM_SPARE_PORT0/DRAM_SPARE_PORT1/ECC_SPARE i_symbol); // First symbol index of DRAM to steer around - + if (l_rc) { - FAPI_ERR("Error updating read mux"); + FAPI_ERR("Error updating read mux on %s.",i_target.toEcmdString()); return l_rc; } @@ -4386,7 +4466,6 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, uint8_t l_dq_pair_index = 0; uint8_t l_bad_dq_pair_index = 0; uint8_t l_bad_dq_pair_count=0; - uint8_t __attribute__((unused)) l_bad_dq_pair = 0xff; // HACK. uint8_t l_dq_pair_mask = 0xC0; uint8_t l_byte_being_steered = 0xff; uint8_t l_bad_symbol = MSS_INVALID_SYMBOL; @@ -4456,7 +4535,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, l_rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_dramWidth); if(l_rc) { - FAPI_ERR("Error getting DRAM width"); + FAPI_ERR("Error getting DRAM width on %s.",i_target.toEcmdString()); return l_rc; } @@ -4464,7 +4543,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, l_rc = FAPI_ATTR_GET(ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR, &i_target, l_valid_dimms); if (l_rc) { - FAPI_ERR("Failed to get attribute: ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR"); + FAPI_ERR("Failed to get attribute: ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR on %s.",i_target.toEcmdString()); return l_rc; } l_valid_dimm[0][0] = (l_valid_dimms & 0x80); // port0, dimm0 @@ -4478,7 +4557,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, { // For each DIMM select on the given port:0,1 for(l_dimm=0; l_dimm<DIMM_DQ_MAX_MBAPORT_DIMMS; l_dimm++ ) - { + { if (l_valid_dimm[l_port][l_dimm]) { // For each rank select on the given DIMM select:0,1,2,3 @@ -4494,7 +4573,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, l_dqBitmap); if (l_rc) { - FAPI_ERR("Error from dimmGetBadDqBitmap"); + FAPI_ERR("Error from dimmGetBadDqBitmap on %s.",i_target.toEcmdString()); return l_rc; } @@ -4520,7 +4599,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, if (l_rc) { - FAPI_ERR("Error reading markstore"); + FAPI_ERR("Error reading markstore on %s.",i_target.toEcmdString()); return l_rc; } @@ -4530,9 +4609,6 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, // Check if symbol mark used (may have been used on other port) l_symbol_mark_used = l_symbol_mark != MSS_INVALID_SYMBOL; - // Initialize to no bad dq pair found yet - l_bad_dq_pair = 0xff; - // For each byte 0-9, where 9 is the spare for(l_byte=0; l_byte<DIMM_DQ_RANK_BITMAP_SIZE; l_byte++ ) { @@ -4566,18 +4642,18 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, // Record bad dq pair - just most recent if multiple bad l_bad_dq_pair_index = l_dq_pair_index; - l_bad_dq_pair = 8*l_byte + 2*l_bad_dq_pair_index; } // Shift mask to next symbol l_dq_pair_mask = l_dq_pair_mask >> 2; } - // If spare is bad but not used, not valid to try repair + // If spare is bad but not used, not valid to try repair if ( l_spare_exists && (l_byte==9) && (l_bad_dq_pair_count > 0) && !l_spare_used) { - FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, Bad unused spare - no valid repair", - l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); + FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); + FAPI_ERR("WARNING: Bad unused spare - no valid repair on %s", i_target.toEcmdString()); + break; } @@ -4602,7 +4678,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, if (l_rc) { - FAPI_ERR("Error updating read mux"); + FAPI_ERR("Error updating read mux on %s.",i_target.toEcmdString()); return l_rc; } @@ -4618,7 +4694,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, if (l_rc) { - FAPI_ERR("Error updating write mux"); + FAPI_ERR("Error updating write mux on %s.",i_target.toEcmdString()); return l_rc; } @@ -4627,7 +4703,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, // Remember which byte is being steered // so we know where to apply chip or symbol mark - // if spare turns out to be bad + // if spare turns out to be bad l_byte_being_steered = l_byte; // Update which rank 0-7 has had repairs applied @@ -4641,8 +4717,9 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, o_repairs_exceeded |= l_repairs_exceeded_translation[1][l_dimm]; } - FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, symbols %d-%d, FIXED CHIP WITH X8 STEER", - l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte], 8*l_byte, 8*l_byte+7,l_bad_symbol, l_bad_symbol+3 ); + FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); + FAPI_ERR("WARNING: dq %d-%d, symbols %d-%d, FIXED CHIP WITH X8 STEER on %s", + 8*l_byte, 8*l_byte+7,l_bad_symbol, l_bad_symbol+3, i_target.toEcmdString()); } @@ -4664,7 +4741,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, if (l_rc) { - FAPI_ERR("Error reading markstore"); + FAPI_ERR("Error reading markstore on %s.",i_target.toEcmdString()); return l_rc; } @@ -4675,7 +4752,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, if (l_byte==9) { l_chip_mark = mss_centaurDQ_to_symbol(8*l_byte_being_steered,l_port) - 3; - FAPI_ERR("WARNING: Bad spare so chip mark goes on l_byte_being_steered = %d", l_byte_being_steered); + FAPI_ERR("WARNING: Bad spare so chip mark goes on l_byte_being_steered = %d on %s", l_byte_being_steered ,i_target.toEcmdString()); } else @@ -4693,7 +4770,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, if (l_rc) { - FAPI_ERR("Error updating markstore"); + FAPI_ERR("Error updating markstore on %s.",i_target.toEcmdString()); return l_rc; } @@ -4711,17 +4788,19 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, o_repairs_exceeded |= l_repairs_exceeded_translation[1][l_dimm]; } - FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, symbols %d-%d, FIXED CHIP WITH X8 CHIP MARK", - l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte], 8*l_byte, 8*l_byte+7,l_chip_mark, l_chip_mark+3 ); + FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); + FAPI_ERR("WARNING: dq %d-%d, symbols %d-%d, FIXED CHIP WITH X8 CHIP MARK on %s", + 8*l_byte, 8*l_byte+7,l_chip_mark, l_chip_mark+3 ,i_target.toEcmdString()); - } + } + // Else, more bad bits than we can repair so update o_repairs_exceeded else { - o_repairs_exceeded |= l_repairs_exceeded_translation[l_port][l_dimm]; + o_repairs_exceeded |= l_repairs_exceeded_translation[l_port][l_dimm]; - l_repair_status[l_port][l_dimm][l_rank]=MSS_REPAIRS_EXCEEDED; + l_repair_status[l_port][l_dimm][l_rank]=MSS_REPAIRS_EXCEEDED; // If port1 repairs exceeded and port0 had a repair, say port0 repairs exceeded too if ((l_repair_status[1][l_dimm][l_rank] == MSS_REPAIRS_EXCEEDED) && (l_repair_status[0][l_dimm][l_rank] == MSS_REPAIRS_APPLIED)) @@ -4729,14 +4808,15 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, o_repairs_exceeded |= l_repairs_exceeded_translation[0][l_dimm]; } - FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, REPAIRS EXCEEDED", - l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte], 8*l_byte, 8*l_byte+7); + FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x",l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); + FAPI_ERR("WARNING: dq %d-%d, REPAIRS EXCEEDED %s", 8*l_byte, 8*l_byte+7, i_target.toEcmdString()); + // Break out of loop on bytes break; } - } // End If bad symbol count > 1 + } // End If bad symbol count > 1 //Else if bad symbol count = 1 @@ -4746,7 +4826,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, if (!l_symbol_mark_used) { - // NOTE: Have to do a read/modify/write so we + // NOTE: Have to do a read/modify/write so we // only update symbol mark, and don't overwrite // chip mark. @@ -4760,7 +4840,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, if (l_rc) { - FAPI_ERR("Error reading markstore"); + FAPI_ERR("Error reading markstore on %s.",i_target.toEcmdString()); return l_rc; } @@ -4770,7 +4850,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, if (l_byte==9) { l_symbol_mark = mss_centaurDQ_to_symbol(8*l_byte_being_steered + 2*l_bad_dq_pair_index,l_port); - FAPI_ERR("WARNING: Bad spare so symbol mark goes on l_byte_being_steered = %d", l_byte_being_steered); + FAPI_ERR("WARNING: Bad spare so symbol mark goes on l_byte_being_steered = %d on %s", l_byte_being_steered, i_target.toEcmdString()); } else @@ -4789,7 +4869,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, if (l_rc) { - FAPI_ERR("Error updating markstore"); + FAPI_ERR("Error updating markstore on %s.",i_target.toEcmdString()); return l_rc; } @@ -4807,11 +4887,9 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, o_repairs_exceeded |= l_repairs_exceeded_translation[1][l_dimm]; } - FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, symbol %d, FIXED SYMBOL WITH X2 SYMBOL MARK", - l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte], - 8*l_byte + 2*l_bad_dq_pair_index, 8*l_byte + 2*l_bad_dq_pair_index + 1, - l_symbol_mark ); - + FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); + FAPI_ERR("WARNING: dq %d-%d, symbol %d, FIXED SYMBOL WITH X2 SYMBOL MARK on %s", + 8*l_byte + 2*l_bad_dq_pair_index, 8*l_byte + 2*l_bad_dq_pair_index + 1, l_symbol_mark, i_target.toEcmdString()); } @@ -4832,7 +4910,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, if (l_rc) { - FAPI_ERR("Error updating read mux"); + FAPI_ERR("Error updating read mux on %s.",i_target.toEcmdString()); return l_rc; } @@ -4848,7 +4926,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, if (l_rc) { - FAPI_ERR("Error updating write mux"); + FAPI_ERR("Error updating write mux on %s.",i_target.toEcmdString()); return l_rc; } @@ -4857,7 +4935,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, // Remember which byte is being steered // so we where to apply chip or symbol mark - // if spare turns out to be bad + // if spare turns out to be bad l_byte_being_steered = l_byte; // Update which rank 0-7 has had repairs applied @@ -4871,11 +4949,11 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, o_repairs_exceeded |= l_repairs_exceeded_translation[1][l_dimm]; } - FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, symbols %d-%d, FIXED SYMBOL WITH X8 STEER", - l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte], - 8*l_byte + 2*l_bad_dq_pair_index, 8*l_byte + 2*l_bad_dq_pair_index + 1, - l_bad_symbol, - l_bad_symbol + 3); + FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); + FAPI_ERR("WARNING: dq %d-%d, symbols %d-%d, FIXED SYMBOL WITH X8 STEER on %s", + 8*l_byte + 2*l_bad_dq_pair_index, 8*l_byte + 2*l_bad_dq_pair_index + 1, l_bad_symbol, l_bad_symbol + 3, i_target.toEcmdString()); + + } @@ -4883,7 +4961,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, else if (!l_chip_mark_used) { - // NOTE: Have to do a read/modify/write so we + // NOTE: Have to do a read/modify/write so we // only update chip mark, and don't overwrite // symbol mark. @@ -4897,7 +4975,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, if (l_rc) { - FAPI_ERR("Error reading markstore"); + FAPI_ERR("Error reading markstore on %s.",i_target.toEcmdString()); return l_rc; } @@ -4908,7 +4986,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, if (l_byte==9) { l_chip_mark = mss_centaurDQ_to_symbol(8*l_byte_being_steered,l_port) - 3; - FAPI_ERR("WARNING: Bad spare so chip mark goes on l_byte_being_steered = %d", l_byte_being_steered); + FAPI_ERR("WARNING: Bad spare so chip mark goes on l_byte_being_steered = %d on %s", l_byte_being_steered, i_target.toEcmdString()); } else @@ -4926,7 +5004,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, if (l_rc) { - FAPI_ERR("Error updating markstore"); + FAPI_ERR("Error updating markstore on %s.",i_target.toEcmdString()); return l_rc; } @@ -4944,11 +5022,9 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, o_repairs_exceeded |= l_repairs_exceeded_translation[1][l_dimm]; } - FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, symbols %d-%d, FIXED SYMBOL WITH X8 CHIP MARK", - l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte], - 8*l_byte + 2*l_bad_dq_pair_index, 8*l_byte + 2*l_bad_dq_pair_index + 1, - l_chip_mark, - l_chip_mark + 3); + FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); + FAPI_ERR("WARNING: dq %d-%d, symbols %d-%d, FIXED SYMBOL WITH X8 CHIP MARK on %s", + 8*l_byte + 2*l_bad_dq_pair_index, 8*l_byte + 2*l_bad_dq_pair_index + 1, l_chip_mark, l_chip_mark + 3, i_target.toEcmdString()); } @@ -4967,9 +5043,10 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, o_repairs_exceeded |= l_repairs_exceeded_translation[0][l_dimm]; } - FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, REPAIRS EXCEEDED", - l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte], - 8*l_byte + 2*l_bad_dq_pair_index, 8*l_byte + 2*l_bad_dq_pair_index + 1); + FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); + FAPI_ERR("WARNING: dq %d-%d, REPAIRS EXCEEDED on %s", + 8*l_byte + 2*l_bad_dq_pair_index, 8*l_byte + 2*l_bad_dq_pair_index + 1, i_target.toEcmdString()); + // Break out of loop on bytes break; @@ -5066,7 +5143,7 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, MAINT0_MBA_MAINT_BUFF3_DATA2_0x03010687, // 5 DW11 MAINT0_MBA_MAINT_BUFF1_DATA3_0x03010668, // 6 DW13 MAINT0_MBA_MAINT_BUFF3_DATA3_0x03010688}},//7 DW15 - + // UE trap 1: // Port0 {{MAINT0_MBA_MAINT_BUFF0_DATA4_0x03010659, // 0 DW0 @@ -5106,13 +5183,13 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, uint8_t l_port = 0; // 0,1 uint8_t l_beat = 0; // 0-7 uint8_t l_byte = 0; // 0-9 - uint8_t l_loop = 0; + uint8_t l_loop = 0; ecmdDataBufferBase l_data(64); ecmdDataBufferBase l_UE_trap0_signature(64); ecmdDataBufferBase l_UE_trap1_signature(64); ecmdDataBufferBase l_mbmmr(64); ecmdDataBufferBase l_mbmct(64); - ecmdDataBufferBase l_mbstr(64); + ecmdDataBufferBase l_mbstr(64); uint8_t l_initPattern = 0; uint8_t l_cmd_type = 0; fapi::Target l_targetCentaur; @@ -5130,7 +5207,7 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, uint8_t l_ECC_c3_c2_c1_c0_23 = 0; uint8_t l_dramSparePort0Symbol = MSS_INVALID_SYMBOL; uint8_t l_dramSparePort1Symbol = MSS_INVALID_SYMBOL; - uint8_t l_eccSpareSymbol = MSS_INVALID_SYMBOL; + uint8_t l_eccSpareSymbol = MSS_INVALID_SYMBOL; //---------------------------------------------------- // Initialize o_bad_bits @@ -5153,7 +5230,7 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, l_rc = fapiGetParentChip(i_target, l_targetCentaur); if(l_rc) { - FAPI_ERR("Error getting Centaur parent target for the given MBA"); + FAPI_ERR("Error getting Centaur parent target for the given MBA, on %s.",i_target.toEcmdString()); return l_rc; } @@ -5161,13 +5238,13 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbaPosition); if(l_rc) { - FAPI_ERR("Error getting MBA position"); + FAPI_ERR("Error getting MBA position on %s.",i_target.toEcmdString()); return l_rc; } // MBMMR[4:7] contains the pattern index l_rc = fapiGetScom(l_targetCentaur, mss_mbmmr[l_mbaPosition], l_mbmmr); - if(l_rc) return l_rc; + if(l_rc) return l_rc; l_ecmd_rc |= l_mbmmr.extractPreserve(&l_initPattern, 4, 4, 8-4); if(l_ecmd_rc) { @@ -5188,14 +5265,14 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, // No isolation if cmd is timebased steer cleanup if (l_cmd_type == 2) { - FAPI_ERR("WARNING: rank%d maint UE during steer cleanup - no bad bit isolation possible.", i_rank); + FAPI_ERR("WARNING: rank%d maint UE during steer cleanup - no bad bit isolation possible on %s.", i_rank, i_target.toEcmdString()); return l_rc; } // No isolation if pattern is random if (l_initPattern == 8) { - FAPI_ERR("WARNING: rank%d maint UE with random pattern - no bad bit isolation possible.", i_rank); + FAPI_ERR("WARNING: rank%d maint UE with random pattern - no bad bit isolation possible on %s.", i_rank, i_target.toEcmdString()); return l_rc; } @@ -5212,7 +5289,7 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, //---------------------------------------------------- l_rc = fapiGetScom(i_target, MAINT0_MBA_MAINT_BUFF0_DATA0_0x03010655, l_UE_trap0_signature); if(l_rc) return l_rc; - + l_rc = fapiGetScom(i_target, MAINT0_MBA_MAINT_BUFF0_DATA4_0x03010659, l_UE_trap1_signature); if(l_rc) return l_rc; @@ -5232,28 +5309,28 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, } else { - FAPI_ERR("IPL UE trapping didn't work."); - + FAPI_ERR("IPL UE trapping didn't work on i_rank = %d on %s.", i_rank, i_target.toEcmdString()); + // Read for FFDC: MBSTR[59]: UE trap enable bit l_rc = fapiGetScom(l_targetCentaur, mss_mbstr[l_mbaPosition], l_mbstr); if(l_rc) return l_rc; - + // Calling out MBA target high, deconfig, gard const fapi::Target & MBA = i_target; // FFDC: Capture UE trap contents ecmdDataBufferBase & UE_TRAP0 = l_UE_trap0_signature; - ecmdDataBufferBase & UE_TRAP1 = l_UE_trap1_signature; + ecmdDataBufferBase & UE_TRAP1 = l_UE_trap1_signature; // FFDC: MBMCT[0:4] contains the cmd type - ecmdDataBufferBase & MBMCT = l_mbmct; + ecmdDataBufferBase & MBMCT = l_mbmct; // FFDC: MBMMR[4:7] contains the pattern index - ecmdDataBufferBase & MBMMR = l_mbmmr; + ecmdDataBufferBase & MBMMR = l_mbmmr; // FFDC: MBSTR[59]: UE trap enable bit - ecmdDataBufferBase & MBSTR = l_mbstr; - + ecmdDataBufferBase & MBSTR = l_mbstr; + // Create new log FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_NO_UE_TRAP); - + return l_rc; } @@ -5267,7 +5344,7 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, { l_tmp_data_diff[0] = 0; l_tmp_data_diff[1] = 0; - + FAPI_INF("port%d", l_port); for(l_beat=0; l_beat<8; l_beat++ ) { @@ -5287,7 +5364,7 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, FAPI_INF("***************************************** l_tmp_diff: 0x%.8X 0x%.8X", l_tmp_data_diff[0], l_tmp_data_diff[1]); } - // Put l_tmp_diff into a ecmdDataBufferBase to make it easier + // Put l_tmp_diff into a ecmdDataBufferBase to make it easier // to get into o_bad_bits l_ecmd_rc |= l_diff.insert(l_tmp_data_diff[0], 0, 32, 0); l_ecmd_rc |= l_diff.insert(l_tmp_data_diff[1], 32, 32, 0); @@ -5316,7 +5393,7 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, //---------------------------------------------------- for(l_loop=0; l_loop<4; l_loop++ ) - { + { l_tag_MDI = 0; l_tmp_65th_byte_diff = 0; @@ -5348,7 +5425,7 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, { // Checkbit0_1 maps to port0 bit 64, which is on byte8 o_bad_bits[0][8] |= 0x80; - } + } // Check for mismatch in bit 1: Tag0_2 if (l_tmp_65th_byte_diff & 0x40) @@ -5378,7 +5455,7 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, //---------------------------------------------------- for(l_loop=0; l_loop<4; l_loop++ ) - { + { l_ECC = 0; l_rc = fapiGetScom(i_target, maintBufferRead65thByteRegs[l_UE_trap][l_loop], l_data); @@ -5424,7 +5501,7 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, o_bad_bits[0][8] |= l_ECC_c6_c5_c4_01 | l_ECC_c6_c5_c4_23; // The 8 bits of ECC_c3_c2_c1_c0 maps to byte8 byte on port1 o_bad_bits[1][8] |= l_ECC_c3_c2_c1_c0_01 | l_ECC_c3_c2_c1_c0_23; - + //---------------------------------------------------- // Spare: Mark byte9 bad if bad bits found in position being steered @@ -5471,10 +5548,10 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, } //---------------------------------------------------- - // Show results + // Show results //---------------------------------------------------- - FAPI_ERR("WARNING: IPL UE isolation results for rank = %d.", i_rank); + FAPI_ERR("WARNING: IPL UE isolation results for rank = %d on %s.", i_rank, i_target.toEcmdString()); FAPI_ERR("WARNING: Expected pattern = 0x%.8X", mss_maintBufferData[l_initPattern][0][0]); for(l_port=0; l_port<2; l_port++ ) { |
