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author | Richard J. Knight <rjknight@us.ibm.com> | 2013-07-24 10:50:00 -0500 |
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committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-09-13 10:00:51 -0500 |
commit | b082024bbc723c6c9a3a15c03011302ffef4efdf (patch) | |
tree | f540671ba70bcb6e95567579aec4713861998d8a /src/usr/hwpf/hwp/nest_chiplets | |
parent | 7747d54277d67621aab5ae715c3c4db372aa8c2b (diff) | |
download | talos-hostboot-b082024bbc723c6c9a3a15c03011302ffef4efdf.tar.gz talos-hostboot-b082024bbc723c6c9a3a15c03011302ffef4efdf.zip |
INITPROC hwp updates (hostboot integration)
CQ:SW205470
Change-Id: I7adc6b2efefe09e559efedf791538903c61f4e50
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/6148
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf/hwp/nest_chiplets')
-rw-r--r-- | src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C | 63 | ||||
-rw-r--r-- | src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H | 24 |
2 files changed, 84 insertions, 3 deletions
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C index 085e110a6..8a9df2e70 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_pcie_scominit.C,v 1.6 2013/04/08 14:57:39 jmcgill Exp $ +// $Id: proc_pcie_scominit.C,v 1.7 2013/05/15 04:18:56 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_scominit.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -379,7 +379,7 @@ fapi::ReturnCode proc_pcie_scominit_iop_complete( data); if (!rc.ok()) { - FAPI_ERR("proc_pcie_scominit_iop_complete: Error from fapiPutScom (PCIE%d_ETU_RESET_0x%016llX)", + FAPI_ERR("proc_pcie_scominit_iop_complete: Error from fapiPutScom (PCIE%d_ETU_RESET_0x%08X)", i, PROC_PCIE_SCOMINIT_ETU_RESET[i]); break; } @@ -389,6 +389,65 @@ fapi::ReturnCode proc_pcie_scominit_iop_complete( break; } + // configure IOP FIR + for (size_t i = 0; i < PROC_PCIE_SCOMINIT_NUM_IOP; i++) + { + rc_ecmd |= data.flushTo0(); + if (rc_ecmd) + { + FAPI_ERR("proc_pcie_scominit_iop_complete: Error 0x%x setting up PLL FIR register clear data buffer", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + // clear FIR + rc = fapiPutScom(i_target, + PROC_PCIE_SCOMINIT_PLL_FIR[i], + data); + if (!rc.ok()) + { + FAPI_ERR("proc_pcie_scominit_iop_complete: Error from fapiPutScom (PCIE_IOP%d_PLL_FIR_0x%08X)", + i, PROC_PCIE_SCOMINIT_PLL_FIR[i]); + break; + } + + // clear FIR WOF + rc = fapiPutScom(i_target, + PROC_PCIE_SCOMINIT_PLL_FIR_WOF[i], + data); + if (!rc.ok()) + { + FAPI_ERR("proc_pcie_scominit_iop_complete: Error from fapiPutScom (PCIE_IOP%d_PLL_FIR_WOF_0x%08X)", + i, PROC_PCIE_SCOMINIT_PLL_FIR_WOF[i]); + break; + } + + rc_ecmd |= data.setDoubleWord(0, PCIE_PLL_FIR_MASK_VAL); + if (rc_ecmd) + { + FAPI_ERR("proc_pcie_scominit_iop_complete: Error 0x%x setting up PLL FIR mask register data buffer", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + // unmask + rc = fapiPutScom(i_target, + PROC_PCIE_SCOMINIT_PLL_FIR_MASK[i], + data); + if (!rc.ok()) + { + FAPI_ERR("proc_pcie_scominit_iop_complete: Error from fapiPutScom (PCIE_IOP%d_PLL_FIR_MASK_0x%08X)", + i, PROC_PCIE_SCOMINIT_PLL_FIR_MASK[i]); + break; + } + } + if (!rc.ok()) + { + break; + } + } while(0); // mark function exit diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H index a57646d40..1a0b5920d 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_pcie_scominit.H,v 1.3 2013/04/08 14:57:41 jmcgill Exp $ +// $Id: proc_pcie_scominit.H,v 1.4 2013/05/15 04:18:58 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_scominit.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -120,6 +120,28 @@ const uint64_t PROC_PCIE_SCOMINIT_PLL_GLOBAL_CONTROL2[PROC_PCIE_SCOMINIT_NUM_IOP }; const uint32_t PLL_GLOBAL_CONTROL2_PROG_COMPLETE_BIT = 50; +// PCIe PLL FIR register field/bit definitions +const uint32_t PROC_PCIE_SCOMINIT_PLL_FIR[PROC_PCIE_SCOMINIT_NUM_IOP] = +{ + PCIE_IOP0_PLL_FIR_0x09011400, + PCIE_IOP1_PLL_FIR_0x09011840 +}; + +const uint32_t PROC_PCIE_SCOMINIT_PLL_FIR_WOF[PROC_PCIE_SCOMINIT_NUM_IOP] = +{ + PCIE_IOP0_PLL_FIR_WOF_0x09011408, + PCIE_IOP1_PLL_FIR_WOF_0x09011848 +}; + +const uint32_t PROC_PCIE_SCOMINIT_PLL_FIR_MASK[PROC_PCIE_SCOMINIT_NUM_IOP] = +{ + PCIE_IOP0_PLL_FIR_MASK_0x09011403, + PCIE_IOP1_PLL_FIR_MASK_0x09011843 +}; + +const uint64_t PCIE_PLL_FIR_MASK_VAL = 0x0080000000000000ULL; + + //------------------------------------------------------------------------------ // Structure definitions //------------------------------------------------------------------------------ |